1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 /*************************************\ 20 * Attach/Detach Functions and helpers * 21 \*************************************/ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include "ath5k.h" 26 #include "reg.h" 27 #include "debug.h" 28 #include "base.h" 29 30 /** 31 * ath5k_hw_post - Power On Self Test helper function 32 * 33 * @ah: The &struct ath5k_hw 34 */ 35 static int ath5k_hw_post(struct ath5k_hw *ah) 36 { 37 38 static const u32 static_pattern[4] = { 39 0x55555555, 0xaaaaaaaa, 40 0x66666666, 0x99999999 41 }; 42 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) }; 43 int i, c; 44 u16 cur_reg; 45 u32 var_pattern; 46 u32 init_val; 47 u32 cur_val; 48 49 for (c = 0; c < 2; c++) { 50 51 cur_reg = regs[c]; 52 53 /* Save previous value */ 54 init_val = ath5k_hw_reg_read(ah, cur_reg); 55 56 for (i = 0; i < 256; i++) { 57 var_pattern = i << 16 | i; 58 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 59 cur_val = ath5k_hw_reg_read(ah, cur_reg); 60 61 if (cur_val != var_pattern) { 62 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); 63 return -EAGAIN; 64 } 65 66 /* Found on ndiswrapper dumps */ 67 var_pattern = 0x0039080f; 68 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 69 } 70 71 for (i = 0; i < 4; i++) { 72 var_pattern = static_pattern[i]; 73 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 74 cur_val = ath5k_hw_reg_read(ah, cur_reg); 75 76 if (cur_val != var_pattern) { 77 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); 78 return -EAGAIN; 79 } 80 81 /* Found on ndiswrapper dumps */ 82 var_pattern = 0x003b080f; 83 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 84 } 85 86 /* Restore previous value */ 87 ath5k_hw_reg_write(ah, init_val, cur_reg); 88 89 } 90 91 return 0; 92 93 } 94 95 /** 96 * ath5k_hw_attach - Check if hw is supported and init the needed structs 97 * 98 * @sc: The &struct ath5k_softc we got from the driver's attach function 99 * 100 * Check if the device is supported, perform a POST and initialize the needed 101 * structs. Returns -ENOMEM if we don't have memory for the needed structs, 102 * -ENODEV if the device is not supported or prints an error msg if something 103 * else went wrong. 104 */ 105 int ath5k_hw_attach(struct ath5k_softc *sc) 106 { 107 struct ath5k_hw *ah = sc->ah; 108 struct ath_common *common = ath5k_hw_common(ah); 109 struct pci_dev *pdev = sc->pdev; 110 struct ath5k_eeprom_info *ee; 111 int ret; 112 u32 srev; 113 114 /* 115 * HW information 116 */ 117 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 118 ah->ah_turbo = false; 119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 120 ah->ah_imr = 0; 121 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 122 ah->ah_software_retry = false; 123 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT; 124 ah->ah_noise_floor = -95; /* until first NF calibration is run */ 125 sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO; 126 ah->ah_current_channel = &sc->channels[0]; 127 128 /* 129 * Find the mac version 130 */ 131 srev = ath5k_hw_reg_read(ah, AR5K_SREV); 132 if (srev < AR5K_SREV_AR5311) 133 ah->ah_version = AR5K_AR5210; 134 else if (srev < AR5K_SREV_AR5212) 135 ah->ah_version = AR5K_AR5211; 136 else 137 ah->ah_version = AR5K_AR5212; 138 139 /* Fill the ath5k_hw struct with the needed functions */ 140 ret = ath5k_hw_init_desc_functions(ah); 141 if (ret) 142 goto err_free; 143 144 /* Bring device out of sleep and reset its units */ 145 ret = ath5k_hw_nic_wakeup(ah, 0, true); 146 if (ret) 147 goto err_free; 148 149 /* Get MAC, PHY and RADIO revisions */ 150 ah->ah_mac_srev = srev; 151 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); 152 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & 153 0xffffffff; 154 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, 155 CHANNEL_5GHZ); 156 ah->ah_phy = AR5K_PHY(0); 157 158 /* Try to identify radio chip based on its srev */ 159 switch (ah->ah_radio_5ghz_revision & 0xf0) { 160 case AR5K_SREV_RAD_5111: 161 ah->ah_radio = AR5K_RF5111; 162 ah->ah_single_chip = false; 163 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 164 CHANNEL_2GHZ); 165 break; 166 case AR5K_SREV_RAD_5112: 167 case AR5K_SREV_RAD_2112: 168 ah->ah_radio = AR5K_RF5112; 169 ah->ah_single_chip = false; 170 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 171 CHANNEL_2GHZ); 172 break; 173 case AR5K_SREV_RAD_2413: 174 ah->ah_radio = AR5K_RF2413; 175 ah->ah_single_chip = true; 176 break; 177 case AR5K_SREV_RAD_5413: 178 ah->ah_radio = AR5K_RF5413; 179 ah->ah_single_chip = true; 180 break; 181 case AR5K_SREV_RAD_2316: 182 ah->ah_radio = AR5K_RF2316; 183 ah->ah_single_chip = true; 184 break; 185 case AR5K_SREV_RAD_2317: 186 ah->ah_radio = AR5K_RF2317; 187 ah->ah_single_chip = true; 188 break; 189 case AR5K_SREV_RAD_5424: 190 if (ah->ah_mac_version == AR5K_SREV_AR2425 || 191 ah->ah_mac_version == AR5K_SREV_AR2417){ 192 ah->ah_radio = AR5K_RF2425; 193 ah->ah_single_chip = true; 194 } else { 195 ah->ah_radio = AR5K_RF5413; 196 ah->ah_single_chip = true; 197 } 198 break; 199 default: 200 /* Identify radio based on mac/phy srev */ 201 if (ah->ah_version == AR5K_AR5210) { 202 ah->ah_radio = AR5K_RF5110; 203 ah->ah_single_chip = false; 204 } else if (ah->ah_version == AR5K_AR5211) { 205 ah->ah_radio = AR5K_RF5111; 206 ah->ah_single_chip = false; 207 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 208 CHANNEL_2GHZ); 209 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || 210 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || 211 ah->ah_phy_revision == AR5K_SREV_PHY_2425) { 212 ah->ah_radio = AR5K_RF2425; 213 ah->ah_single_chip = true; 214 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; 215 } else if (srev == AR5K_SREV_AR5213A && 216 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { 217 ah->ah_radio = AR5K_RF5112; 218 ah->ah_single_chip = false; 219 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; 220 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) { 221 ah->ah_radio = AR5K_RF2316; 222 ah->ah_single_chip = true; 223 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; 224 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || 225 ah->ah_phy_revision == AR5K_SREV_PHY_5413) { 226 ah->ah_radio = AR5K_RF5413; 227 ah->ah_single_chip = true; 228 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; 229 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || 230 ah->ah_phy_revision == AR5K_SREV_PHY_2413) { 231 ah->ah_radio = AR5K_RF2413; 232 ah->ah_single_chip = true; 233 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; 234 } else { 235 ATH5K_ERR(sc, "Couldn't identify radio revision.\n"); 236 ret = -ENODEV; 237 goto err_free; 238 } 239 } 240 241 242 /* Return on unsuported chips (unsupported eeprom etc) */ 243 if ((srev >= AR5K_SREV_AR5416) && 244 (srev < AR5K_SREV_AR2425)) { 245 ATH5K_ERR(sc, "Device not yet supported.\n"); 246 ret = -ENODEV; 247 goto err_free; 248 } 249 250 /* 251 * POST 252 */ 253 ret = ath5k_hw_post(ah); 254 if (ret) 255 goto err_free; 256 257 /* Enable pci core retry fix on Hainan (5213A) and later chips */ 258 if (srev >= AR5K_SREV_AR5213A) 259 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX); 260 261 /* 262 * Get card capabilities, calibration values etc 263 * TODO: EEPROM work 264 */ 265 ret = ath5k_eeprom_init(ah); 266 if (ret) { 267 ATH5K_ERR(sc, "unable to init EEPROM\n"); 268 goto err_free; 269 } 270 271 ee = &ah->ah_capabilities.cap_eeprom; 272 273 /* 274 * Write PCI-E power save settings 275 */ 276 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) { 277 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES); 278 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES); 279 280 /* Shut off RX when elecidle is asserted */ 281 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); 282 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); 283 284 /* If serdes programing is enabled, increase PCI-E 285 * tx power for systems with long trace from host 286 * to minicard connector. */ 287 if (ee->ee_serdes) 288 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES); 289 else 290 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES); 291 292 /* Shut off PLL and CLKREQ active in L1 */ 293 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES); 294 295 /* Preserve other settings */ 296 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES); 297 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES); 298 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES); 299 300 /* Reset SERDES to load new settings */ 301 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET); 302 mdelay(1); 303 } 304 305 /* Get misc capabilities */ 306 ret = ath5k_hw_set_capabilities(ah); 307 if (ret) { 308 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n", 309 sc->pdev->device); 310 goto err_free; 311 } 312 313 /* Crypto settings */ 314 common->keymax = (sc->ah->ah_version == AR5K_AR5210 ? 315 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211); 316 317 if (srev >= AR5K_SREV_AR5212_V4 && 318 (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 && 319 !AR5K_EEPROM_AES_DIS(ee->ee_misc5))) 320 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 321 322 if (srev >= AR5K_SREV_AR2414) { 323 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; 324 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE, 325 AR5K_MISC_MODE_COMBINED_MIC); 326 } 327 328 /* MAC address is cleared until add_interface */ 329 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){}); 330 331 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ 332 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN); 333 ath5k_hw_set_bssid(ah); 334 ath5k_hw_set_opmode(ah, sc->opmode); 335 336 ath5k_hw_rfgain_opt_init(ah); 337 338 ath5k_hw_init_nfcal_hist(ah); 339 340 /* turn on HW LEDs */ 341 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT); 342 343 return 0; 344 err_free: 345 kfree(ah); 346 return ret; 347 } 348 349 /** 350 * ath5k_hw_detach - Free the ath5k_hw struct 351 * 352 * @ah: The &struct ath5k_hw 353 */ 354 void ath5k_hw_detach(struct ath5k_hw *ah) 355 { 356 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status); 357 358 if (ah->ah_rf_banks != NULL) 359 kfree(ah->ah_rf_banks); 360 361 ath5k_eeprom_detach(ah); 362 363 /* assume interrupts are down */ 364 } 365