1 /* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _ATH5K_H 19 #define _ATH5K_H 20 21 /* TODO: Clean up channel debugging (doesn't work anyway) and start 22 * working on reg. control code using all available eeprom information 23 * (rev. engineering needed) */ 24 #define CHAN_DEBUG 0 25 26 #include <linux/io.h> 27 #include <linux/interrupt.h> 28 #include <linux/types.h> 29 #include <linux/average.h> 30 #include <linux/leds.h> 31 #include <net/mac80211.h> 32 33 /* RX/TX descriptor hw structs 34 * TODO: Driver part should only see sw structs */ 35 #include "desc.h" 36 37 /* EEPROM structs/offsets 38 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 39 * and clean up common bits, then introduce set/get functions in eeprom.c */ 40 #include "eeprom.h" 41 #include "debug.h" 42 #include "../ath.h" 43 #include "ani.h" 44 45 /* PCI IDs */ 46 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 47 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 48 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 49 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 50 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 51 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 52 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 53 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 54 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 55 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 56 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 57 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 58 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 59 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 60 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 61 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 65 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 66 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 67 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 68 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 69 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 70 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 71 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 72 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 73 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 74 75 /****************************\ 76 GENERIC DRIVER DEFINITIONS 77 \****************************/ 78 79 #define ATH5K_PRINTF(fmt, ...) \ 80 printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__) 81 82 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 83 printk(_level "ath5k %s: " _fmt, \ 84 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 85 ##__VA_ARGS__) 86 87 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 88 if (net_ratelimit()) \ 89 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 90 } while (0) 91 92 #define ATH5K_INFO(_sc, _fmt, ...) \ 93 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 94 95 #define ATH5K_WARN(_sc, _fmt, ...) \ 96 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 97 98 #define ATH5K_ERR(_sc, _fmt, ...) \ 99 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 100 101 /* 102 * AR5K REGISTER ACCESS 103 */ 104 105 /* Some macros to read/write fields */ 106 107 /* First shift, then mask */ 108 #define AR5K_REG_SM(_val, _flags) \ 109 (((_val) << _flags##_S) & (_flags)) 110 111 /* First mask, then shift */ 112 #define AR5K_REG_MS(_val, _flags) \ 113 (((_val) & (_flags)) >> _flags##_S) 114 115 /* Some registers can hold multiple values of interest. For this 116 * reason when we want to write to these registers we must first 117 * retrieve the values which we do not want to clear (lets call this 118 * old_data) and then set the register with this and our new_value: 119 * ( old_data | new_value) */ 120 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 121 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 122 (((_val) << _flags##_S) & (_flags)), _reg) 123 124 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 126 (_mask)) | (_flags), _reg) 127 128 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 129 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 130 131 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 132 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 133 134 /* Access QCU registers per queue */ 135 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ 136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 137 138 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 139 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 140 141 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 142 _reg |= 1 << _queue; \ 143 } while (0) 144 145 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 146 _reg &= ~(1 << _queue); \ 147 } while (0) 148 149 /* Used while writing initvals */ 150 #define AR5K_REG_WAIT(_i) do { \ 151 if (_i % 64) \ 152 udelay(1); \ 153 } while (0) 154 155 /* 156 * Some tunable values (these should be changeable by the user) 157 * TODO: Make use of them and add more options OR use debug/configfs 158 */ 159 #define AR5K_TUNE_DMA_BEACON_RESP 2 160 #define AR5K_TUNE_SW_BEACON_RESP 10 161 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 162 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 163 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 164 #define AR5K_TUNE_REGISTER_TIMEOUT 20000 165 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to 166 * be the max value. */ 167 #define AR5K_TUNE_RSSI_THRES 129 168 /* This must be set when setting the RSSI threshold otherwise it can 169 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 170 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep 171 * track of it. Max value depends on hardware. For AR5210 this is just 7. 172 * For AR5211+ this seems to be up to 255. */ 173 #define AR5K_TUNE_BMISS_THRES 7 174 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000 175 #define AR5K_TUNE_BEACON_INTERVAL 100 176 #define AR5K_TUNE_AIFS 2 177 #define AR5K_TUNE_AIFS_11B 2 178 #define AR5K_TUNE_AIFS_XR 0 179 #define AR5K_TUNE_CWMIN 15 180 #define AR5K_TUNE_CWMIN_11B 31 181 #define AR5K_TUNE_CWMIN_XR 3 182 #define AR5K_TUNE_CWMAX 1023 183 #define AR5K_TUNE_CWMAX_11B 1023 184 #define AR5K_TUNE_CWMAX_XR 7 185 #define AR5K_TUNE_NOISE_FLOOR -72 186 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 187 #define AR5K_TUNE_MAX_TXPOWER 63 188 #define AR5K_TUNE_DEFAULT_TXPOWER 25 189 #define AR5K_TUNE_TPC_TXPOWER false 190 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 191 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 192 #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 193 194 #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 195 196 #define AR5K_INIT_CARR_SENSE_EN 1 197 198 /*Swap RX/TX Descriptor for big endian archs*/ 199 #if defined(__BIG_ENDIAN) 200 #define AR5K_INIT_CFG ( \ 201 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 202 ) 203 #else 204 #define AR5K_INIT_CFG 0x00000000 205 #endif 206 207 /* Initial values */ 208 #define AR5K_INIT_CYCRSSI_THR1 2 209 210 /* Tx retry limit defaults from standard */ 211 #define AR5K_INIT_RETRY_SHORT 7 212 #define AR5K_INIT_RETRY_LONG 4 213 214 /* Slot time */ 215 #define AR5K_INIT_SLOT_TIME_TURBO 6 216 #define AR5K_INIT_SLOT_TIME_DEFAULT 9 217 #define AR5K_INIT_SLOT_TIME_HALF_RATE 13 218 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 219 #define AR5K_INIT_SLOT_TIME_B 20 220 #define AR5K_SLOT_TIME_MAX 0xffff 221 222 /* SIFS */ 223 #define AR5K_INIT_SIFS_TURBO 6 224 #define AR5K_INIT_SIFS_DEFAULT_BG 10 225 #define AR5K_INIT_SIFS_DEFAULT_A 16 226 #define AR5K_INIT_SIFS_HALF_RATE 32 227 #define AR5K_INIT_SIFS_QUARTER_RATE 64 228 229 /* Used to calculate tx time for non 5/10/40MHz 230 * operation */ 231 /* It's preamble time + signal time (16 + 4) */ 232 #define AR5K_INIT_OFDM_PREAMPLE_TIME 20 233 /* Preamble time for 40MHz (turbo) operation (min ?) */ 234 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 235 #define AR5K_INIT_OFDM_SYMBOL_TIME 4 236 #define AR5K_INIT_OFDM_PLCP_BITS 22 237 238 /* Rx latency for 5 and 10MHz operation (max ?) */ 239 #define AR5K_INIT_RX_LAT_MAX 63 240 /* Tx latencies from initvals (5212 only but no problem 241 * because we only tweak them on 5212) */ 242 #define AR5K_INIT_TX_LAT_A 54 243 #define AR5K_INIT_TX_LAT_BG 384 244 /* Tx latency for 40MHz (turbo) operation (min ?) */ 245 #define AR5K_INIT_TX_LAT_MIN 32 246 /* Default Tx/Rx latencies (same for 5211)*/ 247 #define AR5K_INIT_TX_LATENCY_5210 54 248 #define AR5K_INIT_RX_LATENCY_5210 29 249 250 /* Tx frame to Tx data start delay */ 251 #define AR5K_INIT_TXF2TXD_START_DEFAULT 14 252 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 253 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 254 255 /* We need to increase PHY switch and agc settling time 256 * on turbo mode */ 257 #define AR5K_SWITCH_SETTLING 5760 258 #define AR5K_SWITCH_SETTLING_TURBO 7168 259 260 #define AR5K_AGC_SETTLING 28 261 /* 38 on 5210 but shouldn't matter */ 262 #define AR5K_AGC_SETTLING_TURBO 37 263 264 265 /* GENERIC CHIPSET DEFINITIONS */ 266 267 /* MAC Chips */ 268 enum ath5k_version { 269 AR5K_AR5210 = 0, 270 AR5K_AR5211 = 1, 271 AR5K_AR5212 = 2, 272 }; 273 274 /* PHY Chips */ 275 enum ath5k_radio { 276 AR5K_RF5110 = 0, 277 AR5K_RF5111 = 1, 278 AR5K_RF5112 = 2, 279 AR5K_RF2413 = 3, 280 AR5K_RF5413 = 4, 281 AR5K_RF2316 = 5, 282 AR5K_RF2317 = 6, 283 AR5K_RF2425 = 7, 284 }; 285 286 /* 287 * Common silicon revision/version values 288 */ 289 290 #define AR5K_SREV_UNKNOWN 0xffff 291 292 #define AR5K_SREV_AR5210 0x00 /* Crete */ 293 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 294 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 295 #define AR5K_SREV_AR5311B 0x30 /* Spirit */ 296 #define AR5K_SREV_AR5211 0x40 /* Oahu */ 297 #define AR5K_SREV_AR5212 0x50 /* Venice */ 298 #define AR5K_SREV_AR5312_R2 0x52 /* AP31 */ 299 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 300 #define AR5K_SREV_AR5213 0x55 /* ??? */ 301 #define AR5K_SREV_AR5312_R7 0x57 /* AP30 */ 302 #define AR5K_SREV_AR2313_R8 0x58 /* AP43 */ 303 #define AR5K_SREV_AR5213A 0x59 /* Hainan */ 304 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 305 #define AR5K_SREV_AR2414 0x70 /* Griffin */ 306 #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */ 307 #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */ 308 #define AR5K_SREV_AR5424 0x90 /* Condor */ 309 #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */ 310 #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */ 311 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 312 #define AR5K_SREV_AR5414 0xa0 /* Eagle */ 313 #define AR5K_SREV_AR2415 0xb0 /* Talon */ 314 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 315 #define AR5K_SREV_AR5418 0xca /* PCI-E */ 316 #define AR5K_SREV_AR2425 0xe0 /* Swan */ 317 #define AR5K_SREV_AR2417 0xf0 /* Nala */ 318 319 #define AR5K_SREV_RAD_5110 0x00 320 #define AR5K_SREV_RAD_5111 0x10 321 #define AR5K_SREV_RAD_5111A 0x15 322 #define AR5K_SREV_RAD_2111 0x20 323 #define AR5K_SREV_RAD_5112 0x30 324 #define AR5K_SREV_RAD_5112A 0x35 325 #define AR5K_SREV_RAD_5112B 0x36 326 #define AR5K_SREV_RAD_2112 0x40 327 #define AR5K_SREV_RAD_2112A 0x45 328 #define AR5K_SREV_RAD_2112B 0x46 329 #define AR5K_SREV_RAD_2413 0x50 330 #define AR5K_SREV_RAD_5413 0x60 331 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 332 #define AR5K_SREV_RAD_2317 0x80 333 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 334 #define AR5K_SREV_RAD_2425 0xa2 335 #define AR5K_SREV_RAD_5133 0xc0 336 337 #define AR5K_SREV_PHY_5211 0x30 338 #define AR5K_SREV_PHY_5212 0x41 339 #define AR5K_SREV_PHY_5212A 0x42 340 #define AR5K_SREV_PHY_5212B 0x43 341 #define AR5K_SREV_PHY_2413 0x45 342 #define AR5K_SREV_PHY_5413 0x61 343 #define AR5K_SREV_PHY_2425 0x70 344 345 /* TODO add support to mac80211 for vendor-specific rates and modes */ 346 347 /* 348 * Some of this information is based on Documentation from: 349 * 350 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 351 * 352 * Modulation for Atheros' eXtended Range - range enhancing extension that is 353 * supposed to double the distance an Atheros client device can keep a 354 * connection with an Atheros access point. This is achieved by increasing 355 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 356 * the 802.11 specifications demand. In addition, new (proprietary) data rates 357 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 358 * 359 * Please note that can you either use XR or TURBO but you cannot use both, 360 * they are exclusive. 361 * 362 */ 363 #define MODULATION_XR 0x00000200 364 /* 365 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 366 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 367 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 368 * channels. To use this feature your Access Point must also support it. 369 * There is also a distinction between "static" and "dynamic" turbo modes: 370 * 371 * - Static: is the dumb version: devices set to this mode stick to it until 372 * the mode is turned off. 373 * - Dynamic: is the intelligent version, the network decides itself if it 374 * is ok to use turbo. As soon as traffic is detected on adjacent channels 375 * (which would get used in turbo mode), or when a non-turbo station joins 376 * the network, turbo mode won't be used until the situation changes again. 377 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 378 * monitors the used radio band in order to decide whether turbo mode may 379 * be used or not. 380 * 381 * This article claims Super G sticks to bonding of channels 5 and 6 for 382 * USA: 383 * 384 * http://www.pcworld.com/article/id,113428-page,1/article.html 385 * 386 * The channel bonding seems to be driver specific though. In addition to 387 * deciding what channels will be used, these "Turbo" modes are accomplished 388 * by also enabling the following features: 389 * 390 * - Bursting: allows multiple frames to be sent at once, rather than pausing 391 * after each frame. Bursting is a standards-compliant feature that can be 392 * used with any Access Point. 393 * - Fast frames: increases the amount of information that can be sent per 394 * frame, also resulting in a reduction of transmission overhead. It is a 395 * proprietary feature that needs to be supported by the Access Point. 396 * - Compression: data frames are compressed in real time using a Lempel Ziv 397 * algorithm. This is done transparently. Once this feature is enabled, 398 * compression and decompression takes place inside the chipset, without 399 * putting additional load on the host CPU. 400 * 401 */ 402 #define MODULATION_TURBO 0x00000080 403 404 enum ath5k_driver_mode { 405 AR5K_MODE_11A = 0, 406 AR5K_MODE_11B = 1, 407 AR5K_MODE_11G = 2, 408 AR5K_MODE_MAX = 3 409 }; 410 411 enum ath5k_ant_mode { 412 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 413 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 414 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 415 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 416 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 417 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 418 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 419 AR5K_ANTMODE_MAX, 420 }; 421 422 enum ath5k_bw_mode { 423 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 424 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 425 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 426 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 427 }; 428 429 /****************\ 430 TX DEFINITIONS 431 \****************/ 432 433 /* 434 * TX Status descriptor 435 */ 436 struct ath5k_tx_status { 437 u16 ts_seqnum; 438 u16 ts_tstamp; 439 u8 ts_status; 440 u8 ts_final_idx; 441 u8 ts_final_retry; 442 s8 ts_rssi; 443 u8 ts_shortretry; 444 u8 ts_virtcol; 445 u8 ts_antenna; 446 }; 447 448 #define AR5K_TXSTAT_ALTRATE 0x80 449 #define AR5K_TXERR_XRETRY 0x01 450 #define AR5K_TXERR_FILT 0x02 451 #define AR5K_TXERR_FIFO 0x04 452 453 /** 454 * enum ath5k_tx_queue - Queue types used to classify tx queues. 455 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 456 * @AR5K_TX_QUEUE_DATA: A normal data queue 457 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 458 * @AR5K_TX_QUEUE_BEACON: The beacon queue 459 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 460 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 461 */ 462 enum ath5k_tx_queue { 463 AR5K_TX_QUEUE_INACTIVE = 0, 464 AR5K_TX_QUEUE_DATA, 465 AR5K_TX_QUEUE_XR_DATA, 466 AR5K_TX_QUEUE_BEACON, 467 AR5K_TX_QUEUE_CAB, 468 AR5K_TX_QUEUE_UAPSD, 469 }; 470 471 #define AR5K_NUM_TX_QUEUES 10 472 #define AR5K_NUM_TX_QUEUES_NOQCU 2 473 474 /* 475 * Queue syb-types to classify normal data queues. 476 * These are the 4 Access Categories as defined in 477 * WME spec. 0 is the lowest priority and 4 is the 478 * highest. Normal data that hasn't been classified 479 * goes to the Best Effort AC. 480 */ 481 enum ath5k_tx_queue_subtype { 482 AR5K_WME_AC_BK = 0, /*Background traffic*/ 483 AR5K_WME_AC_BE, /*Best-effort (normal) traffic*/ 484 AR5K_WME_AC_VI, /*Video traffic*/ 485 AR5K_WME_AC_VO, /*Voice traffic*/ 486 }; 487 488 /* 489 * Queue ID numbers as returned by the hw functions, each number 490 * represents a hw queue. If hw does not support hw queues 491 * (eg 5210) all data goes in one queue. These match 492 * d80211 definitions (net80211/MadWiFi don't use them). 493 */ 494 enum ath5k_tx_queue_id { 495 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 496 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 497 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 498 AR5K_TX_QUEUE_ID_DATA_MAX = 3, /*IEEE80211_TX_QUEUE_DATA3*/ 499 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 500 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 501 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 502 AR5K_TX_QUEUE_ID_UAPSD = 8, 503 AR5K_TX_QUEUE_ID_XR_DATA = 9, 504 }; 505 506 /* 507 * Flags to set hw queue's parameters... 508 */ 509 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 510 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 511 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 512 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 513 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 514 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 515 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 516 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 517 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 518 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 519 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 520 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 521 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 522 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 523 524 /* 525 * Data transmit queue state. One of these exists for each 526 * hardware transmit queue. Packets sent to us from above 527 * are assigned to queues based on their priority. Not all 528 * devices support a complete set of hardware transmit queues. 529 * For those devices the array sc_ac2q will map multiple 530 * priorities to fewer hardware queues (typically all to one 531 * hardware queue). 532 */ 533 struct ath5k_txq { 534 unsigned int qnum; /* hardware q number */ 535 u32 *link; /* link ptr in last TX desc */ 536 struct list_head q; /* transmit queue */ 537 spinlock_t lock; /* lock on q and link */ 538 bool setup; 539 int txq_len; /* number of queued buffers */ 540 int txq_max; /* max allowed num of queued buffers */ 541 bool txq_poll_mark; 542 unsigned int txq_stuck; /* informational counter */ 543 }; 544 545 /* 546 * A struct to hold tx queue's parameters 547 */ 548 struct ath5k_txq_info { 549 enum ath5k_tx_queue tqi_type; 550 enum ath5k_tx_queue_subtype tqi_subtype; 551 u16 tqi_flags; /* Tx queue flags (see above) */ 552 u8 tqi_aifs; /* Arbitrated Interframe Space */ 553 u16 tqi_cw_min; /* Minimum Contention Window */ 554 u16 tqi_cw_max; /* Maximum Contention Window */ 555 u32 tqi_cbr_period; /* Constant bit rate period */ 556 u32 tqi_cbr_overflow_limit; 557 u32 tqi_burst_time; 558 u32 tqi_ready_time; /* Time queue waits after an event */ 559 }; 560 561 /* 562 * Transmit packet types. 563 * used on tx control descriptor 564 */ 565 enum ath5k_pkt_type { 566 AR5K_PKT_TYPE_NORMAL = 0, 567 AR5K_PKT_TYPE_ATIM = 1, 568 AR5K_PKT_TYPE_PSPOLL = 2, 569 AR5K_PKT_TYPE_BEACON = 3, 570 AR5K_PKT_TYPE_PROBE_RESP = 4, 571 AR5K_PKT_TYPE_PIFS = 5, 572 }; 573 574 /* 575 * TX power and TPC settings 576 */ 577 #define AR5K_TXPOWER_OFDM(_r, _v) ( \ 578 ((0 & 1) << ((_v) + 6)) | \ 579 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 580 ) 581 582 #define AR5K_TXPOWER_CCK(_r, _v) ( \ 583 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 584 ) 585 586 /* 587 * DMA size definitions (2^(n+2)) 588 */ 589 enum ath5k_dmasize { 590 AR5K_DMASIZE_4B = 0, 591 AR5K_DMASIZE_8B, 592 AR5K_DMASIZE_16B, 593 AR5K_DMASIZE_32B, 594 AR5K_DMASIZE_64B, 595 AR5K_DMASIZE_128B, 596 AR5K_DMASIZE_256B, 597 AR5K_DMASIZE_512B 598 }; 599 600 601 /****************\ 602 RX DEFINITIONS 603 \****************/ 604 605 /* 606 * RX Status descriptor 607 */ 608 struct ath5k_rx_status { 609 u16 rs_datalen; 610 u16 rs_tstamp; 611 u8 rs_status; 612 u8 rs_phyerr; 613 s8 rs_rssi; 614 u8 rs_keyix; 615 u8 rs_rate; 616 u8 rs_antenna; 617 u8 rs_more; 618 }; 619 620 #define AR5K_RXERR_CRC 0x01 621 #define AR5K_RXERR_PHY 0x02 622 #define AR5K_RXERR_FIFO 0x04 623 #define AR5K_RXERR_DECRYPT 0x08 624 #define AR5K_RXERR_MIC 0x10 625 #define AR5K_RXKEYIX_INVALID ((u8) -1) 626 #define AR5K_TXKEYIX_INVALID ((u32) -1) 627 628 629 /**************************\ 630 BEACON TIMERS DEFINITIONS 631 \**************************/ 632 633 #define AR5K_BEACON_PERIOD 0x0000ffff 634 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 635 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 636 637 638 /* 639 * TSF to TU conversion: 640 * 641 * TSF is a 64bit value in usec (microseconds). 642 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 643 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 644 */ 645 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 646 647 648 /*******************************\ 649 GAIN OPTIMIZATION DEFINITIONS 650 \*******************************/ 651 652 enum ath5k_rfgain { 653 AR5K_RFGAIN_INACTIVE = 0, 654 AR5K_RFGAIN_ACTIVE, 655 AR5K_RFGAIN_READ_REQUESTED, 656 AR5K_RFGAIN_NEED_CHANGE, 657 }; 658 659 struct ath5k_gain { 660 u8 g_step_idx; 661 u8 g_current; 662 u8 g_target; 663 u8 g_low; 664 u8 g_high; 665 u8 g_f_corr; 666 u8 g_state; 667 }; 668 669 /********************\ 670 COMMON DEFINITIONS 671 \********************/ 672 673 #define AR5K_SLOT_TIME_9 396 674 #define AR5K_SLOT_TIME_20 880 675 #define AR5K_SLOT_TIME_MAX 0xffff 676 677 /* 678 * The following structure is used to map 2GHz channels to 679 * 5GHz Atheros channels. 680 * TODO: Clean up 681 */ 682 struct ath5k_athchan_2ghz { 683 u32 a2_flags; 684 u16 a2_athchan; 685 }; 686 687 688 /******************\ 689 RATE DEFINITIONS 690 \******************/ 691 692 /** 693 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32. 694 * 695 * The rate code is used to get the RX rate or set the TX rate on the 696 * hardware descriptors. It is also used for internal modulation control 697 * and settings. 698 * 699 * This is the hardware rate map we are aware of: 700 * 701 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 702 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 703 * 704 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 705 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 706 * 707 * rate_code 17 18 19 20 21 22 23 24 708 * rate_kbps ? ? ? ? ? ? ? 11000 709 * 710 * rate_code 25 26 27 28 29 30 31 32 711 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 712 * 713 * "S" indicates CCK rates with short preamble. 714 * 715 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 716 * lowest 4 bits, so they are the same as below with a 0xF mask. 717 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 718 * We handle this in ath5k_setup_bands(). 719 */ 720 #define AR5K_MAX_RATES 32 721 722 /* B */ 723 #define ATH5K_RATE_CODE_1M 0x1B 724 #define ATH5K_RATE_CODE_2M 0x1A 725 #define ATH5K_RATE_CODE_5_5M 0x19 726 #define ATH5K_RATE_CODE_11M 0x18 727 /* A and G */ 728 #define ATH5K_RATE_CODE_6M 0x0B 729 #define ATH5K_RATE_CODE_9M 0x0F 730 #define ATH5K_RATE_CODE_12M 0x0A 731 #define ATH5K_RATE_CODE_18M 0x0E 732 #define ATH5K_RATE_CODE_24M 0x09 733 #define ATH5K_RATE_CODE_36M 0x0D 734 #define ATH5K_RATE_CODE_48M 0x08 735 #define ATH5K_RATE_CODE_54M 0x0C 736 /* XR */ 737 #define ATH5K_RATE_CODE_XR_500K 0x07 738 #define ATH5K_RATE_CODE_XR_1M 0x02 739 #define ATH5K_RATE_CODE_XR_2M 0x06 740 #define ATH5K_RATE_CODE_XR_3M 0x01 741 742 /* adding this flag to rate_code enables short preamble */ 743 #define AR5K_SET_SHORT_PREAMBLE 0x04 744 745 /* 746 * Crypto definitions 747 */ 748 749 #define AR5K_KEYCACHE_SIZE 8 750 extern int ath5k_modparam_nohwcrypt; 751 752 /***********************\ 753 HW RELATED DEFINITIONS 754 \***********************/ 755 756 /* 757 * Misc definitions 758 */ 759 #define AR5K_RSSI_EP_MULTIPLIER (1 << 7) 760 761 #define AR5K_ASSERT_ENTRY(_e, _s) do { \ 762 if (_e >= _s) \ 763 return false; \ 764 } while (0) 765 766 /* 767 * Hardware interrupt abstraction 768 */ 769 770 /** 771 * enum ath5k_int - Hardware interrupt masks helpers 772 * 773 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 774 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 775 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 776 * @AR5K_INT_RXNOFRM: No frame received (?) 777 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 778 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 779 * LinkPtr is NULL. For more details, refer to: 780 * http://www.freepatentsonline.com/20030225739.html 781 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 782 * Note that Rx overrun is not always fatal, on some chips we can continue 783 * operation without resetting the card, that's why int_fatal is not 784 * common for all chips. 785 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 786 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 787 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 788 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 789 * We currently do increments on interrupt by 790 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 791 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 792 * one of the PHY error counters reached the maximum value and should be 793 * read and cleared. 794 * @AR5K_INT_RXPHY: RX PHY Error 795 * @AR5K_INT_RXKCM: RX Key cache miss 796 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 797 * beacon that must be handled in software. The alternative is if you 798 * have VEOL support, in that case you let the hardware deal with things. 799 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 800 * beacons from the AP have associated with, we should probably try to 801 * reassociate. When in IBSS mode this might mean we have not received 802 * any beacons from any local stations. Note that every station in an 803 * IBSS schedules to send beacons at the Target Beacon Transmission Time 804 * (TBTT) with a random backoff. 805 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 806 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 807 * until properly handled 808 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 809 * errors. These types of errors we can enable seem to be of type 810 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 811 * @AR5K_INT_GLOBAL: Used to clear and set the IER 812 * @AR5K_INT_NOCARD: signals the card has been removed 813 * @AR5K_INT_COMMON: common interrupts shared among MACs with the same 814 * bit value 815 * 816 * These are mapped to take advantage of some common bits 817 * between the MACs, to be able to set intr properties 818 * easier. Some of them are not used yet inside hw.c. Most map 819 * to the respective hw interrupt value as they are common among different 820 * MACs. 821 */ 822 enum ath5k_int { 823 AR5K_INT_RXOK = 0x00000001, 824 AR5K_INT_RXDESC = 0x00000002, 825 AR5K_INT_RXERR = 0x00000004, 826 AR5K_INT_RXNOFRM = 0x00000008, 827 AR5K_INT_RXEOL = 0x00000010, 828 AR5K_INT_RXORN = 0x00000020, 829 AR5K_INT_TXOK = 0x00000040, 830 AR5K_INT_TXDESC = 0x00000080, 831 AR5K_INT_TXERR = 0x00000100, 832 AR5K_INT_TXNOFRM = 0x00000200, 833 AR5K_INT_TXEOL = 0x00000400, 834 AR5K_INT_TXURN = 0x00000800, 835 AR5K_INT_MIB = 0x00001000, 836 AR5K_INT_SWI = 0x00002000, 837 AR5K_INT_RXPHY = 0x00004000, 838 AR5K_INT_RXKCM = 0x00008000, 839 AR5K_INT_SWBA = 0x00010000, 840 AR5K_INT_BRSSI = 0x00020000, 841 AR5K_INT_BMISS = 0x00040000, 842 AR5K_INT_FATAL = 0x00080000, /* Non common */ 843 AR5K_INT_BNR = 0x00100000, /* Non common */ 844 AR5K_INT_TIM = 0x00200000, /* Non common */ 845 AR5K_INT_DTIM = 0x00400000, /* Non common */ 846 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 847 AR5K_INT_GPIO = 0x01000000, 848 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 849 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 850 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 851 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 852 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 853 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 854 AR5K_INT_GLOBAL = 0x80000000, 855 856 AR5K_INT_TX_ALL = AR5K_INT_TXOK 857 | AR5K_INT_TXDESC 858 | AR5K_INT_TXERR 859 | AR5K_INT_TXEOL 860 | AR5K_INT_TXURN, 861 862 AR5K_INT_RX_ALL = AR5K_INT_RXOK 863 | AR5K_INT_RXDESC 864 | AR5K_INT_RXERR 865 | AR5K_INT_RXNOFRM 866 | AR5K_INT_RXEOL 867 | AR5K_INT_RXORN, 868 869 AR5K_INT_COMMON = AR5K_INT_RXOK 870 | AR5K_INT_RXDESC 871 | AR5K_INT_RXERR 872 | AR5K_INT_RXNOFRM 873 | AR5K_INT_RXEOL 874 | AR5K_INT_RXORN 875 | AR5K_INT_TXOK 876 | AR5K_INT_TXDESC 877 | AR5K_INT_TXERR 878 | AR5K_INT_TXNOFRM 879 | AR5K_INT_TXEOL 880 | AR5K_INT_TXURN 881 | AR5K_INT_MIB 882 | AR5K_INT_SWI 883 | AR5K_INT_RXPHY 884 | AR5K_INT_RXKCM 885 | AR5K_INT_SWBA 886 | AR5K_INT_BRSSI 887 | AR5K_INT_BMISS 888 | AR5K_INT_GPIO 889 | AR5K_INT_GLOBAL, 890 891 AR5K_INT_NOCARD = 0xffffffff 892 }; 893 894 /* mask which calibration is active at the moment */ 895 enum ath5k_calibration_mask { 896 AR5K_CALIBRATION_FULL = 0x01, 897 AR5K_CALIBRATION_SHORT = 0x02, 898 AR5K_CALIBRATION_ANI = 0x04, 899 }; 900 901 /* 902 * Power management 903 */ 904 enum ath5k_power_mode { 905 AR5K_PM_UNDEFINED = 0, 906 AR5K_PM_AUTO, 907 AR5K_PM_AWAKE, 908 AR5K_PM_FULL_SLEEP, 909 AR5K_PM_NETWORK_SLEEP, 910 }; 911 912 /* 913 * These match net80211 definitions (not used in 914 * mac80211). 915 * TODO: Clean this up 916 */ 917 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 918 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 919 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 920 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 921 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 922 923 /* GPIO-controlled software LED */ 924 #define AR5K_SOFTLED_PIN 0 925 #define AR5K_SOFTLED_ON 0 926 #define AR5K_SOFTLED_OFF 1 927 928 929 /* XXX: we *may* move cap_range stuff to struct wiphy */ 930 struct ath5k_capabilities { 931 /* 932 * Supported PHY modes 933 * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...) 934 */ 935 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 936 937 /* 938 * Frequency range (without regulation restrictions) 939 */ 940 struct { 941 u16 range_2ghz_min; 942 u16 range_2ghz_max; 943 u16 range_5ghz_min; 944 u16 range_5ghz_max; 945 } cap_range; 946 947 /* 948 * Values stored in the EEPROM (some of them...) 949 */ 950 struct ath5k_eeprom_info cap_eeprom; 951 952 /* 953 * Queue information 954 */ 955 struct { 956 u8 q_tx_num; 957 } cap_queues; 958 959 bool cap_has_phyerr_counters; 960 }; 961 962 /* size of noise floor history (keep it a power of two) */ 963 #define ATH5K_NF_CAL_HIST_MAX 8 964 struct ath5k_nfcal_hist { 965 s16 index; /* current index into nfval */ 966 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 967 }; 968 969 #define ATH5K_LED_MAX_NAME_LEN 31 970 971 /* 972 * State for LED triggers 973 */ 974 struct ath5k_led { 975 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */ 976 struct ath5k_hw *ah; /* driver state */ 977 struct led_classdev led_dev; /* led classdev */ 978 }; 979 980 /* Rfkill */ 981 struct ath5k_rfkill { 982 /* GPIO PIN for rfkill */ 983 u16 gpio; 984 /* polarity of rfkill GPIO PIN */ 985 bool polarity; 986 /* RFKILL toggle tasklet */ 987 struct tasklet_struct toggleq; 988 }; 989 990 /* statistics */ 991 struct ath5k_statistics { 992 /* antenna use */ 993 unsigned int antenna_rx[5]; /* frames count per antenna RX */ 994 unsigned int antenna_tx[5]; /* frames count per antenna TX */ 995 996 /* frame errors */ 997 unsigned int rx_all_count; /* all RX frames, including errors */ 998 unsigned int tx_all_count; /* all TX frames, including errors */ 999 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts 1000 * and the MAC headers for each packet 1001 */ 1002 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts 1003 * and the MAC headers and padding for 1004 * each packet. 1005 */ 1006 unsigned int rxerr_crc; 1007 unsigned int rxerr_phy; 1008 unsigned int rxerr_phy_code[32]; 1009 unsigned int rxerr_fifo; 1010 unsigned int rxerr_decrypt; 1011 unsigned int rxerr_mic; 1012 unsigned int rxerr_proc; 1013 unsigned int rxerr_jumbo; 1014 unsigned int txerr_retry; 1015 unsigned int txerr_fifo; 1016 unsigned int txerr_filt; 1017 1018 /* MIB counters */ 1019 unsigned int ack_fail; 1020 unsigned int rts_fail; 1021 unsigned int rts_ok; 1022 unsigned int fcs_error; 1023 unsigned int beacons; 1024 1025 unsigned int mib_intr; 1026 unsigned int rxorn_intr; 1027 unsigned int rxeol_intr; 1028 }; 1029 1030 /* 1031 * Misc defines 1032 */ 1033 1034 #define AR5K_MAX_GPIO 10 1035 #define AR5K_MAX_RF_BANKS 8 1036 1037 #if CHAN_DEBUG 1038 #define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200) 1039 #else 1040 #define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20) 1041 #endif 1042 1043 #define ATH_RXBUF 40 /* number of RX buffers */ 1044 #define ATH_TXBUF 200 /* number of TX buffers */ 1045 #define ATH_BCBUF 4 /* number of beacon buffers */ 1046 #define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */ 1047 #define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */ 1048 1049 /* Driver state associated with an instance of a device */ 1050 struct ath5k_hw { 1051 struct ath_common common; 1052 1053 struct pci_dev *pdev; 1054 struct device *dev; /* for dma mapping */ 1055 int irq; 1056 u16 devid; 1057 void __iomem *iobase; /* address of the device */ 1058 struct mutex lock; /* dev-level lock */ 1059 struct ieee80211_hw *hw; /* IEEE 802.11 common */ 1060 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 1061 struct ieee80211_channel channels[ATH_CHAN_MAX]; 1062 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 1063 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 1064 enum nl80211_iftype opmode; 1065 1066 #ifdef CONFIG_ATH5K_DEBUG 1067 struct ath5k_dbg_info debug; /* debug info */ 1068 #endif /* CONFIG_ATH5K_DEBUG */ 1069 1070 struct ath5k_buf *bufptr; /* allocated buffer ptr */ 1071 struct ath5k_desc *desc; /* TX/RX descriptors */ 1072 dma_addr_t desc_daddr; /* DMA (physical) address */ 1073 size_t desc_len; /* size of TX/RX descriptors */ 1074 1075 DECLARE_BITMAP(status, 6); 1076 #define ATH_STAT_INVALID 0 /* disable hardware accesses */ 1077 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ 1078 #define ATH_STAT_PROMISC 2 1079 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */ 1080 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */ 1081 #define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */ 1082 1083 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ 1084 struct ieee80211_channel *curchan; /* current h/w channel */ 1085 1086 u16 nvifs; 1087 1088 enum ath5k_int imask; /* interrupt mask copy */ 1089 1090 spinlock_t irqlock; 1091 bool rx_pending; /* rx tasklet pending */ 1092 bool tx_pending; /* tx tasklet pending */ 1093 1094 u8 bssidmask[ETH_ALEN]; 1095 1096 unsigned int led_pin, /* GPIO pin for driving LED */ 1097 led_on; /* pin setting for LED on */ 1098 1099 struct work_struct reset_work; /* deferred chip reset */ 1100 1101 struct list_head rxbuf; /* receive buffer */ 1102 spinlock_t rxbuflock; 1103 u32 *rxlink; /* link ptr in last RX desc */ 1104 struct tasklet_struct rxtq; /* rx intr tasklet */ 1105 struct ath5k_led rx_led; /* rx led */ 1106 1107 struct list_head txbuf; /* transmit buffer */ 1108 spinlock_t txbuflock; 1109 unsigned int txbuf_len; /* buf count in txbuf list */ 1110 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */ 1111 struct tasklet_struct txtq; /* tx intr tasklet */ 1112 struct ath5k_led tx_led; /* tx led */ 1113 1114 struct ath5k_rfkill rf_kill; 1115 1116 struct tasklet_struct calib; /* calibration tasklet */ 1117 1118 spinlock_t block; /* protects beacon */ 1119 struct tasklet_struct beacontq; /* beacon intr tasklet */ 1120 struct list_head bcbuf; /* beacon buffer */ 1121 struct ieee80211_vif *bslot[ATH_BCBUF]; 1122 u16 num_ap_vifs; 1123 u16 num_adhoc_vifs; 1124 unsigned int bhalq, /* SW q for outgoing beacons */ 1125 bmisscount, /* missed beacon transmits */ 1126 bintval, /* beacon interval in TU */ 1127 bsent; 1128 unsigned int nexttbtt; /* next beacon time in TU */ 1129 struct ath5k_txq *cabq; /* content after beacon */ 1130 1131 int power_level; /* Requested tx power in dBm */ 1132 bool assoc; /* associate state */ 1133 bool enable_beacon; /* true if beacons are on */ 1134 1135 struct ath5k_statistics stats; 1136 1137 struct ath5k_ani_state ani_state; 1138 struct tasklet_struct ani_tasklet; /* ANI calibration */ 1139 1140 struct delayed_work tx_complete_work; 1141 1142 struct survey_info survey; /* collected survey info */ 1143 1144 enum ath5k_int ah_imr; 1145 1146 struct ieee80211_channel *ah_current_channel; 1147 bool ah_calibration; 1148 bool ah_single_chip; 1149 1150 enum ath5k_version ah_version; 1151 enum ath5k_radio ah_radio; 1152 u32 ah_mac_srev; 1153 u16 ah_mac_version; 1154 u16 ah_phy_revision; 1155 u16 ah_radio_5ghz_revision; 1156 u16 ah_radio_2ghz_revision; 1157 1158 #define ah_modes ah_capabilities.cap_mode 1159 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1160 1161 u8 ah_retry_long; 1162 u8 ah_retry_short; 1163 1164 u32 ah_use_32khz_clock; 1165 1166 u8 ah_coverage_class; 1167 bool ah_ack_bitrate_high; 1168 u8 ah_bwmode; 1169 bool ah_short_slot; 1170 1171 /* Antenna Control */ 1172 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1173 u8 ah_ant_mode; 1174 u8 ah_tx_ant; 1175 u8 ah_def_ant; 1176 1177 struct ath5k_capabilities ah_capabilities; 1178 1179 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1180 u32 ah_txq_status; 1181 u32 ah_txq_imr_txok; 1182 u32 ah_txq_imr_txerr; 1183 u32 ah_txq_imr_txurn; 1184 u32 ah_txq_imr_txdesc; 1185 u32 ah_txq_imr_txeol; 1186 u32 ah_txq_imr_cbrorn; 1187 u32 ah_txq_imr_cbrurn; 1188 u32 ah_txq_imr_qtrig; 1189 u32 ah_txq_imr_nofrm; 1190 u32 ah_txq_isr; 1191 u32 *ah_rf_banks; 1192 size_t ah_rf_banks_size; 1193 size_t ah_rf_regs_count; 1194 struct ath5k_gain ah_gain; 1195 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1196 1197 1198 struct { 1199 /* Temporary tables used for interpolation */ 1200 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1201 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1202 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1203 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1204 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1205 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1206 u8 txp_min_idx; 1207 bool txp_tpc; 1208 /* Values in 0.25dB units */ 1209 s16 txp_min_pwr; 1210 s16 txp_max_pwr; 1211 s16 txp_cur_pwr; 1212 /* Values in 0.5dB units */ 1213 s16 txp_offset; 1214 s16 txp_ofdm; 1215 s16 txp_cck_ofdm_gainf_delta; 1216 /* Value in dB units */ 1217 s16 txp_cck_ofdm_pwr_delta; 1218 bool txp_setup; 1219 } ah_txpower; 1220 1221 struct ath5k_nfcal_hist ah_nfcal_hist; 1222 1223 /* average beacon RSSI in our BSS (used by ANI) */ 1224 struct ewma ah_beacon_rssi_avg; 1225 1226 /* noise floor from last periodic calibration */ 1227 s32 ah_noise_floor; 1228 1229 /* Calibration timestamp */ 1230 unsigned long ah_cal_next_full; 1231 unsigned long ah_cal_next_ani; 1232 unsigned long ah_cal_next_nf; 1233 1234 /* Calibration mask */ 1235 u8 ah_cal_mask; 1236 1237 /* 1238 * Function pointers 1239 */ 1240 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1241 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1242 unsigned int, unsigned int, unsigned int, unsigned int, 1243 unsigned int, unsigned int, unsigned int, unsigned int); 1244 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1245 struct ath5k_tx_status *); 1246 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1247 struct ath5k_rx_status *); 1248 }; 1249 1250 struct ath_bus_ops { 1251 enum ath_bus_type ath_bus_type; 1252 void (*read_cachesize)(struct ath_common *common, int *csz); 1253 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 1254 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac); 1255 }; 1256 1257 /* 1258 * Prototypes 1259 */ 1260 extern const struct ieee80211_ops ath5k_hw_ops; 1261 1262 /* Initialization and detach functions */ 1263 int ath5k_hw_init(struct ath5k_hw *ah); 1264 void ath5k_hw_deinit(struct ath5k_hw *ah); 1265 1266 int ath5k_sysfs_register(struct ath5k_hw *ah); 1267 void ath5k_sysfs_unregister(struct ath5k_hw *ah); 1268 1269 /*Chip id helper functions */ 1270 int ath5k_hw_read_srev(struct ath5k_hw *ah); 1271 1272 /* LED functions */ 1273 int ath5k_init_leds(struct ath5k_hw *ah); 1274 void ath5k_led_enable(struct ath5k_hw *ah); 1275 void ath5k_led_off(struct ath5k_hw *ah); 1276 void ath5k_unregister_leds(struct ath5k_hw *ah); 1277 1278 1279 /* Reset Functions */ 1280 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1281 int ath5k_hw_on_hold(struct ath5k_hw *ah); 1282 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1283 struct ieee80211_channel *channel, bool fast, bool skip_pcu); 1284 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1285 bool is_set); 1286 /* Power management functions */ 1287 1288 1289 /* Clock rate related functions */ 1290 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1291 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1292 void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1293 1294 1295 /* DMA Related Functions */ 1296 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1297 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1298 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1299 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1300 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1301 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1302 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1303 u32 phys_addr); 1304 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1305 /* Interrupt handling */ 1306 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1307 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1308 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1309 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1310 /* Init/Stop functions */ 1311 void ath5k_hw_dma_init(struct ath5k_hw *ah); 1312 int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1313 1314 /* EEPROM access functions */ 1315 int ath5k_eeprom_init(struct ath5k_hw *ah); 1316 void ath5k_eeprom_detach(struct ath5k_hw *ah); 1317 1318 1319 /* Protocol Control Unit Functions */ 1320 /* Helpers */ 1321 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 1322 int len, struct ieee80211_rate *rate, bool shortpre); 1323 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1324 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1325 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1326 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1327 /* RX filter control*/ 1328 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1329 void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1330 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1331 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1332 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1333 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1334 /* Receive (DRU) start/stop functions */ 1335 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1336 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1337 /* Beacon control functions */ 1338 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1339 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1340 void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1341 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1342 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1343 /* Init function */ 1344 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1345 u8 mode); 1346 1347 /* Queue Control Unit, DFS Control Unit Functions */ 1348 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1349 struct ath5k_txq_info *queue_info); 1350 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1351 const struct ath5k_txq_info *queue_info); 1352 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1353 enum ath5k_tx_queue queue_type, 1354 struct ath5k_txq_info *queue_info); 1355 void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah, 1356 unsigned int queue); 1357 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1358 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1359 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1360 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); 1361 /* Init function */ 1362 int ath5k_hw_init_queues(struct ath5k_hw *ah); 1363 1364 /* Hardware Descriptor Functions */ 1365 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1366 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1367 u32 size, unsigned int flags); 1368 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1369 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1370 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1371 1372 1373 /* GPIO Functions */ 1374 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1375 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1376 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1377 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1378 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1379 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1380 u32 interrupt_level); 1381 1382 1383 /* RFkill Functions */ 1384 void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1385 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1386 1387 1388 /* Misc functions TODO: Cleanup */ 1389 int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1390 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1391 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1392 1393 1394 /* Initial register settings functions */ 1395 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1396 1397 1398 /* PHY functions */ 1399 /* Misc PHY functions */ 1400 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band); 1401 int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1402 /* Gain_F optimization */ 1403 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1404 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1405 /* PHY/RF channel functions */ 1406 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1407 /* PHY calibration */ 1408 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1409 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1410 struct ieee80211_channel *channel); 1411 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1412 /* Spur mitigation */ 1413 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1414 struct ieee80211_channel *channel); 1415 /* Antenna control */ 1416 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1417 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1418 /* TX power setup */ 1419 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1420 /* Init function */ 1421 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1422 u8 mode, bool fast); 1423 1424 /* 1425 * Functions used internally 1426 */ 1427 1428 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1429 { 1430 return &ah->common; 1431 } 1432 1433 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1434 { 1435 return &(ath5k_hw_common(ah)->regulatory); 1436 } 1437 1438 #ifdef CONFIG_ATHEROS_AR231X 1439 #define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000) 1440 1441 static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) 1442 { 1443 /* On AR2315 and AR2317 the PCI clock domain registers 1444 * are outside of the WMAC register space */ 1445 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && 1446 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) 1447 return AR5K_AR2315_PCI_BASE + reg; 1448 1449 return ah->iobase + reg; 1450 } 1451 1452 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1453 { 1454 return __raw_readl(ath5k_ahb_reg(ah, reg)); 1455 } 1456 1457 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1458 { 1459 __raw_writel(val, ath5k_ahb_reg(ah, reg)); 1460 } 1461 1462 #else 1463 1464 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1465 { 1466 return ioread32(ah->iobase + reg); 1467 } 1468 1469 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1470 { 1471 iowrite32(val, ah->iobase + reg); 1472 } 1473 1474 #endif 1475 1476 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) 1477 { 1478 return ath5k_hw_common(ah)->bus_ops->ath_bus_type; 1479 } 1480 1481 static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) 1482 { 1483 common->bus_ops->read_cachesize(common, csz); 1484 } 1485 1486 static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) 1487 { 1488 struct ath_common *common = ath5k_hw_common(ah); 1489 return common->bus_ops->eeprom_read(common, off, data); 1490 } 1491 1492 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1493 { 1494 u32 retval = 0, bit, i; 1495 1496 for (i = 0; i < bits; i++) { 1497 bit = (val >> i) & 1; 1498 retval = (retval << 1) | bit; 1499 } 1500 1501 return retval; 1502 } 1503 1504 #endif 1505