1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_WMI_H 8 #define ATH12K_WMI_H 9 10 #include <net/mac80211.h> 11 #include "htc.h" 12 13 /* Naming conventions for structures: 14 * 15 * _cmd means that this is a firmware command sent from host to firmware. 16 * 17 * _event means that this is a firmware event sent from firmware to host 18 * 19 * _params is a structure which is embedded either into _cmd or _event (or 20 * both), it is not sent individually. 21 * 22 * _arg is used inside the host, the firmware does not see that at all. 23 */ 24 25 struct ath12k_base; 26 struct ath12k; 27 struct ath12k_link_vif; 28 struct ath12k_fw_stats; 29 struct ath12k_reg_tpc_power_info; 30 31 /* There is no signed version of __le32, so for a temporary solution come 32 * up with our own version. The idea is from fs/ntfs/endian.h. 33 * 34 * Use a_ prefix so that it doesn't conflict if we get proper support to 35 * linux/types.h. 36 */ 37 typedef __s32 __bitwise a_sle32; 38 39 static inline a_sle32 a_cpu_to_sle32(s32 val) 40 { 41 return (__force a_sle32)cpu_to_le32(val); 42 } 43 44 static inline s32 a_sle32_to_cpu(a_sle32 val) 45 { 46 return le32_to_cpu((__force __le32)val); 47 } 48 49 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 50 #define MAX_HE_NSS 8 51 #define MAX_HE_MODULATION 8 52 #define MAX_HE_RU 4 53 #define HE_MODULATION_NONE 7 54 #define HE_PET_0_USEC 0 55 #define HE_PET_8_USEC 1 56 #define HE_PET_16_USEC 2 57 58 #define WMI_MAX_CHAINS 8 59 60 #define WMI_MAX_NUM_SS MAX_HE_NSS 61 #define WMI_MAX_NUM_RU MAX_HE_RU 62 63 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 64 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 65 #define WMI_TLV_CMD_UNSUPPORTED 0 66 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 67 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 68 69 struct wmi_cmd_hdr { 70 __le32 cmd_id; 71 } __packed; 72 73 struct wmi_tlv { 74 __le32 header; 75 u8 value[]; 76 } __packed; 77 78 #define WMI_TLV_LEN GENMASK(15, 0) 79 #define WMI_TLV_TAG GENMASK(31, 16) 80 #define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header) 81 82 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 83 #define WMI_MAX_MEM_REQS 32 84 #define ATH12K_MAX_HW_LISTEN_INTERVAL 5 85 86 #define WMI_HOST_RC_DS_FLAG 0x01 87 #define WMI_HOST_RC_CW40_FLAG 0x02 88 #define WMI_HOST_RC_SGI_FLAG 0x04 89 #define WMI_HOST_RC_HT_FLAG 0x08 90 #define WMI_HOST_RC_RTSCTS_FLAG 0x10 91 #define WMI_HOST_RC_TX_STBC_FLAG 0x20 92 #define WMI_HOST_RC_RX_STBC_FLAG 0xC0 93 #define WMI_HOST_RC_RX_STBC_FLAG_S 6 94 #define WMI_HOST_RC_WEP_TKIP_FLAG 0x100 95 #define WMI_HOST_RC_TS_FLAG 0x200 96 #define WMI_HOST_RC_UAPSD_FLAG 0x400 97 98 #define WMI_HT_CAP_ENABLED 0x0001 99 #define WMI_HT_CAP_HT20_SGI 0x0002 100 #define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 101 #define WMI_HT_CAP_TX_STBC 0x0008 102 #define WMI_HT_CAP_TX_STBC_MASK_SHIFT 3 103 #define WMI_HT_CAP_RX_STBC 0x0030 104 #define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4 105 #define WMI_HT_CAP_LDPC 0x0040 106 #define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 107 #define WMI_HT_CAP_MPDU_DENSITY 0x0700 108 #define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT 8 109 #define WMI_HT_CAP_HT40_SGI 0x0800 110 #define WMI_HT_CAP_RX_LDPC 0x1000 111 #define WMI_HT_CAP_TX_LDPC 0x2000 112 #define WMI_HT_CAP_IBF_BFER 0x4000 113 114 /* These macros should be used when we wish to advertise STBC support for 115 * only 1SS or 2SS or 3SS. 116 */ 117 #define WMI_HT_CAP_RX_STBC_1SS 0x0010 118 #define WMI_HT_CAP_RX_STBC_2SS 0x0020 119 #define WMI_HT_CAP_RX_STBC_3SS 0x0030 120 121 #define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED | \ 122 WMI_HT_CAP_HT20_SGI | \ 123 WMI_HT_CAP_HT40_SGI | \ 124 WMI_HT_CAP_TX_STBC | \ 125 WMI_HT_CAP_RX_STBC | \ 126 WMI_HT_CAP_LDPC) 127 128 #define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003 129 #define WMI_VHT_CAP_RX_LDPC 0x00000010 130 #define WMI_VHT_CAP_SGI_80MHZ 0x00000020 131 #define WMI_VHT_CAP_SGI_160MHZ 0x00000040 132 #define WMI_VHT_CAP_TX_STBC 0x00000080 133 #define WMI_VHT_CAP_RX_STBC_MASK 0x00000300 134 #define WMI_VHT_CAP_RX_STBC_MASK_SHIFT 8 135 #define WMI_VHT_CAP_SU_BFER 0x00000800 136 #define WMI_VHT_CAP_SU_BFEE 0x00001000 137 #define WMI_VHT_CAP_MAX_CS_ANT_MASK 0x0000E000 138 #define WMI_VHT_CAP_MAX_CS_ANT_MASK_SHIFT 13 139 #define WMI_VHT_CAP_MAX_SND_DIM_MASK 0x00070000 140 #define WMI_VHT_CAP_MAX_SND_DIM_MASK_SHIFT 16 141 #define WMI_VHT_CAP_MU_BFER 0x00080000 142 #define WMI_VHT_CAP_MU_BFEE 0x00100000 143 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000 144 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIT 23 145 #define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000 146 #define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000 147 148 #define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002 149 150 /* These macros should be used when we wish to advertise STBC support for 151 * only 1SS or 2SS or 3SS. 152 */ 153 #define WMI_VHT_CAP_RX_STBC_1SS 0x00000100 154 #define WMI_VHT_CAP_RX_STBC_2SS 0x00000200 155 #define WMI_VHT_CAP_RX_STBC_3SS 0x00000300 156 157 #define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \ 158 WMI_VHT_CAP_SGI_80MHZ | \ 159 WMI_VHT_CAP_TX_STBC | \ 160 WMI_VHT_CAP_RX_STBC_MASK | \ 161 WMI_VHT_CAP_RX_LDPC | \ 162 WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \ 163 WMI_VHT_CAP_RX_FIXED_ANT | \ 164 WMI_VHT_CAP_TX_FIXED_ANT) 165 166 #define WLAN_SCAN_MAX_HINT_S_SSID 10 167 #define WLAN_SCAN_MAX_HINT_BSSID 10 168 #define MAX_RNR_BSS 5 169 170 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 171 172 #define WMI_BA_MODE_BUFFER_SIZE_256 3 173 174 /* HW mode config type replicated from FW header 175 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 176 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 177 * one in 2G and another in 5G. 178 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 179 * same band; no tx allowed. 180 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 181 * Support for both PHYs within one band is planned 182 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 183 * but could be extended to other bands in the future. 184 * The separation of the band between the two PHYs needs 185 * to be communicated separately. 186 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 187 * as in WMI_HW_MODE_SBS, and 3rd on the other band 188 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 189 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 190 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 191 */ 192 enum wmi_host_hw_mode_config_type { 193 WMI_HOST_HW_MODE_SINGLE = 0, 194 WMI_HOST_HW_MODE_DBS = 1, 195 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 196 WMI_HOST_HW_MODE_SBS = 3, 197 WMI_HOST_HW_MODE_DBS_SBS = 4, 198 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 199 200 /* keep last */ 201 WMI_HOST_HW_MODE_MAX 202 }; 203 204 /* HW mode priority values used to detect the preferred HW mode 205 * on the available modes. 206 */ 207 enum wmi_host_hw_mode_priority { 208 WMI_HOST_HW_MODE_DBS_SBS_PRI, 209 WMI_HOST_HW_MODE_DBS_PRI, 210 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 211 WMI_HOST_HW_MODE_SBS_PRI, 212 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 213 WMI_HOST_HW_MODE_SINGLE_PRI, 214 215 /* keep last the lowest priority */ 216 WMI_HOST_HW_MODE_MAX_PRI 217 }; 218 219 enum WMI_HOST_WLAN_BAND { 220 WMI_HOST_WLAN_2GHZ_CAP = 1, 221 WMI_HOST_WLAN_5GHZ_CAP = 2, 222 WMI_HOST_WLAN_2GHZ_5GHZ_CAP = 3, 223 }; 224 225 enum wmi_cmd_group { 226 /* 0 to 2 are reserved */ 227 WMI_GRP_START = 0x3, 228 WMI_GRP_SCAN = WMI_GRP_START, 229 WMI_GRP_PDEV = 0x4, 230 WMI_GRP_VDEV = 0x5, 231 WMI_GRP_PEER = 0x6, 232 WMI_GRP_MGMT = 0x7, 233 WMI_GRP_BA_NEG = 0x8, 234 WMI_GRP_STA_PS = 0x9, 235 WMI_GRP_DFS = 0xa, 236 WMI_GRP_ROAM = 0xb, 237 WMI_GRP_OFL_SCAN = 0xc, 238 WMI_GRP_P2P = 0xd, 239 WMI_GRP_AP_PS = 0xe, 240 WMI_GRP_RATE_CTRL = 0xf, 241 WMI_GRP_PROFILE = 0x10, 242 WMI_GRP_SUSPEND = 0x11, 243 WMI_GRP_BCN_FILTER = 0x12, 244 WMI_GRP_WOW = 0x13, 245 WMI_GRP_RTT = 0x14, 246 WMI_GRP_SPECTRAL = 0x15, 247 WMI_GRP_STATS = 0x16, 248 WMI_GRP_ARP_NS_OFL = 0x17, 249 WMI_GRP_NLO_OFL = 0x18, 250 WMI_GRP_GTK_OFL = 0x19, 251 WMI_GRP_CSA_OFL = 0x1a, 252 WMI_GRP_CHATTER = 0x1b, 253 WMI_GRP_TID_ADDBA = 0x1c, 254 WMI_GRP_MISC = 0x1d, 255 WMI_GRP_GPIO = 0x1e, 256 WMI_GRP_FWTEST = 0x1f, 257 WMI_GRP_TDLS = 0x20, 258 WMI_GRP_RESMGR = 0x21, 259 WMI_GRP_STA_SMPS = 0x22, 260 WMI_GRP_WLAN_HB = 0x23, 261 WMI_GRP_RMC = 0x24, 262 WMI_GRP_MHF_OFL = 0x25, 263 WMI_GRP_LOCATION_SCAN = 0x26, 264 WMI_GRP_OEM = 0x27, 265 WMI_GRP_NAN = 0x28, 266 WMI_GRP_COEX = 0x29, 267 WMI_GRP_OBSS_OFL = 0x2a, 268 WMI_GRP_LPI = 0x2b, 269 WMI_GRP_EXTSCAN = 0x2c, 270 WMI_GRP_DHCP_OFL = 0x2d, 271 WMI_GRP_IPA = 0x2e, 272 WMI_GRP_MDNS_OFL = 0x2f, 273 WMI_GRP_SAP_OFL = 0x30, 274 WMI_GRP_OCB = 0x31, 275 WMI_GRP_SOC = 0x32, 276 WMI_GRP_PKT_FILTER = 0x33, 277 WMI_GRP_MAWC = 0x34, 278 WMI_GRP_PMF_OFFLOAD = 0x35, 279 WMI_GRP_BPF_OFFLOAD = 0x36, 280 WMI_GRP_NAN_DATA = 0x37, 281 WMI_GRP_PROTOTYPE = 0x38, 282 WMI_GRP_MONITOR = 0x39, 283 WMI_GRP_REGULATORY = 0x3a, 284 WMI_GRP_HW_DATA_FILTER = 0x3b, 285 WMI_GRP_WLM = 0x3c, 286 WMI_GRP_11K_OFFLOAD = 0x3d, 287 WMI_GRP_TWT = 0x3e, 288 WMI_GRP_MOTION_DET = 0x3f, 289 WMI_GRP_SPATIAL_REUSE = 0x40, 290 WMI_GRP_MLO = 0x48, 291 }; 292 293 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 294 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 295 296 enum wmi_tlv_cmd_id { 297 WMI_CMD_UNSUPPORTED = 0, 298 WMI_INIT_CMDID = 0x1, 299 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 300 WMI_STOP_SCAN_CMDID, 301 WMI_SCAN_CHAN_LIST_CMDID, 302 WMI_SCAN_SCH_PRIO_TBL_CMDID, 303 WMI_SCAN_UPDATE_REQUEST_CMDID, 304 WMI_SCAN_PROB_REQ_OUI_CMDID, 305 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 306 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 307 WMI_PDEV_SET_CHANNEL_CMDID, 308 WMI_PDEV_SET_PARAM_CMDID, 309 WMI_PDEV_PKTLOG_ENABLE_CMDID, 310 WMI_PDEV_PKTLOG_DISABLE_CMDID, 311 WMI_PDEV_SET_WMM_PARAMS_CMDID, 312 WMI_PDEV_SET_HT_CAP_IE_CMDID, 313 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 314 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 315 WMI_PDEV_SET_QUIET_MODE_CMDID, 316 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 317 WMI_PDEV_GET_TPC_CONFIG_CMDID, 318 WMI_PDEV_SET_BASE_MACADDR_CMDID, 319 WMI_PDEV_DUMP_CMDID, 320 WMI_PDEV_SET_LED_CONFIG_CMDID, 321 WMI_PDEV_GET_TEMPERATURE_CMDID, 322 WMI_PDEV_SET_LED_FLASHING_CMDID, 323 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 324 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 325 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 326 WMI_PDEV_SET_CTL_TABLE_CMDID, 327 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 328 WMI_PDEV_FIPS_CMDID, 329 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 330 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 331 WMI_PDEV_GET_NFCAL_POWER_CMDID, 332 WMI_PDEV_GET_TPC_CMDID, 333 WMI_MIB_STATS_ENABLE_CMDID, 334 WMI_PDEV_SET_PCL_CMDID, 335 WMI_PDEV_SET_HW_MODE_CMDID, 336 WMI_PDEV_SET_MAC_CONFIG_CMDID, 337 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 338 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 339 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 340 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 341 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 342 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 343 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 344 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 345 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 346 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 347 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 348 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 349 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 350 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 351 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 352 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 353 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 354 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 355 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 356 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 357 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 358 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 359 WMI_PDEV_PKTLOG_FILTER_CMDID, 360 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID = 0x4044, 361 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID = 0x4045, 362 WMI_PDEV_SET_BIOS_INTERFACE_CMDID = 0x404A, 363 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 364 WMI_VDEV_DELETE_CMDID, 365 WMI_VDEV_START_REQUEST_CMDID, 366 WMI_VDEV_RESTART_REQUEST_CMDID, 367 WMI_VDEV_UP_CMDID, 368 WMI_VDEV_STOP_CMDID, 369 WMI_VDEV_DOWN_CMDID, 370 WMI_VDEV_SET_PARAM_CMDID, 371 WMI_VDEV_INSTALL_KEY_CMDID, 372 WMI_VDEV_WNM_SLEEPMODE_CMDID, 373 WMI_VDEV_WMM_ADDTS_CMDID, 374 WMI_VDEV_WMM_DELTS_CMDID, 375 WMI_VDEV_SET_WMM_PARAMS_CMDID, 376 WMI_VDEV_SET_GTX_PARAMS_CMDID, 377 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 378 WMI_VDEV_PLMREQ_START_CMDID, 379 WMI_VDEV_PLMREQ_STOP_CMDID, 380 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 381 WMI_VDEV_SET_IE_CMDID, 382 WMI_VDEV_RATEMASK_CMDID, 383 WMI_VDEV_ATF_REQUEST_CMDID, 384 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 385 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 386 WMI_VDEV_SET_QUIET_MODE_CMDID, 387 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 388 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 389 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 390 WMI_VDEV_SET_ARP_STAT_CMDID, 391 WMI_VDEV_GET_ARP_STAT_CMDID, 392 WMI_VDEV_GET_TX_POWER_CMDID, 393 WMI_VDEV_LIMIT_OFFCHAN_CMDID, 394 WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID, 395 WMI_VDEV_CHAINMASK_CONFIG_CMDID, 396 WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID, 397 WMI_VDEV_GET_MWS_COEX_INFO_CMDID, 398 WMI_VDEV_DELETE_ALL_PEER_CMDID, 399 WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID, 400 WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID, 401 WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID, 402 WMI_VDEV_SET_PCL_CMDID, 403 WMI_VDEV_GET_BIG_DATA_CMDID, 404 WMI_VDEV_GET_BIG_DATA_P2_CMDID, 405 WMI_VDEV_SET_TPC_POWER_CMDID, 406 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 407 WMI_PEER_DELETE_CMDID, 408 WMI_PEER_FLUSH_TIDS_CMDID, 409 WMI_PEER_SET_PARAM_CMDID, 410 WMI_PEER_ASSOC_CMDID, 411 WMI_PEER_ADD_WDS_ENTRY_CMDID, 412 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 413 WMI_PEER_MCAST_GROUP_CMDID, 414 WMI_PEER_INFO_REQ_CMDID, 415 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 416 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 417 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 418 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 419 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 420 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 421 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 422 WMI_PEER_ATF_REQUEST_CMDID, 423 WMI_PEER_BWF_REQUEST_CMDID, 424 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 425 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 426 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 427 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 428 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 429 WMI_PDEV_SEND_BCN_CMDID, 430 WMI_BCN_TMPL_CMDID, 431 WMI_BCN_FILTER_RX_CMDID, 432 WMI_PRB_REQ_FILTER_RX_CMDID, 433 WMI_MGMT_TX_CMDID, 434 WMI_PRB_TMPL_CMDID, 435 WMI_MGMT_TX_SEND_CMDID, 436 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 437 WMI_PDEV_SEND_FD_CMDID, 438 WMI_BCN_OFFLOAD_CTRL_CMDID, 439 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 440 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 441 WMI_FILS_DISCOVERY_TMPL_CMDID, 442 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 443 WMI_ADDBA_SEND_CMDID, 444 WMI_ADDBA_STATUS_CMDID, 445 WMI_DELBA_SEND_CMDID, 446 WMI_ADDBA_SET_RESP_CMDID, 447 WMI_SEND_SINGLEAMSDU_CMDID, 448 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 449 WMI_STA_POWERSAVE_PARAM_CMDID, 450 WMI_STA_MIMO_PS_MODE_CMDID, 451 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 452 WMI_PDEV_DFS_DISABLE_CMDID, 453 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 454 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 455 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 456 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 457 WMI_VDEV_ADFS_CH_CFG_CMDID, 458 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 459 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 460 WMI_ROAM_SCAN_RSSI_THRESHOLD, 461 WMI_ROAM_SCAN_PERIOD, 462 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 463 WMI_ROAM_AP_PROFILE, 464 WMI_ROAM_CHAN_LIST, 465 WMI_ROAM_SCAN_CMD, 466 WMI_ROAM_SYNCH_COMPLETE, 467 WMI_ROAM_SET_RIC_REQUEST_CMDID, 468 WMI_ROAM_INVOKE_CMDID, 469 WMI_ROAM_FILTER_CMDID, 470 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 471 WMI_ROAM_CONFIGURE_MAWC_CMDID, 472 WMI_ROAM_SET_MBO_PARAM_CMDID, 473 WMI_ROAM_PER_CONFIG_CMDID, 474 WMI_ROAM_BTM_CONFIG_CMDID, 475 WMI_ENABLE_FILS_CMDID, 476 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 477 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 478 WMI_OFL_SCAN_PERIOD, 479 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 480 WMI_P2P_DEV_SET_DISCOVERABILITY, 481 WMI_P2P_GO_SET_BEACON_IE, 482 WMI_P2P_GO_SET_PROBE_RESP_IE, 483 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 484 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 485 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 486 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 487 WMI_P2P_SET_OPPPS_PARAM_CMDID, 488 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 489 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 490 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 491 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 492 WMI_AP_PS_EGAP_PARAM_CMDID, 493 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 494 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 495 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 496 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 497 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 498 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 499 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 500 WMI_PDEV_RESUME_CMDID, 501 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 502 WMI_RMV_BCN_FILTER_CMDID, 503 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 504 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 505 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 506 WMI_WOW_ENABLE_CMDID, 507 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 508 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 509 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 510 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 511 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 512 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 513 WMI_EXTWOW_ENABLE_CMDID, 514 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 515 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 516 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 517 WMI_WOW_UDP_SVC_OFLD_CMDID, 518 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 519 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 520 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 521 WMI_RTT_TSF_CMDID, 522 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 523 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 524 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 525 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 526 WMI_REQUEST_STATS_EXT_CMDID, 527 WMI_REQUEST_LINK_STATS_CMDID, 528 WMI_START_LINK_STATS_CMDID, 529 WMI_CLEAR_LINK_STATS_CMDID, 530 WMI_GET_FW_MEM_DUMP_CMDID, 531 WMI_DEBUG_MESG_FLUSH_CMDID, 532 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 533 WMI_REQUEST_WLAN_STATS_CMDID, 534 WMI_REQUEST_RCPI_CMDID, 535 WMI_REQUEST_PEER_STATS_INFO_CMDID, 536 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 537 WMI_REQUEST_WLM_STATS_CMDID, 538 WMI_REQUEST_CTRL_PATH_STATS_CMDID, 539 WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID = WMI_REQUEST_CTRL_PATH_STATS_CMDID + 3, 540 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 541 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 542 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 543 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 544 WMI_APFIND_CMDID, 545 WMI_PASSPOINT_LIST_CONFIG_CMDID, 546 WMI_NLO_CONFIGURE_MAWC_CMDID, 547 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 548 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 549 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 550 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 551 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 552 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 553 WMI_CHATTER_COALESCING_QUERY_CMDID, 554 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 555 WMI_PEER_TID_DELBA_CMDID, 556 WMI_STA_DTIM_PS_METHOD_CMDID, 557 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 558 WMI_STA_KEEPALIVE_CMDID, 559 WMI_BA_REQ_SSN_CMDID, 560 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 561 WMI_PDEV_UTF_CMDID, 562 WMI_DBGLOG_CFG_CMDID, 563 WMI_PDEV_QVIT_CMDID, 564 WMI_PDEV_FTM_INTG_CMDID, 565 WMI_VDEV_SET_KEEPALIVE_CMDID, 566 WMI_VDEV_GET_KEEPALIVE_CMDID, 567 WMI_FORCE_FW_HANG_CMDID, 568 WMI_SET_MCASTBCAST_FILTER_CMDID, 569 WMI_THERMAL_MGMT_CMDID, 570 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 571 WMI_TPC_CHAINMASK_CONFIG_CMDID, 572 WMI_SET_ANTENNA_DIVERSITY_CMDID, 573 WMI_OCB_SET_SCHED_CMDID, 574 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 575 WMI_LRO_CONFIG_CMDID, 576 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 577 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 578 WMI_VDEV_WISA_CMDID, 579 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 580 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 581 WMI_READ_DATA_FROM_FLASH_CMDID, 582 WMI_THERM_THROT_SET_CONF_CMDID, 583 WMI_RUNTIME_DPD_RECAL_CMDID, 584 WMI_GET_TPC_POWER_CMDID, 585 WMI_IDLE_TRIGGER_MONITOR_CMDID, 586 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 587 WMI_GPIO_OUTPUT_CMDID, 588 WMI_TXBF_CMDID, 589 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 590 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 591 WMI_UNIT_TEST_CMDID, 592 WMI_FWTEST_CMDID, 593 WMI_QBOOST_CFG_CMDID, 594 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 595 WMI_TDLS_PEER_UPDATE_CMDID, 596 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 597 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 598 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 599 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 600 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 601 WMI_STA_SMPS_PARAM_CMDID, 602 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 603 WMI_HB_SET_TCP_PARAMS_CMDID, 604 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 605 WMI_HB_SET_UDP_PARAMS_CMDID, 606 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 607 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 608 WMI_RMC_SET_ACTION_PERIOD_CMDID, 609 WMI_RMC_CONFIG_CMDID, 610 WMI_RMC_SET_MANUAL_LEADER_CMDID, 611 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 612 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 613 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 614 WMI_BATCH_SCAN_DISABLE_CMDID, 615 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 616 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 617 WMI_OEM_REQUEST_CMDID, 618 WMI_LPI_OEM_REQ_CMDID, 619 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 620 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 621 WMI_CHAN_AVOID_UPDATE_CMDID, 622 WMI_COEX_CONFIG_CMDID, 623 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 624 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 625 WMI_SAR_LIMITS_CMDID, 626 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 627 WMI_OBSS_SCAN_DISABLE_CMDID, 628 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 629 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 630 WMI_LPI_START_SCAN_CMDID, 631 WMI_LPI_STOP_SCAN_CMDID, 632 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 633 WMI_EXTSCAN_STOP_CMDID, 634 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 635 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 636 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 637 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 638 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 639 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 640 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 641 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 642 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 643 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 644 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 645 WMI_MDNS_SET_FQDN_CMDID, 646 WMI_MDNS_SET_RESPONSE_CMDID, 647 WMI_MDNS_GET_STATS_CMDID, 648 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 649 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 650 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 651 WMI_OCB_SET_UTC_TIME_CMDID, 652 WMI_OCB_START_TIMING_ADVERT_CMDID, 653 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 654 WMI_OCB_GET_TSF_TIMER_CMDID, 655 WMI_DCC_GET_STATS_CMDID, 656 WMI_DCC_CLEAR_STATS_CMDID, 657 WMI_DCC_UPDATE_NDL_CMDID, 658 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 659 WMI_SOC_SET_HW_MODE_CMDID, 660 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 661 WMI_SOC_SET_ANTENNA_MODE_CMDID, 662 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 663 WMI_PACKET_FILTER_ENABLE_CMDID, 664 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 665 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 666 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 667 WMI_BPF_GET_VDEV_STATS_CMDID, 668 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 669 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 670 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 671 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 672 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 673 WMI_11D_SCAN_START_CMDID, 674 WMI_11D_SCAN_STOP_CMDID, 675 WMI_SET_INIT_COUNTRY_CMDID, 676 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 677 WMI_NDP_INITIATOR_REQ_CMDID, 678 WMI_NDP_RESPONDER_REQ_CMDID, 679 WMI_NDP_END_REQ_CMDID, 680 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 681 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 682 WMI_TWT_DISABLE_CMDID, 683 WMI_TWT_ADD_DIALOG_CMDID, 684 WMI_TWT_DEL_DIALOG_CMDID, 685 WMI_TWT_PAUSE_DIALOG_CMDID, 686 WMI_TWT_RESUME_DIALOG_CMDID, 687 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 688 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 689 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 690 WMI_MLO_LINK_SET_ACTIVE_CMDID = WMI_TLV_CMD(WMI_GRP_MLO), 691 WMI_MLO_SETUP_CMDID, 692 WMI_MLO_READY_CMDID, 693 WMI_MLO_TEARDOWN_CMDID, 694 }; 695 696 enum wmi_tlv_event_id { 697 WMI_SERVICE_READY_EVENTID = 0x1, 698 WMI_READY_EVENTID, 699 WMI_SERVICE_AVAILABLE_EVENTID, 700 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 701 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 702 WMI_CHAN_INFO_EVENTID, 703 WMI_PHYERR_EVENTID, 704 WMI_PDEV_DUMP_EVENTID, 705 WMI_TX_PAUSE_EVENTID, 706 WMI_DFS_RADAR_EVENTID, 707 WMI_PDEV_L1SS_TRACK_EVENTID, 708 WMI_PDEV_TEMPERATURE_EVENTID, 709 WMI_SERVICE_READY_EXT_EVENTID, 710 WMI_PDEV_FIPS_EVENTID, 711 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 712 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 713 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 714 WMI_PDEV_TPC_EVENTID, 715 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 716 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 717 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 718 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 719 WMI_PDEV_ANTDIV_STATUS_EVENTID, 720 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 721 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 722 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 723 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 724 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 725 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 726 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 727 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 728 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 729 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 730 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 731 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 732 WMI_PDEV_RAP_INFO_EVENTID, 733 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 734 WMI_SERVICE_READY_EXT2_EVENTID, 735 WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID = 736 WMI_SERVICE_READY_EXT2_EVENTID + 4, 737 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 738 WMI_VDEV_STOPPED_EVENTID, 739 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 740 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 741 WMI_VDEV_TSF_REPORT_EVENTID, 742 WMI_VDEV_DELETE_RESP_EVENTID, 743 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 744 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 745 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 746 WMI_PEER_INFO_EVENTID, 747 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 748 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 749 WMI_PEER_STATE_EVENTID, 750 WMI_PEER_ASSOC_CONF_EVENTID, 751 WMI_PEER_DELETE_RESP_EVENTID, 752 WMI_PEER_RATECODE_LIST_EVENTID, 753 WMI_WDS_PEER_EVENTID, 754 WMI_PEER_STA_PS_STATECHG_EVENTID, 755 WMI_PEER_ANTDIV_INFO_EVENTID, 756 WMI_PEER_RESERVED0_EVENTID, 757 WMI_PEER_RESERVED1_EVENTID, 758 WMI_PEER_RESERVED2_EVENTID, 759 WMI_PEER_RESERVED3_EVENTID, 760 WMI_PEER_RESERVED4_EVENTID, 761 WMI_PEER_RESERVED5_EVENTID, 762 WMI_PEER_RESERVED6_EVENTID, 763 WMI_PEER_RESERVED7_EVENTID, 764 WMI_PEER_RESERVED8_EVENTID, 765 WMI_PEER_RESERVED9_EVENTID, 766 WMI_PEER_RESERVED10_EVENTID, 767 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 768 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 769 WMI_HOST_SWBA_EVENTID, 770 WMI_TBTTOFFSET_UPDATE_EVENTID, 771 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 772 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 773 WMI_MGMT_TX_COMPLETION_EVENTID, 774 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 775 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 776 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 777 WMI_HOST_FILS_DISCOVERY_EVENTID, 778 WMI_MGMT_RX_FW_CONSUMED_EVENTID = WMI_HOST_FILS_DISCOVERY_EVENTID + 3, 779 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 780 WMI_TX_ADDBA_COMPLETE_EVENTID, 781 WMI_BA_RSP_SSN_EVENTID, 782 WMI_AGGR_STATE_TRIG_EVENTID, 783 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 784 WMI_PROFILE_MATCH, 785 WMI_ROAM_SYNCH_EVENTID, 786 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 787 WMI_P2P_NOA_EVENTID, 788 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 789 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 790 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 791 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 792 WMI_D0_WOW_DISABLE_ACK_EVENTID, 793 WMI_WOW_INITIAL_WAKEUP_EVENTID, 794 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 795 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 796 WMI_RTT_ERROR_REPORT_EVENTID, 797 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 798 WMI_IFACE_LINK_STATS_EVENTID, 799 WMI_PEER_LINK_STATS_EVENTID, 800 WMI_RADIO_LINK_STATS_EVENTID, 801 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 802 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 803 WMI_INST_RSSI_STATS_EVENTID, 804 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 805 WMI_REPORT_STATS_EVENTID, 806 WMI_UPDATE_RCPI_EVENTID, 807 WMI_PEER_STATS_INFO_EVENTID, 808 WMI_RADIO_CHAN_STATS_EVENTID, 809 WMI_WLM_STATS_EVENTID, 810 WMI_CTRL_PATH_STATS_EVENTID, 811 WMI_HALPHY_STATS_CTRL_PATH_EVENTID, 812 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 813 WMI_NLO_SCAN_COMPLETE_EVENTID, 814 WMI_APFIND_EVENTID, 815 WMI_PASSPOINT_MATCH_EVENTID, 816 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 817 WMI_GTK_REKEY_FAIL_EVENTID, 818 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 819 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 820 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 821 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 822 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 823 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 824 WMI_PDEV_UTF_EVENTID, 825 WMI_DEBUG_MESG_EVENTID, 826 WMI_UPDATE_STATS_EVENTID, 827 WMI_DEBUG_PRINT_EVENTID, 828 WMI_DCS_INTERFERENCE_EVENTID, 829 WMI_PDEV_QVIT_EVENTID, 830 WMI_WLAN_PROFILE_DATA_EVENTID, 831 WMI_PDEV_FTM_INTG_EVENTID, 832 WMI_WLAN_FREQ_AVOID_EVENTID, 833 WMI_VDEV_GET_KEEPALIVE_EVENTID, 834 WMI_THERMAL_MGMT_EVENTID, 835 WMI_DIAG_DATA_CONTAINER_EVENTID, 836 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 837 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 838 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 839 WMI_DIAG_EVENTID, 840 WMI_OCB_SET_SCHED_EVENTID, 841 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 842 WMI_RSSI_BREACH_EVENTID, 843 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 844 WMI_PDEV_UTF_SCPC_EVENTID, 845 WMI_READ_DATA_FROM_FLASH_EVENTID, 846 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 847 WMI_PKGID_EVENTID, 848 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 849 WMI_UPLOADH_EVENTID, 850 WMI_CAPTUREH_EVENTID, 851 WMI_RFKILL_STATE_CHANGE_EVENTID, 852 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 853 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 854 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 855 WMI_BATCH_SCAN_RESULT_EVENTID, 856 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 857 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 858 WMI_OEM_ERROR_REPORT_EVENTID, 859 WMI_OEM_RESPONSE_EVENTID, 860 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 861 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 862 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 863 WMI_NAN_STARTED_CLUSTER_EVENTID, 864 WMI_NAN_JOINED_CLUSTER_EVENTID, 865 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 866 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 867 WMI_LPI_STATUS_EVENTID, 868 WMI_LPI_HANDOFF_EVENTID, 869 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 870 WMI_EXTSCAN_OPERATION_EVENTID, 871 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 872 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 873 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 874 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 875 WMI_EXTSCAN_CAPABILITIES_EVENTID, 876 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 877 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 878 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 879 WMI_SAP_OFL_DEL_STA_EVENTID, 880 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 881 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 882 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 883 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 884 WMI_DCC_GET_STATS_RESP_EVENTID, 885 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 886 WMI_DCC_STATS_EVENTID, 887 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 888 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 889 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 890 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 891 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 892 WMI_BPF_VDEV_STATS_INFO_EVENTID, 893 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 894 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 895 WMI_11D_NEW_COUNTRY_EVENTID, 896 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 897 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 898 WMI_NDP_INITIATOR_RSP_EVENTID, 899 WMI_NDP_RESPONDER_RSP_EVENTID, 900 WMI_NDP_END_RSP_EVENTID, 901 WMI_NDP_INDICATION_EVENTID, 902 WMI_NDP_CONFIRM_EVENTID, 903 WMI_NDP_END_INDICATION_EVENTID, 904 905 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 906 WMI_TWT_DISABLE_EVENTID, 907 WMI_TWT_ADD_DIALOG_EVENTID, 908 WMI_TWT_DEL_DIALOG_EVENTID, 909 WMI_TWT_PAUSE_DIALOG_EVENTID, 910 WMI_TWT_RESUME_DIALOG_EVENTID, 911 WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MLO), 912 WMI_MLO_SETUP_COMPLETE_EVENTID, 913 WMI_MLO_TEARDOWN_COMPLETE_EVENTID, 914 }; 915 916 enum wmi_tlv_pdev_param { 917 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 918 WMI_PDEV_PARAM_RX_CHAIN_MASK, 919 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 920 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 921 WMI_PDEV_PARAM_TXPOWER_SCALE, 922 WMI_PDEV_PARAM_BEACON_GEN_MODE, 923 WMI_PDEV_PARAM_BEACON_TX_MODE, 924 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 925 WMI_PDEV_PARAM_PROTECTION_MODE, 926 WMI_PDEV_PARAM_DYNAMIC_BW, 927 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 928 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 929 WMI_PDEV_PARAM_STA_KICKOUT_TH, 930 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 931 WMI_PDEV_PARAM_LTR_ENABLE, 932 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 933 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 934 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 935 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 936 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 937 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 938 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 939 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 940 WMI_PDEV_PARAM_L1SS_ENABLE, 941 WMI_PDEV_PARAM_DSLEEP_ENABLE, 942 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 943 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 944 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 945 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 946 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 947 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 948 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 949 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 950 WMI_PDEV_PARAM_PMF_QOS, 951 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 952 WMI_PDEV_PARAM_DCS, 953 WMI_PDEV_PARAM_ANI_ENABLE, 954 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 955 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 956 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 957 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 958 WMI_PDEV_PARAM_DYNTXCHAIN, 959 WMI_PDEV_PARAM_PROXY_STA, 960 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 961 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 962 WMI_PDEV_PARAM_RFKILL_ENABLE, 963 WMI_PDEV_PARAM_BURST_DUR, 964 WMI_PDEV_PARAM_BURST_ENABLE, 965 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 966 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 967 WMI_PDEV_PARAM_L1SS_TRACK, 968 WMI_PDEV_PARAM_HYST_EN, 969 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 970 WMI_PDEV_PARAM_LED_SYS_STATE, 971 WMI_PDEV_PARAM_LED_ENABLE, 972 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 973 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 974 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 975 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 976 WMI_PDEV_PARAM_CTS_CBW, 977 WMI_PDEV_PARAM_WNTS_CONFIG, 978 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 979 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 980 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 981 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 982 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 983 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 984 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 985 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 986 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 987 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 988 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 989 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 990 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 991 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 992 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 993 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 994 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 995 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 996 WMI_PDEV_PARAM_AGGR_BURST, 997 WMI_PDEV_PARAM_RX_DECAP_MODE, 998 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 999 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 1000 WMI_PDEV_PARAM_ANTENNA_GAIN, 1001 WMI_PDEV_PARAM_RX_FILTER, 1002 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 1003 WMI_PDEV_PARAM_PROXY_STA_MODE, 1004 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 1005 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 1006 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 1007 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 1008 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 1009 WMI_PDEV_PARAM_BLOCK_INTERBSS, 1010 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 1011 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 1012 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 1013 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 1014 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 1015 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 1016 WMI_PDEV_PARAM_EN_STATS, 1017 WMI_PDEV_PARAM_MU_GROUP_POLICY, 1018 WMI_PDEV_PARAM_NOISE_DETECTION, 1019 WMI_PDEV_PARAM_NOISE_THRESHOLD, 1020 WMI_PDEV_PARAM_DPD_ENABLE, 1021 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 1022 WMI_PDEV_PARAM_ATF_STRICT_SCH, 1023 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 1024 WMI_PDEV_PARAM_ANT_PLZN, 1025 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 1026 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 1027 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 1028 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 1029 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 1030 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 1031 WMI_PDEV_PARAM_CCA_THRESHOLD, 1032 WMI_PDEV_PARAM_RTS_FIXED_RATE, 1033 WMI_PDEV_PARAM_PDEV_RESET, 1034 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 1035 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 1036 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 1037 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 1038 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 1039 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 1040 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 1041 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 1042 WMI_PDEV_PARAM_PROPAGATION_DELAY, 1043 WMI_PDEV_PARAM_ENA_ANT_DIV, 1044 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 1045 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 1046 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 1047 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 1048 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 1049 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 1050 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 1051 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 1052 WMI_PDEV_PARAM_TX_SCH_DELAY, 1053 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 1054 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 1055 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 1056 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 1057 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 1058 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 1059 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 1060 }; 1061 1062 enum wmi_tlv_vdev_param { 1063 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 1064 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 1065 WMI_VDEV_PARAM_BEACON_INTERVAL, 1066 WMI_VDEV_PARAM_LISTEN_INTERVAL, 1067 WMI_VDEV_PARAM_MULTICAST_RATE, 1068 WMI_VDEV_PARAM_MGMT_TX_RATE, 1069 WMI_VDEV_PARAM_SLOT_TIME, 1070 WMI_VDEV_PARAM_PREAMBLE, 1071 WMI_VDEV_PARAM_SWBA_TIME, 1072 WMI_VDEV_STATS_UPDATE_PERIOD, 1073 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 1074 WMI_VDEV_HOST_SWBA_INTERVAL, 1075 WMI_VDEV_PARAM_DTIM_PERIOD, 1076 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 1077 WMI_VDEV_PARAM_WDS, 1078 WMI_VDEV_PARAM_ATIM_WINDOW, 1079 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 1080 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 1081 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 1082 WMI_VDEV_PARAM_FEATURE_WMM, 1083 WMI_VDEV_PARAM_CHWIDTH, 1084 WMI_VDEV_PARAM_CHEXTOFFSET, 1085 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 1086 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 1087 WMI_VDEV_PARAM_MGMT_RATE, 1088 WMI_VDEV_PARAM_PROTECTION_MODE, 1089 WMI_VDEV_PARAM_FIXED_RATE, 1090 WMI_VDEV_PARAM_SGI, 1091 WMI_VDEV_PARAM_LDPC, 1092 WMI_VDEV_PARAM_TX_STBC, 1093 WMI_VDEV_PARAM_RX_STBC, 1094 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1095 WMI_VDEV_PARAM_DEF_KEYID, 1096 WMI_VDEV_PARAM_NSS, 1097 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1098 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1099 WMI_VDEV_PARAM_MCAST_INDICATE, 1100 WMI_VDEV_PARAM_DHCP_INDICATE, 1101 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1102 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1103 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1104 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1105 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1106 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1107 WMI_VDEV_PARAM_TXBF, 1108 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1109 WMI_VDEV_PARAM_DROP_UNENCRY, 1110 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1111 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1112 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1113 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1114 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1115 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1116 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1117 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1118 WMI_VDEV_PARAM_TX_PWRLIMIT, 1119 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1120 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1121 WMI_VDEV_PARAM_ENABLE_RMC, 1122 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1123 WMI_VDEV_PARAM_MAX_RATE, 1124 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1125 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1126 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1127 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1128 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1129 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1130 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1131 WMI_VDEV_PARAM_INACTIVITY_CNT, 1132 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1133 WMI_VDEV_PARAM_DTIM_POLICY, 1134 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1135 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1136 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1137 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1138 WMI_VDEV_PARAM_DISCONNECT_TH, 1139 WMI_VDEV_PARAM_RTSCTS_RATE, 1140 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1141 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1142 WMI_VDEV_PARAM_TXPOWER_SCALE, 1143 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1144 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1145 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1146 WMI_VDEV_PARAM_CABQ_MAXDUR, 1147 WMI_VDEV_PARAM_MFPTEST_SET, 1148 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1149 WMI_VDEV_PARAM_VHT_SGIMASK, 1150 WMI_VDEV_PARAM_VHT80_RATEMASK, 1151 WMI_VDEV_PARAM_PROXY_STA, 1152 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1153 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1154 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1155 WMI_VDEV_PARAM_SENSOR_AP, 1156 WMI_VDEV_PARAM_BEACON_RATE, 1157 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1158 WMI_VDEV_PARAM_STA_KICKOUT, 1159 WMI_VDEV_PARAM_CAPABILITIES, 1160 WMI_VDEV_PARAM_TSF_INCREMENT, 1161 WMI_VDEV_PARAM_AMPDU_PER_AC, 1162 WMI_VDEV_PARAM_RX_FILTER, 1163 WMI_VDEV_PARAM_MGMT_TX_POWER, 1164 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1165 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1166 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1167 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1168 WMI_VDEV_PARAM_HE_DCM, 1169 WMI_VDEV_PARAM_HE_RANGE_EXT, 1170 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1171 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1172 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1173 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1174 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1175 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1176 WMI_VDEV_PARAM_BSS_COLOR, 1177 WMI_VDEV_PARAM_SET_HEMU_MODE, 1178 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1179 }; 1180 1181 enum wmi_tlv_peer_flags { 1182 WMI_PEER_AUTH = 0x00000001, 1183 WMI_PEER_QOS = 0x00000002, 1184 WMI_PEER_NEED_PTK_4_WAY = 0x00000004, 1185 WMI_PEER_NEED_GTK_2_WAY = 0x00000010, 1186 WMI_PEER_HE = 0x00000400, 1187 WMI_PEER_APSD = 0x00000800, 1188 WMI_PEER_HT = 0x00001000, 1189 WMI_PEER_40MHZ = 0x00002000, 1190 WMI_PEER_STBC = 0x00008000, 1191 WMI_PEER_LDPC = 0x00010000, 1192 WMI_PEER_DYN_MIMOPS = 0x00020000, 1193 WMI_PEER_STATIC_MIMOPS = 0x00040000, 1194 WMI_PEER_SPATIAL_MUX = 0x00200000, 1195 WMI_PEER_TWT_REQ = 0x00400000, 1196 WMI_PEER_TWT_RESP = 0x00800000, 1197 WMI_PEER_VHT = 0x02000000, 1198 WMI_PEER_80MHZ = 0x04000000, 1199 WMI_PEER_PMF = 0x08000000, 1200 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1201 WMI_PEER_160MHZ = 0x40000000, 1202 WMI_PEER_SAFEMODE_EN = 0x80000000, 1203 }; 1204 1205 enum wmi_tlv_peer_flags_ext { 1206 WMI_PEER_EXT_EHT = BIT(0), 1207 WMI_PEER_EXT_320MHZ = BIT(1), 1208 }; 1209 1210 /** Enum list of TLV Tags for each parameter structure type. */ 1211 enum wmi_tlv_tag { 1212 WMI_TAG_LAST_RESERVED = 15, 1213 WMI_TAG_FIRST_ARRAY_ENUM, 1214 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1215 WMI_TAG_ARRAY_BYTE, 1216 WMI_TAG_ARRAY_STRUCT, 1217 WMI_TAG_ARRAY_FIXED_STRUCT, 1218 WMI_TAG_ARRAY_INT16, 1219 WMI_TAG_LAST_ARRAY_ENUM = 31, 1220 WMI_TAG_SERVICE_READY_EVENT, 1221 WMI_TAG_HAL_REG_CAPABILITIES, 1222 WMI_TAG_WLAN_HOST_MEM_REQ, 1223 WMI_TAG_READY_EVENT, 1224 WMI_TAG_SCAN_EVENT, 1225 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1226 WMI_TAG_CHAN_INFO_EVENT, 1227 WMI_TAG_COMB_PHYERR_RX_HDR, 1228 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1229 WMI_TAG_VDEV_STOPPED_EVENT, 1230 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1231 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1232 WMI_TAG_MGMT_RX_HDR, 1233 WMI_TAG_TBTT_OFFSET_EVENT, 1234 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1235 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1236 WMI_TAG_ROAM_EVENT, 1237 WMI_TAG_WOW_EVENT_INFO, 1238 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1239 WMI_TAG_RTT_EVENT_HEADER, 1240 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1241 WMI_TAG_RTT_MEAS_EVENT, 1242 WMI_TAG_ECHO_EVENT, 1243 WMI_TAG_FTM_INTG_EVENT, 1244 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1245 WMI_TAG_GPIO_INPUT_EVENT, 1246 WMI_TAG_CSA_EVENT, 1247 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1248 WMI_TAG_IGTK_INFO, 1249 WMI_TAG_DCS_INTERFERENCE_EVENT, 1250 WMI_TAG_ATH_DCS_CW_INT, 1251 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1252 WMI_TAG_ATH_DCS_CW_INT, 1253 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1254 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1255 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1256 WMI_TAG_WLAN_PROFILE_CTX_T, 1257 WMI_TAG_WLAN_PROFILE_T, 1258 WMI_TAG_PDEV_QVIT_EVENT, 1259 WMI_TAG_HOST_SWBA_EVENT, 1260 WMI_TAG_TIM_INFO, 1261 WMI_TAG_P2P_NOA_INFO, 1262 WMI_TAG_STATS_EVENT, 1263 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1264 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1265 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1266 WMI_TAG_INIT_CMD, 1267 WMI_TAG_RESOURCE_CONFIG, 1268 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1269 WMI_TAG_START_SCAN_CMD, 1270 WMI_TAG_STOP_SCAN_CMD, 1271 WMI_TAG_SCAN_CHAN_LIST_CMD, 1272 WMI_TAG_CHANNEL, 1273 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1274 WMI_TAG_PDEV_SET_PARAM_CMD, 1275 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1276 WMI_TAG_WMM_PARAMS, 1277 WMI_TAG_PDEV_SET_QUIET_CMD, 1278 WMI_TAG_VDEV_CREATE_CMD, 1279 WMI_TAG_VDEV_DELETE_CMD, 1280 WMI_TAG_VDEV_START_REQUEST_CMD, 1281 WMI_TAG_P2P_NOA_DESCRIPTOR, 1282 WMI_TAG_P2P_GO_SET_BEACON_IE, 1283 WMI_TAG_GTK_OFFLOAD_CMD, 1284 WMI_TAG_VDEV_UP_CMD, 1285 WMI_TAG_VDEV_STOP_CMD, 1286 WMI_TAG_VDEV_DOWN_CMD, 1287 WMI_TAG_VDEV_SET_PARAM_CMD, 1288 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1289 WMI_TAG_PEER_CREATE_CMD, 1290 WMI_TAG_PEER_DELETE_CMD, 1291 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1292 WMI_TAG_PEER_SET_PARAM_CMD, 1293 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1294 WMI_TAG_VHT_RATE_SET, 1295 WMI_TAG_BCN_TMPL_CMD, 1296 WMI_TAG_PRB_TMPL_CMD, 1297 WMI_TAG_BCN_PRB_INFO, 1298 WMI_TAG_PEER_TID_ADDBA_CMD, 1299 WMI_TAG_PEER_TID_DELBA_CMD, 1300 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1301 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1302 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1303 WMI_TAG_ROAM_SCAN_MODE, 1304 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1305 WMI_TAG_ROAM_SCAN_PERIOD, 1306 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1307 WMI_TAG_PDEV_SUSPEND_CMD, 1308 WMI_TAG_PDEV_RESUME_CMD, 1309 WMI_TAG_ADD_BCN_FILTER_CMD, 1310 WMI_TAG_RMV_BCN_FILTER_CMD, 1311 WMI_TAG_WOW_ENABLE_CMD, 1312 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1313 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1314 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1315 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1316 WMI_TAG_ARP_OFFLOAD_TUPLE, 1317 WMI_TAG_NS_OFFLOAD_TUPLE, 1318 WMI_TAG_FTM_INTG_CMD, 1319 WMI_TAG_STA_KEEPALIVE_CMD, 1320 WMI_TAG_STA_KEEPALVE_ARP_RESPONSE, 1321 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1322 WMI_TAG_AP_PS_PEER_CMD, 1323 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1324 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1325 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1326 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1327 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1328 WMI_TAG_WOW_DEL_PATTERN_CMD, 1329 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1330 WMI_TAG_RTT_MEASREQ_HEAD, 1331 WMI_TAG_RTT_MEASREQ_BODY, 1332 WMI_TAG_RTT_TSF_CMD, 1333 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1334 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1335 WMI_TAG_REQUEST_STATS_CMD, 1336 WMI_TAG_NLO_CONFIG_CMD, 1337 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1338 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1339 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1340 WMI_TAG_CHATTER_SET_MODE_CMD, 1341 WMI_TAG_ECHO_CMD, 1342 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1343 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1344 WMI_TAG_FORCE_FW_HANG_CMD, 1345 WMI_TAG_GPIO_CONFIG_CMD, 1346 WMI_TAG_GPIO_OUTPUT_CMD, 1347 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1348 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1349 WMI_TAG_BCN_TX_HDR, 1350 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1351 WMI_TAG_MGMT_TX_HDR, 1352 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1353 WMI_TAG_ADDBA_SEND_CMD, 1354 WMI_TAG_DELBA_SEND_CMD, 1355 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1356 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1357 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1358 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1359 WMI_TAG_PDEV_SET_HT_IE_CMD, 1360 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1361 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1362 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1363 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1364 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1365 WMI_TAG_PEER_MCAST_GROUP_CMD, 1366 WMI_TAG_ROAM_AP_PROFILE, 1367 WMI_TAG_AP_PROFILE, 1368 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1369 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1370 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1371 WMI_TAG_WOW_ADD_PATTERN_CMD, 1372 WMI_TAG_WOW_BITMAP_PATTERN_T, 1373 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1374 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1375 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1376 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1377 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1378 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1379 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1380 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1381 WMI_TAG_TXBF_CMD, 1382 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1383 WMI_TAG_NLO_EVENT, 1384 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1385 WMI_TAG_UPLOAD_H_HDR, 1386 WMI_TAG_CAPTURE_H_EVENT_HDR, 1387 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1388 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1389 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1390 WMI_TAG_VDEV_WMM_DELTS_CMD, 1391 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1392 WMI_TAG_TDLS_SET_STATE_CMD, 1393 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1394 WMI_TAG_TDLS_PEER_EVENT, 1395 WMI_TAG_TDLS_PEER_CAPABILITIES, 1396 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1397 WMI_TAG_ROAM_CHAN_LIST, 1398 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1399 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1400 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1401 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1402 WMI_TAG_BA_REQ_SSN_CMD, 1403 WMI_TAG_BA_RSP_SSN_EVENT, 1404 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1405 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1406 WMI_TAG_P2P_SET_OPPPS_CMD, 1407 WMI_TAG_P2P_SET_NOA_CMD, 1408 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1409 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1410 WMI_TAG_STA_SMPS_PARAM_CMD, 1411 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1412 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1413 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1414 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1415 WMI_TAG_P2P_NOA_EVENT, 1416 WMI_TAG_HB_SET_ENABLE_CMD, 1417 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1418 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1419 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1420 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1421 WMI_TAG_HB_IND_EVENT, 1422 WMI_TAG_TX_PAUSE_EVENT, 1423 WMI_TAG_RFKILL_EVENT, 1424 WMI_TAG_DFS_RADAR_EVENT, 1425 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1426 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1427 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1428 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1429 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1430 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1431 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1432 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1433 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1434 WMI_TAG_VDEV_PLMREQ_START_CMD, 1435 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1436 WMI_TAG_THERMAL_MGMT_CMD, 1437 WMI_TAG_THERMAL_MGMT_EVENT, 1438 WMI_TAG_PEER_INFO_REQ_CMD, 1439 WMI_TAG_PEER_INFO_EVENT, 1440 WMI_TAG_PEER_INFO, 1441 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1442 WMI_TAG_RMC_SET_MODE_CMD, 1443 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1444 WMI_TAG_RMC_CONFIG_CMD, 1445 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1446 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1447 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1448 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1449 WMI_TAG_NAN_CMD_PARAM, 1450 WMI_TAG_NAN_EVENT_HDR, 1451 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1452 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1453 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1454 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1455 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1456 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1457 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1458 WMI_TAG_ROAM_SCAN_CMD, 1459 WMI_TAG_REQ_STATS_EXT_CMD, 1460 WMI_TAG_STATS_EXT_EVENT, 1461 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1462 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1463 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1464 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1465 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1466 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1467 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1468 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1469 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1470 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1471 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1472 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1473 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1474 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1475 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1476 WMI_TAG_START_LINK_STATS_CMD, 1477 WMI_TAG_CLEAR_LINK_STATS_CMD, 1478 WMI_TAG_REQUEST_LINK_STATS_CMD, 1479 WMI_TAG_IFACE_LINK_STATS_EVENT, 1480 WMI_TAG_RADIO_LINK_STATS_EVENT, 1481 WMI_TAG_PEER_STATS_EVENT, 1482 WMI_TAG_CHANNEL_STATS, 1483 WMI_TAG_RADIO_LINK_STATS, 1484 WMI_TAG_RATE_STATS, 1485 WMI_TAG_PEER_LINK_STATS, 1486 WMI_TAG_WMM_AC_STATS, 1487 WMI_TAG_IFACE_LINK_STATS, 1488 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1489 WMI_TAG_LPI_START_SCAN_CMD, 1490 WMI_TAG_LPI_STOP_SCAN_CMD, 1491 WMI_TAG_LPI_RESULT_EVENT, 1492 WMI_TAG_PEER_STATE_EVENT, 1493 WMI_TAG_EXTSCAN_BUCKET_CMD, 1494 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1495 WMI_TAG_EXTSCAN_START_CMD, 1496 WMI_TAG_EXTSCAN_STOP_CMD, 1497 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1498 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1499 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1500 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1501 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1502 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1503 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1504 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1505 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1506 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1507 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1508 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1509 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1510 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1511 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1512 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1513 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1514 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1515 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1516 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1517 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1518 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1519 WMI_TAG_UNIT_TEST_CMD, 1520 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1521 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1522 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1523 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1524 WMI_TAG_ROAM_SYNCH_EVENT, 1525 WMI_TAG_ROAM_SYNCH_COMPLETE, 1526 WMI_TAG_EXTWOW_ENABLE_CMD, 1527 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1528 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1529 WMI_TAG_LPI_STATUS_EVENT, 1530 WMI_TAG_LPI_HANDOFF_EVENT, 1531 WMI_TAG_VDEV_RATE_STATS_EVENT, 1532 WMI_TAG_VDEV_RATE_HT_INFO, 1533 WMI_TAG_RIC_REQUEST, 1534 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1535 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1536 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1537 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1538 WMI_TAG_RIC_TSPEC, 1539 WMI_TAG_TPC_CHAINMASK_CONFIG, 1540 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1541 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1542 WMI_TAG_KEY_MATERIAL, 1543 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1544 WMI_TAG_SET_LED_FLASHING_CMD, 1545 WMI_TAG_MDNS_OFFLOAD_CMD, 1546 WMI_TAG_MDNS_SET_FQDN_CMD, 1547 WMI_TAG_MDNS_SET_RESP_CMD, 1548 WMI_TAG_MDNS_GET_STATS_CMD, 1549 WMI_TAG_MDNS_STATS_EVENT, 1550 WMI_TAG_ROAM_INVOKE_CMD, 1551 WMI_TAG_PDEV_RESUME_EVENT, 1552 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1553 WMI_TAG_SAP_OFL_ENABLE_CMD, 1554 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1555 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1556 WMI_TAG_APFIND_CMD_PARAM, 1557 WMI_TAG_APFIND_EVENT_HDR, 1558 WMI_TAG_OCB_SET_SCHED_CMD, 1559 WMI_TAG_OCB_SET_SCHED_EVENT, 1560 WMI_TAG_OCB_SET_CONFIG_CMD, 1561 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1562 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1563 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1564 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1565 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1566 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1567 WMI_TAG_DCC_GET_STATS_CMD, 1568 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1569 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1570 WMI_TAG_DCC_CLEAR_STATS_CMD, 1571 WMI_TAG_DCC_UPDATE_NDL_CMD, 1572 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1573 WMI_TAG_DCC_STATS_EVENT, 1574 WMI_TAG_OCB_CHANNEL, 1575 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1576 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1577 WMI_TAG_DCC_NDL_CHAN, 1578 WMI_TAG_QOS_PARAMETER, 1579 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1580 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1581 WMI_TAG_ROAM_FILTER, 1582 WMI_TAG_PASSPOINT_CONFIG_CMD, 1583 WMI_TAG_PASSPOINT_EVENT_HDR, 1584 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1585 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1586 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1587 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1588 WMI_TAG_GET_FW_MEM_DUMP, 1589 WMI_TAG_UPDATE_FW_MEM_DUMP, 1590 WMI_TAG_FW_MEM_DUMP_PARAMS, 1591 WMI_TAG_DEBUG_MESG_FLUSH, 1592 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1593 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1594 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1595 WMI_TAG_VDEV_SET_IE_CMD, 1596 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1597 WMI_TAG_RSSI_BREACH_EVENT, 1598 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1599 WMI_TAG_SOC_SET_PCL_CMD, 1600 WMI_TAG_SOC_SET_HW_MODE_CMD, 1601 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1602 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1603 WMI_TAG_VDEV_TXRX_STREAMS, 1604 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1605 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1606 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1607 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1608 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1609 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1610 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1611 WMI_TAG_PACKET_FILTER_CONFIG, 1612 WMI_TAG_PACKET_FILTER_ENABLE, 1613 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1614 WMI_TAG_MGMT_TX_SEND_CMD, 1615 WMI_TAG_MGMT_TX_COMPL_EVENT, 1616 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1617 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1618 WMI_TAG_LRO_INFO_CMD, 1619 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1620 WMI_TAG_SERVICE_READY_EXT_EVENT, 1621 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1622 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1623 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1624 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1625 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1626 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1627 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1628 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1629 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1630 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1631 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1632 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1633 WMI_TAG_SCPC_EVENT, 1634 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1635 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1636 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1637 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1638 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1639 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1640 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1641 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1642 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1643 WMI_TAG_PEER_DELETE_RESP_EVENT, 1644 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1645 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1646 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1647 WMI_TAG_VDEV_CONFIG_RATEMASK, 1648 WMI_TAG_PDEV_FIPS_CMD, 1649 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1650 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1651 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1652 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1653 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1654 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1655 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1656 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1657 WMI_TAG_FWTEST_SET_PARAM_CMD, 1658 WMI_TAG_PEER_ATF_REQUEST, 1659 WMI_TAG_VDEV_ATF_REQUEST, 1660 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1661 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1662 WMI_TAG_INST_RSSI_STATS_RESP, 1663 WMI_TAG_MED_UTIL_REPORT_EVENT, 1664 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1665 WMI_TAG_WDS_ADDR_EVENT, 1666 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1667 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1668 WMI_TAG_PDEV_TPC_EVENT, 1669 WMI_TAG_ANI_OFDM_EVENT, 1670 WMI_TAG_ANI_CCK_EVENT, 1671 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1672 WMI_TAG_PDEV_FIPS_EVENT, 1673 WMI_TAG_ATF_PEER_INFO, 1674 WMI_TAG_PDEV_GET_TPC_CMD, 1675 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1676 WMI_TAG_QBOOST_CFG_CMD, 1677 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1678 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1679 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1680 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1681 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1682 WMI_TAG_PEER_MCS_RATE_INFO, 1683 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1684 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1685 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1686 WMI_TAG_MU_REPORT_TOTAL_MU, 1687 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1688 WMI_TAG_ROAM_SET_MBO, 1689 WMI_TAG_MIB_STATS_ENABLE_CMD, 1690 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1691 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1692 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1693 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1694 WMI_TAG_NDI_GET_CAP_REQ, 1695 WMI_TAG_NDP_INITIATOR_REQ, 1696 WMI_TAG_NDP_RESPONDER_REQ, 1697 WMI_TAG_NDP_END_REQ, 1698 WMI_TAG_NDI_CAP_RSP_EVENT, 1699 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1700 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1701 WMI_TAG_NDP_END_RSP_EVENT, 1702 WMI_TAG_NDP_INDICATION_EVENT, 1703 WMI_TAG_NDP_CONFIRM_EVENT, 1704 WMI_TAG_NDP_END_INDICATION_EVENT, 1705 WMI_TAG_VDEV_SET_QUIET_CMD, 1706 WMI_TAG_PDEV_SET_PCL_CMD, 1707 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1708 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1709 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1710 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1711 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1712 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1713 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1714 WMI_TAG_COEX_CONFIG_CMD, 1715 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1716 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1717 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1718 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1719 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1720 WMI_TAG_MAC_PHY_CAPABILITIES, 1721 WMI_TAG_HW_MODE_CAPABILITIES, 1722 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1723 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1724 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1725 WMI_TAG_VDEV_WISA_CMD, 1726 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1727 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1728 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1729 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1730 WMI_TAG_NDP_END_RSP_PER_NDI, 1731 WMI_TAG_PEER_BWF_REQUEST, 1732 WMI_TAG_BWF_PEER_INFO, 1733 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1734 WMI_TAG_RMC_SET_LEADER_CMD, 1735 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1736 WMI_TAG_PER_CHAIN_RSSI_STATS, 1737 WMI_TAG_RSSI_STATS, 1738 WMI_TAG_P2P_LO_START_CMD, 1739 WMI_TAG_P2P_LO_STOP_CMD, 1740 WMI_TAG_P2P_LO_STOPPED_EVENT, 1741 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1742 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1743 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1744 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1745 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1746 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1747 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1748 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1749 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1750 WMI_TAG_TLV_BUF_LEN_PARAM, 1751 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1752 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1753 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1754 WMI_TAG_PEER_ANTDIV_INFO, 1755 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1756 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1757 WMI_TAG_MNT_FILTER_CMD, 1758 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1759 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1760 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1761 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1762 WMI_TAG_CHAN_CCA_STATS, 1763 WMI_TAG_PEER_SIGNAL_STATS, 1764 WMI_TAG_TX_STATS, 1765 WMI_TAG_PEER_AC_TX_STATS, 1766 WMI_TAG_RX_STATS, 1767 WMI_TAG_PEER_AC_RX_STATS, 1768 WMI_TAG_REPORT_STATS_EVENT, 1769 WMI_TAG_CHAN_CCA_STATS_THRESH, 1770 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1771 WMI_TAG_TX_STATS_THRESH, 1772 WMI_TAG_RX_STATS_THRESH, 1773 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1774 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1775 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1776 WMI_TAG_RX_AGGR_FAILURE_INFO, 1777 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1778 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1779 WMI_TAG_PDEV_BAND_TO_MAC, 1780 WMI_TAG_TBTT_OFFSET_INFO, 1781 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1782 WMI_TAG_SAR_LIMITS_CMD, 1783 WMI_TAG_SAR_LIMIT_CMD_ROW, 1784 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1785 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1786 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1787 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1788 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1789 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1790 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1791 WMI_TAG_VENDOR_OUI, 1792 WMI_TAG_REQUEST_RCPI_CMD, 1793 WMI_TAG_UPDATE_RCPI_EVENT, 1794 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1795 WMI_TAG_PEER_STATS_INFO, 1796 WMI_TAG_PEER_STATS_INFO_EVENT, 1797 WMI_TAG_PKGID_EVENT, 1798 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1799 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1800 WMI_TAG_REGULATORY_RULE_STRUCT, 1801 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1802 WMI_TAG_11D_SCAN_START_CMD, 1803 WMI_TAG_11D_SCAN_STOP_CMD, 1804 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1805 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1806 WMI_TAG_RADIO_CHAN_STATS, 1807 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1808 WMI_TAG_ROAM_PER_CONFIG, 1809 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1810 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1811 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1812 WMI_TAG_HW_DATA_FILTER_CMD, 1813 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1814 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1815 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1816 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1817 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1818 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1819 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1820 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1821 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1822 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1823 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1824 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1825 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1826 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1827 WMI_TAG_IFACE_OFFLOAD_STATS, 1828 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1829 WMI_TAG_RSSI_CTL_EXT, 1830 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1831 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1832 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1833 WMI_TAG_VDEV_TX_POWER_EVENT, 1834 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1835 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1836 WMI_TAG_TX_SEND_PARAMS, 1837 WMI_TAG_HE_RATE_SET, 1838 WMI_TAG_CONGESTION_STATS, 1839 WMI_TAG_SET_INIT_COUNTRY_CMD, 1840 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1841 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1842 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1843 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1844 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1845 WMI_TAG_THERM_THROT_STATS_EVENT, 1846 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1847 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1848 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1849 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1850 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1851 WMI_TAG_OEM_INDIRECT_DATA, 1852 WMI_TAG_OEM_DMA_BUF_RELEASE, 1853 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1854 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1855 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1856 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1857 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1858 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1859 WMI_TAG_UNIT_TEST_EVENT, 1860 WMI_TAG_ROAM_FILS_OFFLOAD, 1861 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1862 WMI_TAG_PMK_CACHE, 1863 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1864 WMI_TAG_ROAM_FILS_SYNCH, 1865 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1866 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1867 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1868 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1869 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1870 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1871 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1872 WMI_TAG_BTM_CONFIG, 1873 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1874 WMI_TAG_WLM_CONFIG_CMD, 1875 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1876 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1877 WMI_TAG_ROAM_CND_SCORING_PARAM, 1878 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1879 WMI_TAG_VENDOR_OUI_EXT, 1880 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1881 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1882 WMI_TAG_ENABLE_FILS_CMD, 1883 WMI_TAG_HOST_SWFDA_EVENT, 1884 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1885 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1886 WMI_TAG_STATS_PERIOD, 1887 WMI_TAG_NDL_SCHEDULE_UPDATE, 1888 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1889 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1890 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1891 WMI_TAG_SAR2_RESULT_EVENT, 1892 WMI_TAG_SAR_CAPABILITIES, 1893 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1894 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1895 WMI_TAG_DMA_RING_CAPABILITIES, 1896 WMI_TAG_DMA_RING_CFG_REQ, 1897 WMI_TAG_DMA_RING_CFG_RSP, 1898 WMI_TAG_DMA_BUF_RELEASE, 1899 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1900 WMI_TAG_SAR_GET_LIMITS_CMD, 1901 WMI_TAG_SAR_GET_LIMITS_EVENT, 1902 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1903 WMI_TAG_OFFLOAD_11K_REPORT, 1904 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1905 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1906 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1907 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1908 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1909 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1910 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1911 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1912 WMI_TAG_PDEV_GET_NFCAL_POWER, 1913 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1914 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1915 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1916 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1917 WMI_TAG_TWT_ENABLE_CMD, 1918 WMI_TAG_TWT_DISABLE_CMD, 1919 WMI_TAG_TWT_ADD_DIALOG_CMD, 1920 WMI_TAG_TWT_DEL_DIALOG_CMD, 1921 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1922 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1923 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1924 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1925 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1926 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1927 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1928 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1929 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1930 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1931 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1932 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1933 WMI_TAG_GET_TPC_POWER_CMD, 1934 WMI_TAG_GET_TPC_POWER_EVENT, 1935 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1936 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1937 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1938 WMI_TAG_MOTION_DET_START_STOP_CMD, 1939 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1940 WMI_TAG_MOTION_DET_EVENT, 1941 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1942 WMI_TAG_NDP_TRANSPORT_IP, 1943 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1944 WMI_TAG_ESP_ESTIMATE_EVENT, 1945 WMI_TAG_NAN_HOST_CONFIG, 1946 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1947 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1948 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1949 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1950 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1951 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1952 WMI_TAG_PEER_EXTD2_STATS, 1953 WMI_TAG_HPCS_PULSE_START_CMD, 1954 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1955 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1956 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1957 WMI_TAG_NAN_EVENT_INFO, 1958 WMI_TAG_NDP_CHANNEL_INFO, 1959 WMI_TAG_NDP_CMD, 1960 WMI_TAG_NDP_EVENT, 1961 /* TODO add all the missing cmds */ 1962 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1963 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1964 WMI_TAG_SERVICE_READY_EXT2_EVENT = 0x334, 1965 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1966 WMI_TAG_MAC_PHY_CAPABILITIES_EXT = 0x36F, 1967 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 1968 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 1969 WMI_TAG_TPC_STATS_GET_CMD = 0x38B, 1970 WMI_TAG_TPC_STATS_EVENT_FIXED_PARAM, 1971 WMI_TAG_TPC_STATS_CONFIG_EVENT, 1972 WMI_TAG_TPC_STATS_REG_PWR_ALLOWED, 1973 WMI_TAG_TPC_STATS_RATES_ARRAY, 1974 WMI_TAG_TPC_STATS_CTL_PWR_TABLE_EVENT, 1975 WMI_TAG_VDEV_SET_TPC_POWER_CMD = 0x3B5, 1976 WMI_TAG_VDEV_CH_POWER_INFO, 1977 WMI_TAG_MLO_LINK_SET_ACTIVE_CMD = 0x3BE, 1978 WMI_TAG_EHT_RATE_SET = 0x3C4, 1979 WMI_TAG_DCS_AWGN_INT_TYPE = 0x3C5, 1980 WMI_TAG_MLO_TX_SEND_PARAMS, 1981 WMI_TAG_MLO_PARTNER_LINK_PARAMS, 1982 WMI_TAG_MLO_PARTNER_LINK_PARAMS_PEER_ASSOC, 1983 WMI_TAG_MLO_SETUP_CMD = 0x3C9, 1984 WMI_TAG_MLO_SETUP_COMPLETE_EVENT, 1985 WMI_TAG_MLO_READY_CMD, 1986 WMI_TAG_MLO_TEARDOWN_CMD, 1987 WMI_TAG_MLO_TEARDOWN_COMPLETE, 1988 WMI_TAG_MLO_PEER_ASSOC_PARAMS = 0x3D0, 1989 WMI_TAG_MLO_PEER_CREATE_PARAMS = 0x3D5, 1990 WMI_TAG_MLO_VDEV_START_PARAMS = 0x3D6, 1991 WMI_TAG_MLO_VDEV_CREATE_PARAMS = 0x3D7, 1992 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1993 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD = 0x3D9, 1994 WMI_TAG_PDEV_SET_BIOS_INTERFACE_CMD = 0x3FB, 1995 WMI_TAG_HALPHY_CTRL_PATH_CMD_FIXED_PARAM = 0x442, 1996 WMI_TAG_HALPHY_CTRL_PATH_EVENT_FIXED_PARAM, 1997 WMI_TAG_MAX 1998 }; 1999 2000 enum wmi_tlv_service { 2001 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 2002 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 2003 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 2004 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 2005 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 2006 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 2007 WMI_TLV_SERVICE_AP_UAPSD = 6, 2008 WMI_TLV_SERVICE_AP_DFS = 7, 2009 WMI_TLV_SERVICE_11AC = 8, 2010 WMI_TLV_SERVICE_BLOCKACK = 9, 2011 WMI_TLV_SERVICE_PHYERR = 10, 2012 WMI_TLV_SERVICE_BCN_FILTER = 11, 2013 WMI_TLV_SERVICE_RTT = 12, 2014 WMI_TLV_SERVICE_WOW = 13, 2015 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 2016 WMI_TLV_SERVICE_IRAM_TIDS = 15, 2017 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 2018 WMI_TLV_SERVICE_NLO = 17, 2019 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 2020 WMI_TLV_SERVICE_SCAN_SCH = 19, 2021 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 2022 WMI_TLV_SERVICE_CHATTER = 21, 2023 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 2024 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 2025 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 2026 WMI_TLV_SERVICE_GPIO = 25, 2027 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 2028 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 2029 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 2030 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 2031 WMI_TLV_SERVICE_TX_ENCAP = 30, 2032 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 2033 WMI_TLV_SERVICE_EARLY_RX = 32, 2034 WMI_TLV_SERVICE_STA_SMPS = 33, 2035 WMI_TLV_SERVICE_FWTEST = 34, 2036 WMI_TLV_SERVICE_STA_WMMAC = 35, 2037 WMI_TLV_SERVICE_TDLS = 36, 2038 WMI_TLV_SERVICE_BURST = 37, 2039 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 2040 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 2041 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 2042 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 2043 WMI_TLV_SERVICE_WLAN_HB = 42, 2044 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 2045 WMI_TLV_SERVICE_BATCH_SCAN = 44, 2046 WMI_TLV_SERVICE_QPOWER = 45, 2047 WMI_TLV_SERVICE_PLMREQ = 46, 2048 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 2049 WMI_TLV_SERVICE_RMC = 48, 2050 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 2051 WMI_TLV_SERVICE_COEX_SAR = 50, 2052 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 2053 WMI_TLV_SERVICE_NAN = 52, 2054 WMI_TLV_SERVICE_L1SS_STAT = 53, 2055 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 2056 WMI_TLV_SERVICE_OBSS_SCAN = 55, 2057 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 2058 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 2059 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 2060 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 2061 WMI_TLV_SERVICE_LPASS = 60, 2062 WMI_TLV_SERVICE_EXTSCAN = 61, 2063 WMI_TLV_SERVICE_D0WOW = 62, 2064 WMI_TLV_SERVICE_HSOFFLOAD = 63, 2065 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 2066 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 2067 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 2068 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 2069 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 2070 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 2071 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 2072 WMI_TLV_SERVICE_OCB = 71, 2073 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 2074 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 2075 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 2076 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 2077 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 2078 WMI_TLV_SERVICE_EXT_MSG = 77, 2079 WMI_TLV_SERVICE_MAWC = 78, 2080 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 2081 WMI_TLV_SERVICE_EGAP = 80, 2082 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 2083 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 2084 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 2085 WMI_TLV_SERVICE_ATF = 84, 2086 WMI_TLV_SERVICE_COEX_GPIO = 85, 2087 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 2088 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 2089 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 2090 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 2091 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 2092 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 2093 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 2094 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 2095 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 2096 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 2097 WMI_TLV_SERVICE_NAN_DATA = 96, 2098 WMI_TLV_SERVICE_NAN_RTT = 97, 2099 WMI_TLV_SERVICE_11AX = 98, 2100 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 2101 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 2102 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 2103 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 2104 WMI_TLV_SERVICE_MESH_11S = 103, 2105 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 2106 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 2107 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 2108 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 2109 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 2110 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 2111 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 2112 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 2113 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 2114 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 2115 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2116 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2117 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2118 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2119 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2120 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2121 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2122 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2123 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2124 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2125 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2126 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2127 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2128 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2129 2130 WMI_MAX_SERVICE = 128, 2131 2132 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2133 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2134 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2135 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2136 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2137 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2138 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2139 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2140 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2141 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2142 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2143 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2144 WMI_TLV_SERVICE_THERM_THROT = 140, 2145 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2146 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2147 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2148 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2149 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2150 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2151 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2152 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2153 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2154 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2155 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2156 WMI_TLV_SERVICE_STA_TWT = 152, 2157 WMI_TLV_SERVICE_AP_TWT = 153, 2158 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2159 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2160 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2161 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2162 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2163 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2164 WMI_TLV_SERVICE_MOTION_DET = 160, 2165 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2166 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2167 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2168 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2169 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2170 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2171 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2172 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2173 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2174 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2175 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2176 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2177 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2178 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2179 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2180 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2181 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2182 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2183 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2184 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2185 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2186 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2187 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2188 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2189 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2190 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2191 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2192 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2193 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2194 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2195 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2196 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2197 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2198 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2199 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2200 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2201 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2202 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2203 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2204 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2205 WMI_TLV_SERVICE_PS_TDCC = 201, 2206 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2207 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2208 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2209 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2210 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2211 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2212 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2213 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2214 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2215 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2216 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2217 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2218 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2219 WMI_TLV_SERVICE_EXT2_MSG = 220, 2220 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2221 2222 WMI_MAX_EXT_SERVICE = 256, 2223 2224 WMI_TLV_SERVICE_EXT_TPC_REG_SUPPORT = 280, 2225 2226 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2227 2228 WMI_TLV_SERVICE_11BE = 289, 2229 2230 WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, 2231 2232 WMI_TLV_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, 2233 2234 WMI_MAX_EXT2_SERVICE, 2235 }; 2236 2237 enum { 2238 WMI_SMPS_FORCED_MODE_NONE = 0, 2239 WMI_SMPS_FORCED_MODE_DISABLED, 2240 WMI_SMPS_FORCED_MODE_STATIC, 2241 WMI_SMPS_FORCED_MODE_DYNAMIC 2242 }; 2243 2244 enum wmi_tpc_chainmask { 2245 WMI_TPC_CHAINMASK_CONFIG_BAND_2G = 0, 2246 WMI_TPC_CHAINMASK_CONFIG_BAND_5G = 1, 2247 WMI_NUM_SUPPORTED_BAND_MAX = 2, 2248 }; 2249 2250 enum wmi_peer_param { 2251 WMI_PEER_MIMO_PS_STATE = 1, 2252 WMI_PEER_AMPDU = 2, 2253 WMI_PEER_AUTHORIZE = 3, 2254 WMI_PEER_CHWIDTH = 4, 2255 WMI_PEER_NSS = 5, 2256 WMI_PEER_USE_4ADDR = 6, 2257 WMI_PEER_MEMBERSHIP = 7, 2258 WMI_PEER_USERPOS = 8, 2259 WMI_PEER_CRIT_PROTO_HINT_ENABLED = 9, 2260 WMI_PEER_TX_FAIL_CNT_THR = 10, 2261 WMI_PEER_SET_HW_RETRY_CTS2S = 11, 2262 WMI_PEER_IBSS_ATIM_WINDOW_LENGTH = 12, 2263 WMI_PEER_PHYMODE = 13, 2264 WMI_PEER_USE_FIXED_PWR = 14, 2265 WMI_PEER_PARAM_FIXED_RATE = 15, 2266 WMI_PEER_SET_MU_WHITELIST = 16, 2267 WMI_PEER_SET_MAX_TX_RATE = 17, 2268 WMI_PEER_SET_MIN_TX_RATE = 18, 2269 WMI_PEER_SET_DEFAULT_ROUTING = 19, 2270 WMI_PEER_CHWIDTH_PUNCTURE_20MHZ_BITMAP = 39, 2271 }; 2272 2273 #define WMI_PEER_PUNCTURE_BITMAP GENMASK(23, 8) 2274 2275 enum wmi_slot_time { 2276 WMI_VDEV_SLOT_TIME_LONG = 1, 2277 WMI_VDEV_SLOT_TIME_SHORT = 2, 2278 }; 2279 2280 enum wmi_preamble { 2281 WMI_VDEV_PREAMBLE_LONG = 1, 2282 WMI_VDEV_PREAMBLE_SHORT = 2, 2283 }; 2284 2285 enum wmi_peer_smps_state { 2286 WMI_PEER_SMPS_PS_NONE = 0, 2287 WMI_PEER_SMPS_STATIC = 1, 2288 WMI_PEER_SMPS_DYNAMIC = 2 2289 }; 2290 2291 enum wmi_peer_chwidth { 2292 WMI_PEER_CHWIDTH_20MHZ = 0, 2293 WMI_PEER_CHWIDTH_40MHZ = 1, 2294 WMI_PEER_CHWIDTH_80MHZ = 2, 2295 WMI_PEER_CHWIDTH_160MHZ = 3, 2296 WMI_PEER_CHWIDTH_320MHZ = 4, 2297 }; 2298 2299 enum wmi_beacon_gen_mode { 2300 WMI_BEACON_STAGGERED_MODE = 0, 2301 WMI_BEACON_BURST_MODE = 1 2302 }; 2303 2304 enum wmi_direct_buffer_module { 2305 WMI_DIRECT_BUF_SPECTRAL = 0, 2306 WMI_DIRECT_BUF_CFR = 1, 2307 2308 /* keep it last */ 2309 WMI_DIRECT_BUF_MAX 2310 }; 2311 2312 struct ath12k_wmi_pdev_band_arg { 2313 u32 pdev_id; 2314 u32 start_freq; 2315 u32 end_freq; 2316 }; 2317 2318 struct ath12k_wmi_ppe_threshold_arg { 2319 u32 numss_m1; 2320 u32 ru_bit_mask; 2321 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2322 }; 2323 2324 #define PSOC_HOST_MAX_PHY_SIZE (3) 2325 #define ATH12K_11B_SUPPORT BIT(0) 2326 #define ATH12K_11G_SUPPORT BIT(1) 2327 #define ATH12K_11A_SUPPORT BIT(2) 2328 #define ATH12K_11N_SUPPORT BIT(3) 2329 #define ATH12K_11AC_SUPPORT BIT(4) 2330 #define ATH12K_11AX_SUPPORT BIT(5) 2331 2332 struct ath12k_wmi_hal_reg_capabilities_ext_arg { 2333 u32 phy_id; 2334 u32 eeprom_reg_domain; 2335 u32 eeprom_reg_domain_ext; 2336 u32 regcap1; 2337 u32 regcap2; 2338 u32 wireless_modes; 2339 u32 low_2ghz_chan; 2340 u32 high_2ghz_chan; 2341 u32 low_5ghz_chan; 2342 u32 high_5ghz_chan; 2343 }; 2344 2345 #define WMI_HOST_MAX_PDEV 3 2346 2347 struct ath12k_wmi_host_mem_chunk_params { 2348 __le32 tlv_header; 2349 __le32 req_id; 2350 __le32 ptr; 2351 __le32 size; 2352 } __packed; 2353 2354 struct ath12k_wmi_host_mem_chunk_arg { 2355 void *vaddr; 2356 dma_addr_t paddr; 2357 u32 len; 2358 u32 req_id; 2359 }; 2360 2361 enum ath12k_peer_metadata_version { 2362 ATH12K_PEER_METADATA_V0, 2363 ATH12K_PEER_METADATA_V1, 2364 ATH12K_PEER_METADATA_V1A, 2365 ATH12K_PEER_METADATA_V1B 2366 }; 2367 2368 struct ath12k_wmi_resource_config_arg { 2369 u32 num_vdevs; 2370 u32 num_peers; 2371 u32 num_active_peers; 2372 u32 num_offload_peers; 2373 u32 num_offload_reorder_buffs; 2374 u32 num_peer_keys; 2375 u32 num_tids; 2376 u32 ast_skid_limit; 2377 u32 tx_chain_mask; 2378 u32 rx_chain_mask; 2379 u32 rx_timeout_pri[4]; 2380 u32 rx_decap_mode; 2381 u32 scan_max_pending_req; 2382 u32 bmiss_offload_max_vdev; 2383 u32 roam_offload_max_vdev; 2384 u32 roam_offload_max_ap_profiles; 2385 u32 num_mcast_groups; 2386 u32 num_mcast_table_elems; 2387 u32 mcast2ucast_mode; 2388 u32 tx_dbg_log_size; 2389 u32 num_wds_entries; 2390 u32 dma_burst_size; 2391 u32 mac_aggr_delim; 2392 u32 rx_skip_defrag_timeout_dup_detection_check; 2393 u32 vow_config; 2394 u32 gtk_offload_max_vdev; 2395 u32 num_msdu_desc; 2396 u32 max_frag_entries; 2397 u32 max_peer_ext_stats; 2398 u32 smart_ant_cap; 2399 u32 bk_minfree; 2400 u32 be_minfree; 2401 u32 vi_minfree; 2402 u32 vo_minfree; 2403 u32 rx_batchmode; 2404 u32 tt_support; 2405 u32 atf_config; 2406 u32 iphdr_pad_config; 2407 u32 qwrap_config:16, 2408 alloc_frag_desc_for_data_pkt:16; 2409 u32 num_tdls_vdevs; 2410 u32 num_tdls_conn_table_entries; 2411 u32 beacon_tx_offload_max_vdev; 2412 u32 num_multicast_filter_entries; 2413 u32 num_wow_filters; 2414 u32 num_keep_alive_pattern; 2415 u32 keep_alive_pattern_size; 2416 u32 max_tdls_concurrent_sleep_sta; 2417 u32 max_tdls_concurrent_buffer_sta; 2418 u32 wmi_send_separate; 2419 u32 num_ocb_vdevs; 2420 u32 num_ocb_channels; 2421 u32 num_ocb_schedules; 2422 u32 num_ns_ext_tuples_cfg; 2423 u32 bpf_instruction_size; 2424 u32 max_bssid_rx_filters; 2425 u32 use_pdev_id; 2426 u32 peer_map_unmap_version; 2427 u32 sched_params; 2428 u32 twt_ap_pdev_count; 2429 u32 twt_ap_sta_count; 2430 enum ath12k_peer_metadata_version peer_metadata_ver; 2431 u32 ema_max_vap_cnt; 2432 u32 ema_max_profile_period; 2433 bool is_reg_cc_ext_event_supported; 2434 }; 2435 2436 struct ath12k_wmi_init_cmd_arg { 2437 struct ath12k_wmi_resource_config_arg res_cfg; 2438 u8 num_mem_chunks; 2439 struct ath12k_wmi_host_mem_chunk_arg *mem_chunks; 2440 u32 hw_mode_id; 2441 u32 num_band_to_mac; 2442 struct ath12k_wmi_pdev_band_arg band_to_mac[WMI_HOST_MAX_PDEV]; 2443 }; 2444 2445 struct ath12k_wmi_pdev_band_to_mac_params { 2446 __le32 tlv_header; 2447 __le32 pdev_id; 2448 __le32 start_freq; 2449 __le32 end_freq; 2450 } __packed; 2451 2452 /* This is both individual command WMI_PDEV_SET_HW_MODE_CMDID and also part 2453 * of WMI_TAG_INIT_CMD. 2454 */ 2455 struct ath12k_wmi_pdev_set_hw_mode_cmd { 2456 __le32 tlv_header; 2457 __le32 pdev_id; 2458 __le32 hw_mode_index; 2459 __le32 num_band_to_mac; 2460 } __packed; 2461 2462 struct ath12k_wmi_ppe_threshold_params { 2463 __le32 numss_m1; /** NSS - 1*/ 2464 __le32 ru_info; 2465 __le32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2466 } __packed; 2467 2468 #define HW_BD_INFO_SIZE 5 2469 2470 struct ath12k_wmi_abi_version_params { 2471 __le32 abi_version_0; 2472 __le32 abi_version_1; 2473 __le32 abi_version_ns_0; 2474 __le32 abi_version_ns_1; 2475 __le32 abi_version_ns_2; 2476 __le32 abi_version_ns_3; 2477 } __packed; 2478 2479 struct wmi_init_cmd { 2480 __le32 tlv_header; 2481 struct ath12k_wmi_abi_version_params host_abi_vers; 2482 __le32 num_host_mem_chunks; 2483 } __packed; 2484 2485 #define WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT 4 2486 #define WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT 12 2487 #define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_VERSION GENMASK(5, 4) 2488 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2489 #define WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2490 2491 struct ath12k_wmi_resource_config_params { 2492 __le32 tlv_header; 2493 __le32 num_vdevs; 2494 __le32 num_peers; 2495 __le32 num_offload_peers; 2496 __le32 num_offload_reorder_buffs; 2497 __le32 num_peer_keys; 2498 __le32 num_tids; 2499 __le32 ast_skid_limit; 2500 __le32 tx_chain_mask; 2501 __le32 rx_chain_mask; 2502 __le32 rx_timeout_pri[4]; 2503 __le32 rx_decap_mode; 2504 __le32 scan_max_pending_req; 2505 __le32 bmiss_offload_max_vdev; 2506 __le32 roam_offload_max_vdev; 2507 __le32 roam_offload_max_ap_profiles; 2508 __le32 num_mcast_groups; 2509 __le32 num_mcast_table_elems; 2510 __le32 mcast2ucast_mode; 2511 __le32 tx_dbg_log_size; 2512 __le32 num_wds_entries; 2513 __le32 dma_burst_size; 2514 __le32 mac_aggr_delim; 2515 __le32 rx_skip_defrag_timeout_dup_detection_check; 2516 __le32 vow_config; 2517 __le32 gtk_offload_max_vdev; 2518 __le32 num_msdu_desc; 2519 __le32 max_frag_entries; 2520 __le32 num_tdls_vdevs; 2521 __le32 num_tdls_conn_table_entries; 2522 __le32 beacon_tx_offload_max_vdev; 2523 __le32 num_multicast_filter_entries; 2524 __le32 num_wow_filters; 2525 __le32 num_keep_alive_pattern; 2526 __le32 keep_alive_pattern_size; 2527 __le32 max_tdls_concurrent_sleep_sta; 2528 __le32 max_tdls_concurrent_buffer_sta; 2529 __le32 wmi_send_separate; 2530 __le32 num_ocb_vdevs; 2531 __le32 num_ocb_channels; 2532 __le32 num_ocb_schedules; 2533 __le32 flag1; 2534 __le32 smart_ant_cap; 2535 __le32 bk_minfree; 2536 __le32 be_minfree; 2537 __le32 vi_minfree; 2538 __le32 vo_minfree; 2539 __le32 alloc_frag_desc_for_data_pkt; 2540 __le32 num_ns_ext_tuples_cfg; 2541 __le32 bpf_instruction_size; 2542 __le32 max_bssid_rx_filters; 2543 __le32 use_pdev_id; 2544 __le32 max_num_dbs_scan_duty_cycle; 2545 __le32 max_num_group_keys; 2546 __le32 peer_map_unmap_version; 2547 __le32 sched_params; 2548 __le32 twt_ap_pdev_count; 2549 __le32 twt_ap_sta_count; 2550 __le32 max_nlo_ssids; 2551 __le32 num_pkt_filters; 2552 __le32 num_max_sta_vdevs; 2553 __le32 max_bssid_indicator; 2554 __le32 ul_resp_config; 2555 __le32 msdu_flow_override_config0; 2556 __le32 msdu_flow_override_config1; 2557 __le32 flags2; 2558 __le32 host_service_flags; 2559 __le32 max_rnr_neighbours; 2560 __le32 ema_max_vap_cnt; 2561 __le32 ema_max_profile_period; 2562 } __packed; 2563 2564 struct wmi_service_ready_event { 2565 __le32 fw_build_vers; 2566 struct ath12k_wmi_abi_version_params fw_abi_vers; 2567 __le32 phy_capability; 2568 __le32 max_frag_entry; 2569 __le32 num_rf_chains; 2570 __le32 ht_cap_info; 2571 __le32 vht_cap_info; 2572 __le32 vht_supp_mcs; 2573 __le32 hw_min_tx_power; 2574 __le32 hw_max_tx_power; 2575 __le32 sys_cap_info; 2576 __le32 min_pkt_size_enable; 2577 __le32 max_bcn_ie_size; 2578 __le32 num_mem_reqs; 2579 __le32 max_num_scan_channels; 2580 __le32 hw_bd_id; 2581 __le32 hw_bd_info[HW_BD_INFO_SIZE]; 2582 __le32 max_supported_macs; 2583 __le32 wmi_fw_sub_feat_caps; 2584 __le32 num_dbs_hw_modes; 2585 /* txrx_chainmask 2586 * [7:0] - 2G band tx chain mask 2587 * [15:8] - 2G band rx chain mask 2588 * [23:16] - 5G band tx chain mask 2589 * [31:24] - 5G band rx chain mask 2590 */ 2591 __le32 txrx_chainmask; 2592 __le32 default_dbs_hw_mode_index; 2593 __le32 num_msdu_desc; 2594 } __packed; 2595 2596 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32)) 2597 2598 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */ 2599 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32)) 2600 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2601 #define WMI_SERVICE_BITS_IN_SIZE32 4 2602 2603 struct wmi_service_ready_ext_event { 2604 __le32 default_conc_scan_config_bits; 2605 __le32 default_fw_config_bits; 2606 struct ath12k_wmi_ppe_threshold_params ppet; 2607 __le32 he_cap_info; 2608 __le32 mpdu_density; 2609 __le32 max_bssid_rx_filters; 2610 __le32 fw_build_vers_ext; 2611 __le32 max_nlo_ssids; 2612 __le32 max_bssid_indicator; 2613 __le32 he_cap_info_ext; 2614 } __packed; 2615 2616 struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params { 2617 __le32 num_hw_modes; 2618 __le32 num_chainmask_tables; 2619 } __packed; 2620 2621 #define WMI_HW_MODE_CAP_CFG_TYPE GENMASK(27, 0) 2622 2623 struct ath12k_wmi_hw_mode_cap_params { 2624 __le32 tlv_header; 2625 __le32 hw_mode_id; 2626 __le32 phy_id_map; 2627 __le32 hw_mode_config_type; 2628 } __packed; 2629 2630 #define WMI_MAX_HECAP_PHY_SIZE (3) 2631 2632 /* pdev_id is present in lower 16 bits of pdev_and_hw_link_ids in 2633 * ath12k_wmi_mac_phy_caps_params & ath12k_wmi_caps_ext_params. 2634 * 2635 * hw_link_id is present in higher 16 bits of pdev_and_hw_link_ids. 2636 */ 2637 #define WMI_CAPS_PARAMS_PDEV_ID GENMASK(15, 0) 2638 #define WMI_CAPS_PARAMS_HW_LINK_ID GENMASK(31, 16) 2639 2640 struct ath12k_wmi_mac_phy_caps_params { 2641 __le32 hw_mode_id; 2642 __le32 pdev_and_hw_link_ids; 2643 __le32 phy_id; 2644 __le32 supported_flags; 2645 __le32 supported_bands; 2646 __le32 ampdu_density; 2647 __le32 max_bw_supported_2g; 2648 __le32 ht_cap_info_2g; 2649 __le32 vht_cap_info_2g; 2650 __le32 vht_supp_mcs_2g; 2651 __le32 he_cap_info_2g; 2652 __le32 he_supp_mcs_2g; 2653 __le32 tx_chain_mask_2g; 2654 __le32 rx_chain_mask_2g; 2655 __le32 max_bw_supported_5g; 2656 __le32 ht_cap_info_5g; 2657 __le32 vht_cap_info_5g; 2658 __le32 vht_supp_mcs_5g; 2659 __le32 he_cap_info_5g; 2660 __le32 he_supp_mcs_5g; 2661 __le32 tx_chain_mask_5g; 2662 __le32 rx_chain_mask_5g; 2663 __le32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2664 __le32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2665 struct ath12k_wmi_ppe_threshold_params he_ppet2g; 2666 struct ath12k_wmi_ppe_threshold_params he_ppet5g; 2667 __le32 chainmask_table_id; 2668 __le32 lmac_id; 2669 __le32 he_cap_info_2g_ext; 2670 __le32 he_cap_info_5g_ext; 2671 __le32 he_cap_info_internal; 2672 __le32 wireless_modes; 2673 __le32 low_2ghz_chan_freq; 2674 __le32 high_2ghz_chan_freq; 2675 __le32 low_5ghz_chan_freq; 2676 __le32 high_5ghz_chan_freq; 2677 __le32 nss_ratio; 2678 } __packed; 2679 2680 struct ath12k_wmi_hal_reg_caps_ext_params { 2681 __le32 tlv_header; 2682 __le32 phy_id; 2683 __le32 eeprom_reg_domain; 2684 __le32 eeprom_reg_domain_ext; 2685 __le32 regcap1; 2686 __le32 regcap2; 2687 __le32 wireless_modes; 2688 __le32 low_2ghz_chan; 2689 __le32 high_2ghz_chan; 2690 __le32 low_5ghz_chan; 2691 __le32 high_5ghz_chan; 2692 } __packed; 2693 2694 struct ath12k_wmi_soc_hal_reg_caps_params { 2695 __le32 num_phy; 2696 } __packed; 2697 2698 enum wmi_channel_width { 2699 WMI_CHAN_WIDTH_20 = 0, 2700 WMI_CHAN_WIDTH_40 = 1, 2701 WMI_CHAN_WIDTH_80 = 2, 2702 WMI_CHAN_WIDTH_160 = 3, 2703 WMI_CHAN_WIDTH_80P80 = 4, 2704 WMI_CHAN_WIDTH_5 = 5, 2705 WMI_CHAN_WIDTH_10 = 6, 2706 WMI_CHAN_WIDTH_165 = 7, 2707 WMI_CHAN_WIDTH_160P160 = 8, 2708 WMI_CHAN_WIDTH_320 = 9, 2709 }; 2710 2711 #define WMI_MAX_EHTCAP_MAC_SIZE 2 2712 #define WMI_MAX_EHTCAP_PHY_SIZE 3 2713 #define WMI_MAX_EHTCAP_RATE_SET 3 2714 2715 /* Used for EHT MCS-NSS array. Data at each array index follows the format given 2716 * in IEEE P802.11be/D2.0, May 20229.4.2.313.4. 2717 * 2718 * Index interpretation: 2719 * 0 - 20 MHz only sta, all 4 bytes valid 2720 * 1 - index for bandwidths <= 80 MHz except 20 MHz-only, first 3 bytes valid 2721 * 2 - index for 160 MHz, first 3 bytes valid 2722 * 3 - index for 320 MHz, first 3 bytes valid 2723 */ 2724 #define WMI_MAX_EHT_SUPP_MCS_2GHZ_SIZE 2 2725 #define WMI_MAX_EHT_SUPP_MCS_5GHZ_SIZE 4 2726 2727 #define WMI_EHTCAP_TXRX_MCS_NSS_IDX_80 0 2728 #define WMI_EHTCAP_TXRX_MCS_NSS_IDX_160 1 2729 #define WMI_EHTCAP_TXRX_MCS_NSS_IDX_320 2 2730 2731 #define WMI_EHT_MCS_NSS_0_7 GENMASK(3, 0) 2732 #define WMI_EHT_MCS_NSS_8_9 GENMASK(7, 4) 2733 #define WMI_EHT_MCS_NSS_10_11 GENMASK(11, 8) 2734 #define WMI_EHT_MCS_NSS_12_13 GENMASK(15, 12) 2735 2736 struct wmi_service_ready_ext2_event { 2737 __le32 reg_db_version; 2738 __le32 hw_min_max_tx_power_2ghz; 2739 __le32 hw_min_max_tx_power_5ghz; 2740 __le32 chwidth_num_peer_caps; 2741 __le32 preamble_puncture_bw; 2742 __le32 max_user_per_ppdu_ofdma; 2743 __le32 max_user_per_ppdu_mumimo; 2744 __le32 target_cap_flags; 2745 __le32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 2746 __le32 max_num_linkview_peers; 2747 __le32 max_num_msduq_supported_per_tid; 2748 __le32 default_num_msduq_supported_per_tid; 2749 } __packed; 2750 2751 struct ath12k_wmi_dbs_or_sbs_cap_params { 2752 __le32 hw_mode_id; 2753 __le32 sbs_lower_band_end_freq; 2754 } __packed; 2755 2756 struct ath12k_wmi_caps_ext_params { 2757 __le32 hw_mode_id; 2758 __le32 pdev_and_hw_link_ids; 2759 __le32 phy_id; 2760 __le32 wireless_modes_ext; 2761 __le32 eht_cap_mac_info_2ghz[WMI_MAX_EHTCAP_MAC_SIZE]; 2762 __le32 eht_cap_mac_info_5ghz[WMI_MAX_EHTCAP_MAC_SIZE]; 2763 __le32 rsvd0[2]; 2764 __le32 eht_cap_phy_info_2ghz[WMI_MAX_EHTCAP_PHY_SIZE]; 2765 __le32 eht_cap_phy_info_5ghz[WMI_MAX_EHTCAP_PHY_SIZE]; 2766 struct ath12k_wmi_ppe_threshold_params eht_ppet_2ghz; 2767 struct ath12k_wmi_ppe_threshold_params eht_ppet_5ghz; 2768 __le32 eht_cap_info_internal; 2769 __le32 eht_supp_mcs_ext_2ghz[WMI_MAX_EHT_SUPP_MCS_2GHZ_SIZE]; 2770 __le32 eht_supp_mcs_ext_5ghz[WMI_MAX_EHT_SUPP_MCS_5GHZ_SIZE]; 2771 __le32 eml_capability; 2772 __le32 mld_capability; 2773 } __packed; 2774 2775 /* 2 word representation of MAC addr */ 2776 struct ath12k_wmi_mac_addr_params { 2777 u8 addr[ETH_ALEN]; 2778 u8 padding[2]; 2779 } __packed; 2780 2781 struct ath12k_wmi_dma_ring_caps_params { 2782 __le32 tlv_header; 2783 __le32 pdev_id; 2784 __le32 module_id; 2785 __le32 min_elem; 2786 __le32 min_buf_sz; 2787 __le32 min_buf_align; 2788 } __packed; 2789 2790 struct ath12k_wmi_ready_event_min_params { 2791 struct ath12k_wmi_abi_version_params fw_abi_vers; 2792 struct ath12k_wmi_mac_addr_params mac_addr; 2793 __le32 status; 2794 __le32 num_dscp_table; 2795 __le32 num_extra_mac_addr; 2796 __le32 num_total_peers; 2797 __le32 num_extra_peers; 2798 } __packed; 2799 2800 struct wmi_ready_event { 2801 struct ath12k_wmi_ready_event_min_params ready_event_min; 2802 __le32 max_ast_index; 2803 __le32 pktlog_defs_checksum; 2804 } __packed; 2805 2806 struct wmi_service_available_event { 2807 __le32 wmi_service_segment_offset; 2808 __le32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2809 } __packed; 2810 2811 struct ath12k_wmi_vdev_create_arg { 2812 u8 if_id; 2813 u32 type; 2814 u32 subtype; 2815 struct { 2816 u8 tx; 2817 u8 rx; 2818 } chains[NUM_NL80211_BANDS]; 2819 u32 pdev_id; 2820 u8 if_stats_id; 2821 u32 mbssid_flags; 2822 u32 mbssid_tx_vdev_id; 2823 u8 mld_addr[ETH_ALEN]; 2824 }; 2825 2826 #define ATH12K_MAX_VDEV_STATS_ID 0x30 2827 #define ATH12K_INVAL_VDEV_STATS_ID 0xFF 2828 2829 struct wmi_vdev_create_cmd { 2830 __le32 tlv_header; 2831 __le32 vdev_id; 2832 __le32 vdev_type; 2833 __le32 vdev_subtype; 2834 struct ath12k_wmi_mac_addr_params vdev_macaddr; 2835 __le32 num_cfg_txrx_streams; 2836 __le32 pdev_id; 2837 __le32 mbssid_flags; 2838 __le32 mbssid_tx_vdev_id; 2839 __le32 vdev_stats_id_valid; 2840 __le32 vdev_stats_id; 2841 } __packed; 2842 2843 struct ath12k_wmi_vdev_txrx_streams_params { 2844 __le32 tlv_header; 2845 __le32 band; 2846 __le32 supported_tx_streams; 2847 __le32 supported_rx_streams; 2848 } __packed; 2849 2850 struct wmi_vdev_create_mlo_params { 2851 __le32 tlv_header; 2852 struct ath12k_wmi_mac_addr_params mld_macaddr; 2853 } __packed; 2854 2855 #define ATH12K_WMI_FLAG_MLO_ENABLED BIT(0) 2856 #define ATH12K_WMI_FLAG_MLO_ASSOC_LINK BIT(1) 2857 #define ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC BIT(2) 2858 #define ATH12K_WMI_FLAG_MLO_LOGICAL_LINK_IDX_VALID BIT(3) 2859 #define ATH12K_WMI_FLAG_MLO_PEER_ID_VALID BIT(4) 2860 #define ATH12K_WMI_FLAG_MLO_MCAST_VDEV BIT(5) 2861 #define ATH12K_WMI_FLAG_MLO_EMLSR_SUPPORT BIT(6) 2862 #define ATH12K_WMI_FLAG_MLO_FORCED_INACTIVE BIT(7) 2863 #define ATH12K_WMI_FLAG_MLO_LINK_ADD BIT(8) 2864 2865 struct wmi_vdev_start_mlo_params { 2866 __le32 tlv_header; 2867 __le32 flags; 2868 } __packed; 2869 2870 struct wmi_partner_link_info { 2871 __le32 tlv_header; 2872 __le32 vdev_id; 2873 __le32 hw_link_id; 2874 struct ath12k_wmi_mac_addr_params vdev_addr; 2875 } __packed; 2876 2877 struct wmi_vdev_delete_cmd { 2878 __le32 tlv_header; 2879 __le32 vdev_id; 2880 } __packed; 2881 2882 struct ath12k_wmi_vdev_up_params { 2883 u32 vdev_id; 2884 u32 aid; 2885 const u8 *bssid; 2886 const u8 *tx_bssid; 2887 u32 nontx_profile_idx; 2888 u32 nontx_profile_cnt; 2889 }; 2890 2891 struct wmi_vdev_up_cmd { 2892 __le32 tlv_header; 2893 __le32 vdev_id; 2894 __le32 vdev_assoc_id; 2895 struct ath12k_wmi_mac_addr_params vdev_bssid; 2896 struct ath12k_wmi_mac_addr_params tx_vdev_bssid; 2897 __le32 nontx_profile_idx; 2898 __le32 nontx_profile_cnt; 2899 } __packed; 2900 2901 struct wmi_vdev_stop_cmd { 2902 __le32 tlv_header; 2903 __le32 vdev_id; 2904 } __packed; 2905 2906 struct wmi_vdev_down_cmd { 2907 __le32 tlv_header; 2908 __le32 vdev_id; 2909 } __packed; 2910 2911 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2912 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2913 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2914 2915 #define ATH12K_WMI_SSID_LEN 32 2916 2917 struct ath12k_wmi_ssid_params { 2918 __le32 ssid_len; 2919 u8 ssid[ATH12K_WMI_SSID_LEN]; 2920 } __packed; 2921 2922 #define ATH12K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ) 2923 2924 enum wmi_vdev_mbssid_flags { 2925 WMI_VDEV_MBSSID_FLAGS_NON_MBSSID_AP = BIT(0), 2926 WMI_VDEV_MBSSID_FLAGS_TRANSMIT_AP = BIT(1), 2927 WMI_VDEV_MBSSID_FLAGS_NON_TRANSMIT_AP = BIT(2), 2928 WMI_VDEV_MBSSID_FLAGS_EMA_MODE = BIT(3), 2929 WMI_VDEV_MBSSID_FLAGS_SCAN_MODE_VAP = BIT(4), 2930 }; 2931 2932 struct wmi_vdev_start_request_cmd { 2933 __le32 tlv_header; 2934 __le32 vdev_id; 2935 __le32 requestor_id; 2936 __le32 beacon_interval; 2937 __le32 dtim_period; 2938 __le32 flags; 2939 struct ath12k_wmi_ssid_params ssid; 2940 __le32 bcn_tx_rate; 2941 __le32 bcn_txpower; 2942 __le32 num_noa_descriptors; 2943 __le32 disable_hw_ack; 2944 __le32 preferred_tx_streams; 2945 __le32 preferred_rx_streams; 2946 __le32 he_ops; 2947 __le32 cac_duration_ms; 2948 __le32 regdomain; 2949 __le32 min_data_rate; 2950 __le32 mbssid_flags; /* uses enum wmi_vdev_mbssid_flags */ 2951 __le32 mbssid_tx_vdev_id; 2952 __le32 eht_ops; 2953 __le32 punct_bitmap; 2954 } __packed; 2955 2956 #define MGMT_TX_DL_FRM_LEN 64 2957 2958 struct ath12k_wmi_channel_arg { 2959 u8 chan_id; 2960 u8 pwr; 2961 u32 mhz; 2962 u32 half_rate:1, 2963 quarter_rate:1, 2964 dfs_set:1, 2965 dfs_set_cfreq2:1, 2966 is_chan_passive:1, 2967 allow_ht:1, 2968 allow_vht:1, 2969 allow_he:1, 2970 set_agile:1, 2971 psc_channel:1; 2972 u32 phy_mode; 2973 u32 cfreq1; 2974 u32 cfreq2; 2975 char maxpower; 2976 char minpower; 2977 char maxregpower; 2978 u8 antennamax; 2979 u8 reg_class_id; 2980 }; 2981 2982 enum wmi_phy_mode { 2983 MODE_11A = 0, 2984 MODE_11G = 1, /* 11b/g Mode */ 2985 MODE_11B = 2, /* 11b Mode */ 2986 MODE_11GONLY = 3, /* 11g only Mode */ 2987 MODE_11NA_HT20 = 4, 2988 MODE_11NG_HT20 = 5, 2989 MODE_11NA_HT40 = 6, 2990 MODE_11NG_HT40 = 7, 2991 MODE_11AC_VHT20 = 8, 2992 MODE_11AC_VHT40 = 9, 2993 MODE_11AC_VHT80 = 10, 2994 MODE_11AC_VHT20_2G = 11, 2995 MODE_11AC_VHT40_2G = 12, 2996 MODE_11AC_VHT80_2G = 13, 2997 MODE_11AC_VHT80_80 = 14, 2998 MODE_11AC_VHT160 = 15, 2999 MODE_11AX_HE20 = 16, 3000 MODE_11AX_HE40 = 17, 3001 MODE_11AX_HE80 = 18, 3002 MODE_11AX_HE80_80 = 19, 3003 MODE_11AX_HE160 = 20, 3004 MODE_11AX_HE20_2G = 21, 3005 MODE_11AX_HE40_2G = 22, 3006 MODE_11AX_HE80_2G = 23, 3007 MODE_11BE_EHT20 = 24, 3008 MODE_11BE_EHT40 = 25, 3009 MODE_11BE_EHT80 = 26, 3010 MODE_11BE_EHT80_80 = 27, 3011 MODE_11BE_EHT160 = 28, 3012 MODE_11BE_EHT160_160 = 29, 3013 MODE_11BE_EHT320 = 30, 3014 MODE_11BE_EHT20_2G = 31, 3015 MODE_11BE_EHT40_2G = 32, 3016 MODE_UNKNOWN = 33, 3017 MODE_MAX = 33, 3018 }; 3019 3020 #define ATH12K_WMI_MLO_MAX_LINKS 4 3021 3022 struct wmi_ml_partner_info { 3023 u32 vdev_id; 3024 u32 hw_link_id; 3025 u8 addr[ETH_ALEN]; 3026 bool assoc_link; 3027 bool primary_umac; 3028 bool logical_link_idx_valid; 3029 u32 logical_link_idx; 3030 }; 3031 3032 struct wmi_ml_arg { 3033 bool enabled; 3034 bool assoc_link; 3035 bool mcast_link; 3036 bool link_add; 3037 u8 num_partner_links; 3038 struct wmi_ml_partner_info partner_info[ATH12K_WMI_MLO_MAX_LINKS]; 3039 }; 3040 3041 struct wmi_vdev_start_req_arg { 3042 u32 vdev_id; 3043 u32 freq; 3044 u32 band_center_freq1; 3045 u32 band_center_freq2; 3046 bool passive; 3047 bool allow_ibss; 3048 bool allow_ht; 3049 bool allow_vht; 3050 bool ht40plus; 3051 bool chan_radar; 3052 bool freq2_radar; 3053 bool allow_he; 3054 u32 min_power; 3055 u32 max_power; 3056 u32 max_reg_power; 3057 u32 max_antenna_gain; 3058 enum wmi_phy_mode mode; 3059 u32 bcn_intval; 3060 u32 dtim_period; 3061 u8 *ssid; 3062 u32 ssid_len; 3063 u32 bcn_tx_rate; 3064 u32 bcn_tx_power; 3065 bool disable_hw_ack; 3066 bool hidden_ssid; 3067 bool pmf_enabled; 3068 u32 he_ops; 3069 u32 cac_duration_ms; 3070 u32 regdomain; 3071 u32 pref_rx_streams; 3072 u32 pref_tx_streams; 3073 u32 num_noa_descriptors; 3074 u32 min_data_rate; 3075 u32 mbssid_flags; 3076 u32 mbssid_tx_vdev_id; 3077 u32 punct_bitmap; 3078 struct wmi_ml_arg ml; 3079 }; 3080 3081 struct ath12k_wmi_peer_create_arg { 3082 const u8 *peer_addr; 3083 u32 peer_type; 3084 u32 vdev_id; 3085 bool ml_enabled; 3086 }; 3087 3088 struct wmi_peer_create_mlo_params { 3089 __le32 tlv_header; 3090 __le32 flags; 3091 }; 3092 3093 struct ath12k_wmi_pdev_set_regdomain_arg { 3094 u16 current_rd_in_use; 3095 u16 current_rd_2g; 3096 u16 current_rd_5g; 3097 u32 ctl_2g; 3098 u32 ctl_5g; 3099 u8 dfs_domain; 3100 u32 pdev_id; 3101 }; 3102 3103 struct ath12k_wmi_rx_reorder_queue_remove_arg { 3104 u8 *peer_macaddr; 3105 u16 vdev_id; 3106 u32 peer_tid_bitmap; 3107 }; 3108 3109 #define WMI_HOST_PDEV_ID_SOC 0xFF 3110 #define WMI_HOST_PDEV_ID_0 0 3111 #define WMI_HOST_PDEV_ID_1 1 3112 #define WMI_HOST_PDEV_ID_2 2 3113 3114 #define WMI_PDEV_ID_SOC 0 3115 #define WMI_PDEV_ID_1ST 1 3116 #define WMI_PDEV_ID_2ND 2 3117 #define WMI_PDEV_ID_3RD 3 3118 3119 /* Freq units in MHz */ 3120 #define REG_RULE_START_FREQ 0x0000ffff 3121 #define REG_RULE_END_FREQ 0xffff0000 3122 #define REG_RULE_FLAGS 0x0000ffff 3123 #define REG_RULE_MAX_BW 0x0000ffff 3124 #define REG_RULE_REG_PWR 0x00ff0000 3125 #define REG_RULE_ANT_GAIN 0xff000000 3126 #define REG_RULE_PSD_INFO BIT(2) 3127 #define REG_RULE_PSD_EIRP 0xffff0000 3128 3129 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 3130 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 3131 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 3132 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 3133 3134 #define HECAP_PHYDWORD_0 0 3135 #define HECAP_PHYDWORD_1 1 3136 #define HECAP_PHYDWORD_2 2 3137 3138 #define HECAP_PHY_SU_BFER BIT(31) 3139 #define HECAP_PHY_SU_BFEE BIT(0) 3140 #define HECAP_PHY_MU_BFER BIT(1) 3141 #define HECAP_PHY_UL_MUMIMO BIT(22) 3142 #define HECAP_PHY_UL_MUOFDMA BIT(23) 3143 3144 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 3145 u32_get_bits(hecap_phy[HECAP_PHYDWORD_0], HECAP_PHY_SU_BFER) 3146 3147 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 3148 u32_get_bits(hecap_phy[HECAP_PHYDWORD_1], HECAP_PHY_SU_BFEE) 3149 3150 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 3151 u32_get_bits(hecap_phy[HECAP_PHYDWORD_1], HECAP_PHY_MU_BFER) 3152 3153 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 3154 u32_get_bits(hecap_phy[HECAP_PHYDWORD_0], HECAP_PHY_UL_MUMIMO) 3155 3156 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 3157 u32_get_bits(hecap_phy[HECAP_PHYDWORD_0], HECAP_PHY_UL_MUOFDMA) 3158 3159 #define HE_MODE_SU_TX_BFEE BIT(0) 3160 #define HE_MODE_SU_TX_BFER BIT(1) 3161 #define HE_MODE_MU_TX_BFEE BIT(2) 3162 #define HE_MODE_MU_TX_BFER BIT(3) 3163 #define HE_MODE_DL_OFDMA BIT(4) 3164 #define HE_MODE_UL_OFDMA BIT(5) 3165 #define HE_MODE_UL_MUMIMO BIT(6) 3166 3167 #define HE_DL_MUOFDMA_ENABLE 1 3168 #define HE_UL_MUOFDMA_ENABLE 1 3169 #define HE_DL_MUMIMO_ENABLE 1 3170 #define HE_MU_BFEE_ENABLE 1 3171 #define HE_SU_BFEE_ENABLE 1 3172 3173 #define HE_VHT_SOUNDING_MODE_ENABLE 1 3174 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 3175 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 3176 3177 /* HE or VHT Sounding */ 3178 #define HE_VHT_SOUNDING_MODE BIT(0) 3179 /* SU or MU Sounding */ 3180 #define HE_SU_MU_SOUNDING_MODE BIT(2) 3181 /* Trig or Non-Trig Sounding */ 3182 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 3183 3184 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 3185 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 3186 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 3187 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 3188 3189 enum wmi_peer_type { 3190 WMI_PEER_TYPE_DEFAULT = 0, 3191 WMI_PEER_TYPE_BSS = 1, 3192 WMI_PEER_TYPE_TDLS = 2, 3193 }; 3194 3195 struct wmi_peer_create_cmd { 3196 __le32 tlv_header; 3197 __le32 vdev_id; 3198 struct ath12k_wmi_mac_addr_params peer_macaddr; 3199 __le32 peer_type; 3200 } __packed; 3201 3202 struct wmi_peer_delete_cmd { 3203 __le32 tlv_header; 3204 __le32 vdev_id; 3205 struct ath12k_wmi_mac_addr_params peer_macaddr; 3206 } __packed; 3207 3208 struct wmi_peer_reorder_queue_setup_cmd { 3209 __le32 tlv_header; 3210 __le32 vdev_id; 3211 struct ath12k_wmi_mac_addr_params peer_macaddr; 3212 __le32 tid; 3213 __le32 queue_ptr_lo; 3214 __le32 queue_ptr_hi; 3215 __le32 queue_no; 3216 __le32 ba_window_size_valid; 3217 __le32 ba_window_size; 3218 } __packed; 3219 3220 struct wmi_peer_reorder_queue_remove_cmd { 3221 __le32 tlv_header; 3222 __le32 vdev_id; 3223 struct ath12k_wmi_mac_addr_params peer_macaddr; 3224 __le32 tid_mask; 3225 } __packed; 3226 3227 enum wmi_bss_chan_info_req_type { 3228 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3229 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3230 }; 3231 3232 struct wmi_pdev_set_param_cmd { 3233 __le32 tlv_header; 3234 __le32 pdev_id; 3235 __le32 param_id; 3236 __le32 param_value; 3237 } __packed; 3238 3239 struct wmi_pdev_set_ps_mode_cmd { 3240 __le32 tlv_header; 3241 __le32 vdev_id; 3242 __le32 sta_ps_mode; 3243 } __packed; 3244 3245 struct wmi_pdev_suspend_cmd { 3246 __le32 tlv_header; 3247 __le32 pdev_id; 3248 __le32 suspend_opt; 3249 } __packed; 3250 3251 struct wmi_pdev_resume_cmd { 3252 __le32 tlv_header; 3253 __le32 pdev_id; 3254 } __packed; 3255 3256 struct wmi_pdev_bss_chan_info_req_cmd { 3257 __le32 tlv_header; 3258 /* ref wmi_bss_chan_info_req_type */ 3259 __le32 req_type; 3260 __le32 pdev_id; 3261 } __packed; 3262 3263 struct wmi_ap_ps_peer_cmd { 3264 __le32 tlv_header; 3265 __le32 vdev_id; 3266 struct ath12k_wmi_mac_addr_params peer_macaddr; 3267 __le32 param; 3268 __le32 value; 3269 } __packed; 3270 3271 struct wmi_sta_powersave_param_cmd { 3272 __le32 tlv_header; 3273 __le32 vdev_id; 3274 __le32 param; 3275 __le32 value; 3276 } __packed; 3277 3278 struct wmi_pdev_set_regdomain_cmd { 3279 __le32 tlv_header; 3280 __le32 pdev_id; 3281 __le32 reg_domain; 3282 __le32 reg_domain_2g; 3283 __le32 reg_domain_5g; 3284 __le32 conformance_test_limit_2g; 3285 __le32 conformance_test_limit_5g; 3286 __le32 dfs_domain; 3287 } __packed; 3288 3289 struct wmi_peer_set_param_cmd { 3290 __le32 tlv_header; 3291 __le32 vdev_id; 3292 struct ath12k_wmi_mac_addr_params peer_macaddr; 3293 __le32 param_id; 3294 __le32 param_value; 3295 } __packed; 3296 3297 struct wmi_peer_flush_tids_cmd { 3298 __le32 tlv_header; 3299 __le32 vdev_id; 3300 struct ath12k_wmi_mac_addr_params peer_macaddr; 3301 __le32 peer_tid_bitmap; 3302 } __packed; 3303 3304 struct wmi_dfs_phyerr_offload_cmd { 3305 __le32 tlv_header; 3306 __le32 pdev_id; 3307 } __packed; 3308 3309 struct wmi_bcn_offload_ctrl_cmd { 3310 __le32 tlv_header; 3311 __le32 vdev_id; 3312 __le32 bcn_ctrl_op; 3313 } __packed; 3314 3315 enum scan_dwelltime_adaptive_mode { 3316 SCAN_DWELL_MODE_DEFAULT = 0, 3317 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3318 SCAN_DWELL_MODE_MODERATE = 2, 3319 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3320 SCAN_DWELL_MODE_STATIC = 4 3321 }; 3322 3323 #define WLAN_SCAN_MAX_NUM_SSID 10 3324 #define WLAN_SCAN_MAX_NUM_BSSID 10 3325 3326 struct ath12k_wmi_element_info_arg { 3327 u32 len; 3328 u8 *ptr; 3329 }; 3330 3331 #define WMI_IE_BITMAP_SIZE 8 3332 3333 #define WMI_SCAN_MAX_NUM_SSID 0x0A 3334 /* prefix used by scan requestor ids on the host */ 3335 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3336 3337 /* prefix used by scan request ids generated on the host */ 3338 /* host cycles through the lower 12 bits to generate ids */ 3339 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3340 3341 #define WLAN_SCAN_PARAMS_MAX_SSID 16 3342 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 3343 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 512 3344 3345 /* Values lower than this may be refused by some firmware revisions with a scan 3346 * completion with a timedout reason. 3347 */ 3348 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3349 3350 /* Scan priority numbers must be sequential, starting with 0 */ 3351 enum wmi_scan_priority { 3352 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3353 WMI_SCAN_PRIORITY_LOW, 3354 WMI_SCAN_PRIORITY_MEDIUM, 3355 WMI_SCAN_PRIORITY_HIGH, 3356 WMI_SCAN_PRIORITY_VERY_HIGH, 3357 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3358 }; 3359 3360 enum wmi_scan_event_type { 3361 WMI_SCAN_EVENT_STARTED = BIT(0), 3362 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3363 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3364 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3365 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3366 /* possibly by high-prio scan */ 3367 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3368 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3369 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3370 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3371 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3372 WMI_SCAN_EVENT_RESUMED = BIT(10), 3373 WMI_SCAN_EVENT_MAX = BIT(15), 3374 }; 3375 3376 enum wmi_scan_completion_reason { 3377 WMI_SCAN_REASON_COMPLETED, 3378 WMI_SCAN_REASON_CANCELLED, 3379 WMI_SCAN_REASON_PREEMPTED, 3380 WMI_SCAN_REASON_TIMEDOUT, 3381 WMI_SCAN_REASON_INTERNAL_FAILURE, 3382 WMI_SCAN_REASON_MAX, 3383 }; 3384 3385 struct wmi_start_scan_cmd { 3386 __le32 tlv_header; 3387 __le32 scan_id; 3388 __le32 scan_req_id; 3389 __le32 vdev_id; 3390 __le32 scan_priority; 3391 __le32 notify_scan_events; 3392 __le32 dwell_time_active; 3393 __le32 dwell_time_passive; 3394 __le32 min_rest_time; 3395 __le32 max_rest_time; 3396 __le32 repeat_probe_time; 3397 __le32 probe_spacing_time; 3398 __le32 idle_time; 3399 __le32 max_scan_time; 3400 __le32 probe_delay; 3401 __le32 scan_ctrl_flags; 3402 __le32 burst_duration; 3403 __le32 num_chan; 3404 __le32 num_bssid; 3405 __le32 num_ssids; 3406 __le32 ie_len; 3407 __le32 n_probes; 3408 struct ath12k_wmi_mac_addr_params mac_addr; 3409 struct ath12k_wmi_mac_addr_params mac_mask; 3410 u32 ie_bitmap[WMI_IE_BITMAP_SIZE]; 3411 __le32 num_vendor_oui; 3412 __le32 scan_ctrl_flags_ext; 3413 __le32 dwell_time_active_2g; 3414 __le32 dwell_time_active_6g; 3415 __le32 dwell_time_passive_6g; 3416 __le32 scan_start_offset; 3417 } __packed; 3418 3419 #define WMI_SCAN_FLAG_PASSIVE 0x1 3420 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3421 #define WMI_SCAN_ADD_CCK_RATES 0x4 3422 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3423 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3424 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3425 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3426 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3427 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3428 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3429 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3430 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3431 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3432 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3433 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3434 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3435 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3436 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3437 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3438 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3439 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3440 3441 #define WMI_SCAN_DWELL_MODE_MASK GENMASK(23, 21) 3442 3443 enum { 3444 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3445 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3446 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3447 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3448 WMI_SCAN_DWELL_MODE_STATIC = 4, 3449 }; 3450 3451 struct ath12k_wmi_hint_short_ssid_arg { 3452 u32 freq_flags; 3453 u32 short_ssid; 3454 }; 3455 3456 struct ath12k_wmi_hint_bssid_arg { 3457 u32 freq_flags; 3458 struct ath12k_wmi_mac_addr_params bssid; 3459 }; 3460 3461 struct ath12k_wmi_scan_req_arg { 3462 u32 scan_id; 3463 u32 scan_req_id; 3464 u32 vdev_id; 3465 u32 pdev_id; 3466 enum wmi_scan_priority scan_priority; 3467 u32 scan_ev_started:1, 3468 scan_ev_completed:1, 3469 scan_ev_bss_chan:1, 3470 scan_ev_foreign_chan:1, 3471 scan_ev_dequeued:1, 3472 scan_ev_preempted:1, 3473 scan_ev_start_failed:1, 3474 scan_ev_restarted:1, 3475 scan_ev_foreign_chn_exit:1, 3476 scan_ev_invalid:1, 3477 scan_ev_gpio_timeout:1, 3478 scan_ev_suspended:1, 3479 scan_ev_resumed:1; 3480 u32 dwell_time_active; 3481 u32 dwell_time_active_2g; 3482 u32 dwell_time_passive; 3483 u32 dwell_time_active_6g; 3484 u32 dwell_time_passive_6g; 3485 u32 min_rest_time; 3486 u32 max_rest_time; 3487 u32 repeat_probe_time; 3488 u32 probe_spacing_time; 3489 u32 idle_time; 3490 u32 max_scan_time; 3491 u32 probe_delay; 3492 u32 scan_f_passive:1, 3493 scan_f_bcast_probe:1, 3494 scan_f_cck_rates:1, 3495 scan_f_ofdm_rates:1, 3496 scan_f_chan_stat_evnt:1, 3497 scan_f_filter_prb_req:1, 3498 scan_f_bypass_dfs_chn:1, 3499 scan_f_continue_on_err:1, 3500 scan_f_offchan_mgmt_tx:1, 3501 scan_f_offchan_data_tx:1, 3502 scan_f_promisc_mode:1, 3503 scan_f_capture_phy_err:1, 3504 scan_f_strict_passive_pch:1, 3505 scan_f_half_rate:1, 3506 scan_f_quarter_rate:1, 3507 scan_f_force_active_dfs_chn:1, 3508 scan_f_add_tpc_ie_in_probe:1, 3509 scan_f_add_ds_ie_in_probe:1, 3510 scan_f_add_spoofed_mac_in_probe:1, 3511 scan_f_add_rand_seq_in_probe:1, 3512 scan_f_en_ie_whitelist_in_probe:1, 3513 scan_f_forced:1, 3514 scan_f_2ghz:1, 3515 scan_f_5ghz:1, 3516 scan_f_80mhz:1; 3517 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3518 u32 burst_duration; 3519 u32 num_chan; 3520 u32 num_bssid; 3521 u32 num_ssids; 3522 u32 n_probes; 3523 u32 *chan_list; 3524 u32 notify_scan_events; 3525 struct cfg80211_ssid ssid[WLAN_SCAN_MAX_NUM_SSID]; 3526 struct ath12k_wmi_mac_addr_params bssid_list[WLAN_SCAN_MAX_NUM_BSSID]; 3527 struct ath12k_wmi_element_info_arg extraie; 3528 u32 num_hint_s_ssid; 3529 u32 num_hint_bssid; 3530 struct ath12k_wmi_hint_short_ssid_arg hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3531 struct ath12k_wmi_hint_bssid_arg hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3532 }; 3533 3534 struct wmi_ssid_arg { 3535 int len; 3536 const u8 *ssid; 3537 }; 3538 3539 struct wmi_bssid_arg { 3540 const u8 *bssid; 3541 }; 3542 3543 #define WMI_SCAN_STOP_ONE 0x00000000 3544 #define WMI_SCAN_STOP_VAP_ALL 0x01000000 3545 #define WMI_SCAN_STOP_ALL 0x04000000 3546 3547 /* Prefix 0xA000 indicates that the scan request 3548 * is trigger by HOST 3549 */ 3550 #define ATH12K_SCAN_ID 0xA000 3551 3552 enum scan_cancel_req_type { 3553 WLAN_SCAN_CANCEL_SINGLE = 1, 3554 WLAN_SCAN_CANCEL_VDEV_ALL, 3555 WLAN_SCAN_CANCEL_PDEV_ALL, 3556 }; 3557 3558 struct ath12k_wmi_scan_cancel_arg { 3559 u32 requester; 3560 u32 scan_id; 3561 enum scan_cancel_req_type req_type; 3562 u32 vdev_id; 3563 u32 pdev_id; 3564 }; 3565 3566 struct wmi_bcn_send_from_host_cmd { 3567 __le32 tlv_header; 3568 __le32 vdev_id; 3569 __le32 data_len; 3570 union { 3571 __le32 frag_ptr; 3572 __le32 frag_ptr_lo; 3573 }; 3574 __le32 frame_ctrl; 3575 __le32 dtim_flag; 3576 __le32 bcn_antenna; 3577 __le32 frag_ptr_hi; 3578 }; 3579 3580 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3581 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3582 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3583 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3584 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3585 #define WMI_CHAN_INFO_DFS BIT(10) 3586 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3587 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3588 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3589 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3590 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3591 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3592 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3593 #define WMI_CHAN_INFO_PSC BIT(18) 3594 3595 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3596 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3597 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3598 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3599 3600 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3601 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3602 3603 struct ath12k_wmi_channel_params { 3604 __le32 tlv_header; 3605 __le32 mhz; 3606 __le32 band_center_freq1; 3607 __le32 band_center_freq2; 3608 __le32 info; 3609 __le32 reg_info_1; 3610 __le32 reg_info_2; 3611 } __packed; 3612 3613 enum wmi_sta_ps_mode { 3614 WMI_STA_PS_MODE_DISABLED = 0, 3615 WMI_STA_PS_MODE_ENABLED = 1, 3616 }; 3617 3618 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3619 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3620 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3621 3622 #define ATH12K_WMI_FW_HANG_ASSERT_TYPE 1 3623 #define ATH12K_WMI_FW_HANG_DELAY 0 3624 3625 /* type, 0:unused 1: ASSERT 2: not respond detect command 3626 * delay_time_ms, the simulate will delay time 3627 */ 3628 3629 struct wmi_force_fw_hang_cmd { 3630 __le32 tlv_header; 3631 __le32 type; 3632 __le32 delay_time_ms; 3633 } __packed; 3634 3635 struct wmi_vdev_set_param_cmd { 3636 __le32 tlv_header; 3637 __le32 vdev_id; 3638 __le32 param_id; 3639 __le32 param_value; 3640 } __packed; 3641 3642 struct wmi_get_pdev_temperature_cmd { 3643 __le32 tlv_header; 3644 __le32 param; 3645 __le32 pdev_id; 3646 } __packed; 3647 3648 #define WMI_P2P_MAX_NOA_DESCRIPTORS 4 3649 3650 struct wmi_p2p_noa_event { 3651 __le32 vdev_id; 3652 } __packed; 3653 3654 struct ath12k_wmi_p2p_noa_descriptor { 3655 __le32 type_count; /* 255: continuous schedule, 0: reserved */ 3656 __le32 duration; /* Absent period duration in micro seconds */ 3657 __le32 interval; /* Absent period interval in micro seconds */ 3658 __le32 start_time; /* 32 bit tsf time when in starts */ 3659 } __packed; 3660 3661 #define WMI_P2P_NOA_INFO_CHANGED_FLAG BIT(0) 3662 #define WMI_P2P_NOA_INFO_INDEX GENMASK(15, 8) 3663 #define WMI_P2P_NOA_INFO_OPP_PS BIT(16) 3664 #define WMI_P2P_NOA_INFO_CTWIN_TU GENMASK(23, 17) 3665 #define WMI_P2P_NOA_INFO_DESC_NUM GENMASK(31, 24) 3666 3667 struct ath12k_wmi_p2p_noa_info { 3668 /* Bit 0 - Flag to indicate an update in NOA schedule 3669 * Bits 7-1 - Reserved 3670 * Bits 15-8 - Index (identifies the instance of NOA sub element) 3671 * Bit 16 - Opp PS state of the AP 3672 * Bits 23-17 - Ctwindow in TUs 3673 * Bits 31-24 - Number of NOA descriptors 3674 */ 3675 __le32 noa_attr; 3676 struct ath12k_wmi_p2p_noa_descriptor descriptors[WMI_P2P_MAX_NOA_DESCRIPTORS]; 3677 } __packed; 3678 3679 #define MAX_WMI_UTF_LEN 252 3680 3681 struct ath12k_wmi_ftm_seg_hdr_params { 3682 __le32 len; 3683 __le32 msgref; 3684 __le32 segmentinfo; 3685 __le32 pdev_id; 3686 } __packed; 3687 3688 struct ath12k_wmi_ftm_cmd { 3689 __le32 tlv_header; 3690 struct ath12k_wmi_ftm_seg_hdr_params seg_hdr; 3691 u8 data[]; 3692 } __packed; 3693 3694 struct ath12k_wmi_ftm_event { 3695 struct ath12k_wmi_ftm_seg_hdr_params seg_hdr; 3696 u8 data[]; 3697 } __packed; 3698 3699 #define WMI_BEACON_TX_BUFFER_SIZE 512 3700 3701 #define WMI_EMA_BEACON_CNT GENMASK(7, 0) 3702 #define WMI_EMA_BEACON_IDX GENMASK(15, 8) 3703 #define WMI_EMA_BEACON_FIRST GENMASK(23, 16) 3704 #define WMI_EMA_BEACON_LAST GENMASK(31, 24) 3705 3706 struct ath12k_wmi_bcn_tmpl_ema_arg { 3707 u8 bcn_cnt; 3708 u8 bcn_index; 3709 }; 3710 3711 struct wmi_bcn_tmpl_cmd { 3712 __le32 tlv_header; 3713 __le32 vdev_id; 3714 __le32 tim_ie_offset; 3715 __le32 buf_len; 3716 __le32 csa_switch_count_offset; 3717 __le32 ext_csa_switch_count_offset; 3718 __le32 csa_event_bitmap; 3719 __le32 mbssid_ie_offset; 3720 __le32 esp_ie_offset; 3721 __le32 csc_switch_count_offset; 3722 __le32 csc_event_bitmap; 3723 __le32 mu_edca_ie_offset; 3724 __le32 feature_enable_bitmap; 3725 __le32 ema_params; 3726 } __packed; 3727 3728 struct wmi_p2p_go_set_beacon_ie_cmd { 3729 __le32 tlv_header; 3730 __le32 vdev_id; 3731 __le32 ie_buf_len; 3732 } __packed; 3733 3734 struct wmi_vdev_install_key_cmd { 3735 __le32 tlv_header; 3736 __le32 vdev_id; 3737 struct ath12k_wmi_mac_addr_params peer_macaddr; 3738 __le32 key_idx; 3739 __le32 key_flags; 3740 __le32 key_cipher; 3741 __le64 key_rsc_counter; 3742 __le64 key_global_rsc_counter; 3743 __le64 key_tsc_counter; 3744 u8 wpi_key_rsc_counter[16]; 3745 u8 wpi_key_tsc_counter[16]; 3746 __le32 key_len; 3747 __le32 key_txmic_len; 3748 __le32 key_rxmic_len; 3749 __le32 is_group_key_id_valid; 3750 __le32 group_key_id; 3751 3752 /* Followed by key_data containing key followed by 3753 * tx mic and then rx mic 3754 */ 3755 } __packed; 3756 3757 struct wmi_vdev_install_key_arg { 3758 u32 vdev_id; 3759 const u8 *macaddr; 3760 u32 key_idx; 3761 u32 key_flags; 3762 u32 key_cipher; 3763 u32 ieee80211_key_cipher; 3764 u32 key_len; 3765 u32 key_txmic_len; 3766 u32 key_rxmic_len; 3767 u64 key_rsc_counter; 3768 const void *key_data; 3769 }; 3770 3771 #define WMI_MAX_SUPPORTED_RATES 128 3772 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3773 #define WMI_HOST_MAX_HE_RATE_SET 3 3774 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3775 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3776 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3777 3778 #define ATH12K_WMI_MLO_MAX_PARTNER_LINKS \ 3779 (ATH12K_WMI_MLO_MAX_LINKS + ATH12K_MAX_NUM_BRIDGE_LINKS - 1) 3780 3781 struct peer_assoc_mlo_params { 3782 bool enabled; 3783 bool assoc_link; 3784 bool primary_umac; 3785 bool peer_id_valid; 3786 bool logical_link_idx_valid; 3787 bool bridge_peer; 3788 u8 mld_addr[ETH_ALEN]; 3789 u32 logical_link_idx; 3790 u32 ml_peer_id; 3791 u32 ieee_link_id; 3792 u8 num_partner_links; 3793 struct wmi_ml_partner_info partner_info[ATH12K_WMI_MLO_MAX_LINKS]; 3794 u16 eml_cap; 3795 }; 3796 3797 struct wmi_rate_set_arg { 3798 u32 num_rates; 3799 u8 rates[WMI_MAX_SUPPORTED_RATES]; 3800 }; 3801 3802 struct ath12k_wmi_peer_assoc_arg { 3803 u32 vdev_id; 3804 u32 peer_new_assoc; 3805 u32 peer_associd; 3806 u32 peer_flags; 3807 u32 peer_caps; 3808 u32 peer_listen_intval; 3809 u32 peer_ht_caps; 3810 u32 peer_max_mpdu; 3811 u32 peer_mpdu_density; 3812 u32 peer_rate_caps; 3813 u32 peer_nss; 3814 u32 peer_vht_caps; 3815 u32 peer_phymode; 3816 u32 peer_ht_info[2]; 3817 struct wmi_rate_set_arg peer_legacy_rates; 3818 struct wmi_rate_set_arg peer_ht_rates; 3819 u32 rx_max_rate; 3820 u32 rx_mcs_set; 3821 u32 tx_max_rate; 3822 u32 tx_mcs_set; 3823 u8 vht_capable; 3824 u8 min_data_rate; 3825 u32 tx_max_mcs_nss; 3826 u32 peer_bw_rxnss_override; 3827 bool is_pmf_enabled; 3828 bool is_wme_set; 3829 bool qos_flag; 3830 bool apsd_flag; 3831 bool ht_flag; 3832 bool bw_40; 3833 bool bw_80; 3834 bool bw_160; 3835 bool bw_320; 3836 bool stbc_flag; 3837 bool ldpc_flag; 3838 bool static_mimops_flag; 3839 bool dynamic_mimops_flag; 3840 bool spatial_mux_flag; 3841 bool vht_flag; 3842 bool vht_ng_flag; 3843 bool need_ptk_4_way; 3844 bool need_gtk_2_way; 3845 bool auth_flag; 3846 bool safe_mode_enabled; 3847 bool amsdu_disable; 3848 /* Use common structure */ 3849 u8 peer_mac[ETH_ALEN]; 3850 3851 bool he_flag; 3852 u32 peer_he_cap_macinfo[2]; 3853 u32 peer_he_cap_macinfo_internal; 3854 u32 peer_he_caps_6ghz; 3855 u32 peer_he_ops; 3856 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3857 u32 peer_he_mcs_count; 3858 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3859 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3860 bool twt_responder; 3861 bool twt_requester; 3862 struct ath12k_wmi_ppe_threshold_arg peer_ppet; 3863 bool eht_flag; 3864 u32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE]; 3865 u32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE]; 3866 u32 peer_eht_mcs_count; 3867 u32 peer_eht_rx_mcs_set[WMI_MAX_EHTCAP_RATE_SET]; 3868 u32 peer_eht_tx_mcs_set[WMI_MAX_EHTCAP_RATE_SET]; 3869 struct ath12k_wmi_ppe_threshold_arg peer_eht_ppet; 3870 u32 punct_bitmap; 3871 bool is_assoc; 3872 struct peer_assoc_mlo_params ml; 3873 bool eht_disable_mcs15; 3874 }; 3875 3876 #define ATH12K_WMI_FLAG_MLO_ENABLED BIT(0) 3877 #define ATH12K_WMI_FLAG_MLO_ASSOC_LINK BIT(1) 3878 #define ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC BIT(2) 3879 #define ATH12K_WMI_FLAG_MLO_LINK_ID_VALID BIT(3) 3880 #define ATH12K_WMI_FLAG_MLO_PEER_ID_VALID BIT(4) 3881 3882 struct wmi_peer_assoc_mlo_partner_info_params { 3883 __le32 tlv_header; 3884 __le32 vdev_id; 3885 __le32 hw_link_id; 3886 __le32 flags; 3887 __le32 logical_link_idx; 3888 } __packed; 3889 3890 struct wmi_peer_assoc_mlo_params { 3891 __le32 tlv_header; 3892 __le32 flags; 3893 struct ath12k_wmi_mac_addr_params mld_addr; 3894 __le32 logical_link_idx; 3895 __le32 ml_peer_id; 3896 __le32 ieee_link_id; 3897 __le32 emlsr_trans_timeout_us; 3898 __le32 emlsr_trans_delay_us; 3899 __le32 emlsr_padding_delay_us; 3900 } __packed; 3901 3902 struct wmi_peer_assoc_complete_cmd { 3903 __le32 tlv_header; 3904 struct ath12k_wmi_mac_addr_params peer_macaddr; 3905 __le32 vdev_id; 3906 __le32 peer_new_assoc; 3907 __le32 peer_associd; 3908 __le32 peer_flags; 3909 __le32 peer_caps; 3910 __le32 peer_listen_intval; 3911 __le32 peer_ht_caps; 3912 __le32 peer_max_mpdu; 3913 __le32 peer_mpdu_density; 3914 __le32 peer_rate_caps; 3915 __le32 peer_nss; 3916 __le32 peer_vht_caps; 3917 __le32 peer_phymode; 3918 __le32 peer_ht_info[2]; 3919 __le32 num_peer_legacy_rates; 3920 __le32 num_peer_ht_rates; 3921 __le32 peer_bw_rxnss_override; 3922 struct ath12k_wmi_ppe_threshold_params peer_ppet; 3923 __le32 peer_he_cap_info; 3924 __le32 peer_he_ops; 3925 __le32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3926 __le32 peer_he_mcs; 3927 __le32 peer_he_cap_info_ext; 3928 __le32 peer_he_cap_info_internal; 3929 __le32 min_data_rate; 3930 __le32 peer_he_caps_6ghz; 3931 __le32 sta_type; 3932 __le32 bss_max_idle_option; 3933 __le32 auth_mode; 3934 __le32 peer_flags_ext; 3935 __le32 punct_bitmap; 3936 __le32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE]; 3937 __le32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE]; 3938 __le32 peer_eht_ops; 3939 struct ath12k_wmi_ppe_threshold_params peer_eht_ppet; 3940 } __packed; 3941 3942 struct wmi_stop_scan_cmd { 3943 __le32 tlv_header; 3944 __le32 requestor; 3945 __le32 scan_id; 3946 __le32 req_type; 3947 __le32 vdev_id; 3948 __le32 pdev_id; 3949 } __packed; 3950 3951 struct ath12k_wmi_scan_chan_list_arg { 3952 struct list_head list; 3953 u32 pdev_id; 3954 u16 nallchans; 3955 struct ath12k_wmi_channel_arg channel[]; 3956 }; 3957 3958 struct wmi_scan_chan_list_cmd { 3959 __le32 tlv_header; 3960 __le32 num_scan_chans; 3961 __le32 flags; 3962 __le32 pdev_id; 3963 } __packed; 3964 3965 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3966 3967 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3968 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3969 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3970 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3971 3972 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3973 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3974 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3975 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3976 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3977 3978 struct wmi_mgmt_send_cmd { 3979 __le32 tlv_header; 3980 __le32 vdev_id; 3981 __le32 desc_id; 3982 __le32 chanfreq; 3983 __le32 paddr_lo; 3984 __le32 paddr_hi; 3985 __le32 frame_len; 3986 __le32 buf_len; 3987 __le32 tx_params_valid; 3988 3989 /* This TLV is followed by struct wmi_mgmt_frame */ 3990 3991 /* Followed by struct wmi_mgmt_send_params */ 3992 } __packed; 3993 3994 struct wmi_sta_powersave_mode_cmd { 3995 __le32 tlv_header; 3996 __le32 vdev_id; 3997 __le32 sta_ps_mode; 3998 } __packed; 3999 4000 struct wmi_sta_smps_force_mode_cmd { 4001 __le32 tlv_header; 4002 __le32 vdev_id; 4003 __le32 forced_mode; 4004 } __packed; 4005 4006 struct wmi_sta_smps_param_cmd { 4007 __le32 tlv_header; 4008 __le32 vdev_id; 4009 __le32 param; 4010 __le32 value; 4011 } __packed; 4012 4013 struct ath12k_wmi_bcn_prb_info_params { 4014 __le32 tlv_header; 4015 __le32 caps; 4016 __le32 erp; 4017 } __packed; 4018 4019 enum { 4020 WMI_PDEV_SUSPEND, 4021 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 4022 }; 4023 4024 struct wmi_pdev_green_ap_ps_enable_cmd_param { 4025 __le32 tlv_header; 4026 __le32 pdev_id; 4027 __le32 enable; 4028 } __packed; 4029 4030 struct ath12k_wmi_ap_ps_arg { 4031 u32 vdev_id; 4032 u32 param; 4033 u32 value; 4034 }; 4035 4036 enum set_init_cc_type { 4037 WMI_COUNTRY_INFO_TYPE_ALPHA, 4038 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 4039 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 4040 }; 4041 4042 enum set_init_cc_flags { 4043 INVALID_CC, 4044 CC_IS_SET, 4045 REGDMN_IS_SET, 4046 ALPHA_IS_SET, 4047 }; 4048 4049 struct ath12k_wmi_init_country_arg { 4050 union { 4051 u16 country_code; 4052 u16 regdom_id; 4053 u8 alpha2[3]; 4054 } cc_info; 4055 enum set_init_cc_flags flags; 4056 }; 4057 4058 struct wmi_init_country_cmd { 4059 __le32 tlv_header; 4060 __le32 pdev_id; 4061 __le32 init_cc_type; 4062 union { 4063 __le32 country_code; 4064 __le32 regdom_id; 4065 __le32 alpha2; 4066 } cc_info; 4067 } __packed; 4068 4069 struct wmi_11d_scan_start_arg { 4070 u32 vdev_id; 4071 u32 scan_period_msec; 4072 u32 start_interval_msec; 4073 }; 4074 4075 struct wmi_11d_scan_start_cmd { 4076 __le32 tlv_header; 4077 __le32 vdev_id; 4078 __le32 scan_period_msec; 4079 __le32 start_interval_msec; 4080 } __packed; 4081 4082 struct wmi_11d_scan_stop_cmd { 4083 __le32 tlv_header; 4084 __le32 vdev_id; 4085 } __packed; 4086 4087 struct wmi_11d_new_cc_event { 4088 __le32 new_alpha2; 4089 } __packed; 4090 4091 struct wmi_delba_send_cmd { 4092 __le32 tlv_header; 4093 __le32 vdev_id; 4094 struct ath12k_wmi_mac_addr_params peer_macaddr; 4095 __le32 tid; 4096 __le32 initiator; 4097 __le32 reasoncode; 4098 } __packed; 4099 4100 struct wmi_addba_setresponse_cmd { 4101 __le32 tlv_header; 4102 __le32 vdev_id; 4103 struct ath12k_wmi_mac_addr_params peer_macaddr; 4104 __le32 tid; 4105 __le32 statuscode; 4106 } __packed; 4107 4108 struct wmi_addba_send_cmd { 4109 __le32 tlv_header; 4110 __le32 vdev_id; 4111 struct ath12k_wmi_mac_addr_params peer_macaddr; 4112 __le32 tid; 4113 __le32 buffersize; 4114 } __packed; 4115 4116 struct wmi_addba_clear_resp_cmd { 4117 __le32 tlv_header; 4118 __le32 vdev_id; 4119 struct ath12k_wmi_mac_addr_params peer_macaddr; 4120 } __packed; 4121 4122 #define DFS_PHYERR_UNIT_TEST_CMD 0 4123 #define DFS_UNIT_TEST_MODULE 0x2b 4124 #define DFS_UNIT_TEST_TOKEN 0xAA 4125 4126 enum dfs_test_args_idx { 4127 DFS_TEST_CMDID = 0, 4128 DFS_TEST_PDEV_ID, 4129 DFS_TEST_RADAR_PARAM, 4130 DFS_MAX_TEST_ARGS, 4131 }; 4132 4133 struct wmi_dfs_unit_test_arg { 4134 u32 cmd_id; 4135 u32 pdev_id; 4136 u32 radar_param; 4137 }; 4138 4139 struct wmi_unit_test_cmd { 4140 __le32 tlv_header; 4141 __le32 vdev_id; 4142 __le32 module_id; 4143 __le32 num_args; 4144 __le32 diag_token; 4145 /* Followed by test args*/ 4146 } __packed; 4147 4148 #define MAX_SUPPORTED_RATES 128 4149 4150 struct ath12k_wmi_vht_rate_set_params { 4151 __le32 tlv_header; 4152 __le32 rx_max_rate; 4153 __le32 rx_mcs_set; 4154 __le32 tx_max_rate; 4155 __le32 tx_mcs_set; 4156 __le32 tx_max_mcs_nss; 4157 } __packed; 4158 4159 struct ath12k_wmi_he_rate_set_params { 4160 __le32 tlv_header; 4161 __le32 rx_mcs_set; 4162 __le32 tx_mcs_set; 4163 } __packed; 4164 4165 struct ath12k_wmi_eht_rate_set_params { 4166 __le32 tlv_header; 4167 __le32 rx_mcs_set; 4168 __le32 tx_mcs_set; 4169 } __packed; 4170 4171 #define MAX_REG_RULES 10 4172 #define REG_ALPHA2_LEN 2 4173 #define MAX_6GHZ_REG_RULES 5 4174 4175 struct wmi_set_current_country_arg { 4176 u8 alpha2[REG_ALPHA2_LEN]; 4177 }; 4178 4179 struct wmi_set_current_country_cmd { 4180 __le32 tlv_header; 4181 __le32 pdev_id; 4182 __le32 new_alpha2; 4183 } __packed; 4184 4185 enum wmi_start_event_param { 4186 WMI_VDEV_START_RESP_EVENT = 0, 4187 WMI_VDEV_RESTART_RESP_EVENT, 4188 }; 4189 4190 struct wmi_vdev_start_resp_event { 4191 __le32 vdev_id; 4192 __le32 requestor_id; 4193 /* enum wmi_start_event_param */ 4194 __le32 resp_type; 4195 __le32 status; 4196 __le32 chain_mask; 4197 __le32 smps_mode; 4198 union { 4199 __le32 mac_id; 4200 __le32 pdev_id; 4201 }; 4202 __le32 cfgd_tx_streams; 4203 __le32 cfgd_rx_streams; 4204 __le32 max_allowed_tx_power; 4205 } __packed; 4206 4207 /* VDEV start response status codes */ 4208 enum wmi_vdev_start_resp_status_code { 4209 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4210 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4211 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4212 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4213 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4214 }; 4215 4216 enum wmi_reg_6g_ap_type { 4217 WMI_REG_INDOOR_AP = 0, 4218 WMI_REG_STD_POWER_AP = 1, 4219 WMI_REG_VLP_AP = 2, 4220 WMI_REG_CURRENT_MAX_AP_TYPE, 4221 WMI_REG_MAX_SUPP_AP_TYPE = WMI_REG_VLP_AP, 4222 WMI_REG_MAX_AP_TYPE = 7, 4223 }; 4224 4225 enum wmi_reg_6g_client_type { 4226 WMI_REG_DEFAULT_CLIENT = 0, 4227 WMI_REG_SUBORDINATE_CLIENT = 1, 4228 WMI_REG_MAX_CLIENT_TYPE = 2, 4229 }; 4230 4231 /* Regulatory Rule Flags Passed by FW */ 4232 #define REGULATORY_CHAN_DISABLED BIT(0) 4233 #define REGULATORY_CHAN_NO_IR BIT(1) 4234 #define REGULATORY_CHAN_RADAR BIT(3) 4235 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4236 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4237 4238 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4239 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4240 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4241 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4242 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4243 4244 enum { 4245 WMI_REG_SET_CC_STATUS_PASS = 0, 4246 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4247 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4248 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4249 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4250 WMI_REG_SET_CC_STATUS_FAIL = 5, 4251 }; 4252 4253 #define WMI_REG_CLIENT_MAX 4 4254 4255 struct wmi_reg_chan_list_cc_ext_event { 4256 __le32 status_code; 4257 __le32 phy_id; 4258 __le32 alpha2; 4259 __le32 num_phy; 4260 __le32 country_id; 4261 __le32 domain_code; 4262 __le32 dfs_region; 4263 __le32 phybitmap; 4264 __le32 min_bw_2g; 4265 __le32 max_bw_2g; 4266 __le32 min_bw_5g; 4267 __le32 max_bw_5g; 4268 __le32 num_2g_reg_rules; 4269 __le32 num_5g_reg_rules; 4270 __le32 client_type; 4271 __le32 rnr_tpe_usable; 4272 __le32 unspecified_ap_usable; 4273 __le32 domain_code_6g_ap_lpi; 4274 __le32 domain_code_6g_ap_sp; 4275 __le32 domain_code_6g_ap_vlp; 4276 __le32 domain_code_6g_client_lpi[WMI_REG_CLIENT_MAX]; 4277 __le32 domain_code_6g_client_sp[WMI_REG_CLIENT_MAX]; 4278 __le32 domain_code_6g_client_vlp[WMI_REG_CLIENT_MAX]; 4279 __le32 domain_code_6g_super_id; 4280 __le32 min_bw_6g_ap_sp; 4281 __le32 max_bw_6g_ap_sp; 4282 __le32 min_bw_6g_ap_lpi; 4283 __le32 max_bw_6g_ap_lpi; 4284 __le32 min_bw_6g_ap_vlp; 4285 __le32 max_bw_6g_ap_vlp; 4286 __le32 min_bw_6g_client_sp[WMI_REG_CLIENT_MAX]; 4287 __le32 max_bw_6g_client_sp[WMI_REG_CLIENT_MAX]; 4288 __le32 min_bw_6g_client_lpi[WMI_REG_CLIENT_MAX]; 4289 __le32 max_bw_6g_client_lpi[WMI_REG_CLIENT_MAX]; 4290 __le32 min_bw_6g_client_vlp[WMI_REG_CLIENT_MAX]; 4291 __le32 max_bw_6g_client_vlp[WMI_REG_CLIENT_MAX]; 4292 __le32 num_6g_reg_rules_ap_sp; 4293 __le32 num_6g_reg_rules_ap_lpi; 4294 __le32 num_6g_reg_rules_ap_vlp; 4295 __le32 num_6g_reg_rules_cl_sp[WMI_REG_CLIENT_MAX]; 4296 __le32 num_6g_reg_rules_cl_lpi[WMI_REG_CLIENT_MAX]; 4297 __le32 num_6g_reg_rules_cl_vlp[WMI_REG_CLIENT_MAX]; 4298 } __packed; 4299 4300 struct ath12k_wmi_reg_rule_ext_params { 4301 __le32 tlv_header; 4302 __le32 freq_info; 4303 __le32 bw_pwr_info; 4304 __le32 flag_info; 4305 __le32 psd_power_info; 4306 } __packed; 4307 4308 struct wmi_vdev_delete_resp_event { 4309 __le32 vdev_id; 4310 } __packed; 4311 4312 struct wmi_peer_delete_resp_event { 4313 __le32 vdev_id; 4314 struct ath12k_wmi_mac_addr_params peer_macaddr; 4315 } __packed; 4316 4317 struct wmi_bcn_tx_status_event { 4318 __le32 vdev_id; 4319 __le32 tx_status; 4320 } __packed; 4321 4322 struct wmi_vdev_stopped_event { 4323 __le32 vdev_id; 4324 } __packed; 4325 4326 struct wmi_pdev_bss_chan_info_event { 4327 __le32 freq; /* Units in MHz */ 4328 __le32 noise_floor; /* units are dBm */ 4329 /* rx clear - how often the channel was unused */ 4330 __le32 rx_clear_count_low; 4331 __le32 rx_clear_count_high; 4332 /* cycle count - elapsed time during measured period, in clock ticks */ 4333 __le32 cycle_count_low; 4334 __le32 cycle_count_high; 4335 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4336 __le32 tx_cycle_count_low; 4337 __le32 tx_cycle_count_high; 4338 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4339 __le32 rx_cycle_count_low; 4340 __le32 rx_cycle_count_high; 4341 /*rx_cycle cnt for my bss in 64bits format */ 4342 __le32 rx_bss_cycle_count_low; 4343 __le32 rx_bss_cycle_count_high; 4344 __le32 pdev_id; 4345 } __packed; 4346 4347 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4348 4349 struct wmi_vdev_install_key_compl_event { 4350 __le32 vdev_id; 4351 struct ath12k_wmi_mac_addr_params peer_macaddr; 4352 __le32 key_idx; 4353 __le32 key_flags; 4354 __le32 status; 4355 } __packed; 4356 4357 struct wmi_vdev_install_key_complete_arg { 4358 u32 vdev_id; 4359 const u8 *macaddr; 4360 u32 key_idx; 4361 u32 key_flags; 4362 u32 status; 4363 }; 4364 4365 struct wmi_peer_assoc_conf_event { 4366 __le32 vdev_id; 4367 struct ath12k_wmi_mac_addr_params peer_macaddr; 4368 } __packed; 4369 4370 struct wmi_peer_assoc_conf_arg { 4371 u32 vdev_id; 4372 const u8 *macaddr; 4373 }; 4374 4375 struct wmi_fils_discovery_event { 4376 __le32 vdev_id; 4377 __le32 fils_tt; 4378 __le32 tbtt; 4379 } __packed; 4380 4381 struct wmi_probe_resp_tx_status_event { 4382 __le32 vdev_id; 4383 __le32 tx_status; 4384 } __packed; 4385 4386 struct wmi_pdev_ctl_failsafe_chk_event { 4387 __le32 pdev_id; 4388 __le32 ctl_failsafe_status; 4389 } __packed; 4390 4391 struct ath12k_wmi_pdev_csa_event { 4392 __le32 pdev_id; 4393 __le32 current_switch_count; 4394 __le32 num_vdevs; 4395 } __packed; 4396 4397 struct ath12k_wmi_pdev_radar_event { 4398 __le32 pdev_id; 4399 __le32 detection_mode; 4400 __le32 chan_freq; 4401 __le32 chan_width; 4402 __le32 detector_id; 4403 __le32 segment_id; 4404 __le32 timestamp; 4405 __le32 is_chirp; 4406 a_sle32 freq_offset; 4407 a_sle32 sidx; 4408 } __packed; 4409 4410 struct wmi_pdev_temperature_event { 4411 /* temperature value in Celsius degree */ 4412 a_sle32 temp; 4413 __le32 pdev_id; 4414 } __packed; 4415 4416 #define WMI_RX_STATUS_OK 0x00 4417 #define WMI_RX_STATUS_ERR_CRC 0x01 4418 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4419 #define WMI_RX_STATUS_ERR_MIC 0x10 4420 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4421 4422 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4423 4424 struct ath12k_wmi_mgmt_rx_arg { 4425 u32 chan_freq; 4426 u32 channel; 4427 u32 snr; 4428 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4429 u32 rate; 4430 enum wmi_phy_mode phy_mode; 4431 u32 buf_len; 4432 int status; 4433 u32 flags; 4434 int rssi; 4435 u32 tsf_delta; 4436 u8 pdev_id; 4437 }; 4438 4439 #define ATH_MAX_ANTENNA 4 4440 4441 struct ath12k_wmi_mgmt_rx_params { 4442 __le32 channel; 4443 __le32 snr; 4444 __le32 rate; 4445 __le32 phy_mode; 4446 __le32 buf_len; 4447 __le32 status; 4448 __le32 rssi_ctl[ATH_MAX_ANTENNA]; 4449 __le32 flags; 4450 a_sle32 rssi; 4451 __le32 tsf_delta; 4452 __le32 rx_tsf_l32; 4453 __le32 rx_tsf_u32; 4454 __le32 pdev_id; 4455 __le32 chan_freq; 4456 } __packed; 4457 4458 #define MAX_ANTENNA_EIGHT 8 4459 4460 struct wmi_mgmt_tx_compl_event { 4461 __le32 desc_id; 4462 __le32 status; 4463 __le32 pdev_id; 4464 } __packed; 4465 4466 struct wmi_scan_event { 4467 __le32 event_type; /* %WMI_SCAN_EVENT_ */ 4468 __le32 reason; /* %WMI_SCAN_REASON_ */ 4469 __le32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4470 __le32 scan_req_id; 4471 __le32 scan_id; 4472 __le32 vdev_id; 4473 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4474 * In case of AP it is TSF of the AP vdev 4475 * In case of STA connected state, this is the TSF of the AP 4476 * In case of STA not connected, it will be the free running HW timer 4477 */ 4478 __le32 tsf_timestamp; 4479 } __packed; 4480 4481 struct wmi_peer_sta_kickout_arg { 4482 const u8 *mac_addr; 4483 }; 4484 4485 struct wmi_peer_sta_kickout_event { 4486 struct ath12k_wmi_mac_addr_params peer_macaddr; 4487 } __packed; 4488 4489 #define WMI_ROAM_REASON_MASK GENMASK(3, 0) 4490 #define WMI_ROAM_SUBNET_STATUS_MASK GENMASK(5, 4) 4491 4492 enum wmi_roam_reason { 4493 WMI_ROAM_REASON_BETTER_AP = 1, 4494 WMI_ROAM_REASON_BEACON_MISS = 2, 4495 WMI_ROAM_REASON_LOW_RSSI = 3, 4496 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4497 WMI_ROAM_REASON_HO_FAILED = 5, 4498 4499 /* keep last */ 4500 WMI_ROAM_REASON_MAX, 4501 }; 4502 4503 struct wmi_roam_event { 4504 __le32 vdev_id; 4505 __le32 reason; 4506 __le32 rssi; 4507 } __packed; 4508 4509 #define WMI_CHAN_INFO_START_RESP 0 4510 #define WMI_CHAN_INFO_END_RESP 1 4511 4512 struct wmi_chan_info_event { 4513 __le32 err_code; 4514 __le32 freq; 4515 __le32 cmd_flags; 4516 __le32 noise_floor; 4517 __le32 rx_clear_count; 4518 __le32 cycle_count; 4519 __le32 chan_tx_pwr_range; 4520 __le32 chan_tx_pwr_tp; 4521 __le32 rx_frame_count; 4522 __le32 my_bss_rx_cycle_count; 4523 __le32 rx_11b_mode_data_duration; 4524 __le32 tx_frame_cnt; 4525 __le32 mac_clk_mhz; 4526 __le32 vdev_id; 4527 } __packed; 4528 4529 struct ath12k_wmi_target_cap_arg { 4530 u32 phy_capability; 4531 u32 max_frag_entry; 4532 u32 num_rf_chains; 4533 u32 ht_cap_info; 4534 u32 vht_cap_info; 4535 u32 vht_supp_mcs; 4536 u32 hw_min_tx_power; 4537 u32 hw_max_tx_power; 4538 u32 sys_cap_info; 4539 u32 min_pkt_size_enable; 4540 u32 max_bcn_ie_size; 4541 u32 max_num_scan_channels; 4542 u32 max_supported_macs; 4543 u32 wmi_fw_sub_feat_caps; 4544 u32 txrx_chainmask; 4545 u32 default_dbs_hw_mode_index; 4546 u32 num_msdu_desc; 4547 }; 4548 4549 enum wmi_vdev_type { 4550 WMI_VDEV_TYPE_UNSPEC = 0, 4551 WMI_VDEV_TYPE_AP = 1, 4552 WMI_VDEV_TYPE_STA = 2, 4553 WMI_VDEV_TYPE_IBSS = 3, 4554 WMI_VDEV_TYPE_MONITOR = 4, 4555 }; 4556 4557 enum wmi_vdev_subtype { 4558 WMI_VDEV_SUBTYPE_NONE, 4559 WMI_VDEV_SUBTYPE_P2P_DEVICE, 4560 WMI_VDEV_SUBTYPE_P2P_CLIENT, 4561 WMI_VDEV_SUBTYPE_P2P_GO, 4562 WMI_VDEV_SUBTYPE_PROXY_STA, 4563 WMI_VDEV_SUBTYPE_MESH_NON_11S, 4564 WMI_VDEV_SUBTYPE_MESH_11S, 4565 }; 4566 4567 enum wmi_sta_powersave_param { 4568 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 4569 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 4570 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 4571 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 4572 WMI_STA_PS_PARAM_UAPSD = 4, 4573 }; 4574 4575 enum wmi_sta_ps_param_uapsd { 4576 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4577 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4578 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4579 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4580 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4581 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4582 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4583 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4584 }; 4585 4586 enum wmi_sta_ps_param_tx_wake_threshold { 4587 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 4588 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 4589 4590 /* Values greater than one indicate that many TX attempts per beacon 4591 * interval before the STA will wake up 4592 */ 4593 }; 4594 4595 /* The maximum number of PS-Poll frames the FW will send in response to 4596 * traffic advertised in TIM before waking up (by sending a null frame with PS 4597 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 4598 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 4599 * parameter is used when the RX wake policy is 4600 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 4601 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 4602 */ 4603 enum wmi_sta_ps_param_pspoll_count { 4604 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 4605 /* Values greater than 0 indicate the maximum number of PS-Poll frames 4606 * FW will send before waking up. 4607 */ 4608 }; 4609 4610 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 4611 enum wmi_ap_ps_param_uapsd { 4612 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4613 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4614 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4615 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4616 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4617 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4618 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4619 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4620 }; 4621 4622 /* U-APSD maximum service period of peer station */ 4623 enum wmi_ap_ps_peer_param_max_sp { 4624 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 4625 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 4626 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 4627 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 4628 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 4629 }; 4630 4631 enum wmi_ap_ps_peer_param { 4632 /** Set uapsd configuration for a given peer. 4633 * 4634 * This include the delivery and trigger enabled state for each AC. 4635 * The host MLME needs to set this based on AP capability and stations 4636 * request Set in the association request received from the station. 4637 * 4638 * Lower 8 bits of the value specify the UAPSD configuration. 4639 * 4640 * (see enum wmi_ap_ps_param_uapsd) 4641 * The default value is 0. 4642 */ 4643 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 4644 4645 /** 4646 * Set the service period for a UAPSD capable station 4647 * 4648 * The service period from wme ie in the (re)assoc request frame. 4649 * 4650 * (see enum wmi_ap_ps_peer_param_max_sp) 4651 */ 4652 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 4653 4654 /** Time in seconds for aging out buffered frames 4655 * for STA in power save 4656 */ 4657 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 4658 4659 /** Specify frame types that are considered SIFS 4660 * RESP trigger frame 4661 */ 4662 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 4663 4664 /** Specifies the trigger state of TID. 4665 * Valid only for UAPSD frame type 4666 */ 4667 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 4668 4669 /* Specifies the WNM sleep state of a STA */ 4670 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 4671 }; 4672 4673 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 4674 4675 #define WMI_MAX_KEY_INDEX 3 4676 #define WMI_MAX_KEY_LEN 32 4677 4678 enum wmi_key_type { 4679 WMI_KEY_PAIRWISE = 0, 4680 WMI_KEY_GROUP = 1, 4681 }; 4682 4683 enum wmi_cipher_type { 4684 WMI_CIPHER_NONE = 0, /* clear key */ 4685 WMI_CIPHER_WEP = 1, 4686 WMI_CIPHER_TKIP = 2, 4687 WMI_CIPHER_AES_OCB = 3, 4688 WMI_CIPHER_AES_CCM = 4, 4689 WMI_CIPHER_WAPI = 5, 4690 WMI_CIPHER_CKIP = 6, 4691 WMI_CIPHER_AES_CMAC = 7, 4692 WMI_CIPHER_ANY = 8, 4693 WMI_CIPHER_AES_GCM = 9, 4694 WMI_CIPHER_AES_GMAC = 10, 4695 }; 4696 4697 /* Value to disable fixed rate setting */ 4698 #define WMI_FIXED_RATE_NONE (0xffff) 4699 4700 #define ATH12K_RC_VERSION_OFFSET 28 4701 #define ATH12K_RC_PREAMBLE_OFFSET 8 4702 #define ATH12K_RC_NSS_OFFSET 5 4703 4704 #define ATH12K_HW_RATE_CODE(rate, nss, preamble) \ 4705 ((1 << ATH12K_RC_VERSION_OFFSET) | \ 4706 ((nss) << ATH12K_RC_NSS_OFFSET) | \ 4707 ((preamble) << ATH12K_RC_PREAMBLE_OFFSET) | \ 4708 (rate)) 4709 4710 /* Preamble types to be used with VDEV fixed rate configuration */ 4711 enum wmi_rate_preamble { 4712 WMI_RATE_PREAMBLE_OFDM, 4713 WMI_RATE_PREAMBLE_CCK, 4714 WMI_RATE_PREAMBLE_HT, 4715 WMI_RATE_PREAMBLE_VHT, 4716 WMI_RATE_PREAMBLE_HE, 4717 WMI_RATE_PREAMBLE_EHT, 4718 }; 4719 4720 /** 4721 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 4722 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 4723 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 4724 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 4725 */ 4726 enum wmi_rtscts_prot_mode { 4727 WMI_RTS_CTS_DISABLED = 0, 4728 WMI_USE_RTS_CTS = 1, 4729 WMI_USE_CTS2SELF = 2, 4730 }; 4731 4732 /** 4733 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 4734 * protection mode. 4735 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 4736 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 4737 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 4738 * but if there's a sw retry, both the rate 4739 * series will use RTS-CTS. 4740 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 4741 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 4742 */ 4743 enum wmi_rtscts_profile { 4744 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 4745 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 4746 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 4747 WMI_RTSCTS_ERP = 3, 4748 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 4749 }; 4750 4751 #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr) 4752 4753 enum wmi_sta_ps_param_rx_wake_policy { 4754 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 4755 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 4756 }; 4757 4758 /* Do not change existing values! Used by ath12k_frame_mode parameter 4759 * module parameter. 4760 */ 4761 enum ath12k_hw_txrx_mode { 4762 ATH12K_HW_TXRX_RAW = 0, 4763 ATH12K_HW_TXRX_NATIVE_WIFI = 1, 4764 ATH12K_HW_TXRX_ETHERNET = 2, 4765 }; 4766 4767 struct wmi_wmm_params { 4768 __le32 tlv_header; 4769 __le32 cwmin; 4770 __le32 cwmax; 4771 __le32 aifs; 4772 __le32 txoplimit; 4773 __le32 acm; 4774 __le32 no_ack; 4775 } __packed; 4776 4777 struct wmi_wmm_params_arg { 4778 u8 acm; 4779 u8 aifs; 4780 u16 cwmin; 4781 u16 cwmax; 4782 u16 txop; 4783 u8 no_ack; 4784 }; 4785 4786 struct wmi_vdev_set_wmm_params_cmd { 4787 __le32 tlv_header; 4788 __le32 vdev_id; 4789 struct wmi_wmm_params wmm_params[4]; 4790 __le32 wmm_param_type; 4791 } __packed; 4792 4793 struct wmi_wmm_params_all_arg { 4794 struct wmi_wmm_params_arg ac_be; 4795 struct wmi_wmm_params_arg ac_bk; 4796 struct wmi_wmm_params_arg ac_vi; 4797 struct wmi_wmm_params_arg ac_vo; 4798 }; 4799 4800 #define ATH12K_TWT_DEF_STA_CONG_TIMER_MS 5000 4801 #define ATH12K_TWT_DEF_DEFAULT_SLOT_SIZE 10 4802 #define ATH12K_TWT_DEF_CONGESTION_THRESH_SETUP 50 4803 #define ATH12K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 4804 #define ATH12K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 4805 #define ATH12K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 4806 #define ATH12K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 4807 #define ATH12K_TWT_DEF_MIN_NO_STA_SETUP 10 4808 #define ATH12K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 4809 #define ATH12K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 4810 #define ATH12K_TWT_DEF_MIN_NO_TWT_SLOTS 2 4811 #define ATH12K_TWT_DEF_MAX_NO_STA_TWT 500 4812 #define ATH12K_TWT_DEF_MODE_CHECK_INTERVAL 10000 4813 #define ATH12K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 4814 #define ATH12K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 4815 4816 struct wmi_twt_enable_params_cmd { 4817 __le32 tlv_header; 4818 __le32 pdev_id; 4819 __le32 sta_cong_timer_ms; 4820 __le32 mbss_support; 4821 __le32 default_slot_size; 4822 __le32 congestion_thresh_setup; 4823 __le32 congestion_thresh_teardown; 4824 __le32 congestion_thresh_critical; 4825 __le32 interference_thresh_teardown; 4826 __le32 interference_thresh_setup; 4827 __le32 min_no_sta_setup; 4828 __le32 min_no_sta_teardown; 4829 __le32 no_of_bcast_mcast_slots; 4830 __le32 min_no_twt_slots; 4831 __le32 max_no_sta_twt; 4832 __le32 mode_check_interval; 4833 __le32 add_sta_slot_interval; 4834 __le32 remove_sta_slot_interval; 4835 } __packed; 4836 4837 struct wmi_twt_disable_params_cmd { 4838 __le32 tlv_header; 4839 __le32 pdev_id; 4840 } __packed; 4841 4842 struct wmi_obss_spatial_reuse_params_cmd { 4843 __le32 tlv_header; 4844 __le32 pdev_id; 4845 __le32 enable; 4846 a_sle32 obss_min; 4847 a_sle32 obss_max; 4848 __le32 vdev_id; 4849 } __packed; 4850 4851 #define ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 4852 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 4853 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION 1 4854 4855 #define ATH12K_BSS_COLOR_STA_PERIODS 10000 4856 #define ATH12K_BSS_COLOR_AP_PERIODS 5000 4857 4858 struct wmi_obss_color_collision_cfg_params_cmd { 4859 __le32 tlv_header; 4860 __le32 vdev_id; 4861 __le32 flags; 4862 __le32 evt_type; 4863 __le32 current_bss_color; 4864 __le32 detection_period_ms; 4865 __le32 scan_period_ms; 4866 __le32 free_slot_expiry_time_ms; 4867 } __packed; 4868 4869 struct wmi_bss_color_change_enable_params_cmd { 4870 __le32 tlv_header; 4871 __le32 vdev_id; 4872 __le32 enable; 4873 } __packed; 4874 4875 #define ATH12K_IPV4_TH_SEED_SIZE 5 4876 #define ATH12K_IPV6_TH_SEED_SIZE 11 4877 4878 struct ath12k_wmi_pdev_lro_config_cmd { 4879 __le32 tlv_header; 4880 __le32 lro_enable; 4881 __le32 res; 4882 u32 th_4[ATH12K_IPV4_TH_SEED_SIZE]; 4883 u32 th_6[ATH12K_IPV6_TH_SEED_SIZE]; 4884 __le32 pdev_id; 4885 } __packed; 4886 4887 #define ATH12K_WMI_SPECTRAL_COUNT_DEFAULT 0 4888 #define ATH12K_WMI_SPECTRAL_PERIOD_DEFAULT 224 4889 #define ATH12K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 4890 #define ATH12K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 4891 #define ATH12K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 4892 #define ATH12K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 4893 #define ATH12K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 4894 #define ATH12K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 4895 #define ATH12K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 4896 #define ATH12K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 4897 #define ATH12K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 4898 #define ATH12K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 4899 #define ATH12K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 4900 #define ATH12K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 4901 #define ATH12K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 4902 #define ATH12K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 4903 #define ATH12K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 4904 #define ATH12K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 4905 4906 struct ath12k_wmi_vdev_spectral_conf_arg { 4907 u32 vdev_id; 4908 u32 scan_count; 4909 u32 scan_period; 4910 u32 scan_priority; 4911 u32 scan_fft_size; 4912 u32 scan_gc_ena; 4913 u32 scan_restart_ena; 4914 u32 scan_noise_floor_ref; 4915 u32 scan_init_delay; 4916 u32 scan_nb_tone_thr; 4917 u32 scan_str_bin_thr; 4918 u32 scan_wb_rpt_mode; 4919 u32 scan_rssi_rpt_mode; 4920 u32 scan_rssi_thr; 4921 u32 scan_pwr_format; 4922 u32 scan_rpt_mode; 4923 u32 scan_bin_scale; 4924 u32 scan_dbm_adj; 4925 u32 scan_chn_mask; 4926 }; 4927 4928 struct ath12k_wmi_vdev_spectral_conf_cmd { 4929 __le32 tlv_header; 4930 __le32 vdev_id; 4931 __le32 scan_count; 4932 __le32 scan_period; 4933 __le32 scan_priority; 4934 __le32 scan_fft_size; 4935 __le32 scan_gc_ena; 4936 __le32 scan_restart_ena; 4937 __le32 scan_noise_floor_ref; 4938 __le32 scan_init_delay; 4939 __le32 scan_nb_tone_thr; 4940 __le32 scan_str_bin_thr; 4941 __le32 scan_wb_rpt_mode; 4942 __le32 scan_rssi_rpt_mode; 4943 __le32 scan_rssi_thr; 4944 __le32 scan_pwr_format; 4945 __le32 scan_rpt_mode; 4946 __le32 scan_bin_scale; 4947 __le32 scan_dbm_adj; 4948 __le32 scan_chn_mask; 4949 } __packed; 4950 4951 #define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 4952 #define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 4953 #define ATH12K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 4954 #define ATH12K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 4955 4956 struct ath12k_wmi_vdev_spectral_enable_cmd { 4957 __le32 tlv_header; 4958 __le32 vdev_id; 4959 __le32 trigger_cmd; 4960 __le32 enable_cmd; 4961 } __packed; 4962 4963 struct ath12k_wmi_pdev_dma_ring_cfg_arg { 4964 u32 tlv_header; 4965 u32 pdev_id; 4966 u32 module_id; 4967 u32 base_paddr_lo; 4968 u32 base_paddr_hi; 4969 u32 head_idx_paddr_lo; 4970 u32 head_idx_paddr_hi; 4971 u32 tail_idx_paddr_lo; 4972 u32 tail_idx_paddr_hi; 4973 u32 num_elems; 4974 u32 buf_size; 4975 u32 num_resp_per_event; 4976 u32 event_timeout_ms; 4977 }; 4978 4979 struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd { 4980 __le32 tlv_header; 4981 __le32 pdev_id; 4982 __le32 module_id; /* see enum wmi_direct_buffer_module */ 4983 __le32 base_paddr_lo; 4984 __le32 base_paddr_hi; 4985 __le32 head_idx_paddr_lo; 4986 __le32 head_idx_paddr_hi; 4987 __le32 tail_idx_paddr_lo; 4988 __le32 tail_idx_paddr_hi; 4989 __le32 num_elems; /* Number of elems in the ring */ 4990 __le32 buf_size; /* size of allocated buffer in bytes */ 4991 4992 /* Number of wmi_dma_buf_release_entry packed together */ 4993 __le32 num_resp_per_event; 4994 4995 /* Target should timeout and send whatever resp 4996 * it has if this time expires, units in milliseconds 4997 */ 4998 __le32 event_timeout_ms; 4999 } __packed; 5000 5001 struct ath12k_wmi_dma_buf_release_fixed_params { 5002 __le32 pdev_id; 5003 __le32 module_id; 5004 __le32 num_buf_release_entry; 5005 __le32 num_meta_data_entry; 5006 } __packed; 5007 5008 struct ath12k_wmi_dma_buf_release_entry_params { 5009 __le32 tlv_header; 5010 __le32 paddr_lo; 5011 5012 /* Bits 11:0: address of data 5013 * Bits 31:12: host context data 5014 */ 5015 __le32 paddr_hi; 5016 } __packed; 5017 5018 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5019 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5020 5021 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5022 5023 struct ath12k_wmi_dma_buf_release_meta_data_params { 5024 __le32 tlv_header; 5025 a_sle32 noise_floor[WMI_MAX_CHAINS]; 5026 __le32 reset_delay; 5027 __le32 freq1; 5028 __le32 freq2; 5029 __le32 ch_width; 5030 } __packed; 5031 5032 enum wmi_fils_discovery_cmd_type { 5033 WMI_FILS_DISCOVERY_CMD, 5034 WMI_UNSOL_BCAST_PROBE_RESP, 5035 }; 5036 5037 struct wmi_fils_discovery_cmd { 5038 __le32 tlv_header; 5039 __le32 vdev_id; 5040 __le32 interval; 5041 __le32 config; /* enum wmi_fils_discovery_cmd_type */ 5042 } __packed; 5043 5044 struct wmi_fils_discovery_tmpl_cmd { 5045 __le32 tlv_header; 5046 __le32 vdev_id; 5047 __le32 buf_len; 5048 } __packed; 5049 5050 struct wmi_probe_tmpl_cmd { 5051 __le32 tlv_header; 5052 __le32 vdev_id; 5053 __le32 buf_len; 5054 } __packed; 5055 5056 #define MAX_RADIOS 2 5057 5058 #define WMI_MLO_CMD_TIMEOUT_HZ (5 * HZ) 5059 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5060 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5061 5062 struct ath12k_wmi_pdev { 5063 struct ath12k_wmi_base *wmi_ab; 5064 enum ath12k_htc_ep_id eid; 5065 u32 rx_decap_mode; 5066 }; 5067 5068 struct ath12k_hw_mode_freq_range_arg { 5069 u32 low_2ghz_freq; 5070 u32 high_2ghz_freq; 5071 u32 low_5ghz_freq; 5072 u32 high_5ghz_freq; 5073 }; 5074 5075 struct ath12k_svc_ext_mac_phy_info { 5076 enum wmi_host_hw_mode_config_type hw_mode_config_type; 5077 u32 phy_id; 5078 u32 supported_bands; 5079 struct ath12k_hw_mode_freq_range_arg hw_freq_range; 5080 }; 5081 5082 #define ATH12K_MAX_MAC_PHY_CAP 8 5083 5084 struct ath12k_svc_ext_info { 5085 u32 num_hw_modes; 5086 struct ath12k_svc_ext_mac_phy_info mac_phy_info[ATH12K_MAX_MAC_PHY_CAP]; 5087 }; 5088 5089 /** 5090 * enum ath12k_hw_mode - enum for host mode 5091 * @ATH12K_HW_MODE_SMM: Single mac mode 5092 * @ATH12K_HW_MODE_DBS: DBS mode 5093 * @ATH12K_HW_MODE_SBS: SBS mode with either high share or low share 5094 * @ATH12K_HW_MODE_SBS_UPPER_SHARE: Higher 5 GHz shared with 2.4 GHz 5095 * @ATH12K_HW_MODE_SBS_LOWER_SHARE: Lower 5 GHz shared with 2.4 GHz 5096 * @ATH12K_HW_MODE_MAX: Max, used to indicate invalid mode 5097 */ 5098 enum ath12k_hw_mode { 5099 ATH12K_HW_MODE_SMM, 5100 ATH12K_HW_MODE_DBS, 5101 ATH12K_HW_MODE_SBS, 5102 ATH12K_HW_MODE_SBS_UPPER_SHARE, 5103 ATH12K_HW_MODE_SBS_LOWER_SHARE, 5104 ATH12K_HW_MODE_MAX, 5105 }; 5106 5107 struct ath12k_hw_mode_info { 5108 bool support_dbs:1; 5109 bool support_sbs:1; 5110 5111 struct ath12k_hw_mode_freq_range_arg freq_range_caps[ATH12K_HW_MODE_MAX] 5112 [MAX_RADIOS]; 5113 }; 5114 5115 struct ath12k_wmi_base { 5116 struct ath12k_base *ab; 5117 struct ath12k_wmi_pdev wmi[MAX_RADIOS]; 5118 enum ath12k_htc_ep_id wmi_endpoint_id[MAX_RADIOS]; 5119 u32 max_msg_len[MAX_RADIOS]; 5120 5121 struct completion service_ready; 5122 struct completion unified_ready; 5123 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE); 5124 wait_queue_head_t tx_credits_wq; 5125 u32 num_mem_chunks; 5126 u32 rx_decap_mode; 5127 struct ath12k_wmi_host_mem_chunk_arg mem_chunks[WMI_MAX_MEM_REQS]; 5128 5129 enum wmi_host_hw_mode_config_type preferred_hw_mode; 5130 5131 struct ath12k_wmi_target_cap_arg *targ_cap; 5132 5133 struct ath12k_svc_ext_info svc_ext_info; 5134 u32 sbs_lower_band_end_freq; 5135 struct ath12k_hw_mode_info hw_mode_info; 5136 }; 5137 5138 struct wmi_pdev_set_bios_interface_cmd { 5139 __le32 tlv_header; 5140 __le32 pdev_id; 5141 __le32 param_type_id; 5142 __le32 length; 5143 } __packed; 5144 5145 enum wmi_bios_param_type { 5146 WMI_BIOS_PARAM_CCA_THRESHOLD_TYPE = 0, 5147 WMI_BIOS_PARAM_TAS_CONFIG_TYPE = 1, 5148 WMI_BIOS_PARAM_TAS_DATA_TYPE = 2, 5149 5150 /* bandedge control power */ 5151 WMI_BIOS_PARAM_TYPE_BANDEDGE = 3, 5152 5153 WMI_BIOS_PARAM_TYPE_MAX, 5154 }; 5155 5156 struct wmi_pdev_set_bios_sar_table_cmd { 5157 __le32 tlv_header; 5158 __le32 pdev_id; 5159 __le32 sar_len; 5160 __le32 dbs_backoff_len; 5161 } __packed; 5162 5163 struct wmi_pdev_set_bios_geo_table_cmd { 5164 __le32 tlv_header; 5165 __le32 pdev_id; 5166 __le32 geo_len; 5167 } __packed; 5168 5169 #define ATH12K_FW_STATS_BUF_SIZE (1024 * 1024) 5170 5171 enum wmi_sys_cap_info_flags { 5172 WMI_SYS_CAP_INFO_RXTX_LED = BIT(0), 5173 WMI_SYS_CAP_INFO_RFKILL = BIT(1), 5174 }; 5175 5176 #define WMI_RFKILL_CFG_GPIO_PIN_NUM GENMASK(5, 0) 5177 #define WMI_RFKILL_CFG_RADIO_LEVEL BIT(6) 5178 #define WMI_RFKILL_CFG_PIN_AS_GPIO GENMASK(10, 7) 5179 5180 enum wmi_rfkill_enable_radio { 5181 WMI_RFKILL_ENABLE_RADIO_ON = 0, 5182 WMI_RFKILL_ENABLE_RADIO_OFF = 1, 5183 }; 5184 5185 enum wmi_rfkill_radio_state { 5186 WMI_RFKILL_RADIO_STATE_OFF = 1, 5187 WMI_RFKILL_RADIO_STATE_ON = 2, 5188 }; 5189 5190 struct wmi_rfkill_state_change_event { 5191 __le32 gpio_pin_num; 5192 __le32 int_type; 5193 __le32 radio_state; 5194 } __packed; 5195 5196 struct wmi_twt_enable_event { 5197 __le32 pdev_id; 5198 __le32 status; 5199 } __packed; 5200 5201 struct wmi_twt_disable_event { 5202 __le32 pdev_id; 5203 __le32 status; 5204 } __packed; 5205 5206 struct wmi_mlo_setup_cmd { 5207 __le32 tlv_header; 5208 __le32 mld_group_id; 5209 __le32 pdev_id; 5210 } __packed; 5211 5212 struct wmi_mlo_setup_arg { 5213 __le32 group_id; 5214 u8 num_partner_links; 5215 u8 *partner_link_id; 5216 }; 5217 5218 struct wmi_mlo_ready_cmd { 5219 __le32 tlv_header; 5220 __le32 pdev_id; 5221 } __packed; 5222 5223 enum wmi_mlo_tear_down_reason_code_type { 5224 WMI_MLO_TEARDOWN_SSR_REASON, 5225 }; 5226 5227 struct wmi_mlo_teardown_cmd { 5228 __le32 tlv_header; 5229 __le32 pdev_id; 5230 __le32 reason_code; 5231 } __packed; 5232 5233 struct wmi_mlo_setup_complete_event { 5234 __le32 pdev_id; 5235 __le32 status; 5236 } __packed; 5237 5238 struct wmi_mlo_teardown_complete_event { 5239 __le32 pdev_id; 5240 __le32 status; 5241 } __packed; 5242 5243 /* WOW structures */ 5244 enum wmi_wow_wakeup_event { 5245 WOW_BMISS_EVENT = 0, 5246 WOW_BETTER_AP_EVENT, 5247 WOW_DEAUTH_RECVD_EVENT, 5248 WOW_MAGIC_PKT_RECVD_EVENT, 5249 WOW_GTK_ERR_EVENT, 5250 WOW_FOURWAY_HSHAKE_EVENT, 5251 WOW_EAPOL_RECVD_EVENT, 5252 WOW_NLO_DETECTED_EVENT, 5253 WOW_DISASSOC_RECVD_EVENT, 5254 WOW_PATTERN_MATCH_EVENT, 5255 WOW_CSA_IE_EVENT, 5256 WOW_PROBE_REQ_WPS_IE_EVENT, 5257 WOW_AUTH_REQ_EVENT, 5258 WOW_ASSOC_REQ_EVENT, 5259 WOW_HTT_EVENT, 5260 WOW_RA_MATCH_EVENT, 5261 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5262 WOW_IOAC_MAGIC_EVENT, 5263 WOW_IOAC_SHORT_EVENT, 5264 WOW_IOAC_EXTEND_EVENT, 5265 WOW_IOAC_TIMER_EVENT, 5266 WOW_DFS_PHYERR_RADAR_EVENT, 5267 WOW_BEACON_EVENT, 5268 WOW_CLIENT_KICKOUT_EVENT, 5269 WOW_EVENT_MAX, 5270 }; 5271 5272 enum wmi_wow_interface_cfg { 5273 WOW_IFACE_PAUSE_ENABLED, 5274 WOW_IFACE_PAUSE_DISABLED 5275 }; 5276 5277 #define C2S(x) case x: return #x 5278 5279 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5280 { 5281 switch (ev) { 5282 C2S(WOW_BMISS_EVENT); 5283 C2S(WOW_BETTER_AP_EVENT); 5284 C2S(WOW_DEAUTH_RECVD_EVENT); 5285 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5286 C2S(WOW_GTK_ERR_EVENT); 5287 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5288 C2S(WOW_EAPOL_RECVD_EVENT); 5289 C2S(WOW_NLO_DETECTED_EVENT); 5290 C2S(WOW_DISASSOC_RECVD_EVENT); 5291 C2S(WOW_PATTERN_MATCH_EVENT); 5292 C2S(WOW_CSA_IE_EVENT); 5293 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5294 C2S(WOW_AUTH_REQ_EVENT); 5295 C2S(WOW_ASSOC_REQ_EVENT); 5296 C2S(WOW_HTT_EVENT); 5297 C2S(WOW_RA_MATCH_EVENT); 5298 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5299 C2S(WOW_IOAC_MAGIC_EVENT); 5300 C2S(WOW_IOAC_SHORT_EVENT); 5301 C2S(WOW_IOAC_EXTEND_EVENT); 5302 C2S(WOW_IOAC_TIMER_EVENT); 5303 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5304 C2S(WOW_BEACON_EVENT); 5305 C2S(WOW_CLIENT_KICKOUT_EVENT); 5306 C2S(WOW_EVENT_MAX); 5307 default: 5308 return NULL; 5309 } 5310 } 5311 5312 enum wmi_wow_wake_reason { 5313 WOW_REASON_UNSPECIFIED = -1, 5314 WOW_REASON_NLOD = 0, 5315 WOW_REASON_AP_ASSOC_LOST, 5316 WOW_REASON_LOW_RSSI, 5317 WOW_REASON_DEAUTH_RECVD, 5318 WOW_REASON_DISASSOC_RECVD, 5319 WOW_REASON_GTK_HS_ERR, 5320 WOW_REASON_EAP_REQ, 5321 WOW_REASON_FOURWAY_HS_RECV, 5322 WOW_REASON_TIMER_INTR_RECV, 5323 WOW_REASON_PATTERN_MATCH_FOUND, 5324 WOW_REASON_RECV_MAGIC_PATTERN, 5325 WOW_REASON_P2P_DISC, 5326 WOW_REASON_WLAN_HB, 5327 WOW_REASON_CSA_EVENT, 5328 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5329 WOW_REASON_AUTH_REQ_RECV, 5330 WOW_REASON_ASSOC_REQ_RECV, 5331 WOW_REASON_HTT_EVENT, 5332 WOW_REASON_RA_MATCH, 5333 WOW_REASON_HOST_AUTO_SHUTDOWN, 5334 WOW_REASON_IOAC_MAGIC_EVENT, 5335 WOW_REASON_IOAC_SHORT_EVENT, 5336 WOW_REASON_IOAC_EXTEND_EVENT, 5337 WOW_REASON_IOAC_TIMER_EVENT, 5338 WOW_REASON_ROAM_HO, 5339 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5340 WOW_REASON_BEACON_RECV, 5341 WOW_REASON_CLIENT_KICKOUT_EVENT, 5342 WOW_REASON_PAGE_FAULT = 0x3a, 5343 WOW_REASON_DEBUG_TEST = 0xFF, 5344 }; 5345 5346 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5347 { 5348 switch (reason) { 5349 C2S(WOW_REASON_UNSPECIFIED); 5350 C2S(WOW_REASON_NLOD); 5351 C2S(WOW_REASON_AP_ASSOC_LOST); 5352 C2S(WOW_REASON_LOW_RSSI); 5353 C2S(WOW_REASON_DEAUTH_RECVD); 5354 C2S(WOW_REASON_DISASSOC_RECVD); 5355 C2S(WOW_REASON_GTK_HS_ERR); 5356 C2S(WOW_REASON_EAP_REQ); 5357 C2S(WOW_REASON_FOURWAY_HS_RECV); 5358 C2S(WOW_REASON_TIMER_INTR_RECV); 5359 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5360 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5361 C2S(WOW_REASON_P2P_DISC); 5362 C2S(WOW_REASON_WLAN_HB); 5363 C2S(WOW_REASON_CSA_EVENT); 5364 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5365 C2S(WOW_REASON_AUTH_REQ_RECV); 5366 C2S(WOW_REASON_ASSOC_REQ_RECV); 5367 C2S(WOW_REASON_HTT_EVENT); 5368 C2S(WOW_REASON_RA_MATCH); 5369 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5370 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5371 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5372 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5373 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5374 C2S(WOW_REASON_ROAM_HO); 5375 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5376 C2S(WOW_REASON_BEACON_RECV); 5377 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5378 C2S(WOW_REASON_PAGE_FAULT); 5379 C2S(WOW_REASON_DEBUG_TEST); 5380 default: 5381 return NULL; 5382 } 5383 } 5384 5385 #undef C2S 5386 5387 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5388 #define WOW_DEFAULT_BITMASK_SIZE 148 5389 5390 #define WOW_MIN_PATTERN_SIZE 1 5391 #define WOW_MAX_PATTERN_SIZE 148 5392 #define WOW_MAX_PKT_OFFSET 128 5393 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 5394 sizeof(struct rfc1042_hdr)) 5395 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 5396 offsetof(struct ieee80211_hdr_3addr, addr1)) 5397 5398 struct wmi_wow_bitmap_pattern_params { 5399 __le32 tlv_header; 5400 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 5401 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 5402 __le32 pattern_offset; 5403 __le32 pattern_len; 5404 __le32 bitmask_len; 5405 __le32 pattern_id; 5406 } __packed; 5407 5408 struct wmi_wow_add_pattern_cmd { 5409 __le32 tlv_header; 5410 __le32 vdev_id; 5411 __le32 pattern_id; 5412 __le32 pattern_type; 5413 } __packed; 5414 5415 struct wmi_wow_del_pattern_cmd { 5416 __le32 tlv_header; 5417 __le32 vdev_id; 5418 __le32 pattern_id; 5419 __le32 pattern_type; 5420 } __packed; 5421 5422 enum wmi_tlv_pattern_type { 5423 WOW_PATTERN_MIN = 0, 5424 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5425 WOW_IPV4_SYNC_PATTERN, 5426 WOW_IPV6_SYNC_PATTERN, 5427 WOW_WILD_CARD_PATTERN, 5428 WOW_TIMER_PATTERN, 5429 WOW_MAGIC_PATTERN, 5430 WOW_IPV6_RA_PATTERN, 5431 WOW_IOAC_PKT_PATTERN, 5432 WOW_IOAC_TMR_PATTERN, 5433 WOW_PATTERN_MAX 5434 }; 5435 5436 struct wmi_wow_add_del_event_cmd { 5437 __le32 tlv_header; 5438 __le32 vdev_id; 5439 __le32 is_add; 5440 __le32 event_bitmap; 5441 } __packed; 5442 5443 struct wmi_wow_enable_cmd { 5444 __le32 tlv_header; 5445 __le32 enable; 5446 __le32 pause_iface_config; 5447 __le32 flags; 5448 } __packed; 5449 5450 struct wmi_wow_host_wakeup_cmd { 5451 __le32 tlv_header; 5452 __le32 reserved; 5453 } __packed; 5454 5455 struct wmi_wow_ev_param { 5456 __le32 vdev_id; 5457 __le32 flag; 5458 __le32 wake_reason; 5459 __le32 data_len; 5460 } __packed; 5461 5462 struct wmi_wow_ev_pg_fault_param { 5463 __le32 len; 5464 u8 data[]; 5465 } __packed; 5466 5467 struct wmi_wow_ev_arg { 5468 enum wmi_wow_wake_reason wake_reason; 5469 }; 5470 5471 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 5472 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 5473 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 5474 #define WMI_PNO_MAX_NETW_CHANNELS 26 5475 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 5476 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 5477 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 5478 5479 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 5480 #define WMI_PNO_MAX_PB_REQ_SIZE 450 5481 5482 #define WMI_PNO_24GHZ_DEFAULT_CH 1 5483 #define WMI_PNO_5GHZ_DEFAULT_CH 36 5484 5485 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 5486 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 5487 5488 /* SSID broadcast type */ 5489 enum wmi_ssid_bcast_type { 5490 BCAST_UNKNOWN = 0, 5491 BCAST_NORMAL = 1, 5492 BCAST_HIDDEN = 2, 5493 }; 5494 5495 #define WMI_NLO_MAX_SSIDS 16 5496 #define WMI_NLO_MAX_CHAN 48 5497 5498 #define WMI_NLO_CONFIG_STOP BIT(0) 5499 #define WMI_NLO_CONFIG_START BIT(1) 5500 #define WMI_NLO_CONFIG_RESET BIT(2) 5501 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 5502 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 5503 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 5504 5505 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 5506 * Only one of them can be enabled at a given time 5507 */ 5508 #define WMI_NLO_CONFIG_ENLO BIT(7) 5509 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 5510 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 5511 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 5512 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 5513 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 5514 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 5515 5516 struct wmi_nlo_ssid_params { 5517 __le32 valid; 5518 struct ath12k_wmi_ssid_params ssid; 5519 } __packed; 5520 5521 struct wmi_nlo_enc_params { 5522 __le32 valid; 5523 __le32 enc_type; 5524 } __packed; 5525 5526 struct wmi_nlo_auth_params { 5527 __le32 valid; 5528 __le32 auth_type; 5529 } __packed; 5530 5531 struct wmi_nlo_bcast_nw_params { 5532 __le32 valid; 5533 __le32 bcast_nw_type; 5534 } __packed; 5535 5536 struct wmi_nlo_rssi_params { 5537 __le32 valid; 5538 __le32 rssi; 5539 } __packed; 5540 5541 struct nlo_configured_params { 5542 /* TLV tag and len;*/ 5543 __le32 tlv_header; 5544 struct wmi_nlo_ssid_params ssid; 5545 struct wmi_nlo_enc_params enc_type; 5546 struct wmi_nlo_auth_params auth_type; 5547 struct wmi_nlo_rssi_params rssi_cond; 5548 5549 /* indicates if the SSID is hidden or not */ 5550 struct wmi_nlo_bcast_nw_params bcast_nw_type; 5551 } __packed; 5552 5553 struct wmi_network_type_arg { 5554 struct cfg80211_ssid ssid; 5555 u32 authentication; 5556 u32 encryption; 5557 u32 bcast_nw_type; 5558 u8 channel_count; 5559 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 5560 s32 rssi_threshold; 5561 }; 5562 5563 struct wmi_pno_scan_req_arg { 5564 u8 enable; 5565 u8 vdev_id; 5566 u8 uc_networks_count; 5567 struct wmi_network_type_arg a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 5568 u32 fast_scan_period; 5569 u32 slow_scan_period; 5570 u8 fast_scan_max_cycles; 5571 5572 bool do_passive_scan; 5573 5574 u32 delay_start_time; 5575 u32 active_min_time; 5576 u32 active_max_time; 5577 u32 passive_min_time; 5578 u32 passive_max_time; 5579 5580 /* mac address randomization attributes */ 5581 u32 enable_pno_scan_randomization; 5582 u8 mac_addr[ETH_ALEN]; 5583 u8 mac_addr_mask[ETH_ALEN]; 5584 }; 5585 5586 struct wmi_wow_nlo_config_cmd { 5587 __le32 tlv_header; 5588 __le32 flags; 5589 __le32 vdev_id; 5590 __le32 fast_scan_max_cycles; 5591 __le32 active_dwell_time; 5592 __le32 passive_dwell_time; 5593 __le32 probe_bundle_size; 5594 5595 /* ART = IRT */ 5596 __le32 rest_time; 5597 5598 /* max value that can be reached after scan_backoff_multiplier */ 5599 __le32 max_rest_time; 5600 5601 __le32 scan_backoff_multiplier; 5602 __le32 fast_scan_period; 5603 5604 /* specific to windows */ 5605 __le32 slow_scan_period; 5606 5607 __le32 no_of_ssids; 5608 5609 __le32 num_of_channels; 5610 5611 /* NLO scan start delay time in milliseconds */ 5612 __le32 delay_start_time; 5613 5614 /* MAC Address to use in Probe Req as SA */ 5615 struct ath12k_wmi_mac_addr_params mac_addr; 5616 5617 /* Mask on which MAC has to be randomized */ 5618 struct ath12k_wmi_mac_addr_params mac_mask; 5619 5620 /* IE bitmap to use in Probe Req */ 5621 __le32 ie_bitmap[8]; 5622 5623 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 5624 __le32 num_vendor_oui; 5625 5626 /* Number of connected NLO band preferences */ 5627 __le32 num_cnlo_band_pref; 5628 5629 /* The TLVs will follow. 5630 * nlo_configured_params nlo_list[]; 5631 * u32 channel_list[num_of_channels]; 5632 */ 5633 } __packed; 5634 5635 /* Definition of HW data filtering */ 5636 enum hw_data_filter_type { 5637 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5638 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5639 }; 5640 5641 struct wmi_hw_data_filter_cmd { 5642 __le32 tlv_header; 5643 __le32 vdev_id; 5644 __le32 enable; 5645 __le32 hw_filter_bitmap; 5646 } __packed; 5647 5648 struct wmi_hw_data_filter_arg { 5649 u32 vdev_id; 5650 bool enable; 5651 u32 hw_filter_bitmap; 5652 }; 5653 5654 #define WMI_IPV6_UC_TYPE 0 5655 #define WMI_IPV6_AC_TYPE 1 5656 5657 #define WMI_IPV6_MAX_COUNT 16 5658 #define WMI_IPV4_MAX_COUNT 2 5659 5660 struct wmi_arp_ns_offload_arg { 5661 u8 ipv4_addr[WMI_IPV4_MAX_COUNT][4]; 5662 u32 ipv4_count; 5663 u32 ipv6_count; 5664 u8 ipv6_addr[WMI_IPV6_MAX_COUNT][16]; 5665 u8 self_ipv6_addr[WMI_IPV6_MAX_COUNT][16]; 5666 u8 ipv6_type[WMI_IPV6_MAX_COUNT]; 5667 bool ipv6_valid[WMI_IPV6_MAX_COUNT]; 5668 u8 mac_addr[ETH_ALEN]; 5669 }; 5670 5671 #define WMI_MAX_NS_OFFLOADS 2 5672 #define WMI_MAX_ARP_OFFLOADS 2 5673 5674 #define WMI_ARPOL_FLAGS_VALID BIT(0) 5675 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 5676 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 5677 5678 struct wmi_arp_offload_params { 5679 __le32 tlv_header; 5680 __le32 flags; 5681 u8 target_ipaddr[4]; 5682 u8 remote_ipaddr[4]; 5683 struct ath12k_wmi_mac_addr_params target_mac; 5684 } __packed; 5685 5686 #define WMI_NSOL_FLAGS_VALID BIT(0) 5687 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 5688 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 5689 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 5690 5691 #define WMI_NSOL_MAX_TARGET_IPS 2 5692 5693 struct wmi_ns_offload_params { 5694 __le32 tlv_header; 5695 __le32 flags; 5696 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 5697 u8 solicitation_ipaddr[16]; 5698 u8 remote_ipaddr[16]; 5699 struct ath12k_wmi_mac_addr_params target_mac; 5700 } __packed; 5701 5702 struct wmi_set_arp_ns_offload_cmd { 5703 __le32 tlv_header; 5704 __le32 flags; 5705 __le32 vdev_id; 5706 __le32 num_ns_ext_tuples; 5707 /* The TLVs follow: 5708 * wmi_ns_offload_params ns[WMI_MAX_NS_OFFLOADS]; 5709 * wmi_arp_offload_params arp[WMI_MAX_ARP_OFFLOADS]; 5710 * wmi_ns_offload_params ns_ext[num_ns_ext_tuples]; 5711 */ 5712 } __packed; 5713 5714 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 5715 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 5716 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 5717 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 5718 5719 #define GTK_OFFLOAD_KEK_BYTES 16 5720 #define GTK_OFFLOAD_KCK_BYTES 16 5721 #define GTK_REPLAY_COUNTER_BYTES 8 5722 #define WMI_MAX_KEY_LEN 32 5723 #define IGTK_PN_SIZE 6 5724 5725 struct wmi_gtk_offload_status_event { 5726 __le32 vdev_id; 5727 __le32 flags; 5728 __le32 refresh_cnt; 5729 __le64 replay_ctr; 5730 u8 igtk_key_index; 5731 u8 igtk_key_length; 5732 u8 igtk_key_rsc[IGTK_PN_SIZE]; 5733 u8 igtk_key[WMI_MAX_KEY_LEN]; 5734 u8 gtk_key_index; 5735 u8 gtk_key_length; 5736 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 5737 u8 gtk_key[WMI_MAX_KEY_LEN]; 5738 } __packed; 5739 5740 struct wmi_gtk_rekey_offload_cmd { 5741 __le32 tlv_header; 5742 __le32 vdev_id; 5743 __le32 flags; 5744 u8 kek[GTK_OFFLOAD_KEK_BYTES]; 5745 u8 kck[GTK_OFFLOAD_KCK_BYTES]; 5746 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 5747 } __packed; 5748 5749 struct wmi_sta_keepalive_cmd { 5750 __le32 tlv_header; 5751 __le32 vdev_id; 5752 __le32 enabled; 5753 5754 /* WMI_STA_KEEPALIVE_METHOD_ */ 5755 __le32 method; 5756 5757 /* in seconds */ 5758 __le32 interval; 5759 5760 /* following this structure is the TLV for struct 5761 * wmi_sta_keepalive_arp_resp_params 5762 */ 5763 } __packed; 5764 5765 struct wmi_sta_keepalive_arp_resp_params { 5766 __le32 tlv_header; 5767 __le32 src_ip4_addr; 5768 __le32 dest_ip4_addr; 5769 struct ath12k_wmi_mac_addr_params dest_mac_addr; 5770 } __packed; 5771 5772 struct wmi_sta_keepalive_arg { 5773 u32 vdev_id; 5774 u32 enabled; 5775 u32 method; 5776 u32 interval; 5777 u32 src_ip4_addr; 5778 u32 dest_ip4_addr; 5779 const u8 dest_mac_addr[ETH_ALEN]; 5780 }; 5781 5782 enum wmi_sta_keepalive_method { 5783 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 5784 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 5785 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 5786 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 5787 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 5788 }; 5789 5790 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 5791 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 5792 5793 struct wmi_stats_event { 5794 __le32 stats_id; 5795 __le32 num_pdev_stats; 5796 __le32 num_vdev_stats; 5797 __le32 num_peer_stats; 5798 __le32 num_bcnflt_stats; 5799 __le32 num_chan_stats; 5800 __le32 num_mib_stats; 5801 __le32 pdev_id; 5802 __le32 num_bcn_stats; 5803 __le32 num_peer_extd_stats; 5804 __le32 num_peer_extd2_stats; 5805 } __packed; 5806 5807 enum wmi_stats_id { 5808 WMI_REQUEST_PDEV_STAT = BIT(2), 5809 WMI_REQUEST_VDEV_STAT = BIT(3), 5810 WMI_REQUEST_BCN_STAT = BIT(11), 5811 }; 5812 5813 struct wmi_request_stats_cmd { 5814 __le32 tlv_header; 5815 __le32 stats_id; 5816 __le32 vdev_id; 5817 struct ath12k_wmi_mac_addr_params peer_macaddr; 5818 __le32 pdev_id; 5819 } __packed; 5820 5821 #define WLAN_MAX_AC 4 5822 #define MAX_TX_RATE_VALUES 10 5823 5824 struct wmi_vdev_stats_params { 5825 __le32 vdev_id; 5826 __le32 beacon_snr; 5827 __le32 data_snr; 5828 __le32 num_tx_frames[WLAN_MAX_AC]; 5829 __le32 num_rx_frames; 5830 __le32 num_tx_frames_retries[WLAN_MAX_AC]; 5831 __le32 num_tx_frames_failures[WLAN_MAX_AC]; 5832 __le32 num_rts_fail; 5833 __le32 num_rts_success; 5834 __le32 num_rx_err; 5835 __le32 num_rx_discard; 5836 __le32 num_tx_not_acked; 5837 __le32 tx_rate_history[MAX_TX_RATE_VALUES]; 5838 __le32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 5839 } __packed; 5840 5841 struct ath12k_wmi_bcn_stats_params { 5842 __le32 vdev_id; 5843 __le32 tx_bcn_succ_cnt; 5844 __le32 tx_bcn_outage_cnt; 5845 } __packed; 5846 5847 struct ath12k_wmi_pdev_base_stats_params { 5848 a_sle32 chan_nf; 5849 __le32 tx_frame_count; /* Cycles spent transmitting frames */ 5850 __le32 rx_frame_count; /* Cycles spent receiving frames */ 5851 __le32 rx_clear_count; /* Total channel busy time, evidently */ 5852 __le32 cycle_count; /* Total on-channel time */ 5853 __le32 phy_err_count; 5854 __le32 chan_tx_pwr; 5855 } __packed; 5856 5857 struct ath12k_wmi_pdev_tx_stats_params { 5858 a_sle32 comp_queued; 5859 a_sle32 comp_delivered; 5860 a_sle32 msdu_enqued; 5861 a_sle32 mpdu_enqued; 5862 a_sle32 wmm_drop; 5863 a_sle32 local_enqued; 5864 a_sle32 local_freed; 5865 a_sle32 hw_queued; 5866 a_sle32 hw_reaped; 5867 a_sle32 underrun; 5868 a_sle32 tx_abort; 5869 a_sle32 mpdus_requed; 5870 __le32 tx_ko; 5871 __le32 data_rc; 5872 __le32 self_triggers; 5873 __le32 sw_retry_failure; 5874 __le32 illgl_rate_phy_err; 5875 __le32 pdev_cont_xretry; 5876 __le32 pdev_tx_timeout; 5877 __le32 pdev_resets; 5878 __le32 stateless_tid_alloc_failure; 5879 __le32 phy_underrun; 5880 __le32 txop_ovf; 5881 } __packed; 5882 5883 struct ath12k_wmi_pdev_rx_stats_params { 5884 a_sle32 mid_ppdu_route_change; 5885 a_sle32 status_rcvd; 5886 a_sle32 r0_frags; 5887 a_sle32 r1_frags; 5888 a_sle32 r2_frags; 5889 a_sle32 r3_frags; 5890 a_sle32 htt_msdus; 5891 a_sle32 htt_mpdus; 5892 a_sle32 loc_msdus; 5893 a_sle32 loc_mpdus; 5894 a_sle32 oversize_amsdu; 5895 a_sle32 phy_errs; 5896 a_sle32 phy_err_drop; 5897 a_sle32 mpdu_errs; 5898 } __packed; 5899 5900 struct ath12k_wmi_pdev_stats_params { 5901 struct ath12k_wmi_pdev_base_stats_params base; 5902 struct ath12k_wmi_pdev_tx_stats_params tx; 5903 struct ath12k_wmi_pdev_rx_stats_params rx; 5904 } __packed; 5905 5906 struct ath12k_fw_stats_req_params { 5907 u32 stats_id; 5908 u32 vdev_id; 5909 u32 pdev_id; 5910 }; 5911 5912 #define WMI_REQ_CTRL_PATH_PDEV_TX_STAT 1 5913 #define WMI_REQUEST_CTRL_PATH_STAT_GET 1 5914 5915 #define WMI_TPC_CONFIG BIT(1) 5916 #define WMI_TPC_REG_PWR_ALLOWED BIT(2) 5917 #define WMI_TPC_RATES_ARRAY1 BIT(3) 5918 #define WMI_TPC_RATES_ARRAY2 BIT(4) 5919 #define WMI_TPC_RATES_DL_OFDMA_ARRAY BIT(5) 5920 #define WMI_TPC_CTL_PWR_ARRAY BIT(6) 5921 #define WMI_TPC_CONFIG_PARAM 0x1 5922 #define ATH12K_TPC_RATE_ARRAY_MU GENMASK(15, 8) 5923 #define ATH12K_TPC_RATE_ARRAY_SU GENMASK(7, 0) 5924 #define TPC_STATS_REG_PWR_ALLOWED_TYPE 0 5925 5926 enum wmi_halphy_ctrl_path_stats_id { 5927 WMI_HALPHY_PDEV_TX_SU_STATS = 0, 5928 WMI_HALPHY_PDEV_TX_SUTXBF_STATS, 5929 WMI_HALPHY_PDEV_TX_MU_STATS, 5930 WMI_HALPHY_PDEV_TX_MUTXBF_STATS, 5931 WMI_HALPHY_PDEV_TX_STATS_MAX, 5932 }; 5933 5934 enum ath12k_wmi_tpc_stats_rates_array { 5935 ATH12K_TPC_STATS_RATES_ARRAY1, 5936 ATH12K_TPC_STATS_RATES_ARRAY2, 5937 }; 5938 5939 enum ath12k_wmi_tpc_stats_ctl_array { 5940 ATH12K_TPC_STATS_CTL_ARRAY, 5941 ATH12K_TPC_STATS_CTL_160ARRAY, 5942 }; 5943 5944 enum ath12k_wmi_tpc_stats_events { 5945 ATH12K_TPC_STATS_CONFIG_REG_PWR_EVENT, 5946 ATH12K_TPC_STATS_RATES_EVENT1, 5947 ATH12K_TPC_STATS_RATES_EVENT2, 5948 ATH12K_TPC_STATS_CTL_TABLE_EVENT 5949 }; 5950 5951 struct wmi_request_halphy_ctrl_path_stats_cmd_fixed_params { 5952 __le32 tlv_header; 5953 __le32 stats_id_mask; 5954 __le32 request_id; 5955 __le32 action; 5956 __le32 subid; 5957 } __packed; 5958 5959 struct ath12k_wmi_pdev_tpc_stats_event_fixed_params { 5960 __le32 pdev_id; 5961 __le32 end_of_event; 5962 __le32 event_count; 5963 } __packed; 5964 5965 struct wmi_tpc_config_params { 5966 __le32 reg_domain; 5967 __le32 chan_freq; 5968 __le32 phy_mode; 5969 __le32 twice_antenna_reduction; 5970 __le32 twice_max_reg_power; 5971 __le32 twice_antenna_gain; 5972 __le32 power_limit; 5973 __le32 rate_max; 5974 __le32 num_tx_chain; 5975 __le32 ctl; 5976 __le32 flags; 5977 __le32 caps; 5978 } __packed; 5979 5980 struct wmi_max_reg_power_fixed_params { 5981 __le32 reg_power_type; 5982 __le32 reg_array_len; 5983 __le32 d1; 5984 __le32 d2; 5985 __le32 d3; 5986 __le32 d4; 5987 } __packed; 5988 5989 struct wmi_max_reg_power_allowed_arg { 5990 struct wmi_max_reg_power_fixed_params tpc_reg_pwr; 5991 s16 *reg_pwr_array; 5992 }; 5993 5994 struct wmi_tpc_rates_array_fixed_params { 5995 __le32 rate_array_type; 5996 __le32 rate_array_len; 5997 } __packed; 5998 5999 struct wmi_tpc_rates_array_arg { 6000 struct wmi_tpc_rates_array_fixed_params tpc_rates_array; 6001 s16 *rate_array; 6002 }; 6003 6004 struct wmi_tpc_ctl_pwr_fixed_params { 6005 __le32 ctl_array_type; 6006 __le32 ctl_array_len; 6007 __le32 end_of_ctl_pwr; 6008 __le32 ctl_pwr_count; 6009 __le32 d1; 6010 __le32 d2; 6011 __le32 d3; 6012 __le32 d4; 6013 } __packed; 6014 6015 struct wmi_tpc_ctl_pwr_table_arg { 6016 struct wmi_tpc_ctl_pwr_fixed_params tpc_ctl_pwr; 6017 s8 *ctl_pwr_table; 6018 }; 6019 6020 struct wmi_tpc_stats_arg { 6021 u32 pdev_id; 6022 u32 event_count; 6023 u32 end_of_event; 6024 u32 tlvs_rcvd; 6025 struct wmi_max_reg_power_allowed_arg max_reg_allowed_power; 6026 struct wmi_tpc_rates_array_arg rates_array1; 6027 struct wmi_tpc_rates_array_arg rates_array2; 6028 struct wmi_tpc_config_params tpc_config; 6029 struct wmi_tpc_ctl_pwr_table_arg ctl_array; 6030 }; 6031 6032 struct wmi_vdev_ch_power_params { 6033 __le32 tlv_header; 6034 6035 /* Channel center frequency (MHz) */ 6036 __le32 chan_cfreq; 6037 6038 /* Unit: dBm, either PSD/EIRP power for this frequency or 6039 * incremental for non-PSD BW 6040 */ 6041 __le32 tx_power; 6042 } __packed; 6043 6044 struct wmi_vdev_set_tpc_power_cmd { 6045 __le32 tlv_header; 6046 __le32 vdev_id; 6047 6048 /* Value: 0 or 1, is PSD power or not */ 6049 __le32 psd_power; 6050 6051 /* Maximum EIRP power (dBm units), valid only if power is PSD */ 6052 __le32 eirp_power; 6053 6054 /* Type: WMI_6GHZ_REG_TYPE, used for halphy CTL lookup */ 6055 __le32 power_type_6ghz; 6056 6057 /* This fixed_param TLV is followed by the below TLVs: 6058 * num_pwr_levels of wmi_vdev_ch_power_info 6059 * For PSD power, it is the PSD/EIRP power of the frequency (20 MHz chunks). 6060 * For non-PSD power, the power values are for 20, 40, and till 6061 * BSS BW power levels. 6062 * The num_pwr_levels will be checked by sw how many elements present 6063 * in the variable-length array. 6064 */ 6065 } __packed; 6066 6067 #define CRTL_F_DYNC_FORCE_LINK_NUM GENMASK(3, 2) 6068 6069 struct wmi_mlo_link_set_active_cmd { 6070 __le32 tlv_header; 6071 __le32 force_mode; 6072 __le32 reason; 6073 __le32 use_ieee_link_id_bitmap; 6074 struct ath12k_wmi_mac_addr_params ap_mld_mac_addr; 6075 __le32 ctrl_flags; 6076 } __packed; 6077 6078 struct wmi_mlo_set_active_link_number_params { 6079 __le32 tlv_header; 6080 __le32 num_of_link; 6081 __le32 vdev_type; 6082 __le32 vdev_subtype; 6083 __le32 home_freq; 6084 } __packed; 6085 6086 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_1 GENMASK(7, 0) 6087 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_2 GENMASK(15, 8) 6088 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_3 GENMASK(23, 16) 6089 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_4 GENMASK(31, 24) 6090 6091 struct wmi_disallowed_mlo_mode_bitmap_params { 6092 __le32 tlv_header; 6093 __le32 disallowed_mode_bitmap; 6094 __le32 ieee_link_id_comb; 6095 } __packed; 6096 6097 enum wmi_mlo_link_force_mode { 6098 WMI_MLO_LINK_FORCE_MODE_ACTIVE = 1, 6099 WMI_MLO_LINK_FORCE_MODE_INACTIVE = 2, 6100 WMI_MLO_LINK_FORCE_MODE_ACTIVE_LINK_NUM = 3, 6101 WMI_MLO_LINK_FORCE_MODE_INACTIVE_LINK_NUM = 4, 6102 WMI_MLO_LINK_FORCE_MODE_NO_FORCE = 5, 6103 WMI_MLO_LINK_FORCE_MODE_ACTIVE_INACTIVE = 6, 6104 WMI_MLO_LINK_FORCE_MODE_NON_FORCE_UPDATE = 7, 6105 }; 6106 6107 enum wmi_mlo_link_force_reason { 6108 WMI_MLO_LINK_FORCE_REASON_NEW_CONNECT = 1, 6109 WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, 6110 WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, 6111 WMI_MLO_LINK_FORCE_REASON_TDLS = 4, 6112 WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, 6113 WMI_MLO_LINK_FORCE_REASON_LINK_DELETE = 6, 6114 WMI_MLO_LINK_FORCE_REASON_SINGLE_LINK_EMLSR_OP = 7, 6115 }; 6116 6117 struct wmi_mlo_link_num_arg { 6118 u32 num_of_link; 6119 u32 vdev_type; 6120 u32 vdev_subtype; 6121 u32 home_freq; 6122 }; 6123 6124 struct wmi_mlo_control_flags_arg { 6125 bool overwrite_force_active_bitmap; 6126 bool overwrite_force_inactive_bitmap; 6127 bool dync_force_link_num; 6128 bool post_re_evaluate; 6129 u8 post_re_evaluate_loops; 6130 bool dont_reschedule_workqueue; 6131 }; 6132 6133 struct wmi_ml_link_force_cmd_arg { 6134 u8 ap_mld_mac_addr[ETH_ALEN]; 6135 u16 ieee_link_id_bitmap; 6136 u16 ieee_link_id_bitmap2; 6137 u8 link_num; 6138 }; 6139 6140 struct wmi_ml_disallow_mode_bmap_arg { 6141 u32 disallowed_mode; 6142 union { 6143 u32 ieee_link_id_comb; 6144 u8 ieee_link_id[4]; 6145 }; 6146 }; 6147 6148 /* maximum size of link number param array 6149 * for MLO link set active command 6150 */ 6151 #define WMI_MLO_LINK_NUM_SZ 2 6152 6153 /* maximum size of vdev bitmap array for 6154 * MLO link set active command 6155 */ 6156 #define WMI_MLO_VDEV_BITMAP_SZ 2 6157 6158 /* Max number of disallowed bitmap combination 6159 * sent to firmware 6160 */ 6161 #define WMI_ML_MAX_DISALLOW_BMAP_COMB 4 6162 6163 struct wmi_mlo_link_set_active_arg { 6164 enum wmi_mlo_link_force_mode force_mode; 6165 enum wmi_mlo_link_force_reason reason; 6166 u32 num_link_entry; 6167 u32 num_vdev_bitmap; 6168 u32 num_inactive_vdev_bitmap; 6169 struct wmi_mlo_link_num_arg link_num[WMI_MLO_LINK_NUM_SZ]; 6170 u32 vdev_bitmap[WMI_MLO_VDEV_BITMAP_SZ]; 6171 u32 inactive_vdev_bitmap[WMI_MLO_VDEV_BITMAP_SZ]; 6172 struct wmi_mlo_control_flags_arg ctrl_flags; 6173 bool use_ieee_link_id; 6174 struct wmi_ml_link_force_cmd_arg force_cmd; 6175 u32 num_disallow_mode_comb; 6176 struct wmi_ml_disallow_mode_bmap_arg disallow_bmap[WMI_ML_MAX_DISALLOW_BMAP_COMB]; 6177 }; 6178 6179 void ath12k_wmi_init_qcn9274(struct ath12k_base *ab, 6180 struct ath12k_wmi_resource_config_arg *config); 6181 void ath12k_wmi_init_wcn7850(struct ath12k_base *ab, 6182 struct ath12k_wmi_resource_config_arg *config); 6183 int ath12k_wmi_cmd_send(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb, 6184 u32 cmd_id); 6185 struct sk_buff *ath12k_wmi_alloc_skb(struct ath12k_wmi_base *wmi_sc, u32 len); 6186 int ath12k_wmi_mgmt_send(struct ath12k *ar, u32 vdev_id, u32 buf_id, 6187 struct sk_buff *frame); 6188 int ath12k_wmi_p2p_go_bcn_ie(struct ath12k *ar, u32 vdev_id, 6189 const u8 *p2p_ie); 6190 int ath12k_wmi_bcn_tmpl(struct ath12k_link_vif *arvif, 6191 struct ieee80211_mutable_offsets *offs, 6192 struct sk_buff *bcn, 6193 struct ath12k_wmi_bcn_tmpl_ema_arg *ema_args); 6194 int ath12k_wmi_vdev_down(struct ath12k *ar, u8 vdev_id); 6195 int ath12k_wmi_vdev_up(struct ath12k *ar, struct ath12k_wmi_vdev_up_params *params); 6196 int ath12k_wmi_vdev_stop(struct ath12k *ar, u8 vdev_id); 6197 int ath12k_wmi_vdev_start(struct ath12k *ar, struct wmi_vdev_start_req_arg *arg, 6198 bool restart); 6199 int ath12k_wmi_set_peer_param(struct ath12k *ar, const u8 *peer_addr, 6200 u32 vdev_id, u32 param_id, u32 param_val); 6201 int ath12k_wmi_pdev_set_param(struct ath12k *ar, u32 param_id, 6202 u32 param_value, u8 pdev_id); 6203 int ath12k_wmi_pdev_set_ps_mode(struct ath12k *ar, int vdev_id, u32 enable); 6204 int ath12k_wmi_wait_for_unified_ready(struct ath12k_base *ab); 6205 int ath12k_wmi_cmd_init(struct ath12k_base *ab); 6206 int ath12k_wmi_wait_for_service_ready(struct ath12k_base *ab); 6207 int ath12k_wmi_connect(struct ath12k_base *ab); 6208 int ath12k_wmi_pdev_attach(struct ath12k_base *ab, 6209 u8 pdev_id); 6210 int ath12k_wmi_attach(struct ath12k_base *ab); 6211 void ath12k_wmi_detach(struct ath12k_base *ab); 6212 int ath12k_wmi_vdev_create(struct ath12k *ar, u8 *macaddr, 6213 struct ath12k_wmi_vdev_create_arg *arg); 6214 int ath12k_wmi_send_peer_create_cmd(struct ath12k *ar, 6215 struct ath12k_wmi_peer_create_arg *arg); 6216 int ath12k_wmi_vdev_set_param_cmd(struct ath12k *ar, u32 vdev_id, 6217 u32 param_id, u32 param_value); 6218 6219 int ath12k_wmi_set_sta_ps_param(struct ath12k *ar, u32 vdev_id, 6220 u32 param, u32 param_value); 6221 int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms); 6222 int ath12k_wmi_send_peer_delete_cmd(struct ath12k *ar, 6223 const u8 *peer_addr, u8 vdev_id); 6224 int ath12k_wmi_vdev_delete(struct ath12k *ar, u8 vdev_id); 6225 void ath12k_wmi_start_scan_init(struct ath12k *ar, 6226 struct ath12k_wmi_scan_req_arg *arg); 6227 int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar, 6228 struct ath12k_wmi_scan_req_arg *arg); 6229 int ath12k_wmi_send_scan_stop_cmd(struct ath12k *ar, 6230 struct ath12k_wmi_scan_cancel_arg *arg); 6231 int ath12k_wmi_send_wmm_update_cmd(struct ath12k *ar, u32 vdev_id, 6232 struct wmi_wmm_params_all_arg *param); 6233 int ath12k_wmi_pdev_suspend(struct ath12k *ar, u32 suspend_opt, 6234 u32 pdev_id); 6235 int ath12k_wmi_pdev_resume(struct ath12k *ar, u32 pdev_id); 6236 6237 int ath12k_wmi_send_peer_assoc_cmd(struct ath12k *ar, 6238 struct ath12k_wmi_peer_assoc_arg *arg); 6239 int ath12k_wmi_vdev_install_key(struct ath12k *ar, 6240 struct wmi_vdev_install_key_arg *arg); 6241 int ath12k_wmi_pdev_bss_chan_info_request(struct ath12k *ar, 6242 enum wmi_bss_chan_info_req_type type); 6243 int ath12k_wmi_send_pdev_temperature_cmd(struct ath12k *ar); 6244 int ath12k_wmi_send_peer_flush_tids_cmd(struct ath12k *ar, 6245 u8 peer_addr[ETH_ALEN], 6246 u32 peer_tid_bitmap, 6247 u8 vdev_id); 6248 int ath12k_wmi_send_set_ap_ps_param_cmd(struct ath12k *ar, u8 *peer_addr, 6249 struct ath12k_wmi_ap_ps_arg *arg); 6250 int ath12k_wmi_send_scan_chan_list_cmd(struct ath12k *ar, 6251 struct ath12k_wmi_scan_chan_list_arg *arg); 6252 int ath12k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath12k *ar, 6253 u32 pdev_id); 6254 int ath12k_wmi_addba_clear_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac); 6255 int ath12k_wmi_addba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac, 6256 u32 tid, u32 buf_size); 6257 int ath12k_wmi_addba_set_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac, 6258 u32 tid, u32 status); 6259 int ath12k_wmi_delba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac, 6260 u32 tid, u32 initiator, u32 reason); 6261 int ath12k_wmi_send_bcn_offload_control_cmd(struct ath12k *ar, 6262 u32 vdev_id, u32 bcn_ctrl_op); 6263 int ath12k_wmi_send_init_country_cmd(struct ath12k *ar, 6264 struct ath12k_wmi_init_country_arg *arg); 6265 int 6266 ath12k_wmi_send_set_current_country_cmd(struct ath12k *ar, 6267 struct wmi_set_current_country_arg *arg); 6268 int ath12k_wmi_peer_rx_reorder_queue_setup(struct ath12k *ar, 6269 int vdev_id, const u8 *addr, 6270 dma_addr_t paddr, u8 tid, 6271 u8 ba_window_size_valid, 6272 u32 ba_window_size); 6273 int ath12k_wmi_send_11d_scan_start_cmd(struct ath12k *ar, 6274 struct wmi_11d_scan_start_arg *arg); 6275 int ath12k_wmi_send_11d_scan_stop_cmd(struct ath12k *ar, u32 vdev_id); 6276 int 6277 ath12k_wmi_rx_reord_queue_remove(struct ath12k *ar, 6278 struct ath12k_wmi_rx_reorder_queue_remove_arg *arg); 6279 int ath12k_wmi_send_pdev_set_regdomain(struct ath12k *ar, 6280 struct ath12k_wmi_pdev_set_regdomain_arg *arg); 6281 int ath12k_wmi_simulate_radar(struct ath12k *ar); 6282 int ath12k_wmi_send_twt_enable_cmd(struct ath12k *ar, u32 pdev_id); 6283 int ath12k_wmi_send_twt_disable_cmd(struct ath12k *ar, u32 pdev_id); 6284 int ath12k_wmi_send_obss_spr_cmd(struct ath12k *ar, u32 vdev_id, 6285 struct ieee80211_he_obss_pd *he_obss_pd); 6286 int ath12k_wmi_obss_color_cfg_cmd(struct ath12k *ar, u32 vdev_id, 6287 u8 bss_color, u32 period, 6288 bool enable); 6289 int ath12k_wmi_send_bss_color_change_enable_cmd(struct ath12k *ar, u32 vdev_id, 6290 bool enable); 6291 int ath12k_wmi_pdev_lro_cfg(struct ath12k *ar, int pdev_id); 6292 int ath12k_wmi_pdev_dma_ring_cfg(struct ath12k *ar, 6293 struct ath12k_wmi_pdev_dma_ring_cfg_arg *arg); 6294 int ath12k_wmi_vdev_spectral_enable(struct ath12k *ar, u32 vdev_id, 6295 u32 trigger, u32 enable); 6296 int ath12k_wmi_vdev_spectral_conf(struct ath12k *ar, 6297 struct ath12k_wmi_vdev_spectral_conf_arg *arg); 6298 int ath12k_wmi_fils_discovery_tmpl(struct ath12k *ar, u32 vdev_id, 6299 struct sk_buff *tmpl); 6300 int ath12k_wmi_fils_discovery(struct ath12k *ar, u32 vdev_id, u32 interval, 6301 bool unsol_bcast_probe_resp_enabled); 6302 int ath12k_wmi_probe_resp_tmpl(struct ath12k *ar, u32 vdev_id, 6303 struct sk_buff *tmpl); 6304 int ath12k_wmi_set_hw_mode(struct ath12k_base *ab, 6305 enum wmi_host_hw_mode_config_type mode); 6306 int ath12k_wmi_set_bios_cmd(struct ath12k_base *ab, u32 param_id, 6307 const u8 *buf, size_t buf_len); 6308 int ath12k_wmi_set_bios_sar_cmd(struct ath12k_base *ab, const u8 *psar_table); 6309 int ath12k_wmi_set_bios_geo_cmd(struct ath12k_base *ab, const u8 *pgeo_table); 6310 int ath12k_wmi_send_stats_request_cmd(struct ath12k *ar, u32 stats_id, 6311 u32 vdev_id, u32 pdev_id); 6312 __le32 ath12k_wmi_tlv_hdr(u32 cmd, u32 len); 6313 6314 int ath12k_wmi_send_tpc_stats_request(struct ath12k *ar, 6315 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type); 6316 void ath12k_wmi_free_tpc_stats_mem(struct ath12k *ar); 6317 6318 static inline u32 6319 ath12k_wmi_caps_ext_get_pdev_id(const struct ath12k_wmi_caps_ext_params *param) 6320 { 6321 return le32_get_bits(param->pdev_and_hw_link_ids, WMI_CAPS_PARAMS_PDEV_ID); 6322 } 6323 6324 static inline u32 6325 ath12k_wmi_caps_ext_get_hw_link_id(const struct ath12k_wmi_caps_ext_params *param) 6326 { 6327 return le32_get_bits(param->pdev_and_hw_link_ids, WMI_CAPS_PARAMS_HW_LINK_ID); 6328 } 6329 6330 static inline u32 6331 ath12k_wmi_mac_phy_get_pdev_id(const struct ath12k_wmi_mac_phy_caps_params *param) 6332 { 6333 return le32_get_bits(param->pdev_and_hw_link_ids, 6334 WMI_CAPS_PARAMS_PDEV_ID); 6335 } 6336 6337 static inline u32 6338 ath12k_wmi_mac_phy_get_hw_link_id(const struct ath12k_wmi_mac_phy_caps_params *param) 6339 { 6340 return le32_get_bits(param->pdev_and_hw_link_ids, 6341 WMI_CAPS_PARAMS_HW_LINK_ID); 6342 } 6343 6344 int ath12k_wmi_wow_host_wakeup_ind(struct ath12k *ar); 6345 int ath12k_wmi_wow_enable(struct ath12k *ar); 6346 int ath12k_wmi_wow_del_pattern(struct ath12k *ar, u32 vdev_id, u32 pattern_id); 6347 int ath12k_wmi_wow_add_pattern(struct ath12k *ar, u32 vdev_id, u32 pattern_id, 6348 const u8 *pattern, const u8 *mask, 6349 int pattern_len, int pattern_offset); 6350 int ath12k_wmi_wow_add_wakeup_event(struct ath12k *ar, u32 vdev_id, 6351 enum wmi_wow_wakeup_event event, 6352 u32 enable); 6353 int ath12k_wmi_wow_config_pno(struct ath12k *ar, u32 vdev_id, 6354 struct wmi_pno_scan_req_arg *pno_scan); 6355 int ath12k_wmi_hw_data_filter_cmd(struct ath12k *ar, 6356 struct wmi_hw_data_filter_arg *arg); 6357 int ath12k_wmi_arp_ns_offload(struct ath12k *ar, 6358 struct ath12k_link_vif *arvif, 6359 struct wmi_arp_ns_offload_arg *offload, 6360 bool enable); 6361 int ath12k_wmi_gtk_rekey_offload(struct ath12k *ar, 6362 struct ath12k_link_vif *arvif, bool enable); 6363 int ath12k_wmi_gtk_rekey_getinfo(struct ath12k *ar, 6364 struct ath12k_link_vif *arvif); 6365 int ath12k_wmi_sta_keepalive(struct ath12k *ar, 6366 const struct wmi_sta_keepalive_arg *arg); 6367 int ath12k_wmi_mlo_setup(struct ath12k *ar, struct wmi_mlo_setup_arg *mlo_params); 6368 int ath12k_wmi_mlo_ready(struct ath12k *ar); 6369 int ath12k_wmi_mlo_teardown(struct ath12k *ar); 6370 void ath12k_wmi_fw_stats_dump(struct ath12k *ar, 6371 struct ath12k_fw_stats *fw_stats, u32 stats_id, 6372 char *buf); 6373 bool ath12k_wmi_supports_6ghz_cc_ext(struct ath12k *ar); 6374 int ath12k_wmi_send_vdev_set_tpc_power(struct ath12k *ar, 6375 u32 vdev_id, 6376 struct ath12k_reg_tpc_power_info *param); 6377 int ath12k_wmi_send_mlo_link_set_active_cmd(struct ath12k_base *ab, 6378 struct wmi_mlo_link_set_active_arg *param); 6379 #endif 6380