1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_WMI_H 8 #define ATH12K_WMI_H 9 10 #include <net/mac80211.h> 11 #include "htc.h" 12 #include "cmn_defs.h" 13 14 /* Naming conventions for structures: 15 * 16 * _cmd means that this is a firmware command sent from host to firmware. 17 * 18 * _event means that this is a firmware event sent from firmware to host 19 * 20 * _params is a structure which is embedded either into _cmd or _event (or 21 * both), it is not sent individually. 22 * 23 * _arg is used inside the host, the firmware does not see that at all. 24 */ 25 26 struct ath12k_base; 27 struct ath12k; 28 struct ath12k_link_vif; 29 struct ath12k_fw_stats; 30 struct ath12k_reg_tpc_power_info; 31 32 /* There is no signed version of __le32, so for a temporary solution come 33 * up with our own version. The idea is from fs/ntfs/endian.h. 34 * 35 * Use a_ prefix so that it doesn't conflict if we get proper support to 36 * linux/types.h. 37 */ 38 typedef __s32 __bitwise a_sle32; 39 40 static inline a_sle32 a_cpu_to_sle32(s32 val) 41 { 42 return (__force a_sle32)cpu_to_le32(val); 43 } 44 45 static inline s32 a_sle32_to_cpu(a_sle32 val) 46 { 47 return le32_to_cpu((__force __le32)val); 48 } 49 50 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 51 #define MAX_HE_NSS 8 52 #define MAX_HE_MODULATION 8 53 #define MAX_HE_RU 4 54 #define HE_MODULATION_NONE 7 55 #define HE_PET_0_USEC 0 56 #define HE_PET_8_USEC 1 57 #define HE_PET_16_USEC 2 58 59 #define WMI_MAX_CHAINS 8 60 61 #define WMI_MAX_NUM_SS MAX_HE_NSS 62 #define WMI_MAX_NUM_RU MAX_HE_RU 63 64 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 65 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 66 #define WMI_TLV_CMD_UNSUPPORTED 0 67 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 68 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 69 70 struct wmi_cmd_hdr { 71 __le32 cmd_id; 72 } __packed; 73 74 struct wmi_tlv { 75 __le32 header; 76 u8 value[]; 77 } __packed; 78 79 #define WMI_TLV_LEN GENMASK(15, 0) 80 #define WMI_TLV_TAG GENMASK(31, 16) 81 #define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header) 82 83 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 84 #define WMI_MAX_MEM_REQS 32 85 #define ATH12K_MAX_HW_LISTEN_INTERVAL 5 86 87 #define WMI_HOST_RC_DS_FLAG 0x01 88 #define WMI_HOST_RC_CW40_FLAG 0x02 89 #define WMI_HOST_RC_SGI_FLAG 0x04 90 #define WMI_HOST_RC_HT_FLAG 0x08 91 #define WMI_HOST_RC_RTSCTS_FLAG 0x10 92 #define WMI_HOST_RC_TX_STBC_FLAG 0x20 93 #define WMI_HOST_RC_RX_STBC_FLAG 0xC0 94 #define WMI_HOST_RC_RX_STBC_FLAG_S 6 95 #define WMI_HOST_RC_WEP_TKIP_FLAG 0x100 96 #define WMI_HOST_RC_TS_FLAG 0x200 97 #define WMI_HOST_RC_UAPSD_FLAG 0x400 98 99 #define WMI_HT_CAP_ENABLED 0x0001 100 #define WMI_HT_CAP_HT20_SGI 0x0002 101 #define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 102 #define WMI_HT_CAP_TX_STBC 0x0008 103 #define WMI_HT_CAP_TX_STBC_MASK_SHIFT 3 104 #define WMI_HT_CAP_RX_STBC 0x0030 105 #define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4 106 #define WMI_HT_CAP_LDPC 0x0040 107 #define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 108 #define WMI_HT_CAP_MPDU_DENSITY 0x0700 109 #define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT 8 110 #define WMI_HT_CAP_HT40_SGI 0x0800 111 #define WMI_HT_CAP_RX_LDPC 0x1000 112 #define WMI_HT_CAP_TX_LDPC 0x2000 113 #define WMI_HT_CAP_IBF_BFER 0x4000 114 115 /* These macros should be used when we wish to advertise STBC support for 116 * only 1SS or 2SS or 3SS. 117 */ 118 #define WMI_HT_CAP_RX_STBC_1SS 0x0010 119 #define WMI_HT_CAP_RX_STBC_2SS 0x0020 120 #define WMI_HT_CAP_RX_STBC_3SS 0x0030 121 122 #define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED | \ 123 WMI_HT_CAP_HT20_SGI | \ 124 WMI_HT_CAP_HT40_SGI | \ 125 WMI_HT_CAP_TX_STBC | \ 126 WMI_HT_CAP_RX_STBC | \ 127 WMI_HT_CAP_LDPC) 128 129 #define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003 130 #define WMI_VHT_CAP_RX_LDPC 0x00000010 131 #define WMI_VHT_CAP_SGI_80MHZ 0x00000020 132 #define WMI_VHT_CAP_SGI_160MHZ 0x00000040 133 #define WMI_VHT_CAP_TX_STBC 0x00000080 134 #define WMI_VHT_CAP_RX_STBC_MASK 0x00000300 135 #define WMI_VHT_CAP_RX_STBC_MASK_SHIFT 8 136 #define WMI_VHT_CAP_SU_BFER 0x00000800 137 #define WMI_VHT_CAP_SU_BFEE 0x00001000 138 #define WMI_VHT_CAP_MAX_CS_ANT_MASK 0x0000E000 139 #define WMI_VHT_CAP_MAX_CS_ANT_MASK_SHIFT 13 140 #define WMI_VHT_CAP_MAX_SND_DIM_MASK 0x00070000 141 #define WMI_VHT_CAP_MAX_SND_DIM_MASK_SHIFT 16 142 #define WMI_VHT_CAP_MU_BFER 0x00080000 143 #define WMI_VHT_CAP_MU_BFEE 0x00100000 144 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000 145 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIT 23 146 #define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000 147 #define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000 148 149 #define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002 150 151 /* These macros should be used when we wish to advertise STBC support for 152 * only 1SS or 2SS or 3SS. 153 */ 154 #define WMI_VHT_CAP_RX_STBC_1SS 0x00000100 155 #define WMI_VHT_CAP_RX_STBC_2SS 0x00000200 156 #define WMI_VHT_CAP_RX_STBC_3SS 0x00000300 157 158 #define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \ 159 WMI_VHT_CAP_SGI_80MHZ | \ 160 WMI_VHT_CAP_TX_STBC | \ 161 WMI_VHT_CAP_RX_STBC_MASK | \ 162 WMI_VHT_CAP_RX_LDPC | \ 163 WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \ 164 WMI_VHT_CAP_RX_FIXED_ANT | \ 165 WMI_VHT_CAP_TX_FIXED_ANT) 166 167 #define WLAN_SCAN_MAX_HINT_S_SSID 10 168 #define WLAN_SCAN_MAX_HINT_BSSID 10 169 #define MAX_RNR_BSS 5 170 171 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 172 173 #define WMI_BA_MODE_BUFFER_SIZE_256 3 174 175 /* HW mode config type replicated from FW header 176 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 177 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 178 * one in 2G and another in 5G. 179 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 180 * same band; no tx allowed. 181 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 182 * Support for both PHYs within one band is planned 183 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 184 * but could be extended to other bands in the future. 185 * The separation of the band between the two PHYs needs 186 * to be communicated separately. 187 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 188 * as in WMI_HW_MODE_SBS, and 3rd on the other band 189 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 190 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 191 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 192 */ 193 enum wmi_host_hw_mode_config_type { 194 WMI_HOST_HW_MODE_SINGLE = 0, 195 WMI_HOST_HW_MODE_DBS = 1, 196 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 197 WMI_HOST_HW_MODE_SBS = 3, 198 WMI_HOST_HW_MODE_DBS_SBS = 4, 199 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 200 201 /* keep last */ 202 WMI_HOST_HW_MODE_MAX 203 }; 204 205 /* HW mode priority values used to detect the preferred HW mode 206 * on the available modes. 207 */ 208 enum wmi_host_hw_mode_priority { 209 WMI_HOST_HW_MODE_DBS_SBS_PRI, 210 WMI_HOST_HW_MODE_DBS_PRI, 211 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 212 WMI_HOST_HW_MODE_SBS_PRI, 213 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 214 WMI_HOST_HW_MODE_SINGLE_PRI, 215 216 /* keep last the lowest priority */ 217 WMI_HOST_HW_MODE_MAX_PRI 218 }; 219 220 enum WMI_HOST_WLAN_BAND { 221 WMI_HOST_WLAN_2GHZ_CAP = 1, 222 WMI_HOST_WLAN_5GHZ_CAP = 2, 223 WMI_HOST_WLAN_2GHZ_5GHZ_CAP = 3, 224 }; 225 226 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 227 * Used for HE and EHT auto rate mode. 228 */ 229 enum { 230 /* LTF related configuration */ 231 WMI_AUTORATE_LTF_1X = BIT(0), 232 WMI_AUTORATE_LTF_2X = BIT(1), 233 WMI_AUTORATE_LTF_4X = BIT(2), 234 235 /* GI related configuration */ 236 WMI_AUTORATE_400NS_GI = BIT(8), 237 WMI_AUTORATE_800NS_GI = BIT(9), 238 WMI_AUTORATE_1600NS_GI = BIT(10), 239 WMI_AUTORATE_3200NS_GI = BIT(11), 240 }; 241 242 enum wmi_cmd_group { 243 /* 0 to 2 are reserved */ 244 WMI_GRP_START = 0x3, 245 WMI_GRP_SCAN = WMI_GRP_START, 246 WMI_GRP_PDEV = 0x4, 247 WMI_GRP_VDEV = 0x5, 248 WMI_GRP_PEER = 0x6, 249 WMI_GRP_MGMT = 0x7, 250 WMI_GRP_BA_NEG = 0x8, 251 WMI_GRP_STA_PS = 0x9, 252 WMI_GRP_DFS = 0xa, 253 WMI_GRP_ROAM = 0xb, 254 WMI_GRP_OFL_SCAN = 0xc, 255 WMI_GRP_P2P = 0xd, 256 WMI_GRP_AP_PS = 0xe, 257 WMI_GRP_RATE_CTRL = 0xf, 258 WMI_GRP_PROFILE = 0x10, 259 WMI_GRP_SUSPEND = 0x11, 260 WMI_GRP_BCN_FILTER = 0x12, 261 WMI_GRP_WOW = 0x13, 262 WMI_GRP_RTT = 0x14, 263 WMI_GRP_SPECTRAL = 0x15, 264 WMI_GRP_STATS = 0x16, 265 WMI_GRP_ARP_NS_OFL = 0x17, 266 WMI_GRP_NLO_OFL = 0x18, 267 WMI_GRP_GTK_OFL = 0x19, 268 WMI_GRP_CSA_OFL = 0x1a, 269 WMI_GRP_CHATTER = 0x1b, 270 WMI_GRP_TID_ADDBA = 0x1c, 271 WMI_GRP_MISC = 0x1d, 272 WMI_GRP_GPIO = 0x1e, 273 WMI_GRP_FWTEST = 0x1f, 274 WMI_GRP_TDLS = 0x20, 275 WMI_GRP_RESMGR = 0x21, 276 WMI_GRP_STA_SMPS = 0x22, 277 WMI_GRP_WLAN_HB = 0x23, 278 WMI_GRP_RMC = 0x24, 279 WMI_GRP_MHF_OFL = 0x25, 280 WMI_GRP_LOCATION_SCAN = 0x26, 281 WMI_GRP_OEM = 0x27, 282 WMI_GRP_NAN = 0x28, 283 WMI_GRP_COEX = 0x29, 284 WMI_GRP_OBSS_OFL = 0x2a, 285 WMI_GRP_LPI = 0x2b, 286 WMI_GRP_EXTSCAN = 0x2c, 287 WMI_GRP_DHCP_OFL = 0x2d, 288 WMI_GRP_IPA = 0x2e, 289 WMI_GRP_MDNS_OFL = 0x2f, 290 WMI_GRP_SAP_OFL = 0x30, 291 WMI_GRP_OCB = 0x31, 292 WMI_GRP_SOC = 0x32, 293 WMI_GRP_PKT_FILTER = 0x33, 294 WMI_GRP_MAWC = 0x34, 295 WMI_GRP_PMF_OFFLOAD = 0x35, 296 WMI_GRP_BPF_OFFLOAD = 0x36, 297 WMI_GRP_NAN_DATA = 0x37, 298 WMI_GRP_PROTOTYPE = 0x38, 299 WMI_GRP_MONITOR = 0x39, 300 WMI_GRP_REGULATORY = 0x3a, 301 WMI_GRP_HW_DATA_FILTER = 0x3b, 302 WMI_GRP_WLM = 0x3c, 303 WMI_GRP_11K_OFFLOAD = 0x3d, 304 WMI_GRP_TWT = 0x3e, 305 WMI_GRP_MOTION_DET = 0x3f, 306 WMI_GRP_SPATIAL_REUSE = 0x40, 307 WMI_GRP_MLO = 0x48, 308 }; 309 310 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 311 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 312 313 enum wmi_tlv_cmd_id { 314 WMI_CMD_UNSUPPORTED = 0, 315 WMI_INIT_CMDID = 0x1, 316 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 317 WMI_STOP_SCAN_CMDID, 318 WMI_SCAN_CHAN_LIST_CMDID, 319 WMI_SCAN_SCH_PRIO_TBL_CMDID, 320 WMI_SCAN_UPDATE_REQUEST_CMDID, 321 WMI_SCAN_PROB_REQ_OUI_CMDID, 322 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 323 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 324 WMI_PDEV_SET_CHANNEL_CMDID, 325 WMI_PDEV_SET_PARAM_CMDID, 326 WMI_PDEV_PKTLOG_ENABLE_CMDID, 327 WMI_PDEV_PKTLOG_DISABLE_CMDID, 328 WMI_PDEV_SET_WMM_PARAMS_CMDID, 329 WMI_PDEV_SET_HT_CAP_IE_CMDID, 330 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 331 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 332 WMI_PDEV_SET_QUIET_MODE_CMDID, 333 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 334 WMI_PDEV_GET_TPC_CONFIG_CMDID, 335 WMI_PDEV_SET_BASE_MACADDR_CMDID, 336 WMI_PDEV_DUMP_CMDID, 337 WMI_PDEV_SET_LED_CONFIG_CMDID, 338 WMI_PDEV_GET_TEMPERATURE_CMDID, 339 WMI_PDEV_SET_LED_FLASHING_CMDID, 340 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 341 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 342 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 343 WMI_PDEV_SET_CTL_TABLE_CMDID, 344 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 345 WMI_PDEV_FIPS_CMDID, 346 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 347 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 348 WMI_PDEV_GET_NFCAL_POWER_CMDID, 349 WMI_PDEV_GET_TPC_CMDID, 350 WMI_MIB_STATS_ENABLE_CMDID, 351 WMI_PDEV_SET_PCL_CMDID, 352 WMI_PDEV_SET_HW_MODE_CMDID, 353 WMI_PDEV_SET_MAC_CONFIG_CMDID, 354 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 355 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 356 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 357 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 358 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 359 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 360 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 361 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 362 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 363 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 364 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 365 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 366 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 367 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 368 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 369 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 370 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 371 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 372 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 373 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 374 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 375 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 376 WMI_PDEV_PKTLOG_FILTER_CMDID, 377 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID = 0x403b, 378 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 379 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 380 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 381 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 382 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 383 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID = 0x4044, 384 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID = 0x4045, 385 WMI_PDEV_SET_BIOS_INTERFACE_CMDID = 0x404A, 386 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 387 WMI_VDEV_DELETE_CMDID, 388 WMI_VDEV_START_REQUEST_CMDID, 389 WMI_VDEV_RESTART_REQUEST_CMDID, 390 WMI_VDEV_UP_CMDID, 391 WMI_VDEV_STOP_CMDID, 392 WMI_VDEV_DOWN_CMDID, 393 WMI_VDEV_SET_PARAM_CMDID, 394 WMI_VDEV_INSTALL_KEY_CMDID, 395 WMI_VDEV_WNM_SLEEPMODE_CMDID, 396 WMI_VDEV_WMM_ADDTS_CMDID, 397 WMI_VDEV_WMM_DELTS_CMDID, 398 WMI_VDEV_SET_WMM_PARAMS_CMDID, 399 WMI_VDEV_SET_GTX_PARAMS_CMDID, 400 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 401 WMI_VDEV_PLMREQ_START_CMDID, 402 WMI_VDEV_PLMREQ_STOP_CMDID, 403 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 404 WMI_VDEV_SET_IE_CMDID, 405 WMI_VDEV_RATEMASK_CMDID, 406 WMI_VDEV_ATF_REQUEST_CMDID, 407 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 408 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 409 WMI_VDEV_SET_QUIET_MODE_CMDID, 410 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 411 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 412 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 413 WMI_VDEV_SET_ARP_STAT_CMDID, 414 WMI_VDEV_GET_ARP_STAT_CMDID, 415 WMI_VDEV_GET_TX_POWER_CMDID, 416 WMI_VDEV_LIMIT_OFFCHAN_CMDID, 417 WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID, 418 WMI_VDEV_CHAINMASK_CONFIG_CMDID, 419 WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID, 420 WMI_VDEV_GET_MWS_COEX_INFO_CMDID, 421 WMI_VDEV_DELETE_ALL_PEER_CMDID, 422 WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID, 423 WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID, 424 WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID, 425 WMI_VDEV_SET_PCL_CMDID, 426 WMI_VDEV_GET_BIG_DATA_CMDID, 427 WMI_VDEV_GET_BIG_DATA_P2_CMDID, 428 WMI_VDEV_SET_TPC_POWER_CMDID, 429 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 430 WMI_PEER_DELETE_CMDID, 431 WMI_PEER_FLUSH_TIDS_CMDID, 432 WMI_PEER_SET_PARAM_CMDID, 433 WMI_PEER_ASSOC_CMDID, 434 WMI_PEER_ADD_WDS_ENTRY_CMDID, 435 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 436 WMI_PEER_MCAST_GROUP_CMDID, 437 WMI_PEER_INFO_REQ_CMDID, 438 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 439 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 440 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 441 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 442 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 443 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 444 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 445 WMI_PEER_ATF_REQUEST_CMDID, 446 WMI_PEER_BWF_REQUEST_CMDID, 447 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 448 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 449 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 450 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 451 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 452 WMI_PDEV_SEND_BCN_CMDID, 453 WMI_BCN_TMPL_CMDID, 454 WMI_BCN_FILTER_RX_CMDID, 455 WMI_PRB_REQ_FILTER_RX_CMDID, 456 WMI_MGMT_TX_CMDID, 457 WMI_PRB_TMPL_CMDID, 458 WMI_MGMT_TX_SEND_CMDID, 459 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 460 WMI_PDEV_SEND_FD_CMDID, 461 WMI_BCN_OFFLOAD_CTRL_CMDID, 462 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 463 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 464 WMI_FILS_DISCOVERY_TMPL_CMDID, 465 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 466 WMI_ADDBA_SEND_CMDID, 467 WMI_ADDBA_STATUS_CMDID, 468 WMI_DELBA_SEND_CMDID, 469 WMI_ADDBA_SET_RESP_CMDID, 470 WMI_SEND_SINGLEAMSDU_CMDID, 471 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 472 WMI_STA_POWERSAVE_PARAM_CMDID, 473 WMI_STA_MIMO_PS_MODE_CMDID, 474 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 475 WMI_PDEV_DFS_DISABLE_CMDID, 476 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 477 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 478 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 479 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 480 WMI_VDEV_ADFS_CH_CFG_CMDID, 481 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 482 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 483 WMI_ROAM_SCAN_RSSI_THRESHOLD, 484 WMI_ROAM_SCAN_PERIOD, 485 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 486 WMI_ROAM_AP_PROFILE, 487 WMI_ROAM_CHAN_LIST, 488 WMI_ROAM_SCAN_CMD, 489 WMI_ROAM_SYNCH_COMPLETE, 490 WMI_ROAM_SET_RIC_REQUEST_CMDID, 491 WMI_ROAM_INVOKE_CMDID, 492 WMI_ROAM_FILTER_CMDID, 493 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 494 WMI_ROAM_CONFIGURE_MAWC_CMDID, 495 WMI_ROAM_SET_MBO_PARAM_CMDID, 496 WMI_ROAM_PER_CONFIG_CMDID, 497 WMI_ROAM_BTM_CONFIG_CMDID, 498 WMI_ENABLE_FILS_CMDID, 499 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 500 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 501 WMI_OFL_SCAN_PERIOD, 502 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 503 WMI_P2P_DEV_SET_DISCOVERABILITY, 504 WMI_P2P_GO_SET_BEACON_IE, 505 WMI_P2P_GO_SET_PROBE_RESP_IE, 506 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 507 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 508 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 509 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 510 WMI_P2P_SET_OPPPS_PARAM_CMDID, 511 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 512 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 513 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 514 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 515 WMI_AP_PS_EGAP_PARAM_CMDID, 516 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 517 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 518 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 519 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 520 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 521 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 522 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 523 WMI_PDEV_RESUME_CMDID, 524 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 525 WMI_RMV_BCN_FILTER_CMDID, 526 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 527 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 528 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 529 WMI_WOW_ENABLE_CMDID, 530 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 531 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 532 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 533 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 534 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 535 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 536 WMI_EXTWOW_ENABLE_CMDID, 537 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 538 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 539 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 540 WMI_WOW_UDP_SVC_OFLD_CMDID, 541 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 542 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 543 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 544 WMI_RTT_TSF_CMDID, 545 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 546 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 547 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 548 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 549 WMI_REQUEST_STATS_EXT_CMDID, 550 WMI_REQUEST_LINK_STATS_CMDID, 551 WMI_START_LINK_STATS_CMDID, 552 WMI_CLEAR_LINK_STATS_CMDID, 553 WMI_GET_FW_MEM_DUMP_CMDID, 554 WMI_DEBUG_MESG_FLUSH_CMDID, 555 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 556 WMI_REQUEST_WLAN_STATS_CMDID, 557 WMI_REQUEST_RCPI_CMDID, 558 WMI_REQUEST_PEER_STATS_INFO_CMDID, 559 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 560 WMI_REQUEST_WLM_STATS_CMDID, 561 WMI_REQUEST_CTRL_PATH_STATS_CMDID, 562 WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID = WMI_REQUEST_CTRL_PATH_STATS_CMDID + 3, 563 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 564 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 565 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 566 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 567 WMI_APFIND_CMDID, 568 WMI_PASSPOINT_LIST_CONFIG_CMDID, 569 WMI_NLO_CONFIGURE_MAWC_CMDID, 570 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 571 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 572 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 573 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 574 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 575 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 576 WMI_CHATTER_COALESCING_QUERY_CMDID, 577 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 578 WMI_PEER_TID_DELBA_CMDID, 579 WMI_STA_DTIM_PS_METHOD_CMDID, 580 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 581 WMI_STA_KEEPALIVE_CMDID, 582 WMI_BA_REQ_SSN_CMDID, 583 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 584 WMI_PDEV_UTF_CMDID, 585 WMI_DBGLOG_CFG_CMDID, 586 WMI_PDEV_QVIT_CMDID, 587 WMI_PDEV_FTM_INTG_CMDID, 588 WMI_VDEV_SET_KEEPALIVE_CMDID, 589 WMI_VDEV_GET_KEEPALIVE_CMDID, 590 WMI_FORCE_FW_HANG_CMDID, 591 WMI_SET_MCASTBCAST_FILTER_CMDID, 592 WMI_THERMAL_MGMT_CMDID, 593 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 594 WMI_TPC_CHAINMASK_CONFIG_CMDID, 595 WMI_SET_ANTENNA_DIVERSITY_CMDID, 596 WMI_OCB_SET_SCHED_CMDID, 597 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 598 WMI_LRO_CONFIG_CMDID, 599 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 600 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 601 WMI_VDEV_WISA_CMDID, 602 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 603 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 604 WMI_READ_DATA_FROM_FLASH_CMDID, 605 WMI_THERM_THROT_SET_CONF_CMDID, 606 WMI_RUNTIME_DPD_RECAL_CMDID, 607 WMI_GET_TPC_POWER_CMDID, 608 WMI_IDLE_TRIGGER_MONITOR_CMDID, 609 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 610 WMI_GPIO_OUTPUT_CMDID, 611 WMI_TXBF_CMDID, 612 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 613 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 614 WMI_UNIT_TEST_CMDID, 615 WMI_FWTEST_CMDID, 616 WMI_QBOOST_CFG_CMDID, 617 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 618 WMI_TDLS_PEER_UPDATE_CMDID, 619 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 620 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 621 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 622 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 623 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 624 WMI_STA_SMPS_PARAM_CMDID, 625 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 626 WMI_HB_SET_TCP_PARAMS_CMDID, 627 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 628 WMI_HB_SET_UDP_PARAMS_CMDID, 629 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 630 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 631 WMI_RMC_SET_ACTION_PERIOD_CMDID, 632 WMI_RMC_CONFIG_CMDID, 633 WMI_RMC_SET_MANUAL_LEADER_CMDID, 634 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 635 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 636 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 637 WMI_BATCH_SCAN_DISABLE_CMDID, 638 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 639 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 640 WMI_OEM_REQUEST_CMDID, 641 WMI_LPI_OEM_REQ_CMDID, 642 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 643 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 644 WMI_CHAN_AVOID_UPDATE_CMDID, 645 WMI_COEX_CONFIG_CMDID, 646 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 647 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 648 WMI_SAR_LIMITS_CMDID, 649 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 650 WMI_OBSS_SCAN_DISABLE_CMDID, 651 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 652 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 653 WMI_LPI_START_SCAN_CMDID, 654 WMI_LPI_STOP_SCAN_CMDID, 655 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 656 WMI_EXTSCAN_STOP_CMDID, 657 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 658 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 659 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 660 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 661 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 662 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 663 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 664 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 665 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 666 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 667 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 668 WMI_MDNS_SET_FQDN_CMDID, 669 WMI_MDNS_SET_RESPONSE_CMDID, 670 WMI_MDNS_GET_STATS_CMDID, 671 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 672 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 673 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 674 WMI_OCB_SET_UTC_TIME_CMDID, 675 WMI_OCB_START_TIMING_ADVERT_CMDID, 676 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 677 WMI_OCB_GET_TSF_TIMER_CMDID, 678 WMI_DCC_GET_STATS_CMDID, 679 WMI_DCC_CLEAR_STATS_CMDID, 680 WMI_DCC_UPDATE_NDL_CMDID, 681 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 682 WMI_SOC_SET_HW_MODE_CMDID, 683 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 684 WMI_SOC_SET_ANTENNA_MODE_CMDID, 685 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 686 WMI_PACKET_FILTER_ENABLE_CMDID, 687 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 688 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 689 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 690 WMI_BPF_GET_VDEV_STATS_CMDID, 691 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 692 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 693 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 694 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 695 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 696 WMI_11D_SCAN_START_CMDID, 697 WMI_11D_SCAN_STOP_CMDID, 698 WMI_SET_INIT_COUNTRY_CMDID, 699 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 700 WMI_NDP_INITIATOR_REQ_CMDID, 701 WMI_NDP_RESPONDER_REQ_CMDID, 702 WMI_NDP_END_REQ_CMDID, 703 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 704 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 705 WMI_TWT_DISABLE_CMDID, 706 WMI_TWT_ADD_DIALOG_CMDID, 707 WMI_TWT_DEL_DIALOG_CMDID, 708 WMI_TWT_PAUSE_DIALOG_CMDID, 709 WMI_TWT_RESUME_DIALOG_CMDID, 710 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 711 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 712 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 713 WMI_MLO_LINK_SET_ACTIVE_CMDID = WMI_TLV_CMD(WMI_GRP_MLO), 714 WMI_MLO_SETUP_CMDID, 715 WMI_MLO_READY_CMDID, 716 WMI_MLO_TEARDOWN_CMDID, 717 }; 718 719 enum wmi_tlv_event_id { 720 WMI_SERVICE_READY_EVENTID = 0x1, 721 WMI_READY_EVENTID, 722 WMI_SERVICE_AVAILABLE_EVENTID, 723 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 724 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 725 WMI_CHAN_INFO_EVENTID, 726 WMI_PHYERR_EVENTID, 727 WMI_PDEV_DUMP_EVENTID, 728 WMI_TX_PAUSE_EVENTID, 729 WMI_DFS_RADAR_EVENTID, 730 WMI_PDEV_L1SS_TRACK_EVENTID, 731 WMI_PDEV_TEMPERATURE_EVENTID, 732 WMI_SERVICE_READY_EXT_EVENTID, 733 WMI_PDEV_FIPS_EVENTID, 734 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 735 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 736 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 737 WMI_PDEV_TPC_EVENTID, 738 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 739 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 740 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 741 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 742 WMI_PDEV_ANTDIV_STATUS_EVENTID, 743 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 744 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 745 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 746 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 747 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 748 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 749 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 750 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 751 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 752 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 753 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 754 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 755 WMI_PDEV_RAP_INFO_EVENTID, 756 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 757 WMI_SERVICE_READY_EXT2_EVENTID, 758 WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID = 759 WMI_SERVICE_READY_EXT2_EVENTID + 4, 760 WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID = 761 WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID + 5, 762 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 763 WMI_VDEV_STOPPED_EVENTID, 764 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 765 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 766 WMI_VDEV_TSF_REPORT_EVENTID, 767 WMI_VDEV_DELETE_RESP_EVENTID, 768 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 769 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 770 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 771 WMI_PEER_INFO_EVENTID, 772 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 773 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 774 WMI_PEER_STATE_EVENTID, 775 WMI_PEER_ASSOC_CONF_EVENTID, 776 WMI_PEER_DELETE_RESP_EVENTID, 777 WMI_PEER_RATECODE_LIST_EVENTID, 778 WMI_WDS_PEER_EVENTID, 779 WMI_PEER_STA_PS_STATECHG_EVENTID, 780 WMI_PEER_ANTDIV_INFO_EVENTID, 781 WMI_PEER_RESERVED0_EVENTID, 782 WMI_PEER_RESERVED1_EVENTID, 783 WMI_PEER_RESERVED2_EVENTID, 784 WMI_PEER_RESERVED3_EVENTID, 785 WMI_PEER_RESERVED4_EVENTID, 786 WMI_PEER_RESERVED5_EVENTID, 787 WMI_PEER_RESERVED6_EVENTID, 788 WMI_PEER_RESERVED7_EVENTID, 789 WMI_PEER_RESERVED8_EVENTID, 790 WMI_PEER_RESERVED9_EVENTID, 791 WMI_PEER_RESERVED10_EVENTID, 792 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 793 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 794 WMI_HOST_SWBA_EVENTID, 795 WMI_TBTTOFFSET_UPDATE_EVENTID, 796 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 797 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 798 WMI_MGMT_TX_COMPLETION_EVENTID, 799 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 800 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 801 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 802 WMI_HOST_FILS_DISCOVERY_EVENTID, 803 WMI_MGMT_RX_FW_CONSUMED_EVENTID = WMI_HOST_FILS_DISCOVERY_EVENTID + 3, 804 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 805 WMI_TX_ADDBA_COMPLETE_EVENTID, 806 WMI_BA_RSP_SSN_EVENTID, 807 WMI_AGGR_STATE_TRIG_EVENTID, 808 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 809 WMI_PROFILE_MATCH, 810 WMI_ROAM_SYNCH_EVENTID, 811 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 812 WMI_P2P_NOA_EVENTID, 813 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 814 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 815 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 816 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 817 WMI_D0_WOW_DISABLE_ACK_EVENTID, 818 WMI_WOW_INITIAL_WAKEUP_EVENTID, 819 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 820 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 821 WMI_RTT_ERROR_REPORT_EVENTID, 822 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 823 WMI_IFACE_LINK_STATS_EVENTID, 824 WMI_PEER_LINK_STATS_EVENTID, 825 WMI_RADIO_LINK_STATS_EVENTID, 826 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 827 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 828 WMI_INST_RSSI_STATS_EVENTID, 829 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 830 WMI_REPORT_STATS_EVENTID, 831 WMI_UPDATE_RCPI_EVENTID, 832 WMI_PEER_STATS_INFO_EVENTID, 833 WMI_RADIO_CHAN_STATS_EVENTID, 834 WMI_WLM_STATS_EVENTID, 835 WMI_CTRL_PATH_STATS_EVENTID, 836 WMI_HALPHY_STATS_CTRL_PATH_EVENTID, 837 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 838 WMI_NLO_SCAN_COMPLETE_EVENTID, 839 WMI_APFIND_EVENTID, 840 WMI_PASSPOINT_MATCH_EVENTID, 841 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 842 WMI_GTK_REKEY_FAIL_EVENTID, 843 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 844 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 845 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 846 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 847 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 848 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 849 WMI_PDEV_UTF_EVENTID, 850 WMI_DEBUG_MESG_EVENTID, 851 WMI_UPDATE_STATS_EVENTID, 852 WMI_DEBUG_PRINT_EVENTID, 853 WMI_DCS_INTERFERENCE_EVENTID, 854 WMI_PDEV_QVIT_EVENTID, 855 WMI_WLAN_PROFILE_DATA_EVENTID, 856 WMI_PDEV_FTM_INTG_EVENTID, 857 WMI_WLAN_FREQ_AVOID_EVENTID, 858 WMI_VDEV_GET_KEEPALIVE_EVENTID, 859 WMI_THERMAL_MGMT_EVENTID, 860 WMI_DIAG_DATA_CONTAINER_EVENTID, 861 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 862 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 863 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 864 WMI_DIAG_EVENTID, 865 WMI_OCB_SET_SCHED_EVENTID, 866 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 867 WMI_RSSI_BREACH_EVENTID, 868 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 869 WMI_PDEV_UTF_SCPC_EVENTID, 870 WMI_READ_DATA_FROM_FLASH_EVENTID, 871 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 872 WMI_PKGID_EVENTID, 873 WMI_THERM_THROT_STATS_EVENTID, 874 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 875 WMI_UPLOADH_EVENTID, 876 WMI_CAPTUREH_EVENTID, 877 WMI_RFKILL_STATE_CHANGE_EVENTID, 878 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 879 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 880 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 881 WMI_BATCH_SCAN_RESULT_EVENTID, 882 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 883 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 884 WMI_OEM_ERROR_REPORT_EVENTID, 885 WMI_OEM_RESPONSE_EVENTID, 886 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 887 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 888 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 889 WMI_NAN_STARTED_CLUSTER_EVENTID, 890 WMI_NAN_JOINED_CLUSTER_EVENTID, 891 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 892 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 893 WMI_LPI_STATUS_EVENTID, 894 WMI_LPI_HANDOFF_EVENTID, 895 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 896 WMI_EXTSCAN_OPERATION_EVENTID, 897 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 898 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 899 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 900 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 901 WMI_EXTSCAN_CAPABILITIES_EVENTID, 902 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 903 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 904 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 905 WMI_SAP_OFL_DEL_STA_EVENTID, 906 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 907 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 908 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 909 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 910 WMI_DCC_GET_STATS_RESP_EVENTID, 911 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 912 WMI_DCC_STATS_EVENTID, 913 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 914 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 915 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 916 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 917 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 918 WMI_BPF_VDEV_STATS_INFO_EVENTID, 919 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 920 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 921 WMI_11D_NEW_COUNTRY_EVENTID, 922 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 923 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 924 WMI_NDP_INITIATOR_RSP_EVENTID, 925 WMI_NDP_RESPONDER_RSP_EVENTID, 926 WMI_NDP_END_RSP_EVENTID, 927 WMI_NDP_INDICATION_EVENTID, 928 WMI_NDP_CONFIRM_EVENTID, 929 WMI_NDP_END_INDICATION_EVENTID, 930 931 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 932 WMI_TWT_DISABLE_EVENTID, 933 WMI_TWT_ADD_DIALOG_EVENTID, 934 WMI_TWT_DEL_DIALOG_EVENTID, 935 WMI_TWT_PAUSE_DIALOG_EVENTID, 936 WMI_TWT_RESUME_DIALOG_EVENTID, 937 WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MLO), 938 WMI_MLO_SETUP_COMPLETE_EVENTID, 939 WMI_MLO_TEARDOWN_COMPLETE_EVENTID, 940 }; 941 942 enum wmi_tlv_pdev_param { 943 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 944 WMI_PDEV_PARAM_RX_CHAIN_MASK, 945 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 946 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 947 WMI_PDEV_PARAM_TXPOWER_SCALE, 948 WMI_PDEV_PARAM_BEACON_GEN_MODE, 949 WMI_PDEV_PARAM_BEACON_TX_MODE, 950 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 951 WMI_PDEV_PARAM_PROTECTION_MODE, 952 WMI_PDEV_PARAM_DYNAMIC_BW, 953 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 954 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 955 WMI_PDEV_PARAM_STA_KICKOUT_TH, 956 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 957 WMI_PDEV_PARAM_LTR_ENABLE, 958 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 959 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 960 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 961 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 962 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 963 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 964 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 965 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 966 WMI_PDEV_PARAM_L1SS_ENABLE, 967 WMI_PDEV_PARAM_DSLEEP_ENABLE, 968 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 969 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 970 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 971 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 972 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 973 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 974 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 975 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 976 WMI_PDEV_PARAM_PMF_QOS, 977 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 978 WMI_PDEV_PARAM_DCS, 979 WMI_PDEV_PARAM_ANI_ENABLE, 980 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 981 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 982 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 983 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 984 WMI_PDEV_PARAM_DYNTXCHAIN, 985 WMI_PDEV_PARAM_PROXY_STA, 986 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 987 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 988 WMI_PDEV_PARAM_RFKILL_ENABLE, 989 WMI_PDEV_PARAM_BURST_DUR, 990 WMI_PDEV_PARAM_BURST_ENABLE, 991 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 992 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 993 WMI_PDEV_PARAM_L1SS_TRACK, 994 WMI_PDEV_PARAM_HYST_EN, 995 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 996 WMI_PDEV_PARAM_LED_SYS_STATE, 997 WMI_PDEV_PARAM_LED_ENABLE, 998 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 999 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 1000 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 1001 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 1002 WMI_PDEV_PARAM_CTS_CBW, 1003 WMI_PDEV_PARAM_WNTS_CONFIG, 1004 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 1005 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 1006 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 1007 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 1008 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 1009 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 1010 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 1011 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 1012 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 1013 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 1014 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 1015 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 1016 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 1017 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 1018 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 1019 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 1020 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 1021 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 1022 WMI_PDEV_PARAM_AGGR_BURST, 1023 WMI_PDEV_PARAM_RX_DECAP_MODE, 1024 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 1025 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 1026 WMI_PDEV_PARAM_ANTENNA_GAIN, 1027 WMI_PDEV_PARAM_RX_FILTER, 1028 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 1029 WMI_PDEV_PARAM_PROXY_STA_MODE, 1030 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 1031 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 1032 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 1033 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 1034 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 1035 WMI_PDEV_PARAM_BLOCK_INTERBSS, 1036 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 1037 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 1038 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 1039 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 1040 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 1041 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 1042 WMI_PDEV_PARAM_EN_STATS, 1043 WMI_PDEV_PARAM_MU_GROUP_POLICY, 1044 WMI_PDEV_PARAM_NOISE_DETECTION, 1045 WMI_PDEV_PARAM_NOISE_THRESHOLD, 1046 WMI_PDEV_PARAM_DPD_ENABLE, 1047 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 1048 WMI_PDEV_PARAM_ATF_STRICT_SCH, 1049 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 1050 WMI_PDEV_PARAM_ANT_PLZN, 1051 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 1052 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 1053 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 1054 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 1055 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 1056 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 1057 WMI_PDEV_PARAM_CCA_THRESHOLD, 1058 WMI_PDEV_PARAM_RTS_FIXED_RATE, 1059 WMI_PDEV_PARAM_PDEV_RESET, 1060 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 1061 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 1062 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 1063 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 1064 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 1065 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 1066 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 1067 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 1068 WMI_PDEV_PARAM_PROPAGATION_DELAY, 1069 WMI_PDEV_PARAM_ENA_ANT_DIV, 1070 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 1071 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 1072 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 1073 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 1074 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 1075 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 1076 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 1077 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 1078 WMI_PDEV_PARAM_TX_SCH_DELAY, 1079 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 1080 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 1081 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 1082 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 1083 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 1084 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 1085 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 1086 WMI_PDEV_PARAM_SET_CONG_CTRL_MAX_MSDUS = 0xa6, 1087 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 1088 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 1089 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 1090 }; 1091 1092 enum wmi_tlv_vdev_param { 1093 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 1094 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 1095 WMI_VDEV_PARAM_BEACON_INTERVAL, 1096 WMI_VDEV_PARAM_LISTEN_INTERVAL, 1097 WMI_VDEV_PARAM_MULTICAST_RATE, 1098 WMI_VDEV_PARAM_MGMT_TX_RATE, 1099 WMI_VDEV_PARAM_SLOT_TIME, 1100 WMI_VDEV_PARAM_PREAMBLE, 1101 WMI_VDEV_PARAM_SWBA_TIME, 1102 WMI_VDEV_STATS_UPDATE_PERIOD, 1103 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 1104 WMI_VDEV_HOST_SWBA_INTERVAL, 1105 WMI_VDEV_PARAM_DTIM_PERIOD, 1106 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 1107 WMI_VDEV_PARAM_WDS, 1108 WMI_VDEV_PARAM_ATIM_WINDOW, 1109 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 1110 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 1111 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 1112 WMI_VDEV_PARAM_FEATURE_WMM, 1113 WMI_VDEV_PARAM_CHWIDTH, 1114 WMI_VDEV_PARAM_CHEXTOFFSET, 1115 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 1116 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 1117 WMI_VDEV_PARAM_MGMT_RATE, 1118 WMI_VDEV_PARAM_PROTECTION_MODE, 1119 WMI_VDEV_PARAM_FIXED_RATE, 1120 WMI_VDEV_PARAM_SGI, 1121 WMI_VDEV_PARAM_LDPC, 1122 WMI_VDEV_PARAM_TX_STBC, 1123 WMI_VDEV_PARAM_RX_STBC, 1124 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1125 WMI_VDEV_PARAM_DEF_KEYID, 1126 WMI_VDEV_PARAM_NSS, 1127 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1128 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1129 WMI_VDEV_PARAM_MCAST_INDICATE, 1130 WMI_VDEV_PARAM_DHCP_INDICATE, 1131 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1132 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1133 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1134 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1135 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1136 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1137 WMI_VDEV_PARAM_TXBF, 1138 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1139 WMI_VDEV_PARAM_DROP_UNENCRY, 1140 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1141 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1142 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1143 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1144 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1145 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1146 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1147 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1148 WMI_VDEV_PARAM_TX_PWRLIMIT, 1149 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1150 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1151 WMI_VDEV_PARAM_ENABLE_RMC, 1152 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1153 WMI_VDEV_PARAM_MAX_RATE, 1154 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1155 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1156 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1157 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1158 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1159 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1160 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1161 WMI_VDEV_PARAM_INACTIVITY_CNT, 1162 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1163 WMI_VDEV_PARAM_DTIM_POLICY, 1164 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1165 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1166 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1167 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1168 WMI_VDEV_PARAM_DISCONNECT_TH, 1169 WMI_VDEV_PARAM_RTSCTS_RATE, 1170 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1171 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1172 WMI_VDEV_PARAM_TXPOWER_SCALE, 1173 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1174 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1175 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1176 WMI_VDEV_PARAM_CABQ_MAXDUR, 1177 WMI_VDEV_PARAM_MFPTEST_SET, 1178 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1179 WMI_VDEV_PARAM_VHT_SGIMASK, 1180 WMI_VDEV_PARAM_VHT80_RATEMASK, 1181 WMI_VDEV_PARAM_PROXY_STA, 1182 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1183 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1184 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1185 WMI_VDEV_PARAM_SENSOR_AP, 1186 WMI_VDEV_PARAM_BEACON_RATE, 1187 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1188 WMI_VDEV_PARAM_STA_KICKOUT, 1189 WMI_VDEV_PARAM_CAPABILITIES, 1190 WMI_VDEV_PARAM_TSF_INCREMENT, 1191 WMI_VDEV_PARAM_AMPDU_PER_AC, 1192 WMI_VDEV_PARAM_RX_FILTER, 1193 WMI_VDEV_PARAM_MGMT_TX_POWER, 1194 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1195 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1196 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1197 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1198 WMI_VDEV_PARAM_HE_DCM, 1199 WMI_VDEV_PARAM_HE_RANGE_EXT, 1200 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1201 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1202 WMI_VDEV_PARAM_HE_LTF = 0x74, 1203 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1204 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1205 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1206 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1207 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1208 WMI_VDEV_PARAM_BSS_COLOR, 1209 WMI_VDEV_PARAM_SET_HEMU_MODE, 1210 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1211 WMI_VDEV_PARAM_SET_EHT_MU_MODE = 0x8005, 1212 WMI_VDEV_PARAM_EHT_LTF, 1213 }; 1214 1215 enum wmi_tlv_peer_flags { 1216 WMI_PEER_AUTH = 0x00000001, 1217 WMI_PEER_QOS = 0x00000002, 1218 WMI_PEER_NEED_PTK_4_WAY = 0x00000004, 1219 WMI_PEER_NEED_GTK_2_WAY = 0x00000010, 1220 WMI_PEER_HE = 0x00000400, 1221 WMI_PEER_APSD = 0x00000800, 1222 WMI_PEER_HT = 0x00001000, 1223 WMI_PEER_40MHZ = 0x00002000, 1224 WMI_PEER_STBC = 0x00008000, 1225 WMI_PEER_LDPC = 0x00010000, 1226 WMI_PEER_DYN_MIMOPS = 0x00020000, 1227 WMI_PEER_STATIC_MIMOPS = 0x00040000, 1228 WMI_PEER_SPATIAL_MUX = 0x00200000, 1229 WMI_PEER_TWT_REQ = 0x00400000, 1230 WMI_PEER_TWT_RESP = 0x00800000, 1231 WMI_PEER_VHT = 0x02000000, 1232 WMI_PEER_80MHZ = 0x04000000, 1233 WMI_PEER_PMF = 0x08000000, 1234 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1235 WMI_PEER_160MHZ = 0x40000000, 1236 WMI_PEER_SAFEMODE_EN = 0x80000000, 1237 }; 1238 1239 enum wmi_tlv_peer_flags_ext { 1240 WMI_PEER_EXT_EHT = BIT(0), 1241 WMI_PEER_EXT_320MHZ = BIT(1), 1242 }; 1243 1244 /** Enum list of TLV Tags for each parameter structure type. */ 1245 enum wmi_tlv_tag { 1246 WMI_TAG_LAST_RESERVED = 15, 1247 WMI_TAG_FIRST_ARRAY_ENUM, 1248 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1249 WMI_TAG_ARRAY_BYTE, 1250 WMI_TAG_ARRAY_STRUCT, 1251 WMI_TAG_ARRAY_FIXED_STRUCT, 1252 WMI_TAG_ARRAY_INT16, 1253 WMI_TAG_LAST_ARRAY_ENUM = 31, 1254 WMI_TAG_SERVICE_READY_EVENT, 1255 WMI_TAG_HAL_REG_CAPABILITIES, 1256 WMI_TAG_WLAN_HOST_MEM_REQ, 1257 WMI_TAG_READY_EVENT, 1258 WMI_TAG_SCAN_EVENT, 1259 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1260 WMI_TAG_CHAN_INFO_EVENT, 1261 WMI_TAG_COMB_PHYERR_RX_HDR, 1262 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1263 WMI_TAG_VDEV_STOPPED_EVENT, 1264 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1265 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1266 WMI_TAG_MGMT_RX_HDR, 1267 WMI_TAG_TBTT_OFFSET_EVENT, 1268 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1269 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1270 WMI_TAG_ROAM_EVENT, 1271 WMI_TAG_WOW_EVENT_INFO, 1272 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1273 WMI_TAG_RTT_EVENT_HEADER, 1274 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1275 WMI_TAG_RTT_MEAS_EVENT, 1276 WMI_TAG_ECHO_EVENT, 1277 WMI_TAG_FTM_INTG_EVENT, 1278 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1279 WMI_TAG_GPIO_INPUT_EVENT, 1280 WMI_TAG_CSA_EVENT, 1281 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1282 WMI_TAG_IGTK_INFO, 1283 WMI_TAG_DCS_INTERFERENCE_EVENT, 1284 WMI_TAG_ATH_DCS_CW_INT, 1285 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1286 WMI_TAG_ATH_DCS_CW_INT, 1287 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1288 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1289 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1290 WMI_TAG_WLAN_PROFILE_CTX_T, 1291 WMI_TAG_WLAN_PROFILE_T, 1292 WMI_TAG_PDEV_QVIT_EVENT, 1293 WMI_TAG_HOST_SWBA_EVENT, 1294 WMI_TAG_TIM_INFO, 1295 WMI_TAG_P2P_NOA_INFO, 1296 WMI_TAG_STATS_EVENT, 1297 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1298 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1299 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1300 WMI_TAG_INIT_CMD, 1301 WMI_TAG_RESOURCE_CONFIG, 1302 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1303 WMI_TAG_START_SCAN_CMD, 1304 WMI_TAG_STOP_SCAN_CMD, 1305 WMI_TAG_SCAN_CHAN_LIST_CMD, 1306 WMI_TAG_CHANNEL, 1307 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1308 WMI_TAG_PDEV_SET_PARAM_CMD, 1309 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1310 WMI_TAG_WMM_PARAMS, 1311 WMI_TAG_PDEV_SET_QUIET_CMD, 1312 WMI_TAG_VDEV_CREATE_CMD, 1313 WMI_TAG_VDEV_DELETE_CMD, 1314 WMI_TAG_VDEV_START_REQUEST_CMD, 1315 WMI_TAG_P2P_NOA_DESCRIPTOR, 1316 WMI_TAG_P2P_GO_SET_BEACON_IE, 1317 WMI_TAG_GTK_OFFLOAD_CMD, 1318 WMI_TAG_VDEV_UP_CMD, 1319 WMI_TAG_VDEV_STOP_CMD, 1320 WMI_TAG_VDEV_DOWN_CMD, 1321 WMI_TAG_VDEV_SET_PARAM_CMD, 1322 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1323 WMI_TAG_PEER_CREATE_CMD, 1324 WMI_TAG_PEER_DELETE_CMD, 1325 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1326 WMI_TAG_PEER_SET_PARAM_CMD, 1327 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1328 WMI_TAG_VHT_RATE_SET, 1329 WMI_TAG_BCN_TMPL_CMD, 1330 WMI_TAG_PRB_TMPL_CMD, 1331 WMI_TAG_BCN_PRB_INFO, 1332 WMI_TAG_PEER_TID_ADDBA_CMD, 1333 WMI_TAG_PEER_TID_DELBA_CMD, 1334 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1335 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1336 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1337 WMI_TAG_ROAM_SCAN_MODE, 1338 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1339 WMI_TAG_ROAM_SCAN_PERIOD, 1340 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1341 WMI_TAG_PDEV_SUSPEND_CMD, 1342 WMI_TAG_PDEV_RESUME_CMD, 1343 WMI_TAG_ADD_BCN_FILTER_CMD, 1344 WMI_TAG_RMV_BCN_FILTER_CMD, 1345 WMI_TAG_WOW_ENABLE_CMD, 1346 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1347 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1348 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1349 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1350 WMI_TAG_ARP_OFFLOAD_TUPLE, 1351 WMI_TAG_NS_OFFLOAD_TUPLE, 1352 WMI_TAG_FTM_INTG_CMD, 1353 WMI_TAG_STA_KEEPALIVE_CMD, 1354 WMI_TAG_STA_KEEPALVE_ARP_RESPONSE, 1355 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1356 WMI_TAG_AP_PS_PEER_CMD, 1357 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1358 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1359 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1360 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1361 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1362 WMI_TAG_WOW_DEL_PATTERN_CMD, 1363 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1364 WMI_TAG_RTT_MEASREQ_HEAD, 1365 WMI_TAG_RTT_MEASREQ_BODY, 1366 WMI_TAG_RTT_TSF_CMD, 1367 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1368 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1369 WMI_TAG_REQUEST_STATS_CMD, 1370 WMI_TAG_NLO_CONFIG_CMD, 1371 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1372 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1373 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1374 WMI_TAG_CHATTER_SET_MODE_CMD, 1375 WMI_TAG_ECHO_CMD, 1376 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1377 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1378 WMI_TAG_FORCE_FW_HANG_CMD, 1379 WMI_TAG_GPIO_CONFIG_CMD, 1380 WMI_TAG_GPIO_OUTPUT_CMD, 1381 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1382 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1383 WMI_TAG_BCN_TX_HDR, 1384 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1385 WMI_TAG_MGMT_TX_HDR, 1386 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1387 WMI_TAG_ADDBA_SEND_CMD, 1388 WMI_TAG_DELBA_SEND_CMD, 1389 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1390 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1391 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1392 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1393 WMI_TAG_PDEV_SET_HT_IE_CMD, 1394 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1395 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1396 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1397 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1398 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1399 WMI_TAG_PEER_MCAST_GROUP_CMD, 1400 WMI_TAG_ROAM_AP_PROFILE, 1401 WMI_TAG_AP_PROFILE, 1402 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1403 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1404 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1405 WMI_TAG_WOW_ADD_PATTERN_CMD, 1406 WMI_TAG_WOW_BITMAP_PATTERN_T, 1407 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1408 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1409 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1410 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1411 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1412 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1413 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1414 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1415 WMI_TAG_TXBF_CMD, 1416 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1417 WMI_TAG_NLO_EVENT, 1418 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1419 WMI_TAG_UPLOAD_H_HDR, 1420 WMI_TAG_CAPTURE_H_EVENT_HDR, 1421 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1422 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1423 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1424 WMI_TAG_VDEV_WMM_DELTS_CMD, 1425 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1426 WMI_TAG_TDLS_SET_STATE_CMD, 1427 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1428 WMI_TAG_TDLS_PEER_EVENT, 1429 WMI_TAG_TDLS_PEER_CAPABILITIES, 1430 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1431 WMI_TAG_ROAM_CHAN_LIST, 1432 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1433 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1434 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1435 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1436 WMI_TAG_BA_REQ_SSN_CMD, 1437 WMI_TAG_BA_RSP_SSN_EVENT, 1438 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1439 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1440 WMI_TAG_P2P_SET_OPPPS_CMD, 1441 WMI_TAG_P2P_SET_NOA_CMD, 1442 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1443 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1444 WMI_TAG_STA_SMPS_PARAM_CMD, 1445 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1446 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1447 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1448 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1449 WMI_TAG_P2P_NOA_EVENT, 1450 WMI_TAG_HB_SET_ENABLE_CMD, 1451 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1452 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1453 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1454 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1455 WMI_TAG_HB_IND_EVENT, 1456 WMI_TAG_TX_PAUSE_EVENT, 1457 WMI_TAG_RFKILL_EVENT, 1458 WMI_TAG_DFS_RADAR_EVENT, 1459 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1460 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1461 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1462 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1463 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1464 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1465 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1466 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1467 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1468 WMI_TAG_VDEV_PLMREQ_START_CMD, 1469 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1470 WMI_TAG_THERMAL_MGMT_CMD, 1471 WMI_TAG_THERMAL_MGMT_EVENT, 1472 WMI_TAG_PEER_INFO_REQ_CMD, 1473 WMI_TAG_PEER_INFO_EVENT, 1474 WMI_TAG_PEER_INFO, 1475 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1476 WMI_TAG_RMC_SET_MODE_CMD, 1477 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1478 WMI_TAG_RMC_CONFIG_CMD, 1479 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1480 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1481 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1482 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1483 WMI_TAG_NAN_CMD_PARAM, 1484 WMI_TAG_NAN_EVENT_HDR, 1485 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1486 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1487 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1488 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1489 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1490 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1491 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1492 WMI_TAG_ROAM_SCAN_CMD, 1493 WMI_TAG_REQ_STATS_EXT_CMD, 1494 WMI_TAG_STATS_EXT_EVENT, 1495 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1496 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1497 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1498 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1499 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1500 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1501 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1502 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1503 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1504 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1505 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1506 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1507 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1508 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1509 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1510 WMI_TAG_START_LINK_STATS_CMD, 1511 WMI_TAG_CLEAR_LINK_STATS_CMD, 1512 WMI_TAG_REQUEST_LINK_STATS_CMD, 1513 WMI_TAG_IFACE_LINK_STATS_EVENT, 1514 WMI_TAG_RADIO_LINK_STATS_EVENT, 1515 WMI_TAG_PEER_STATS_EVENT, 1516 WMI_TAG_CHANNEL_STATS, 1517 WMI_TAG_RADIO_LINK_STATS, 1518 WMI_TAG_RATE_STATS, 1519 WMI_TAG_PEER_LINK_STATS, 1520 WMI_TAG_WMM_AC_STATS, 1521 WMI_TAG_IFACE_LINK_STATS, 1522 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1523 WMI_TAG_LPI_START_SCAN_CMD, 1524 WMI_TAG_LPI_STOP_SCAN_CMD, 1525 WMI_TAG_LPI_RESULT_EVENT, 1526 WMI_TAG_PEER_STATE_EVENT, 1527 WMI_TAG_EXTSCAN_BUCKET_CMD, 1528 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1529 WMI_TAG_EXTSCAN_START_CMD, 1530 WMI_TAG_EXTSCAN_STOP_CMD, 1531 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1532 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1533 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1534 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1535 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1536 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1537 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1538 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1539 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1540 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1541 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1542 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1543 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1544 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1545 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1546 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1547 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1548 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1549 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1550 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1551 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1552 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1553 WMI_TAG_UNIT_TEST_CMD, 1554 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1555 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1556 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1557 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1558 WMI_TAG_ROAM_SYNCH_EVENT, 1559 WMI_TAG_ROAM_SYNCH_COMPLETE, 1560 WMI_TAG_EXTWOW_ENABLE_CMD, 1561 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1562 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1563 WMI_TAG_LPI_STATUS_EVENT, 1564 WMI_TAG_LPI_HANDOFF_EVENT, 1565 WMI_TAG_VDEV_RATE_STATS_EVENT, 1566 WMI_TAG_VDEV_RATE_HT_INFO, 1567 WMI_TAG_RIC_REQUEST, 1568 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1569 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1570 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1571 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1572 WMI_TAG_RIC_TSPEC, 1573 WMI_TAG_TPC_CHAINMASK_CONFIG, 1574 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1575 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1576 WMI_TAG_KEY_MATERIAL, 1577 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1578 WMI_TAG_SET_LED_FLASHING_CMD, 1579 WMI_TAG_MDNS_OFFLOAD_CMD, 1580 WMI_TAG_MDNS_SET_FQDN_CMD, 1581 WMI_TAG_MDNS_SET_RESP_CMD, 1582 WMI_TAG_MDNS_GET_STATS_CMD, 1583 WMI_TAG_MDNS_STATS_EVENT, 1584 WMI_TAG_ROAM_INVOKE_CMD, 1585 WMI_TAG_PDEV_RESUME_EVENT, 1586 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1587 WMI_TAG_SAP_OFL_ENABLE_CMD, 1588 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1589 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1590 WMI_TAG_APFIND_CMD_PARAM, 1591 WMI_TAG_APFIND_EVENT_HDR, 1592 WMI_TAG_OCB_SET_SCHED_CMD, 1593 WMI_TAG_OCB_SET_SCHED_EVENT, 1594 WMI_TAG_OCB_SET_CONFIG_CMD, 1595 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1596 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1597 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1598 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1599 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1600 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1601 WMI_TAG_DCC_GET_STATS_CMD, 1602 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1603 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1604 WMI_TAG_DCC_CLEAR_STATS_CMD, 1605 WMI_TAG_DCC_UPDATE_NDL_CMD, 1606 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1607 WMI_TAG_DCC_STATS_EVENT, 1608 WMI_TAG_OCB_CHANNEL, 1609 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1610 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1611 WMI_TAG_DCC_NDL_CHAN, 1612 WMI_TAG_QOS_PARAMETER, 1613 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1614 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1615 WMI_TAG_ROAM_FILTER, 1616 WMI_TAG_PASSPOINT_CONFIG_CMD, 1617 WMI_TAG_PASSPOINT_EVENT_HDR, 1618 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1619 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1620 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1621 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1622 WMI_TAG_GET_FW_MEM_DUMP, 1623 WMI_TAG_UPDATE_FW_MEM_DUMP, 1624 WMI_TAG_FW_MEM_DUMP_PARAMS, 1625 WMI_TAG_DEBUG_MESG_FLUSH, 1626 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1627 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1628 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1629 WMI_TAG_VDEV_SET_IE_CMD, 1630 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1631 WMI_TAG_RSSI_BREACH_EVENT, 1632 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1633 WMI_TAG_SOC_SET_PCL_CMD, 1634 WMI_TAG_SOC_SET_HW_MODE_CMD, 1635 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1636 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1637 WMI_TAG_VDEV_TXRX_STREAMS, 1638 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1639 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1640 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1641 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1642 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1643 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1644 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1645 WMI_TAG_PACKET_FILTER_CONFIG, 1646 WMI_TAG_PACKET_FILTER_ENABLE, 1647 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1648 WMI_TAG_MGMT_TX_SEND_CMD, 1649 WMI_TAG_MGMT_TX_COMPL_EVENT, 1650 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1651 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1652 WMI_TAG_LRO_INFO_CMD, 1653 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1654 WMI_TAG_SERVICE_READY_EXT_EVENT, 1655 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1656 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1657 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1658 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1659 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1660 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1661 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1662 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1663 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1664 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1665 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1666 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1667 WMI_TAG_SCPC_EVENT, 1668 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1669 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1670 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1671 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1672 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1673 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1674 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1675 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1676 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1677 WMI_TAG_PEER_DELETE_RESP_EVENT, 1678 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1679 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1680 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1681 WMI_TAG_VDEV_CONFIG_RATEMASK, 1682 WMI_TAG_PDEV_FIPS_CMD, 1683 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1684 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1685 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1686 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1687 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1688 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1689 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1690 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1691 WMI_TAG_FWTEST_SET_PARAM_CMD, 1692 WMI_TAG_PEER_ATF_REQUEST, 1693 WMI_TAG_VDEV_ATF_REQUEST, 1694 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1695 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1696 WMI_TAG_INST_RSSI_STATS_RESP, 1697 WMI_TAG_MED_UTIL_REPORT_EVENT, 1698 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1699 WMI_TAG_WDS_ADDR_EVENT, 1700 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1701 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1702 WMI_TAG_PDEV_TPC_EVENT, 1703 WMI_TAG_ANI_OFDM_EVENT, 1704 WMI_TAG_ANI_CCK_EVENT, 1705 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1706 WMI_TAG_PDEV_FIPS_EVENT, 1707 WMI_TAG_ATF_PEER_INFO, 1708 WMI_TAG_PDEV_GET_TPC_CMD, 1709 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1710 WMI_TAG_QBOOST_CFG_CMD, 1711 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1712 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1713 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1714 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1715 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1716 WMI_TAG_PEER_MCS_RATE_INFO, 1717 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1718 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1719 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1720 WMI_TAG_MU_REPORT_TOTAL_MU, 1721 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1722 WMI_TAG_ROAM_SET_MBO, 1723 WMI_TAG_MIB_STATS_ENABLE_CMD, 1724 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1725 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1726 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1727 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1728 WMI_TAG_NDI_GET_CAP_REQ, 1729 WMI_TAG_NDP_INITIATOR_REQ, 1730 WMI_TAG_NDP_RESPONDER_REQ, 1731 WMI_TAG_NDP_END_REQ, 1732 WMI_TAG_NDI_CAP_RSP_EVENT, 1733 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1734 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1735 WMI_TAG_NDP_END_RSP_EVENT, 1736 WMI_TAG_NDP_INDICATION_EVENT, 1737 WMI_TAG_NDP_CONFIRM_EVENT, 1738 WMI_TAG_NDP_END_INDICATION_EVENT, 1739 WMI_TAG_VDEV_SET_QUIET_CMD, 1740 WMI_TAG_PDEV_SET_PCL_CMD, 1741 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1742 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1743 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1744 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1745 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1746 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1747 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1748 WMI_TAG_COEX_CONFIG_CMD, 1749 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1750 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1751 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1752 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1753 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1754 WMI_TAG_MAC_PHY_CAPABILITIES, 1755 WMI_TAG_HW_MODE_CAPABILITIES, 1756 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1757 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1758 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1759 WMI_TAG_VDEV_WISA_CMD, 1760 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1761 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1762 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1763 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1764 WMI_TAG_NDP_END_RSP_PER_NDI, 1765 WMI_TAG_PEER_BWF_REQUEST, 1766 WMI_TAG_BWF_PEER_INFO, 1767 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1768 WMI_TAG_RMC_SET_LEADER_CMD, 1769 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1770 WMI_TAG_PER_CHAIN_RSSI_STATS, 1771 WMI_TAG_RSSI_STATS, 1772 WMI_TAG_P2P_LO_START_CMD, 1773 WMI_TAG_P2P_LO_STOP_CMD, 1774 WMI_TAG_P2P_LO_STOPPED_EVENT, 1775 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1776 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1777 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1778 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1779 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1780 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1781 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1782 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1783 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1784 WMI_TAG_TLV_BUF_LEN_PARAM, 1785 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1786 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1787 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1788 WMI_TAG_PEER_ANTDIV_INFO, 1789 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1790 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1791 WMI_TAG_MNT_FILTER_CMD, 1792 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1793 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1794 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1795 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1796 WMI_TAG_CHAN_CCA_STATS, 1797 WMI_TAG_PEER_SIGNAL_STATS, 1798 WMI_TAG_TX_STATS, 1799 WMI_TAG_PEER_AC_TX_STATS, 1800 WMI_TAG_RX_STATS, 1801 WMI_TAG_PEER_AC_RX_STATS, 1802 WMI_TAG_REPORT_STATS_EVENT, 1803 WMI_TAG_CHAN_CCA_STATS_THRESH, 1804 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1805 WMI_TAG_TX_STATS_THRESH, 1806 WMI_TAG_RX_STATS_THRESH, 1807 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1808 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1809 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1810 WMI_TAG_RX_AGGR_FAILURE_INFO, 1811 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1812 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1813 WMI_TAG_PDEV_BAND_TO_MAC, 1814 WMI_TAG_TBTT_OFFSET_INFO, 1815 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1816 WMI_TAG_SAR_LIMITS_CMD, 1817 WMI_TAG_SAR_LIMIT_CMD_ROW, 1818 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1819 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1820 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1821 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1822 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1823 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1824 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1825 WMI_TAG_VENDOR_OUI, 1826 WMI_TAG_REQUEST_RCPI_CMD, 1827 WMI_TAG_UPDATE_RCPI_EVENT, 1828 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1829 WMI_TAG_PEER_STATS_INFO, 1830 WMI_TAG_PEER_STATS_INFO_EVENT, 1831 WMI_TAG_PKGID_EVENT, 1832 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1833 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1834 WMI_TAG_REGULATORY_RULE_STRUCT, 1835 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1836 WMI_TAG_11D_SCAN_START_CMD, 1837 WMI_TAG_11D_SCAN_STOP_CMD, 1838 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1839 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1840 WMI_TAG_RADIO_CHAN_STATS, 1841 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1842 WMI_TAG_ROAM_PER_CONFIG, 1843 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1844 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1845 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1846 WMI_TAG_HW_DATA_FILTER_CMD, 1847 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1848 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1849 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1850 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1851 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1852 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1853 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1854 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1855 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1856 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1857 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1858 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1859 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1860 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1861 WMI_TAG_IFACE_OFFLOAD_STATS, 1862 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1863 WMI_TAG_RSSI_CTL_EXT, 1864 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1865 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1866 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1867 WMI_TAG_VDEV_TX_POWER_EVENT, 1868 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1869 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1870 WMI_TAG_TX_SEND_PARAMS, 1871 WMI_TAG_HE_RATE_SET, 1872 WMI_TAG_CONGESTION_STATS, 1873 WMI_TAG_SET_INIT_COUNTRY_CMD, 1874 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1875 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1876 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1877 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1878 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1879 WMI_TAG_THERM_THROT_STATS_EVENT, 1880 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1881 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1882 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1883 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1884 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1885 WMI_TAG_OEM_INDIRECT_DATA, 1886 WMI_TAG_OEM_DMA_BUF_RELEASE, 1887 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1888 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1889 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1890 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1891 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1892 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1893 WMI_TAG_UNIT_TEST_EVENT, 1894 WMI_TAG_ROAM_FILS_OFFLOAD, 1895 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1896 WMI_TAG_PMK_CACHE, 1897 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1898 WMI_TAG_ROAM_FILS_SYNCH, 1899 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1900 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1901 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1902 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1903 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1904 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1905 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1906 WMI_TAG_BTM_CONFIG, 1907 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1908 WMI_TAG_WLM_CONFIG_CMD, 1909 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1910 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1911 WMI_TAG_ROAM_CND_SCORING_PARAM, 1912 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1913 WMI_TAG_VENDOR_OUI_EXT, 1914 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1915 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1916 WMI_TAG_ENABLE_FILS_CMD, 1917 WMI_TAG_HOST_SWFDA_EVENT, 1918 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1919 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1920 WMI_TAG_STATS_PERIOD, 1921 WMI_TAG_NDL_SCHEDULE_UPDATE, 1922 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1923 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1924 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1925 WMI_TAG_SAR2_RESULT_EVENT, 1926 WMI_TAG_SAR_CAPABILITIES, 1927 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1928 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1929 WMI_TAG_DMA_RING_CAPABILITIES, 1930 WMI_TAG_DMA_RING_CFG_REQ, 1931 WMI_TAG_DMA_RING_CFG_RSP, 1932 WMI_TAG_DMA_BUF_RELEASE, 1933 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1934 WMI_TAG_SAR_GET_LIMITS_CMD, 1935 WMI_TAG_SAR_GET_LIMITS_EVENT, 1936 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1937 WMI_TAG_OFFLOAD_11K_REPORT, 1938 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1939 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1940 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1941 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1942 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1943 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1944 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1945 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1946 WMI_TAG_PDEV_GET_NFCAL_POWER, 1947 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1948 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1949 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1950 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1951 WMI_TAG_TWT_ENABLE_CMD, 1952 WMI_TAG_TWT_DISABLE_CMD, 1953 WMI_TAG_TWT_ADD_DIALOG_CMD, 1954 WMI_TAG_TWT_DEL_DIALOG_CMD, 1955 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1956 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1957 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1958 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1959 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1960 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1961 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1962 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1963 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1964 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1965 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1966 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1967 WMI_TAG_GET_TPC_POWER_CMD, 1968 WMI_TAG_GET_TPC_POWER_EVENT, 1969 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1970 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1971 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1972 WMI_TAG_MOTION_DET_START_STOP_CMD, 1973 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1974 WMI_TAG_MOTION_DET_EVENT, 1975 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1976 WMI_TAG_NDP_TRANSPORT_IP, 1977 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1978 WMI_TAG_ESP_ESTIMATE_EVENT, 1979 WMI_TAG_NAN_HOST_CONFIG, 1980 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1981 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1982 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1983 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1984 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1985 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1986 WMI_TAG_PEER_EXTD2_STATS, 1987 WMI_TAG_HPCS_PULSE_START_CMD, 1988 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1989 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1990 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1991 WMI_TAG_NAN_EVENT_INFO, 1992 WMI_TAG_NDP_CHANNEL_INFO, 1993 WMI_TAG_NDP_CMD, 1994 WMI_TAG_NDP_EVENT, 1995 /* TODO add all the missing cmds */ 1996 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1997 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1998 WMI_TAG_SERVICE_READY_EXT2_EVENT = 0x334, 1999 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 2000 WMI_TAG_MAC_PHY_CAPABILITIES_EXT = 0x36F, 2001 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 2002 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 2003 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 2004 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 2005 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 2006 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 2007 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 2008 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 2009 WMI_TAG_TPC_STATS_GET_CMD = 0x38B, 2010 WMI_TAG_TPC_STATS_EVENT_FIXED_PARAM, 2011 WMI_TAG_TPC_STATS_CONFIG_EVENT, 2012 WMI_TAG_TPC_STATS_REG_PWR_ALLOWED, 2013 WMI_TAG_TPC_STATS_RATES_ARRAY, 2014 WMI_TAG_TPC_STATS_CTL_PWR_TABLE_EVENT, 2015 WMI_TAG_VDEV_SET_TPC_POWER_CMD = 0x3B5, 2016 WMI_TAG_VDEV_CH_POWER_INFO, 2017 WMI_TAG_MLO_LINK_SET_ACTIVE_CMD = 0x3BE, 2018 WMI_TAG_EHT_RATE_SET = 0x3C4, 2019 WMI_TAG_DCS_INCUMBENT_SIGNAL_INTERFERENCE_TYPE = 0x3C5, 2020 WMI_TAG_MLO_TX_SEND_PARAMS, 2021 WMI_TAG_MLO_PARTNER_LINK_PARAMS, 2022 WMI_TAG_MLO_PARTNER_LINK_PARAMS_PEER_ASSOC, 2023 WMI_TAG_MLO_SETUP_CMD = 0x3C9, 2024 WMI_TAG_MLO_SETUP_COMPLETE_EVENT, 2025 WMI_TAG_MLO_READY_CMD, 2026 WMI_TAG_MLO_TEARDOWN_CMD, 2027 WMI_TAG_MLO_TEARDOWN_COMPLETE, 2028 WMI_TAG_MLO_PEER_ASSOC_PARAMS = 0x3D0, 2029 WMI_TAG_MLO_PEER_CREATE_PARAMS = 0x3D5, 2030 WMI_TAG_MLO_VDEV_START_PARAMS = 0x3D6, 2031 WMI_TAG_MLO_VDEV_CREATE_PARAMS = 0x3D7, 2032 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 2033 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD = 0x3D9, 2034 WMI_TAG_PDEV_SET_BIOS_INTERFACE_CMD = 0x3FB, 2035 WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO_FIXED_PARAM = 0x427, 2036 WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO, 2037 WMI_TAG_RSSI_DBM_CONVERSION_TEMP_OFFSET_INFO, 2038 WMI_TAG_HALPHY_CTRL_PATH_CMD_FIXED_PARAM = 0x442, 2039 WMI_TAG_HALPHY_CTRL_PATH_EVENT_FIXED_PARAM, 2040 WMI_TAG_MAX 2041 }; 2042 2043 enum wmi_tlv_service { 2044 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 2045 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 2046 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 2047 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 2048 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 2049 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 2050 WMI_TLV_SERVICE_AP_UAPSD = 6, 2051 WMI_TLV_SERVICE_AP_DFS = 7, 2052 WMI_TLV_SERVICE_11AC = 8, 2053 WMI_TLV_SERVICE_BLOCKACK = 9, 2054 WMI_TLV_SERVICE_PHYERR = 10, 2055 WMI_TLV_SERVICE_BCN_FILTER = 11, 2056 WMI_TLV_SERVICE_RTT = 12, 2057 WMI_TLV_SERVICE_WOW = 13, 2058 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 2059 WMI_TLV_SERVICE_IRAM_TIDS = 15, 2060 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 2061 WMI_TLV_SERVICE_NLO = 17, 2062 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 2063 WMI_TLV_SERVICE_SCAN_SCH = 19, 2064 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 2065 WMI_TLV_SERVICE_CHATTER = 21, 2066 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 2067 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 2068 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 2069 WMI_TLV_SERVICE_GPIO = 25, 2070 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 2071 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 2072 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 2073 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 2074 WMI_TLV_SERVICE_TX_ENCAP = 30, 2075 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 2076 WMI_TLV_SERVICE_EARLY_RX = 32, 2077 WMI_TLV_SERVICE_STA_SMPS = 33, 2078 WMI_TLV_SERVICE_FWTEST = 34, 2079 WMI_TLV_SERVICE_STA_WMMAC = 35, 2080 WMI_TLV_SERVICE_TDLS = 36, 2081 WMI_TLV_SERVICE_BURST = 37, 2082 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 2083 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 2084 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 2085 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 2086 WMI_TLV_SERVICE_WLAN_HB = 42, 2087 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 2088 WMI_TLV_SERVICE_BATCH_SCAN = 44, 2089 WMI_TLV_SERVICE_QPOWER = 45, 2090 WMI_TLV_SERVICE_PLMREQ = 46, 2091 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 2092 WMI_TLV_SERVICE_RMC = 48, 2093 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 2094 WMI_TLV_SERVICE_COEX_SAR = 50, 2095 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 2096 WMI_TLV_SERVICE_NAN = 52, 2097 WMI_TLV_SERVICE_L1SS_STAT = 53, 2098 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 2099 WMI_TLV_SERVICE_OBSS_SCAN = 55, 2100 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 2101 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 2102 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 2103 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 2104 WMI_TLV_SERVICE_LPASS = 60, 2105 WMI_TLV_SERVICE_EXTSCAN = 61, 2106 WMI_TLV_SERVICE_D0WOW = 62, 2107 WMI_TLV_SERVICE_HSOFFLOAD = 63, 2108 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 2109 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 2110 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 2111 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 2112 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 2113 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 2114 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 2115 WMI_TLV_SERVICE_OCB = 71, 2116 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 2117 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 2118 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 2119 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 2120 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 2121 WMI_TLV_SERVICE_EXT_MSG = 77, 2122 WMI_TLV_SERVICE_MAWC = 78, 2123 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 2124 WMI_TLV_SERVICE_EGAP = 80, 2125 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 2126 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 2127 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 2128 WMI_TLV_SERVICE_ATF = 84, 2129 WMI_TLV_SERVICE_COEX_GPIO = 85, 2130 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 2131 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 2132 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 2133 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 2134 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 2135 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 2136 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 2137 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 2138 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 2139 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 2140 WMI_TLV_SERVICE_NAN_DATA = 96, 2141 WMI_TLV_SERVICE_NAN_RTT = 97, 2142 WMI_TLV_SERVICE_11AX = 98, 2143 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 2144 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 2145 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 2146 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 2147 WMI_TLV_SERVICE_MESH_11S = 103, 2148 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 2149 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 2150 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 2151 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 2152 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 2153 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 2154 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 2155 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 2156 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 2157 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 2158 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2159 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2160 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2161 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2162 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2163 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2164 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2165 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2166 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2167 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2168 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2169 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2170 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2171 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2172 2173 WMI_MAX_SERVICE = 128, 2174 2175 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2176 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2177 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2178 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2179 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2180 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2181 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2182 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2183 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2184 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2185 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2186 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2187 WMI_TLV_SERVICE_THERM_THROT = 140, 2188 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2189 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2190 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2191 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2192 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2193 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2194 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2195 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2196 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2197 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2198 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2199 WMI_TLV_SERVICE_STA_TWT = 152, 2200 WMI_TLV_SERVICE_AP_TWT = 153, 2201 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2202 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2203 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2204 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2205 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2206 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2207 WMI_TLV_SERVICE_MOTION_DET = 160, 2208 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2209 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2210 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2211 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2212 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2213 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2214 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2215 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2216 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2217 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2218 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2219 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2220 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2221 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2222 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2223 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2224 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2225 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2226 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2227 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2228 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2229 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2230 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2231 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2232 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2233 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2234 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2235 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2236 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2237 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2238 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2239 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2240 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2241 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2242 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2243 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2244 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2245 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2246 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2247 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2248 WMI_TLV_SERVICE_PS_TDCC = 201, 2249 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2250 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2251 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2252 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2253 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2254 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2255 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2256 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2257 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2258 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2259 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2260 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2261 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2262 WMI_TLV_SERVICE_EXT2_MSG = 220, 2263 WMI_TLV_SERVICE_BEACON_PROTECTION_SUPPORT = 244, 2264 WMI_TLV_SERVICE_5_9GHZ_SUPPORT = 247, 2265 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2266 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2267 2268 WMI_MAX_EXT_SERVICE = 256, 2269 2270 WMI_TLV_SERVICE_EXT_TPC_REG_SUPPORT = 280, 2271 2272 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2273 2274 WMI_TLV_SERVICE_DCS_INCUMBENT_SIGNAL_INTERFERENCE_SUPPORT = 286, 2275 2276 WMI_TLV_SERVICE_11BE = 289, 2277 2278 WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, 2279 2280 WMI_TLV_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, 2281 WMI_TLV_SERVICE_THERM_THROT_POUT_REDUCTION = 410, 2282 WMI_TLV_SERVICE_WDS_NULL_FRAME_SUPPORT = 421, 2283 WMI_TLV_SERVICE_IS_TARGET_IPA = 425, 2284 WMI_TLV_SERVICE_THERM_THROT_TX_CHAIN_MASK = 426, 2285 WMI_TLV_SERVICE_THERM_THROT_5_LEVELS = 429, 2286 WMI_TLV_SERVICE_ETH_OFFLOAD = 461, 2287 2288 WMI_MAX_EXT2_SERVICE, 2289 }; 2290 2291 enum { 2292 WMI_SMPS_FORCED_MODE_NONE = 0, 2293 WMI_SMPS_FORCED_MODE_DISABLED, 2294 WMI_SMPS_FORCED_MODE_STATIC, 2295 WMI_SMPS_FORCED_MODE_DYNAMIC 2296 }; 2297 2298 enum wmi_tpc_chainmask { 2299 WMI_TPC_CHAINMASK_CONFIG_BAND_2G = 0, 2300 WMI_TPC_CHAINMASK_CONFIG_BAND_5G = 1, 2301 WMI_NUM_SUPPORTED_BAND_MAX = 2, 2302 }; 2303 2304 enum wmi_peer_param { 2305 WMI_PEER_MIMO_PS_STATE = 1, 2306 WMI_PEER_AMPDU = 2, 2307 WMI_PEER_AUTHORIZE = 3, 2308 WMI_PEER_CHWIDTH = 4, 2309 WMI_PEER_NSS = 5, 2310 WMI_PEER_USE_4ADDR = 6, 2311 WMI_PEER_MEMBERSHIP = 7, 2312 WMI_PEER_USERPOS = 8, 2313 WMI_PEER_CRIT_PROTO_HINT_ENABLED = 9, 2314 WMI_PEER_TX_FAIL_CNT_THR = 10, 2315 WMI_PEER_SET_HW_RETRY_CTS2S = 11, 2316 WMI_PEER_IBSS_ATIM_WINDOW_LENGTH = 12, 2317 WMI_PEER_PHYMODE = 13, 2318 WMI_PEER_USE_FIXED_PWR = 14, 2319 WMI_PEER_PARAM_FIXED_RATE = 15, 2320 WMI_PEER_SET_MU_WHITELIST = 16, 2321 WMI_PEER_SET_MAX_TX_RATE = 17, 2322 WMI_PEER_SET_MIN_TX_RATE = 18, 2323 WMI_PEER_SET_DEFAULT_ROUTING = 19, 2324 WMI_PEER_CHWIDTH_PUNCTURE_20MHZ_BITMAP = 39, 2325 }; 2326 2327 #define WMI_PEER_PUNCTURE_BITMAP GENMASK(23, 8) 2328 2329 enum wmi_slot_time { 2330 WMI_VDEV_SLOT_TIME_LONG = 1, 2331 WMI_VDEV_SLOT_TIME_SHORT = 2, 2332 }; 2333 2334 enum wmi_dtim_policy { 2335 WMI_DTIM_POLICY_IGNORE = 1, 2336 WMI_DTIM_POLICY_NORMAL = 2, 2337 WMI_DTIM_POLICY_STICK = 3, 2338 WMI_DTIM_POLICY_AUTO = 4, 2339 }; 2340 2341 enum wmi_preamble { 2342 WMI_VDEV_PREAMBLE_LONG = 1, 2343 WMI_VDEV_PREAMBLE_SHORT = 2, 2344 }; 2345 2346 /* 2347 * This will be used to set for WMI_VDEV_PARAM_AP_ENABLE_NAWDS 2348 * whenever 4addr station connects in wds offload case. 2349 * This is for enabling multicast to unicast conversion support in 2350 * firmware 2351 */ 2352 #define WDS_EXT_ENABLE 1 2353 2354 enum wmi_peer_4addr_allow_frame { 2355 WMI_PEER_4ADDR_ALLOW_DATA_FRAME = 1, 2356 WMI_PEER_4ADDR_ALLOW_EAPOL_DATA_FRAME = 2, 2357 }; 2358 2359 enum wmi_peer_smps_state { 2360 WMI_PEER_SMPS_PS_NONE = 0, 2361 WMI_PEER_SMPS_STATIC = 1, 2362 WMI_PEER_SMPS_DYNAMIC = 2 2363 }; 2364 2365 enum wmi_peer_chwidth { 2366 WMI_PEER_CHWIDTH_20MHZ = 0, 2367 WMI_PEER_CHWIDTH_40MHZ = 1, 2368 WMI_PEER_CHWIDTH_80MHZ = 2, 2369 WMI_PEER_CHWIDTH_160MHZ = 3, 2370 WMI_PEER_CHWIDTH_320MHZ = 4, 2371 }; 2372 2373 enum wmi_beacon_gen_mode { 2374 WMI_BEACON_STAGGERED_MODE = 0, 2375 WMI_BEACON_BURST_MODE = 1 2376 }; 2377 2378 enum wmi_direct_buffer_module { 2379 WMI_DIRECT_BUF_SPECTRAL = 0, 2380 WMI_DIRECT_BUF_CFR = 1, 2381 2382 /* keep it last */ 2383 WMI_DIRECT_BUF_MAX 2384 }; 2385 2386 /** 2387 * enum wmi_nss_ratio - NSS ratio received from FW during service ready ext event 2388 * @WMI_NSS_RATIO_1BY2_NSS: Max nss of 160MHz is equals to half of the max nss of 80MHz 2389 * @WMI_NSS_RATIO_3BY4_NSS: Max nss of 160MHz is equals to 3/4 of the max nss of 80MHz 2390 * @WMI_NSS_RATIO_1_NSS: Max nss of 160MHz is equals to the max nss of 80MHz 2391 * @WMI_NSS_RATIO_2_NSS: Max nss of 160MHz is equals to two times the max nss of 80MHz 2392 */ 2393 2394 enum wmi_nss_ratio { 2395 WMI_NSS_RATIO_1BY2_NSS, 2396 WMI_NSS_RATIO_3BY4_NSS, 2397 WMI_NSS_RATIO_1_NSS, 2398 WMI_NSS_RATIO_2_NSS 2399 }; 2400 2401 struct ath12k_wmi_pdev_band_arg { 2402 u32 pdev_id; 2403 u32 start_freq; 2404 u32 end_freq; 2405 }; 2406 2407 struct ath12k_wmi_ppe_threshold_arg { 2408 u32 numss_m1; 2409 u32 ru_bit_mask; 2410 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2411 }; 2412 2413 #define PSOC_HOST_MAX_PHY_SIZE (3) 2414 #define ATH12K_11B_SUPPORT BIT(0) 2415 #define ATH12K_11G_SUPPORT BIT(1) 2416 #define ATH12K_11A_SUPPORT BIT(2) 2417 #define ATH12K_11N_SUPPORT BIT(3) 2418 #define ATH12K_11AC_SUPPORT BIT(4) 2419 #define ATH12K_11AX_SUPPORT BIT(5) 2420 2421 struct ath12k_wmi_hal_reg_capabilities_ext_arg { 2422 u32 phy_id; 2423 u32 eeprom_reg_domain; 2424 u32 eeprom_reg_domain_ext; 2425 u32 regcap1; 2426 u32 regcap2; 2427 u32 wireless_modes; 2428 u32 low_2ghz_chan; 2429 u32 high_2ghz_chan; 2430 u32 low_5ghz_chan; 2431 u32 high_5ghz_chan; 2432 }; 2433 2434 #define WMI_HOST_MAX_PDEV 3 2435 2436 struct ath12k_wmi_host_mem_chunk_params { 2437 __le32 tlv_header; 2438 __le32 req_id; 2439 __le32 ptr; 2440 __le32 size; 2441 } __packed; 2442 2443 struct ath12k_wmi_host_mem_chunk_arg { 2444 void *vaddr; 2445 dma_addr_t paddr; 2446 u32 len; 2447 u32 req_id; 2448 }; 2449 2450 enum ath12k_peer_metadata_version { 2451 ATH12K_PEER_METADATA_V0, 2452 ATH12K_PEER_METADATA_V1, 2453 ATH12K_PEER_METADATA_V1A, 2454 ATH12K_PEER_METADATA_V1B 2455 }; 2456 2457 struct ath12k_wmi_resource_config_arg { 2458 u32 num_vdevs; 2459 u32 num_peers; 2460 u32 num_active_peers; 2461 u32 num_offload_peers; 2462 u32 num_offload_reorder_buffs; 2463 u32 num_peer_keys; 2464 u32 num_tids; 2465 u32 ast_skid_limit; 2466 u32 tx_chain_mask; 2467 u32 rx_chain_mask; 2468 u32 rx_timeout_pri[4]; 2469 u32 rx_decap_mode; 2470 u32 scan_max_pending_req; 2471 u32 bmiss_offload_max_vdev; 2472 u32 roam_offload_max_vdev; 2473 u32 roam_offload_max_ap_profiles; 2474 u32 num_mcast_groups; 2475 u32 num_mcast_table_elems; 2476 u32 mcast2ucast_mode; 2477 u32 tx_dbg_log_size; 2478 u32 num_wds_entries; 2479 u32 dma_burst_size; 2480 u32 mac_aggr_delim; 2481 u32 rx_skip_defrag_timeout_dup_detection_check; 2482 u32 vow_config; 2483 u32 gtk_offload_max_vdev; 2484 u32 num_msdu_desc; 2485 u32 max_frag_entries; 2486 u32 max_peer_ext_stats; 2487 u32 smart_ant_cap; 2488 u32 bk_minfree; 2489 u32 be_minfree; 2490 u32 vi_minfree; 2491 u32 vo_minfree; 2492 u32 rx_batchmode; 2493 u32 tt_support; 2494 u32 atf_config; 2495 u32 iphdr_pad_config; 2496 u32 qwrap_config:16, 2497 alloc_frag_desc_for_data_pkt:16; 2498 u32 num_tdls_vdevs; 2499 u32 num_tdls_conn_table_entries; 2500 u32 beacon_tx_offload_max_vdev; 2501 u32 num_multicast_filter_entries; 2502 u32 num_wow_filters; 2503 u32 num_keep_alive_pattern; 2504 u32 keep_alive_pattern_size; 2505 u32 max_tdls_concurrent_sleep_sta; 2506 u32 max_tdls_concurrent_buffer_sta; 2507 u32 wmi_send_separate; 2508 u32 num_ocb_vdevs; 2509 u32 num_ocb_channels; 2510 u32 num_ocb_schedules; 2511 u32 num_ns_ext_tuples_cfg; 2512 u32 bpf_instruction_size; 2513 u32 max_bssid_rx_filters; 2514 u32 use_pdev_id; 2515 u32 peer_map_unmap_version; 2516 u32 sched_params; 2517 u32 twt_ap_pdev_count; 2518 u32 twt_ap_sta_count; 2519 enum ath12k_peer_metadata_version peer_metadata_ver; 2520 u32 ema_max_vap_cnt; 2521 u32 ema_max_profile_period; 2522 bool is_reg_cc_ext_event_supported; 2523 bool is_wds_null_frame_supported; 2524 }; 2525 2526 struct ath12k_wmi_init_cmd_arg { 2527 struct ath12k_wmi_resource_config_arg res_cfg; 2528 u8 num_mem_chunks; 2529 struct ath12k_wmi_host_mem_chunk_arg *mem_chunks; 2530 u32 hw_mode_id; 2531 u32 num_band_to_mac; 2532 struct ath12k_wmi_pdev_band_arg band_to_mac[WMI_HOST_MAX_PDEV]; 2533 }; 2534 2535 struct ath12k_wmi_pdev_band_to_mac_params { 2536 __le32 tlv_header; 2537 __le32 pdev_id; 2538 __le32 start_freq; 2539 __le32 end_freq; 2540 } __packed; 2541 2542 /* This is both individual command WMI_PDEV_SET_HW_MODE_CMDID and also part 2543 * of WMI_TAG_INIT_CMD. 2544 */ 2545 struct ath12k_wmi_pdev_set_hw_mode_cmd { 2546 __le32 tlv_header; 2547 __le32 pdev_id; 2548 __le32 hw_mode_index; 2549 __le32 num_band_to_mac; 2550 } __packed; 2551 2552 struct ath12k_wmi_ppe_threshold_params { 2553 __le32 numss_m1; /** NSS - 1*/ 2554 __le32 ru_info; 2555 __le32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2556 } __packed; 2557 2558 #define HW_BD_INFO_SIZE 5 2559 2560 struct ath12k_wmi_abi_version_params { 2561 __le32 abi_version_0; 2562 __le32 abi_version_1; 2563 __le32 abi_version_ns_0; 2564 __le32 abi_version_ns_1; 2565 __le32 abi_version_ns_2; 2566 __le32 abi_version_ns_3; 2567 } __packed; 2568 2569 struct wmi_init_cmd { 2570 __le32 tlv_header; 2571 struct ath12k_wmi_abi_version_params host_abi_vers; 2572 __le32 num_host_mem_chunks; 2573 } __packed; 2574 2575 #define WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT 4 2576 #define WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT 12 2577 #define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_VERSION GENMASK(5, 4) 2578 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2579 #define WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2580 #define WMI_RSRC_CFG_FLAGS2_FW_AST_INDICATION_DISABLE BIT(18) 2581 #define WMI_RSRC_CFG_FLAGS2_WDS_NULL_FRAME_SUPPORT BIT(22) 2582 #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) 2583 2584 struct ath12k_wmi_resource_config_params { 2585 __le32 tlv_header; 2586 __le32 num_vdevs; 2587 __le32 num_peers; 2588 __le32 num_offload_peers; 2589 __le32 num_offload_reorder_buffs; 2590 __le32 num_peer_keys; 2591 __le32 num_tids; 2592 __le32 ast_skid_limit; 2593 __le32 tx_chain_mask; 2594 __le32 rx_chain_mask; 2595 __le32 rx_timeout_pri[4]; 2596 __le32 rx_decap_mode; 2597 __le32 scan_max_pending_req; 2598 __le32 bmiss_offload_max_vdev; 2599 __le32 roam_offload_max_vdev; 2600 __le32 roam_offload_max_ap_profiles; 2601 __le32 num_mcast_groups; 2602 __le32 num_mcast_table_elems; 2603 __le32 mcast2ucast_mode; 2604 __le32 tx_dbg_log_size; 2605 __le32 num_wds_entries; 2606 __le32 dma_burst_size; 2607 __le32 mac_aggr_delim; 2608 __le32 rx_skip_defrag_timeout_dup_detection_check; 2609 __le32 vow_config; 2610 __le32 gtk_offload_max_vdev; 2611 __le32 num_msdu_desc; 2612 __le32 max_frag_entries; 2613 __le32 num_tdls_vdevs; 2614 __le32 num_tdls_conn_table_entries; 2615 __le32 beacon_tx_offload_max_vdev; 2616 __le32 num_multicast_filter_entries; 2617 __le32 num_wow_filters; 2618 __le32 num_keep_alive_pattern; 2619 __le32 keep_alive_pattern_size; 2620 __le32 max_tdls_concurrent_sleep_sta; 2621 __le32 max_tdls_concurrent_buffer_sta; 2622 __le32 wmi_send_separate; 2623 __le32 num_ocb_vdevs; 2624 __le32 num_ocb_channels; 2625 __le32 num_ocb_schedules; 2626 __le32 flag1; 2627 __le32 smart_ant_cap; 2628 __le32 bk_minfree; 2629 __le32 be_minfree; 2630 __le32 vi_minfree; 2631 __le32 vo_minfree; 2632 __le32 alloc_frag_desc_for_data_pkt; 2633 __le32 num_ns_ext_tuples_cfg; 2634 __le32 bpf_instruction_size; 2635 __le32 max_bssid_rx_filters; 2636 __le32 use_pdev_id; 2637 __le32 max_num_dbs_scan_duty_cycle; 2638 __le32 max_num_group_keys; 2639 __le32 peer_map_unmap_version; 2640 __le32 sched_params; 2641 __le32 twt_ap_pdev_count; 2642 __le32 twt_ap_sta_count; 2643 __le32 max_nlo_ssids; 2644 __le32 num_pkt_filters; 2645 __le32 num_max_sta_vdevs; 2646 __le32 max_bssid_indicator; 2647 __le32 ul_resp_config; 2648 __le32 msdu_flow_override_config0; 2649 __le32 msdu_flow_override_config1; 2650 __le32 flags2; 2651 __le32 host_service_flags; 2652 __le32 max_rnr_neighbours; 2653 __le32 ema_max_vap_cnt; 2654 __le32 ema_max_profile_period; 2655 } __packed; 2656 2657 struct wmi_service_ready_event { 2658 __le32 fw_build_vers; 2659 struct ath12k_wmi_abi_version_params fw_abi_vers; 2660 __le32 phy_capability; 2661 __le32 max_frag_entry; 2662 __le32 num_rf_chains; 2663 __le32 ht_cap_info; 2664 __le32 vht_cap_info; 2665 __le32 vht_supp_mcs; 2666 __le32 hw_min_tx_power; 2667 __le32 hw_max_tx_power; 2668 __le32 sys_cap_info; 2669 __le32 min_pkt_size_enable; 2670 __le32 max_bcn_ie_size; 2671 __le32 num_mem_reqs; 2672 __le32 max_num_scan_channels; 2673 __le32 hw_bd_id; 2674 __le32 hw_bd_info[HW_BD_INFO_SIZE]; 2675 __le32 max_supported_macs; 2676 __le32 wmi_fw_sub_feat_caps; 2677 __le32 num_dbs_hw_modes; 2678 /* txrx_chainmask 2679 * [7:0] - 2G band tx chain mask 2680 * [15:8] - 2G band rx chain mask 2681 * [23:16] - 5G band tx chain mask 2682 * [31:24] - 5G band rx chain mask 2683 */ 2684 __le32 txrx_chainmask; 2685 __le32 default_dbs_hw_mode_index; 2686 __le32 num_msdu_desc; 2687 } __packed; 2688 2689 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32)) 2690 2691 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */ 2692 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32)) 2693 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2694 #define WMI_SERVICE_BITS_IN_SIZE32 4 2695 2696 struct wmi_service_ready_ext_event { 2697 __le32 default_conc_scan_config_bits; 2698 __le32 default_fw_config_bits; 2699 struct ath12k_wmi_ppe_threshold_params ppet; 2700 __le32 he_cap_info; 2701 __le32 mpdu_density; 2702 __le32 max_bssid_rx_filters; 2703 __le32 fw_build_vers_ext; 2704 __le32 max_nlo_ssids; 2705 __le32 max_bssid_indicator; 2706 __le32 he_cap_info_ext; 2707 } __packed; 2708 2709 struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params { 2710 __le32 num_hw_modes; 2711 __le32 num_chainmask_tables; 2712 } __packed; 2713 2714 #define WMI_HW_MODE_CAP_CFG_TYPE GENMASK(27, 0) 2715 2716 struct ath12k_wmi_hw_mode_cap_params { 2717 __le32 tlv_header; 2718 __le32 hw_mode_id; 2719 __le32 phy_id_map; 2720 __le32 hw_mode_config_type; 2721 } __packed; 2722 2723 #define WMI_MAX_HECAP_PHY_SIZE (3) 2724 #define WMI_NSS_RATIO_EN_DIS_BITPOS BIT(0) 2725 #define WMI_NSS_RATIO_EN_DIS_GET(_val) \ 2726 le32_get_bits(_val, WMI_NSS_RATIO_EN_DIS_BITPOS) 2727 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2728 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2729 le32_get_bits(_val, WMI_NSS_RATIO_INFO_BITPOS) 2730 2731 /* pdev_id is present in lower 16 bits of pdev_and_hw_link_ids in 2732 * ath12k_wmi_mac_phy_caps_params & ath12k_wmi_caps_ext_params. 2733 * 2734 * hw_link_id is present in higher 16 bits of pdev_and_hw_link_ids. 2735 */ 2736 #define WMI_CAPS_PARAMS_PDEV_ID GENMASK(15, 0) 2737 #define WMI_CAPS_PARAMS_HW_LINK_ID GENMASK(31, 16) 2738 2739 struct ath12k_wmi_mac_phy_caps_params { 2740 __le32 hw_mode_id; 2741 __le32 pdev_and_hw_link_ids; 2742 __le32 phy_id; 2743 __le32 supported_flags; 2744 __le32 supported_bands; 2745 __le32 ampdu_density; 2746 __le32 max_bw_supported_2g; 2747 __le32 ht_cap_info_2g; 2748 __le32 vht_cap_info_2g; 2749 __le32 vht_supp_mcs_2g; 2750 __le32 he_cap_info_2g; 2751 __le32 he_supp_mcs_2g; 2752 __le32 tx_chain_mask_2g; 2753 __le32 rx_chain_mask_2g; 2754 __le32 max_bw_supported_5g; 2755 __le32 ht_cap_info_5g; 2756 __le32 vht_cap_info_5g; 2757 __le32 vht_supp_mcs_5g; 2758 __le32 he_cap_info_5g; 2759 __le32 he_supp_mcs_5g; 2760 __le32 tx_chain_mask_5g; 2761 __le32 rx_chain_mask_5g; 2762 __le32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2763 __le32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2764 struct ath12k_wmi_ppe_threshold_params he_ppet2g; 2765 struct ath12k_wmi_ppe_threshold_params he_ppet5g; 2766 __le32 chainmask_table_id; 2767 __le32 lmac_id; 2768 __le32 he_cap_info_2g_ext; 2769 __le32 he_cap_info_5g_ext; 2770 __le32 he_cap_info_internal; 2771 __le32 wireless_modes; 2772 __le32 low_2ghz_chan_freq; 2773 __le32 high_2ghz_chan_freq; 2774 __le32 low_5ghz_chan_freq; 2775 __le32 high_5ghz_chan_freq; 2776 __le32 nss_ratio; 2777 } __packed; 2778 2779 struct ath12k_wmi_hal_reg_caps_ext_params { 2780 __le32 tlv_header; 2781 __le32 phy_id; 2782 __le32 eeprom_reg_domain; 2783 __le32 eeprom_reg_domain_ext; 2784 __le32 regcap1; 2785 __le32 regcap2; 2786 __le32 wireless_modes; 2787 __le32 low_2ghz_chan; 2788 __le32 high_2ghz_chan; 2789 __le32 low_5ghz_chan; 2790 __le32 high_5ghz_chan; 2791 } __packed; 2792 2793 struct ath12k_wmi_soc_hal_reg_caps_params { 2794 __le32 num_phy; 2795 } __packed; 2796 2797 enum wmi_channel_width { 2798 WMI_CHAN_WIDTH_20 = 0, 2799 WMI_CHAN_WIDTH_40 = 1, 2800 WMI_CHAN_WIDTH_80 = 2, 2801 WMI_CHAN_WIDTH_160 = 3, 2802 WMI_CHAN_WIDTH_80P80 = 4, 2803 WMI_CHAN_WIDTH_5 = 5, 2804 WMI_CHAN_WIDTH_10 = 6, 2805 WMI_CHAN_WIDTH_165 = 7, 2806 WMI_CHAN_WIDTH_160P160 = 8, 2807 WMI_CHAN_WIDTH_320 = 9, 2808 }; 2809 2810 #define WMI_MAX_EHTCAP_MAC_SIZE 2 2811 #define WMI_MAX_EHTCAP_PHY_SIZE 3 2812 #define WMI_MAX_EHTCAP_RATE_SET 3 2813 2814 /* Used for EHT MCS-NSS array. Data at each array index follows the format given 2815 * in IEEE P802.11be/D2.0, May 20229.4.2.313.4. 2816 * 2817 * Index interpretation: 2818 * 0 - 20 MHz only sta, all 4 bytes valid 2819 * 1 - index for bandwidths <= 80 MHz except 20 MHz-only, first 3 bytes valid 2820 * 2 - index for 160 MHz, first 3 bytes valid 2821 * 3 - index for 320 MHz, first 3 bytes valid 2822 */ 2823 #define WMI_MAX_EHT_SUPP_MCS_2GHZ_SIZE 2 2824 #define WMI_MAX_EHT_SUPP_MCS_5GHZ_SIZE 4 2825 2826 #define WMI_EHTCAP_TXRX_MCS_NSS_IDX_80 0 2827 #define WMI_EHTCAP_TXRX_MCS_NSS_IDX_160 1 2828 #define WMI_EHTCAP_TXRX_MCS_NSS_IDX_320 2 2829 2830 #define WMI_EHT_MCS_NSS_0_7 GENMASK(3, 0) 2831 #define WMI_EHT_MCS_NSS_8_9 GENMASK(7, 4) 2832 #define WMI_EHT_MCS_NSS_10_11 GENMASK(11, 8) 2833 #define WMI_EHT_MCS_NSS_12_13 GENMASK(15, 12) 2834 2835 #define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION GENMASK(1, 0) 2836 2837 struct wmi_service_ready_ext2_event { 2838 __le32 reg_db_version; 2839 __le32 hw_min_max_tx_power_2ghz; 2840 __le32 hw_min_max_tx_power_5ghz; 2841 __le32 chwidth_num_peer_caps; 2842 __le32 preamble_puncture_bw; 2843 __le32 max_user_per_ppdu_ofdma; 2844 __le32 max_user_per_ppdu_mumimo; 2845 __le32 target_cap_flags; 2846 __le32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 2847 __le32 max_num_linkview_peers; 2848 __le32 max_num_msduq_supported_per_tid; 2849 __le32 default_num_msduq_supported_per_tid; 2850 } __packed; 2851 2852 struct ath12k_wmi_dbs_or_sbs_cap_params { 2853 __le32 hw_mode_id; 2854 __le32 sbs_lower_band_end_freq; 2855 } __packed; 2856 2857 struct ath12k_wmi_caps_ext_params { 2858 __le32 hw_mode_id; 2859 __le32 pdev_and_hw_link_ids; 2860 __le32 phy_id; 2861 __le32 wireless_modes_ext; 2862 __le32 eht_cap_mac_info_2ghz[WMI_MAX_EHTCAP_MAC_SIZE]; 2863 __le32 eht_cap_mac_info_5ghz[WMI_MAX_EHTCAP_MAC_SIZE]; 2864 __le32 rsvd0[2]; 2865 __le32 eht_cap_phy_info_2ghz[WMI_MAX_EHTCAP_PHY_SIZE]; 2866 __le32 eht_cap_phy_info_5ghz[WMI_MAX_EHTCAP_PHY_SIZE]; 2867 struct ath12k_wmi_ppe_threshold_params eht_ppet_2ghz; 2868 struct ath12k_wmi_ppe_threshold_params eht_ppet_5ghz; 2869 __le32 eht_cap_info_internal; 2870 __le32 eht_supp_mcs_ext_2ghz[WMI_MAX_EHT_SUPP_MCS_2GHZ_SIZE]; 2871 __le32 eht_supp_mcs_ext_5ghz[WMI_MAX_EHT_SUPP_MCS_5GHZ_SIZE]; 2872 __le32 eml_capability; 2873 __le32 mld_capability; 2874 } __packed; 2875 2876 /* 2 word representation of MAC addr */ 2877 struct ath12k_wmi_mac_addr_params { 2878 u8 addr[ETH_ALEN]; 2879 u8 padding[2]; 2880 } __packed; 2881 2882 struct ath12k_wmi_dma_ring_caps_params { 2883 __le32 tlv_header; 2884 __le32 pdev_id; 2885 __le32 module_id; 2886 __le32 min_elem; 2887 __le32 min_buf_sz; 2888 __le32 min_buf_align; 2889 } __packed; 2890 2891 struct ath12k_wmi_ready_event_min_params { 2892 struct ath12k_wmi_abi_version_params fw_abi_vers; 2893 struct ath12k_wmi_mac_addr_params mac_addr; 2894 __le32 status; 2895 __le32 num_dscp_table; 2896 __le32 num_extra_mac_addr; 2897 __le32 num_total_peers; 2898 __le32 num_extra_peers; 2899 } __packed; 2900 2901 struct wmi_ready_event { 2902 struct ath12k_wmi_ready_event_min_params ready_event_min; 2903 __le32 max_ast_index; 2904 __le32 pktlog_defs_checksum; 2905 } __packed; 2906 2907 struct wmi_service_available_event { 2908 __le32 wmi_service_segment_offset; 2909 __le32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2910 } __packed; 2911 2912 struct ath12k_wmi_vdev_create_arg { 2913 u8 if_id; 2914 u32 type; 2915 u32 subtype; 2916 struct { 2917 u8 tx; 2918 u8 rx; 2919 } chains[NUM_NL80211_BANDS]; 2920 u32 pdev_id; 2921 u8 if_stats_id; 2922 u32 mbssid_flags; 2923 u32 mbssid_tx_vdev_id; 2924 u8 mld_addr[ETH_ALEN]; 2925 }; 2926 2927 #define ATH12K_MAX_VDEV_STATS_ID 0x30 2928 #define ATH12K_INVAL_VDEV_STATS_ID 0xFF 2929 2930 struct wmi_vdev_create_cmd { 2931 __le32 tlv_header; 2932 __le32 vdev_id; 2933 __le32 vdev_type; 2934 __le32 vdev_subtype; 2935 struct ath12k_wmi_mac_addr_params vdev_macaddr; 2936 __le32 num_cfg_txrx_streams; 2937 __le32 pdev_id; 2938 __le32 mbssid_flags; 2939 __le32 mbssid_tx_vdev_id; 2940 __le32 vdev_stats_id_valid; 2941 __le32 vdev_stats_id; 2942 } __packed; 2943 2944 struct ath12k_wmi_vdev_txrx_streams_params { 2945 __le32 tlv_header; 2946 __le32 band; 2947 __le32 supported_tx_streams; 2948 __le32 supported_rx_streams; 2949 } __packed; 2950 2951 struct wmi_vdev_create_mlo_params { 2952 __le32 tlv_header; 2953 struct ath12k_wmi_mac_addr_params mld_macaddr; 2954 } __packed; 2955 2956 #define ATH12K_WMI_FLAG_MLO_ENABLED BIT(0) 2957 #define ATH12K_WMI_FLAG_MLO_ASSOC_LINK BIT(1) 2958 #define ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC BIT(2) 2959 #define ATH12K_WMI_FLAG_MLO_LOGICAL_LINK_IDX_VALID BIT(3) 2960 #define ATH12K_WMI_FLAG_MLO_PEER_ID_VALID BIT(4) 2961 #define ATH12K_WMI_FLAG_MLO_MCAST_VDEV BIT(5) 2962 #define ATH12K_WMI_FLAG_MLO_EMLSR_SUPPORT BIT(6) 2963 #define ATH12K_WMI_FLAG_MLO_FORCED_INACTIVE BIT(7) 2964 #define ATH12K_WMI_FLAG_MLO_LINK_ADD BIT(8) 2965 #define ATH12K_WMI_FLAG_MLO_START_AS_ACTIVE BIT(17) 2966 #define ATH12K_WMI_FLAG_MLO_IEEE_LINK_IDX_VALID BIT(18) 2967 #define ATH12K_WMI_FLAG_MLO_IEEE_LINK_IDX_VALID_PARTNER BIT(19) 2968 2969 struct wmi_vdev_start_mlo_params { 2970 __le32 tlv_header; 2971 __le32 flags; 2972 __le32 ieee_link_id; 2973 } __packed; 2974 2975 struct wmi_partner_link_info { 2976 __le32 tlv_header; 2977 __le32 vdev_id; 2978 __le32 hw_link_id; 2979 struct ath12k_wmi_mac_addr_params vdev_addr; 2980 __le32 flags; 2981 __le32 ieee_link_id; 2982 } __packed; 2983 2984 struct wmi_vdev_delete_cmd { 2985 __le32 tlv_header; 2986 __le32 vdev_id; 2987 } __packed; 2988 2989 struct ath12k_wmi_vdev_up_params { 2990 u32 vdev_id; 2991 u32 aid; 2992 const u8 *bssid; 2993 const u8 *tx_bssid; 2994 u32 nontx_profile_idx; 2995 u32 nontx_profile_cnt; 2996 }; 2997 2998 struct wmi_vdev_up_cmd { 2999 __le32 tlv_header; 3000 __le32 vdev_id; 3001 __le32 vdev_assoc_id; 3002 struct ath12k_wmi_mac_addr_params vdev_bssid; 3003 struct ath12k_wmi_mac_addr_params tx_vdev_bssid; 3004 __le32 nontx_profile_idx; 3005 __le32 nontx_profile_cnt; 3006 } __packed; 3007 3008 struct wmi_vdev_stop_cmd { 3009 __le32 tlv_header; 3010 __le32 vdev_id; 3011 } __packed; 3012 3013 struct wmi_vdev_down_cmd { 3014 __le32 tlv_header; 3015 __le32 vdev_id; 3016 } __packed; 3017 3018 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 3019 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 3020 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 3021 3022 #define ATH12K_WMI_SSID_LEN 32 3023 3024 struct ath12k_wmi_ssid_params { 3025 __le32 ssid_len; 3026 u8 ssid[ATH12K_WMI_SSID_LEN]; 3027 } __packed; 3028 3029 #define ATH12K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ) 3030 3031 enum wmi_vdev_mbssid_flags { 3032 WMI_VDEV_MBSSID_FLAGS_NON_MBSSID_AP = BIT(0), 3033 WMI_VDEV_MBSSID_FLAGS_TRANSMIT_AP = BIT(1), 3034 WMI_VDEV_MBSSID_FLAGS_NON_TRANSMIT_AP = BIT(2), 3035 WMI_VDEV_MBSSID_FLAGS_EMA_MODE = BIT(3), 3036 WMI_VDEV_MBSSID_FLAGS_SCAN_MODE_VAP = BIT(4), 3037 }; 3038 3039 struct wmi_vdev_start_request_cmd { 3040 __le32 tlv_header; 3041 __le32 vdev_id; 3042 __le32 requestor_id; 3043 __le32 beacon_interval; 3044 __le32 dtim_period; 3045 __le32 flags; 3046 struct ath12k_wmi_ssid_params ssid; 3047 __le32 bcn_tx_rate; 3048 __le32 bcn_txpower; 3049 __le32 num_noa_descriptors; 3050 __le32 disable_hw_ack; 3051 __le32 preferred_tx_streams; 3052 __le32 preferred_rx_streams; 3053 __le32 he_ops; 3054 __le32 cac_duration_ms; 3055 __le32 regdomain; 3056 __le32 min_data_rate; 3057 __le32 mbssid_flags; /* uses enum wmi_vdev_mbssid_flags */ 3058 __le32 mbssid_tx_vdev_id; 3059 __le32 eht_ops; 3060 __le32 punct_bitmap; 3061 } __packed; 3062 3063 #define MGMT_TX_DL_FRM_LEN 64 3064 3065 struct ath12k_wmi_channel_arg { 3066 u8 chan_id; 3067 u8 pwr; 3068 u32 mhz; 3069 u32 half_rate:1, 3070 quarter_rate:1, 3071 dfs_set:1, 3072 dfs_set_cfreq2:1, 3073 is_chan_passive:1, 3074 allow_ht:1, 3075 allow_vht:1, 3076 allow_he:1, 3077 set_agile:1, 3078 psc_channel:1; 3079 u32 phy_mode; 3080 u32 cfreq1; 3081 u32 cfreq2; 3082 char maxpower; 3083 char minpower; 3084 char maxregpower; 3085 u8 antennamax; 3086 u8 reg_class_id; 3087 }; 3088 3089 enum wmi_phy_mode { 3090 MODE_11A = 0, 3091 MODE_11G = 1, /* 11b/g Mode */ 3092 MODE_11B = 2, /* 11b Mode */ 3093 MODE_11GONLY = 3, /* 11g only Mode */ 3094 MODE_11NA_HT20 = 4, 3095 MODE_11NG_HT20 = 5, 3096 MODE_11NA_HT40 = 6, 3097 MODE_11NG_HT40 = 7, 3098 MODE_11AC_VHT20 = 8, 3099 MODE_11AC_VHT40 = 9, 3100 MODE_11AC_VHT80 = 10, 3101 MODE_11AC_VHT20_2G = 11, 3102 MODE_11AC_VHT40_2G = 12, 3103 MODE_11AC_VHT80_2G = 13, 3104 MODE_11AC_VHT80_80 = 14, 3105 MODE_11AC_VHT160 = 15, 3106 MODE_11AX_HE20 = 16, 3107 MODE_11AX_HE40 = 17, 3108 MODE_11AX_HE80 = 18, 3109 MODE_11AX_HE80_80 = 19, 3110 MODE_11AX_HE160 = 20, 3111 MODE_11AX_HE20_2G = 21, 3112 MODE_11AX_HE40_2G = 22, 3113 MODE_11AX_HE80_2G = 23, 3114 MODE_11BE_EHT20 = 24, 3115 MODE_11BE_EHT40 = 25, 3116 MODE_11BE_EHT80 = 26, 3117 MODE_11BE_EHT80_80 = 27, 3118 MODE_11BE_EHT160 = 28, 3119 MODE_11BE_EHT160_160 = 29, 3120 MODE_11BE_EHT320 = 30, 3121 MODE_11BE_EHT20_2G = 31, 3122 MODE_11BE_EHT40_2G = 32, 3123 MODE_UNKNOWN = 33, 3124 MODE_MAX = 33, 3125 }; 3126 3127 #define ATH12K_WMI_MLO_MAX_LINKS 4 3128 3129 struct wmi_ml_partner_info { 3130 u32 vdev_id; 3131 u32 hw_link_id; 3132 u8 addr[ETH_ALEN]; 3133 bool assoc_link; 3134 bool primary_umac; 3135 bool logical_link_idx_valid; 3136 u32 logical_link_idx; 3137 u32 ieee_link_id; 3138 }; 3139 3140 struct wmi_ml_arg { 3141 bool enabled; 3142 bool assoc_link; 3143 bool mcast_link; 3144 bool link_add; 3145 u32 ieee_link_id; 3146 u8 num_partner_links; 3147 struct wmi_ml_partner_info partner_info[ATH12K_WMI_MLO_MAX_LINKS]; 3148 }; 3149 3150 struct wmi_vdev_start_req_arg { 3151 u32 vdev_id; 3152 u32 freq; 3153 u32 band_center_freq1; 3154 u32 band_center_freq2; 3155 bool passive; 3156 bool allow_ibss; 3157 bool allow_ht; 3158 bool allow_vht; 3159 bool ht40plus; 3160 bool chan_radar; 3161 bool freq2_radar; 3162 bool allow_he; 3163 u32 min_power; 3164 u32 max_power; 3165 u32 max_reg_power; 3166 u32 max_antenna_gain; 3167 enum wmi_phy_mode mode; 3168 u32 bcn_intval; 3169 u32 dtim_period; 3170 u8 *ssid; 3171 u32 ssid_len; 3172 u32 bcn_tx_rate; 3173 u32 bcn_tx_power; 3174 bool disable_hw_ack; 3175 bool hidden_ssid; 3176 bool pmf_enabled; 3177 u32 he_ops; 3178 u32 cac_duration_ms; 3179 u32 regdomain; 3180 u32 pref_rx_streams; 3181 u32 pref_tx_streams; 3182 u32 num_noa_descriptors; 3183 u32 min_data_rate; 3184 u32 mbssid_flags; 3185 u32 mbssid_tx_vdev_id; 3186 u32 punct_bitmap; 3187 struct wmi_ml_arg ml; 3188 }; 3189 3190 struct ath12k_wmi_peer_create_arg { 3191 const u8 *peer_addr; 3192 u32 peer_type; 3193 u32 vdev_id; 3194 bool ml_enabled; 3195 }; 3196 3197 struct wmi_peer_create_mlo_params { 3198 __le32 tlv_header; 3199 __le32 flags; 3200 }; 3201 3202 struct ath12k_wmi_pdev_set_regdomain_arg { 3203 u16 current_rd_in_use; 3204 u16 current_rd_2g; 3205 u16 current_rd_5g; 3206 u32 ctl_2g; 3207 u32 ctl_5g; 3208 u8 dfs_domain; 3209 u32 pdev_id; 3210 }; 3211 3212 struct ath12k_wmi_rx_reorder_queue_remove_arg { 3213 u8 *peer_macaddr; 3214 u16 vdev_id; 3215 u32 peer_tid_bitmap; 3216 }; 3217 3218 #define WMI_HOST_PDEV_ID_SOC 0xFF 3219 #define WMI_HOST_PDEV_ID_0 0 3220 #define WMI_HOST_PDEV_ID_1 1 3221 #define WMI_HOST_PDEV_ID_2 2 3222 3223 #define WMI_PDEV_ID_SOC 0 3224 #define WMI_PDEV_ID_1ST 1 3225 #define WMI_PDEV_ID_2ND 2 3226 #define WMI_PDEV_ID_3RD 3 3227 3228 /* Freq units in MHz */ 3229 #define REG_RULE_START_FREQ 0x0000ffff 3230 #define REG_RULE_END_FREQ 0xffff0000 3231 #define REG_RULE_FLAGS 0x0000ffff 3232 #define REG_RULE_MAX_BW 0x0000ffff 3233 #define REG_RULE_REG_PWR 0x00ff0000 3234 #define REG_RULE_ANT_GAIN 0xff000000 3235 #define REG_RULE_PSD_INFO BIT(2) 3236 #define REG_RULE_PSD_EIRP 0xffff0000 3237 3238 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 3239 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 3240 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 3241 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 3242 3243 #define HE_MODE_SU_TX_BFEE BIT(0) 3244 #define HE_MODE_SU_TX_BFER BIT(1) 3245 #define HE_MODE_MU_TX_BFEE BIT(2) 3246 #define HE_MODE_MU_TX_BFER BIT(3) 3247 #define HE_MODE_DL_OFDMA BIT(4) 3248 #define HE_MODE_UL_OFDMA BIT(5) 3249 #define HE_MODE_UL_MUMIMO BIT(6) 3250 3251 #define HE_DL_MUOFDMA_ENABLE 1 3252 #define HE_UL_MUOFDMA_ENABLE 1 3253 #define HE_DL_MUMIMO_ENABLE 1 3254 #define HE_UL_MUMIMO_ENABLE 1 3255 #define HE_MU_BFEE_ENABLE 1 3256 #define HE_SU_BFEE_ENABLE 1 3257 #define HE_MU_BFER_ENABLE 1 3258 #define HE_SU_BFER_ENABLE 1 3259 3260 #define EHT_MODE_SU_TX_BFEE BIT(0) 3261 #define EHT_MODE_SU_TX_BFER BIT(1) 3262 #define EHT_MODE_MU_TX_BFEE BIT(2) 3263 #define EHT_MODE_MU_TX_BFER BIT(3) 3264 #define EHT_MODE_DL_OFDMA BIT(4) 3265 #define EHT_MODE_UL_OFDMA BIT(5) 3266 #define EHT_MODE_MUMIMO BIT(6) 3267 #define EHT_MODE_DL_OFDMA_TXBF BIT(7) 3268 #define EHT_MODE_DL_OFDMA_MUMIMO BIT(8) 3269 #define EHT_MODE_UL_OFDMA_MUMIMO BIT(9) 3270 3271 #define EHT_DL_MUOFDMA_ENABLE 1 3272 #define EHT_UL_MUOFDMA_ENABLE 1 3273 #define EHT_DL_MUMIMO_ENABLE 1 3274 #define EHT_UL_MUMIMO_ENABLE 1 3275 #define EHT_MU_BFEE_ENABLE 1 3276 #define EHT_SU_BFEE_ENABLE 1 3277 #define EHT_MU_BFER_ENABLE 1 3278 #define EHT_SU_BFER_ENABLE 1 3279 3280 #define HE_VHT_SOUNDING_MODE_ENABLE 1 3281 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 3282 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 3283 3284 /* HE or VHT Sounding */ 3285 #define HE_VHT_SOUNDING_MODE BIT(0) 3286 /* SU or MU Sounding */ 3287 #define HE_SU_MU_SOUNDING_MODE BIT(2) 3288 /* Trig or Non-Trig Sounding */ 3289 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 3290 3291 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 3292 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 3293 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 3294 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 3295 3296 enum wmi_peer_type { 3297 WMI_PEER_TYPE_DEFAULT = 0, 3298 WMI_PEER_TYPE_BSS = 1, 3299 WMI_PEER_TYPE_TDLS = 2, 3300 }; 3301 3302 struct wmi_peer_create_cmd { 3303 __le32 tlv_header; 3304 __le32 vdev_id; 3305 struct ath12k_wmi_mac_addr_params peer_macaddr; 3306 __le32 peer_type; 3307 } __packed; 3308 3309 struct wmi_peer_delete_cmd { 3310 __le32 tlv_header; 3311 __le32 vdev_id; 3312 struct ath12k_wmi_mac_addr_params peer_macaddr; 3313 } __packed; 3314 3315 struct wmi_peer_reorder_queue_setup_cmd { 3316 __le32 tlv_header; 3317 __le32 vdev_id; 3318 struct ath12k_wmi_mac_addr_params peer_macaddr; 3319 __le32 tid; 3320 __le32 queue_ptr_lo; 3321 __le32 queue_ptr_hi; 3322 __le32 queue_no; 3323 __le32 ba_window_size_valid; 3324 __le32 ba_window_size; 3325 } __packed; 3326 3327 struct wmi_peer_reorder_queue_remove_cmd { 3328 __le32 tlv_header; 3329 __le32 vdev_id; 3330 struct ath12k_wmi_mac_addr_params peer_macaddr; 3331 __le32 tid_mask; 3332 } __packed; 3333 3334 enum wmi_bss_chan_info_req_type { 3335 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3336 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3337 }; 3338 3339 struct wmi_pdev_set_param_cmd { 3340 __le32 tlv_header; 3341 __le32 pdev_id; 3342 __le32 param_id; 3343 __le32 param_value; 3344 } __packed; 3345 3346 struct wmi_pdev_set_ps_mode_cmd { 3347 __le32 tlv_header; 3348 __le32 vdev_id; 3349 __le32 sta_ps_mode; 3350 } __packed; 3351 3352 struct wmi_pdev_suspend_cmd { 3353 __le32 tlv_header; 3354 __le32 pdev_id; 3355 __le32 suspend_opt; 3356 } __packed; 3357 3358 struct wmi_pdev_resume_cmd { 3359 __le32 tlv_header; 3360 __le32 pdev_id; 3361 } __packed; 3362 3363 struct wmi_pdev_bss_chan_info_req_cmd { 3364 __le32 tlv_header; 3365 /* ref wmi_bss_chan_info_req_type */ 3366 __le32 req_type; 3367 __le32 pdev_id; 3368 } __packed; 3369 3370 struct wmi_ap_ps_peer_cmd { 3371 __le32 tlv_header; 3372 __le32 vdev_id; 3373 struct ath12k_wmi_mac_addr_params peer_macaddr; 3374 __le32 param; 3375 __le32 value; 3376 } __packed; 3377 3378 struct wmi_sta_powersave_param_cmd { 3379 __le32 tlv_header; 3380 __le32 vdev_id; 3381 __le32 param; 3382 __le32 value; 3383 } __packed; 3384 3385 struct wmi_pdev_set_regdomain_cmd { 3386 __le32 tlv_header; 3387 __le32 pdev_id; 3388 __le32 reg_domain; 3389 __le32 reg_domain_2g; 3390 __le32 reg_domain_5g; 3391 __le32 conformance_test_limit_2g; 3392 __le32 conformance_test_limit_5g; 3393 __le32 dfs_domain; 3394 } __packed; 3395 3396 struct wmi_peer_set_param_cmd { 3397 __le32 tlv_header; 3398 __le32 vdev_id; 3399 struct ath12k_wmi_mac_addr_params peer_macaddr; 3400 __le32 param_id; 3401 __le32 param_value; 3402 } __packed; 3403 3404 struct wmi_peer_flush_tids_cmd { 3405 __le32 tlv_header; 3406 __le32 vdev_id; 3407 struct ath12k_wmi_mac_addr_params peer_macaddr; 3408 __le32 peer_tid_bitmap; 3409 } __packed; 3410 3411 struct wmi_dfs_phyerr_offload_cmd { 3412 __le32 tlv_header; 3413 __le32 pdev_id; 3414 } __packed; 3415 3416 struct wmi_bcn_offload_ctrl_cmd { 3417 __le32 tlv_header; 3418 __le32 vdev_id; 3419 __le32 bcn_ctrl_op; 3420 } __packed; 3421 3422 enum scan_dwelltime_adaptive_mode { 3423 SCAN_DWELL_MODE_DEFAULT = 0, 3424 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3425 SCAN_DWELL_MODE_MODERATE = 2, 3426 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3427 SCAN_DWELL_MODE_STATIC = 4 3428 }; 3429 3430 #define WLAN_SCAN_MAX_NUM_SSID 10 3431 #define WLAN_SCAN_MAX_NUM_BSSID 10 3432 3433 struct ath12k_wmi_element_info_arg { 3434 u32 len; 3435 u8 *ptr; 3436 }; 3437 3438 #define WMI_IE_BITMAP_SIZE 8 3439 3440 #define WMI_SCAN_MAX_NUM_SSID 0x0A 3441 /* prefix used by scan requestor ids on the host */ 3442 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3443 3444 /* prefix used by scan request ids generated on the host */ 3445 /* host cycles through the lower 12 bits to generate ids */ 3446 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3447 3448 #define WLAN_SCAN_PARAMS_MAX_SSID 16 3449 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 3450 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 512 3451 3452 /* Values lower than this may be refused by some firmware revisions with a scan 3453 * completion with a timedout reason. 3454 */ 3455 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3456 3457 /* Scan priority numbers must be sequential, starting with 0 */ 3458 enum wmi_scan_priority { 3459 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3460 WMI_SCAN_PRIORITY_LOW, 3461 WMI_SCAN_PRIORITY_MEDIUM, 3462 WMI_SCAN_PRIORITY_HIGH, 3463 WMI_SCAN_PRIORITY_VERY_HIGH, 3464 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3465 }; 3466 3467 enum wmi_scan_event_type { 3468 WMI_SCAN_EVENT_STARTED = BIT(0), 3469 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3470 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3471 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3472 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3473 /* possibly by high-prio scan */ 3474 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3475 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3476 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3477 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3478 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3479 WMI_SCAN_EVENT_RESUMED = BIT(10), 3480 WMI_SCAN_EVENT_MAX = BIT(15), 3481 }; 3482 3483 enum wmi_scan_completion_reason { 3484 WMI_SCAN_REASON_COMPLETED, 3485 WMI_SCAN_REASON_CANCELLED, 3486 WMI_SCAN_REASON_PREEMPTED, 3487 WMI_SCAN_REASON_TIMEDOUT, 3488 WMI_SCAN_REASON_INTERNAL_FAILURE, 3489 WMI_SCAN_REASON_MAX, 3490 }; 3491 3492 struct wmi_start_scan_cmd { 3493 __le32 tlv_header; 3494 __le32 scan_id; 3495 __le32 scan_req_id; 3496 __le32 vdev_id; 3497 __le32 scan_priority; 3498 __le32 notify_scan_events; 3499 __le32 dwell_time_active; 3500 __le32 dwell_time_passive; 3501 __le32 min_rest_time; 3502 __le32 max_rest_time; 3503 __le32 repeat_probe_time; 3504 __le32 probe_spacing_time; 3505 __le32 idle_time; 3506 __le32 max_scan_time; 3507 __le32 probe_delay; 3508 __le32 scan_ctrl_flags; 3509 __le32 burst_duration; 3510 __le32 num_chan; 3511 __le32 num_bssid; 3512 __le32 num_ssids; 3513 __le32 ie_len; 3514 __le32 n_probes; 3515 struct ath12k_wmi_mac_addr_params mac_addr; 3516 struct ath12k_wmi_mac_addr_params mac_mask; 3517 u32 ie_bitmap[WMI_IE_BITMAP_SIZE]; 3518 __le32 num_vendor_oui; 3519 __le32 scan_ctrl_flags_ext; 3520 __le32 dwell_time_active_2g; 3521 __le32 dwell_time_active_6g; 3522 __le32 dwell_time_passive_6g; 3523 __le32 scan_start_offset; 3524 } __packed; 3525 3526 #define WMI_SCAN_FLAG_PASSIVE 0x1 3527 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3528 #define WMI_SCAN_ADD_CCK_RATES 0x4 3529 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3530 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3531 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3532 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3533 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3534 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3535 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3536 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3537 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3538 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3539 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3540 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3541 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3542 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3543 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3544 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3545 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3546 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3547 3548 #define WMI_SCAN_DWELL_MODE_MASK GENMASK(23, 21) 3549 3550 enum { 3551 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3552 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3553 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3554 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3555 WMI_SCAN_DWELL_MODE_STATIC = 4, 3556 }; 3557 3558 struct ath12k_wmi_hint_short_ssid_arg { 3559 u32 freq_flags; 3560 u32 short_ssid; 3561 }; 3562 3563 struct ath12k_wmi_hint_bssid_arg { 3564 u32 freq_flags; 3565 struct ath12k_wmi_mac_addr_params bssid; 3566 }; 3567 3568 struct ath12k_wmi_hint_short_ssid_params { 3569 __le32 freq_flags; 3570 __le32 short_ssid; 3571 }; 3572 3573 struct ath12k_wmi_hint_bssid_params { 3574 __le32 freq_flags; 3575 struct ath12k_wmi_mac_addr_params bssid; 3576 }; 3577 3578 struct ath12k_wmi_scan_req_arg { 3579 u32 scan_id; 3580 u32 scan_req_id; 3581 u32 vdev_id; 3582 u32 pdev_id; 3583 enum wmi_scan_priority scan_priority; 3584 u32 scan_ev_started:1, 3585 scan_ev_completed:1, 3586 scan_ev_bss_chan:1, 3587 scan_ev_foreign_chan:1, 3588 scan_ev_dequeued:1, 3589 scan_ev_preempted:1, 3590 scan_ev_start_failed:1, 3591 scan_ev_restarted:1, 3592 scan_ev_foreign_chn_exit:1, 3593 scan_ev_invalid:1, 3594 scan_ev_gpio_timeout:1, 3595 scan_ev_suspended:1, 3596 scan_ev_resumed:1; 3597 u32 dwell_time_active; 3598 u32 dwell_time_active_2g; 3599 u32 dwell_time_passive; 3600 u32 dwell_time_active_6g; 3601 u32 dwell_time_passive_6g; 3602 u32 min_rest_time; 3603 u32 max_rest_time; 3604 u32 repeat_probe_time; 3605 u32 probe_spacing_time; 3606 u32 idle_time; 3607 u32 max_scan_time; 3608 u32 probe_delay; 3609 u32 scan_f_passive:1, 3610 scan_f_bcast_probe:1, 3611 scan_f_cck_rates:1, 3612 scan_f_ofdm_rates:1, 3613 scan_f_chan_stat_evnt:1, 3614 scan_f_filter_prb_req:1, 3615 scan_f_bypass_dfs_chn:1, 3616 scan_f_continue_on_err:1, 3617 scan_f_offchan_mgmt_tx:1, 3618 scan_f_offchan_data_tx:1, 3619 scan_f_promisc_mode:1, 3620 scan_f_capture_phy_err:1, 3621 scan_f_strict_passive_pch:1, 3622 scan_f_half_rate:1, 3623 scan_f_quarter_rate:1, 3624 scan_f_force_active_dfs_chn:1, 3625 scan_f_add_tpc_ie_in_probe:1, 3626 scan_f_add_ds_ie_in_probe:1, 3627 scan_f_add_spoofed_mac_in_probe:1, 3628 scan_f_add_rand_seq_in_probe:1, 3629 scan_f_en_ie_whitelist_in_probe:1, 3630 scan_f_forced:1, 3631 scan_f_2ghz:1, 3632 scan_f_5ghz:1, 3633 scan_f_80mhz:1; 3634 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3635 u32 burst_duration; 3636 u32 num_chan; 3637 u32 num_bssid; 3638 u32 num_ssids; 3639 u32 n_probes; 3640 u32 notify_scan_events; 3641 struct cfg80211_ssid ssid[WLAN_SCAN_MAX_NUM_SSID]; 3642 struct ath12k_wmi_mac_addr_params bssid_list[WLAN_SCAN_MAX_NUM_BSSID]; 3643 struct ath12k_wmi_element_info_arg extraie; 3644 u32 num_hint_s_ssid; 3645 u32 num_hint_bssid; 3646 struct ath12k_wmi_hint_short_ssid_arg hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3647 struct ath12k_wmi_hint_bssid_arg hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3648 u32 chan_list[] __counted_by(num_chan); 3649 }; 3650 3651 struct wmi_ssid_arg { 3652 int len; 3653 const u8 *ssid; 3654 }; 3655 3656 struct wmi_bssid_arg { 3657 const u8 *bssid; 3658 }; 3659 3660 #define WMI_SCAN_STOP_ONE 0x00000000 3661 #define WMI_SCAN_STOP_VAP_ALL 0x01000000 3662 #define WMI_SCAN_STOP_ALL 0x04000000 3663 3664 /* Prefix 0xA000 indicates that the scan request 3665 * is trigger by HOST 3666 */ 3667 #define ATH12K_SCAN_ID 0xA000 3668 3669 enum scan_cancel_req_type { 3670 WLAN_SCAN_CANCEL_SINGLE = 1, 3671 WLAN_SCAN_CANCEL_VDEV_ALL, 3672 WLAN_SCAN_CANCEL_PDEV_ALL, 3673 }; 3674 3675 struct ath12k_wmi_scan_cancel_arg { 3676 u32 requester; 3677 u32 scan_id; 3678 enum scan_cancel_req_type req_type; 3679 u32 vdev_id; 3680 u32 pdev_id; 3681 }; 3682 3683 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3684 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3685 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3686 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3687 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3688 #define WMI_CHAN_INFO_DFS BIT(10) 3689 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3690 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3691 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3692 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3693 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3694 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3695 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3696 #define WMI_CHAN_INFO_PSC BIT(18) 3697 3698 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3699 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3700 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3701 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3702 3703 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3704 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3705 3706 struct ath12k_wmi_channel_params { 3707 __le32 tlv_header; 3708 __le32 mhz; 3709 __le32 band_center_freq1; 3710 __le32 band_center_freq2; 3711 __le32 info; 3712 __le32 reg_info_1; 3713 __le32 reg_info_2; 3714 } __packed; 3715 3716 enum wmi_sta_ps_mode { 3717 WMI_STA_PS_MODE_DISABLED = 0, 3718 WMI_STA_PS_MODE_ENABLED = 1, 3719 }; 3720 3721 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3722 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3723 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3724 3725 #define ATH12K_WMI_FW_HANG_ASSERT_TYPE 1 3726 #define ATH12K_WMI_FW_HANG_DELAY 0 3727 3728 /* type, 0:unused 1: ASSERT 2: not respond detect command 3729 * delay_time_ms, the simulate will delay time 3730 */ 3731 3732 struct wmi_force_fw_hang_cmd { 3733 __le32 tlv_header; 3734 __le32 type; 3735 __le32 delay_time_ms; 3736 } __packed; 3737 3738 /* Param values to be sent for WMI_VDEV_PARAM_SGI param_id 3739 * which are used in 11n, 11ac systems 3740 * @WMI_GI_800_NS - Always uses 0.8us (Long GI) 3741 * @WMI_GI_400_NS - Firmware switches between 0.4us (Short GI) 3742 * and 0.8us (Long GI) based on packet error rate. 3743 */ 3744 #define WMI_GI_800_NS 0 3745 #define WMI_GI_400_NS 1 3746 3747 struct wmi_vdev_set_param_cmd { 3748 __le32 tlv_header; 3749 __le32 vdev_id; 3750 __le32 param_id; 3751 __le32 param_value; 3752 } __packed; 3753 3754 struct wmi_get_pdev_temperature_cmd { 3755 __le32 tlv_header; 3756 __le32 param; 3757 __le32 pdev_id; 3758 } __packed; 3759 3760 #define WMI_P2P_MAX_NOA_DESCRIPTORS 4 3761 3762 struct wmi_p2p_noa_event { 3763 __le32 vdev_id; 3764 } __packed; 3765 3766 struct ath12k_wmi_p2p_noa_descriptor { 3767 __le32 type_count; /* 255: continuous schedule, 0: reserved */ 3768 __le32 duration; /* Absent period duration in micro seconds */ 3769 __le32 interval; /* Absent period interval in micro seconds */ 3770 __le32 start_time; /* 32 bit tsf time when in starts */ 3771 } __packed; 3772 3773 #define WMI_P2P_NOA_INFO_CHANGED_FLAG BIT(0) 3774 #define WMI_P2P_NOA_INFO_INDEX GENMASK(15, 8) 3775 #define WMI_P2P_NOA_INFO_OPP_PS BIT(16) 3776 #define WMI_P2P_NOA_INFO_CTWIN_TU GENMASK(23, 17) 3777 #define WMI_P2P_NOA_INFO_DESC_NUM GENMASK(31, 24) 3778 3779 struct ath12k_wmi_p2p_noa_info { 3780 /* Bit 0 - Flag to indicate an update in NOA schedule 3781 * Bits 7-1 - Reserved 3782 * Bits 15-8 - Index (identifies the instance of NOA sub element) 3783 * Bit 16 - Opp PS state of the AP 3784 * Bits 23-17 - Ctwindow in TUs 3785 * Bits 31-24 - Number of NOA descriptors 3786 */ 3787 __le32 noa_attr; 3788 struct ath12k_wmi_p2p_noa_descriptor descriptors[WMI_P2P_MAX_NOA_DESCRIPTORS]; 3789 } __packed; 3790 3791 #define MAX_WMI_UTF_LEN 252 3792 3793 struct ath12k_wmi_ftm_seg_hdr_params { 3794 __le32 len; 3795 __le32 msgref; 3796 __le32 segmentinfo; 3797 __le32 pdev_id; 3798 } __packed; 3799 3800 struct ath12k_wmi_ftm_cmd { 3801 __le32 tlv_header; 3802 struct ath12k_wmi_ftm_seg_hdr_params seg_hdr; 3803 u8 data[]; 3804 } __packed; 3805 3806 struct ath12k_wmi_ftm_event { 3807 struct ath12k_wmi_ftm_seg_hdr_params seg_hdr; 3808 u8 data[]; 3809 } __packed; 3810 3811 #define WMI_BEACON_TX_BUFFER_SIZE 512 3812 3813 #define WMI_EMA_BEACON_CNT GENMASK(7, 0) 3814 #define WMI_EMA_BEACON_IDX GENMASK(15, 8) 3815 #define WMI_EMA_BEACON_FIRST GENMASK(23, 16) 3816 #define WMI_EMA_BEACON_LAST GENMASK(31, 24) 3817 3818 #define WMI_BEACON_PROTECTION_EN_BIT BIT(0) 3819 3820 struct ath12k_wmi_bcn_tmpl_ema_arg { 3821 u8 bcn_cnt; 3822 u8 bcn_index; 3823 }; 3824 3825 struct wmi_bcn_tmpl_cmd { 3826 __le32 tlv_header; 3827 __le32 vdev_id; 3828 __le32 tim_ie_offset; 3829 __le32 buf_len; 3830 __le32 csa_switch_count_offset; 3831 __le32 ext_csa_switch_count_offset; 3832 __le32 csa_event_bitmap; 3833 __le32 mbssid_ie_offset; 3834 __le32 esp_ie_offset; 3835 __le32 csc_switch_count_offset; 3836 __le32 csc_event_bitmap; 3837 __le32 mu_edca_ie_offset; 3838 __le32 feature_enable_bitmap; 3839 __le32 ema_params; 3840 } __packed; 3841 3842 struct wmi_p2p_go_set_beacon_ie_cmd { 3843 __le32 tlv_header; 3844 __le32 vdev_id; 3845 __le32 ie_buf_len; 3846 } __packed; 3847 3848 struct wmi_vdev_install_key_cmd { 3849 __le32 tlv_header; 3850 __le32 vdev_id; 3851 struct ath12k_wmi_mac_addr_params peer_macaddr; 3852 __le32 key_idx; 3853 __le32 key_flags; 3854 __le32 key_cipher; 3855 __le64 key_rsc_counter; 3856 __le64 key_global_rsc_counter; 3857 __le64 key_tsc_counter; 3858 u8 wpi_key_rsc_counter[16]; 3859 u8 wpi_key_tsc_counter[16]; 3860 __le32 key_len; 3861 __le32 key_txmic_len; 3862 __le32 key_rxmic_len; 3863 __le32 is_group_key_id_valid; 3864 __le32 group_key_id; 3865 3866 /* Followed by key_data containing key followed by 3867 * tx mic and then rx mic 3868 */ 3869 } __packed; 3870 3871 struct wmi_vdev_install_key_arg { 3872 u32 vdev_id; 3873 const u8 *macaddr; 3874 u32 key_idx; 3875 u32 key_flags; 3876 u32 key_cipher; 3877 u32 ieee80211_key_cipher; 3878 u32 key_len; 3879 u32 key_txmic_len; 3880 u32 key_rxmic_len; 3881 u64 key_rsc_counter; 3882 const void *key_data; 3883 }; 3884 3885 #define WMI_MAX_SUPPORTED_RATES 128 3886 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3887 #define WMI_HOST_MAX_HE_RATE_SET 3 3888 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3889 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3890 3891 #define ATH12K_WMI_MLO_MAX_PARTNER_LINKS \ 3892 (ATH12K_WMI_MLO_MAX_LINKS + ATH12K_MAX_NUM_BRIDGE_LINKS - 1) 3893 3894 struct peer_assoc_mlo_params { 3895 bool enabled; 3896 bool assoc_link; 3897 bool primary_umac; 3898 bool peer_id_valid; 3899 bool logical_link_idx_valid; 3900 bool bridge_peer; 3901 u8 mld_addr[ETH_ALEN]; 3902 u32 logical_link_idx; 3903 u32 ml_peer_id; 3904 u32 ieee_link_id; 3905 u8 num_partner_links; 3906 struct wmi_ml_partner_info partner_info[ATH12K_WMI_MLO_MAX_LINKS]; 3907 u16 eml_cap; 3908 }; 3909 3910 struct wmi_rate_set_arg { 3911 u32 num_rates; 3912 u8 rates[WMI_MAX_SUPPORTED_RATES]; 3913 }; 3914 3915 struct ath12k_wmi_peer_assoc_arg { 3916 u32 vdev_id; 3917 u32 peer_new_assoc; 3918 u32 peer_associd; 3919 u32 peer_flags; 3920 u32 peer_caps; 3921 u32 peer_listen_intval; 3922 u32 peer_ht_caps; 3923 u32 peer_max_mpdu; 3924 u32 peer_mpdu_density; 3925 u32 peer_rate_caps; 3926 u32 peer_nss; 3927 u32 peer_vht_caps; 3928 u32 peer_phymode; 3929 u32 peer_ht_info[2]; 3930 struct wmi_rate_set_arg peer_legacy_rates; 3931 struct wmi_rate_set_arg peer_ht_rates; 3932 u32 rx_max_rate; 3933 u32 rx_mcs_set; 3934 u32 tx_max_rate; 3935 u32 tx_mcs_set; 3936 u8 vht_capable; 3937 u8 min_data_rate; 3938 u32 tx_max_mcs_nss; 3939 u32 peer_bw_rxnss_override; 3940 bool is_pmf_enabled; 3941 bool is_wme_set; 3942 bool qos_flag; 3943 bool apsd_flag; 3944 bool ht_flag; 3945 bool bw_40; 3946 bool bw_80; 3947 bool bw_160; 3948 bool bw_320; 3949 bool stbc_flag; 3950 bool ldpc_flag; 3951 bool static_mimops_flag; 3952 bool dynamic_mimops_flag; 3953 bool spatial_mux_flag; 3954 bool vht_flag; 3955 bool vht_ng_flag; 3956 bool need_ptk_4_way; 3957 bool need_gtk_2_way; 3958 bool auth_flag; 3959 bool safe_mode_enabled; 3960 bool amsdu_disable; 3961 /* Use common structure */ 3962 u8 peer_mac[ETH_ALEN]; 3963 3964 bool he_flag; 3965 u32 peer_he_cap_macinfo[2]; 3966 u32 peer_he_cap_macinfo_internal; 3967 u32 peer_he_caps_6ghz; 3968 u32 peer_he_ops; 3969 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3970 u32 peer_he_mcs_count; 3971 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3972 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3973 bool twt_responder; 3974 bool twt_requester; 3975 struct ath12k_wmi_ppe_threshold_arg peer_ppet; 3976 bool eht_flag; 3977 u32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE]; 3978 u32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE]; 3979 u32 peer_eht_mcs_count; 3980 u32 peer_eht_rx_mcs_set[WMI_MAX_EHTCAP_RATE_SET]; 3981 u32 peer_eht_tx_mcs_set[WMI_MAX_EHTCAP_RATE_SET]; 3982 struct ath12k_wmi_ppe_threshold_arg peer_eht_ppet; 3983 u32 punct_bitmap; 3984 bool is_assoc; 3985 struct peer_assoc_mlo_params ml; 3986 bool eht_disable_mcs15; 3987 }; 3988 3989 #define ATH12K_WMI_FLAG_MLO_ENABLED BIT(0) 3990 #define ATH12K_WMI_FLAG_MLO_ASSOC_LINK BIT(1) 3991 #define ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC BIT(2) 3992 #define ATH12K_WMI_FLAG_MLO_LINK_ID_VALID BIT(3) 3993 #define ATH12K_WMI_FLAG_MLO_PEER_ID_VALID BIT(4) 3994 3995 struct wmi_peer_assoc_mlo_partner_info_params { 3996 __le32 tlv_header; 3997 __le32 vdev_id; 3998 __le32 hw_link_id; 3999 __le32 flags; 4000 __le32 logical_link_idx; 4001 } __packed; 4002 4003 struct wmi_peer_assoc_mlo_params { 4004 __le32 tlv_header; 4005 __le32 flags; 4006 struct ath12k_wmi_mac_addr_params mld_addr; 4007 __le32 logical_link_idx; 4008 __le32 ml_peer_id; 4009 __le32 ieee_link_id; 4010 __le32 emlsr_trans_timeout_us; 4011 __le32 emlsr_trans_delay_us; 4012 __le32 emlsr_padding_delay_us; 4013 } __packed; 4014 4015 struct wmi_peer_assoc_complete_cmd { 4016 __le32 tlv_header; 4017 struct ath12k_wmi_mac_addr_params peer_macaddr; 4018 __le32 vdev_id; 4019 __le32 peer_new_assoc; 4020 __le32 peer_associd; 4021 __le32 peer_flags; 4022 __le32 peer_caps; 4023 __le32 peer_listen_intval; 4024 __le32 peer_ht_caps; 4025 __le32 peer_max_mpdu; 4026 __le32 peer_mpdu_density; 4027 __le32 peer_rate_caps; 4028 __le32 peer_nss; 4029 __le32 peer_vht_caps; 4030 __le32 peer_phymode; 4031 __le32 peer_ht_info[2]; 4032 __le32 num_peer_legacy_rates; 4033 __le32 num_peer_ht_rates; 4034 __le32 peer_bw_rxnss_override; 4035 struct ath12k_wmi_ppe_threshold_params peer_ppet; 4036 __le32 peer_he_cap_info; 4037 __le32 peer_he_ops; 4038 __le32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 4039 __le32 peer_he_mcs; 4040 __le32 peer_he_cap_info_ext; 4041 __le32 peer_he_cap_info_internal; 4042 __le32 min_data_rate; 4043 __le32 peer_he_caps_6ghz; 4044 __le32 sta_type; 4045 __le32 bss_max_idle_option; 4046 __le32 auth_mode; 4047 __le32 peer_flags_ext; 4048 __le32 punct_bitmap; 4049 __le32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE]; 4050 __le32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE]; 4051 __le32 peer_eht_ops; 4052 struct ath12k_wmi_ppe_threshold_params peer_eht_ppet; 4053 } __packed; 4054 4055 struct wmi_stop_scan_cmd { 4056 __le32 tlv_header; 4057 __le32 requestor; 4058 __le32 scan_id; 4059 __le32 req_type; 4060 __le32 vdev_id; 4061 __le32 pdev_id; 4062 } __packed; 4063 4064 struct ath12k_wmi_scan_chan_list_arg { 4065 struct list_head list; 4066 u32 pdev_id; 4067 u16 nallchans; 4068 struct ath12k_wmi_channel_arg channel[]; 4069 }; 4070 4071 struct wmi_scan_chan_list_cmd { 4072 __le32 tlv_header; 4073 __le32 num_scan_chans; 4074 __le32 flags; 4075 __le32 pdev_id; 4076 } __packed; 4077 4078 #define WMI_MGMT_SEND_DOWNLD_LEN 64 4079 #define WMI_MGMT_LINK_AGNOSTIC_ID 0xFFFFFFFF 4080 4081 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 4082 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 4083 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 4084 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 4085 4086 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 4087 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 4088 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 4089 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 4090 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 4091 4092 struct wmi_mgmt_send_cmd { 4093 __le32 tlv_header; 4094 __le32 vdev_id; 4095 __le32 desc_id; 4096 __le32 chanfreq; 4097 __le32 paddr_lo; 4098 __le32 paddr_hi; 4099 __le32 frame_len; 4100 __le32 buf_len; 4101 __le32 tx_params_valid; 4102 4103 /* This TLV is followed by struct wmi_mgmt_frame */ 4104 4105 /* Followed by struct ath12k_wmi_mlo_mgmt_send_params */ 4106 } __packed; 4107 4108 struct ath12k_wmi_mlo_mgmt_send_params { 4109 __le32 tlv_header; 4110 __le32 hw_link_id; 4111 } __packed; 4112 4113 struct ath12k_wmi_mgmt_send_tx_params { 4114 __le32 tlv_header; 4115 __le32 tx_param_dword0; 4116 __le32 tx_param_dword1; 4117 } __packed; 4118 4119 struct wmi_sta_powersave_mode_cmd { 4120 __le32 tlv_header; 4121 __le32 vdev_id; 4122 __le32 sta_ps_mode; 4123 } __packed; 4124 4125 struct wmi_sta_smps_force_mode_cmd { 4126 __le32 tlv_header; 4127 __le32 vdev_id; 4128 __le32 forced_mode; 4129 } __packed; 4130 4131 struct wmi_sta_smps_param_cmd { 4132 __le32 tlv_header; 4133 __le32 vdev_id; 4134 __le32 param; 4135 __le32 value; 4136 } __packed; 4137 4138 struct ath12k_wmi_bcn_prb_info_params { 4139 __le32 tlv_header; 4140 __le32 caps; 4141 __le32 erp; 4142 } __packed; 4143 4144 enum { 4145 WMI_PDEV_SUSPEND, 4146 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 4147 }; 4148 4149 struct wmi_pdev_green_ap_ps_enable_cmd_param { 4150 __le32 tlv_header; 4151 __le32 pdev_id; 4152 __le32 enable; 4153 } __packed; 4154 4155 struct ath12k_wmi_ap_ps_arg { 4156 u32 vdev_id; 4157 u32 param; 4158 u32 value; 4159 }; 4160 4161 enum set_init_cc_type { 4162 WMI_COUNTRY_INFO_TYPE_ALPHA, 4163 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 4164 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 4165 }; 4166 4167 enum set_init_cc_flags { 4168 INVALID_CC, 4169 CC_IS_SET, 4170 REGDMN_IS_SET, 4171 ALPHA_IS_SET, 4172 }; 4173 4174 struct wmi_therm_throt_stats_event { 4175 __le32 pdev_id; 4176 __le32 temp; 4177 __le32 level; 4178 __le32 therm_throt_levels; 4179 } __packed; 4180 4181 #define THERMAL_LEVELS 4 4182 #define ENHANCED_THERMAL_LEVELS 5 4183 4184 struct ath12k_wmi_tt_level_config_param { 4185 s32 tmplwm; 4186 s32 tmphwm; 4187 u32 dcoffpercent; 4188 u32 pout_reduction_db; 4189 }; 4190 4191 struct ath12k_wmi_therm_throt_config_request_cmd { 4192 __le32 tlv_header; 4193 __le32 pdev_id; 4194 __le32 enable; 4195 __le32 dc; 4196 /* After how many duty cycles the firmware sends stats to host */ 4197 __le32 dc_per_event; 4198 __le32 therm_throt_levels; 4199 } __packed; 4200 4201 struct ath12k_wmi_therm_throt_level_config_param { 4202 __le32 tlv_header; 4203 a_sle32 temp_lwm; 4204 a_sle32 temp_hwm; 4205 __le32 dc_off_percent; 4206 __le32 prio; 4207 __le32 pout_reduction_25db; 4208 __le32 tx_chain_mask; 4209 __le32 duty_cycle; 4210 } __packed; 4211 4212 struct ath12k_wmi_thermal_mitigation_arg { 4213 int num_levels; 4214 const struct ath12k_wmi_tt_level_config_param *levelconf; 4215 }; 4216 4217 struct ath12k_wmi_init_country_arg { 4218 union { 4219 u16 country_code; 4220 u16 regdom_id; 4221 u8 alpha2[3]; 4222 } cc_info; 4223 enum set_init_cc_flags flags; 4224 }; 4225 4226 struct wmi_init_country_cmd { 4227 __le32 tlv_header; 4228 __le32 pdev_id; 4229 __le32 init_cc_type; 4230 union { 4231 __le32 country_code; 4232 __le32 regdom_id; 4233 __le32 alpha2; 4234 } cc_info; 4235 } __packed; 4236 4237 struct wmi_11d_scan_start_arg { 4238 u32 vdev_id; 4239 u32 scan_period_msec; 4240 u32 start_interval_msec; 4241 }; 4242 4243 struct wmi_11d_scan_start_cmd { 4244 __le32 tlv_header; 4245 __le32 vdev_id; 4246 __le32 scan_period_msec; 4247 __le32 start_interval_msec; 4248 } __packed; 4249 4250 struct wmi_11d_scan_stop_cmd { 4251 __le32 tlv_header; 4252 __le32 vdev_id; 4253 } __packed; 4254 4255 struct wmi_11d_new_cc_event { 4256 __le32 new_alpha2; 4257 } __packed; 4258 4259 struct wmi_delba_send_cmd { 4260 __le32 tlv_header; 4261 __le32 vdev_id; 4262 struct ath12k_wmi_mac_addr_params peer_macaddr; 4263 __le32 tid; 4264 __le32 initiator; 4265 __le32 reasoncode; 4266 } __packed; 4267 4268 struct wmi_addba_setresponse_cmd { 4269 __le32 tlv_header; 4270 __le32 vdev_id; 4271 struct ath12k_wmi_mac_addr_params peer_macaddr; 4272 __le32 tid; 4273 __le32 statuscode; 4274 } __packed; 4275 4276 struct wmi_addba_send_cmd { 4277 __le32 tlv_header; 4278 __le32 vdev_id; 4279 struct ath12k_wmi_mac_addr_params peer_macaddr; 4280 __le32 tid; 4281 __le32 buffersize; 4282 } __packed; 4283 4284 struct wmi_addba_clear_resp_cmd { 4285 __le32 tlv_header; 4286 __le32 vdev_id; 4287 struct ath12k_wmi_mac_addr_params peer_macaddr; 4288 } __packed; 4289 4290 #define DFS_UNIT_TEST_MODULE 0x2b 4291 #define DFS_UNIT_TEST_TOKEN 0xAA 4292 4293 enum dfs_test_args_idx { 4294 DFS_TEST_CMDID = 0, 4295 DFS_TEST_PDEV_ID, 4296 DFS_TEST_RADAR_PARAM, 4297 DFS_MAX_TEST_ARGS, 4298 }; 4299 4300 #define ATH12K_WMI_INCUMBENT_SIGNAL_UNIT_TEST_MODULE 0x18 4301 #define ATH12K_WMI_INCUMBENT_SIGNAL_UNIT_TEST_TOKEN 0 4302 #define ATH12K_WMI_UNIT_TEST_INCUMBENT_SIGNAL_INTF_TYPE 1 4303 4304 enum ath12k_wmi_incumbent_signal_test_args_idx { 4305 ATH12K_WMI_INCUMBENT_SIGNAL_TEST_INTF, 4306 ATH12K_WMI_INCUMBENT_SIGNAL_TEST_BITMAP, 4307 ATH12K_WMI_INCUMBENT_SIGNAL_MAX_TEST_ARGS, 4308 }; 4309 4310 /* update if another test command requires more */ 4311 #define WMI_UNIT_TEST_ARGS_MAX DFS_MAX_TEST_ARGS 4312 4313 struct wmi_unit_test_arg { 4314 u32 vdev_id; 4315 u32 module_id; 4316 u32 diag_token; 4317 u32 num_args; 4318 u32 args[WMI_UNIT_TEST_ARGS_MAX]; 4319 }; 4320 4321 struct wmi_unit_test_cmd { 4322 __le32 tlv_header; 4323 __le32 vdev_id; 4324 __le32 module_id; 4325 __le32 num_args; 4326 __le32 diag_token; 4327 /* Followed by test args*/ 4328 } __packed; 4329 4330 #define MAX_SUPPORTED_RATES 128 4331 4332 struct ath12k_wmi_vht_rate_set_params { 4333 __le32 tlv_header; 4334 __le32 rx_max_rate; 4335 /* MCS at which the peer can transmit */ 4336 __le32 rx_mcs_set; 4337 __le32 tx_max_rate; 4338 /* MCS at which the peer can receive */ 4339 __le32 tx_mcs_set; 4340 __le32 tx_max_mcs_nss; 4341 } __packed; 4342 4343 struct ath12k_wmi_he_rate_set_params { 4344 __le32 tlv_header; 4345 __le32 rx_mcs_set; 4346 __le32 tx_mcs_set; 4347 } __packed; 4348 4349 struct ath12k_wmi_eht_rate_set_params { 4350 __le32 tlv_header; 4351 __le32 rx_mcs_set; 4352 __le32 tx_mcs_set; 4353 } __packed; 4354 4355 #define MAX_REG_RULES 10 4356 #define REG_ALPHA2_LEN 2 4357 #define MAX_6GHZ_REG_RULES 5 4358 4359 struct wmi_set_current_country_arg { 4360 u8 alpha2[REG_ALPHA2_LEN]; 4361 }; 4362 4363 struct wmi_set_current_country_cmd { 4364 __le32 tlv_header; 4365 __le32 pdev_id; 4366 __le32 new_alpha2; 4367 } __packed; 4368 4369 enum wmi_start_event_param { 4370 WMI_VDEV_START_RESP_EVENT = 0, 4371 WMI_VDEV_RESTART_RESP_EVENT, 4372 }; 4373 4374 struct wmi_vdev_start_resp_event { 4375 __le32 vdev_id; 4376 __le32 requestor_id; 4377 /* enum wmi_start_event_param */ 4378 __le32 resp_type; 4379 __le32 status; 4380 __le32 chain_mask; 4381 __le32 smps_mode; 4382 union { 4383 __le32 mac_id; 4384 __le32 pdev_id; 4385 }; 4386 __le32 cfgd_tx_streams; 4387 __le32 cfgd_rx_streams; 4388 __le32 max_allowed_tx_power; 4389 } __packed; 4390 4391 /* VDEV start response status codes */ 4392 enum wmi_vdev_start_resp_status_code { 4393 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4394 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4395 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4396 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4397 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4398 }; 4399 4400 enum wmi_reg_6g_ap_type { 4401 WMI_REG_INDOOR_AP = 0, 4402 WMI_REG_STD_POWER_AP = 1, 4403 WMI_REG_VLP_AP = 2, 4404 WMI_REG_CURRENT_MAX_AP_TYPE, 4405 WMI_REG_MAX_SUPP_AP_TYPE = WMI_REG_VLP_AP, 4406 WMI_REG_MAX_AP_TYPE = 7, 4407 }; 4408 4409 enum wmi_reg_6g_client_type { 4410 WMI_REG_DEFAULT_CLIENT = 0, 4411 WMI_REG_SUBORDINATE_CLIENT = 1, 4412 WMI_REG_MAX_CLIENT_TYPE = 2, 4413 }; 4414 4415 /* Regulatory Rule Flags Passed by FW */ 4416 #define REGULATORY_CHAN_DISABLED BIT(0) 4417 #define REGULATORY_CHAN_NO_IR BIT(1) 4418 #define REGULATORY_CHAN_RADAR BIT(3) 4419 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4420 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4421 4422 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4423 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4424 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4425 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4426 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4427 4428 enum { 4429 WMI_REG_SET_CC_STATUS_PASS = 0, 4430 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4431 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4432 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4433 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4434 WMI_REG_SET_CC_STATUS_FAIL = 5, 4435 }; 4436 4437 #define WMI_REG_CLIENT_MAX 4 4438 4439 struct wmi_reg_chan_list_cc_ext_event { 4440 __le32 status_code; 4441 __le32 phy_id; 4442 __le32 alpha2; 4443 __le32 num_phy; 4444 __le32 country_id; 4445 __le32 domain_code; 4446 __le32 dfs_region; 4447 __le32 phybitmap; 4448 __le32 min_bw_2g; 4449 __le32 max_bw_2g; 4450 __le32 min_bw_5g; 4451 __le32 max_bw_5g; 4452 __le32 num_2g_reg_rules; 4453 __le32 num_5g_reg_rules; 4454 __le32 client_type; 4455 __le32 rnr_tpe_usable; 4456 __le32 unspecified_ap_usable; 4457 __le32 domain_code_6g_ap_lpi; 4458 __le32 domain_code_6g_ap_sp; 4459 __le32 domain_code_6g_ap_vlp; 4460 __le32 domain_code_6g_client_lpi[WMI_REG_CLIENT_MAX]; 4461 __le32 domain_code_6g_client_sp[WMI_REG_CLIENT_MAX]; 4462 __le32 domain_code_6g_client_vlp[WMI_REG_CLIENT_MAX]; 4463 __le32 domain_code_6g_super_id; 4464 __le32 min_bw_6g_ap_sp; 4465 __le32 max_bw_6g_ap_sp; 4466 __le32 min_bw_6g_ap_lpi; 4467 __le32 max_bw_6g_ap_lpi; 4468 __le32 min_bw_6g_ap_vlp; 4469 __le32 max_bw_6g_ap_vlp; 4470 __le32 min_bw_6g_client_sp[WMI_REG_CLIENT_MAX]; 4471 __le32 max_bw_6g_client_sp[WMI_REG_CLIENT_MAX]; 4472 __le32 min_bw_6g_client_lpi[WMI_REG_CLIENT_MAX]; 4473 __le32 max_bw_6g_client_lpi[WMI_REG_CLIENT_MAX]; 4474 __le32 min_bw_6g_client_vlp[WMI_REG_CLIENT_MAX]; 4475 __le32 max_bw_6g_client_vlp[WMI_REG_CLIENT_MAX]; 4476 __le32 num_6g_reg_rules_ap_sp; 4477 __le32 num_6g_reg_rules_ap_lpi; 4478 __le32 num_6g_reg_rules_ap_vlp; 4479 __le32 num_6g_reg_rules_cl_sp[WMI_REG_CLIENT_MAX]; 4480 __le32 num_6g_reg_rules_cl_lpi[WMI_REG_CLIENT_MAX]; 4481 __le32 num_6g_reg_rules_cl_vlp[WMI_REG_CLIENT_MAX]; 4482 } __packed; 4483 4484 struct ath12k_wmi_reg_rule_ext_params { 4485 __le32 tlv_header; 4486 __le32 freq_info; 4487 __le32 bw_pwr_info; 4488 __le32 flag_info; 4489 __le32 psd_power_info; 4490 } __packed; 4491 4492 struct wmi_vdev_delete_resp_event { 4493 __le32 vdev_id; 4494 } __packed; 4495 4496 struct wmi_peer_delete_resp_event { 4497 __le32 vdev_id; 4498 struct ath12k_wmi_mac_addr_params peer_macaddr; 4499 } __packed; 4500 4501 struct wmi_bcn_tx_status_event { 4502 __le32 vdev_id; 4503 __le32 tx_status; 4504 } __packed; 4505 4506 struct wmi_vdev_stopped_event { 4507 __le32 vdev_id; 4508 } __packed; 4509 4510 struct wmi_pdev_bss_chan_info_event { 4511 __le32 freq; /* Units in MHz */ 4512 __le32 noise_floor; /* units are dBm */ 4513 /* rx clear - how often the channel was unused */ 4514 __le32 rx_clear_count_low; 4515 __le32 rx_clear_count_high; 4516 /* cycle count - elapsed time during measured period, in clock ticks */ 4517 __le32 cycle_count_low; 4518 __le32 cycle_count_high; 4519 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4520 __le32 tx_cycle_count_low; 4521 __le32 tx_cycle_count_high; 4522 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4523 __le32 rx_cycle_count_low; 4524 __le32 rx_cycle_count_high; 4525 /*rx_cycle cnt for my bss in 64bits format */ 4526 __le32 rx_bss_cycle_count_low; 4527 __le32 rx_bss_cycle_count_high; 4528 __le32 pdev_id; 4529 } __packed; 4530 4531 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4532 4533 struct wmi_vdev_install_key_compl_event { 4534 __le32 vdev_id; 4535 struct ath12k_wmi_mac_addr_params peer_macaddr; 4536 __le32 key_idx; 4537 __le32 key_flags; 4538 __le32 status; 4539 } __packed; 4540 4541 struct wmi_vdev_install_key_complete_arg { 4542 u32 vdev_id; 4543 const u8 *macaddr; 4544 u32 key_idx; 4545 u32 key_flags; 4546 u32 status; 4547 }; 4548 4549 struct wmi_peer_assoc_conf_event { 4550 __le32 vdev_id; 4551 struct ath12k_wmi_mac_addr_params peer_macaddr; 4552 } __packed; 4553 4554 struct wmi_peer_assoc_conf_arg { 4555 u32 vdev_id; 4556 const u8 *macaddr; 4557 }; 4558 4559 struct wmi_fils_discovery_event { 4560 __le32 vdev_id; 4561 __le32 fils_tt; 4562 __le32 tbtt; 4563 } __packed; 4564 4565 struct wmi_probe_resp_tx_status_event { 4566 __le32 vdev_id; 4567 __le32 tx_status; 4568 } __packed; 4569 4570 struct wmi_pdev_ctl_failsafe_chk_event { 4571 __le32 pdev_id; 4572 __le32 ctl_failsafe_status; 4573 } __packed; 4574 4575 struct ath12k_wmi_pdev_csa_event { 4576 __le32 pdev_id; 4577 __le32 current_switch_count; 4578 __le32 num_vdevs; 4579 } __packed; 4580 4581 struct ath12k_wmi_pdev_radar_event { 4582 __le32 pdev_id; 4583 __le32 detection_mode; 4584 __le32 chan_freq; 4585 __le32 chan_width; 4586 __le32 detector_id; 4587 __le32 segment_id; 4588 __le32 timestamp; 4589 __le32 is_chirp; 4590 a_sle32 freq_offset; 4591 a_sle32 sidx; 4592 } __packed; 4593 4594 #define ATH12K_WMI_DCS_INCUMBENT_SIGNAL_INTERFERENCE 0x04 4595 4596 struct ath12k_wmi_dcs_interference_ev_fixed_params { 4597 __le32 interference_type; 4598 __le32 pdev_id; 4599 } __packed; 4600 4601 struct ath12k_wmi_incumbent_signal_interference_params { 4602 __le32 chan_width; 4603 __le32 chan_freq; 4604 __le32 center_freq0; 4605 __le32 center_freq1; 4606 __le32 chan_bw_interference_bitmap; 4607 } __packed; 4608 4609 struct ath12k_wmi_incumbent_signal_interference_arg { 4610 u32 chan_width; 4611 u32 chan_freq; 4612 u32 center_freq0; 4613 u32 center_freq1; 4614 u32 chan_bw_interference_bitmap; 4615 }; 4616 4617 struct ath12k_wmi_intf_arg { 4618 u32 interference_type; 4619 u32 pdev_id; 4620 }; 4621 4622 enum ath12k_wmi_dcs_interference_chan_segment { 4623 /* 4624 * Firmware reports interference bitmap in primary-based order. 4625 * Bit 0 is the primary 20 MHz, bit 1 is the adjacent 20 MHz within 4626 * the primary 40 MHz. Bits 2-3 cover the secondary 40 MHz, bits 4-7 4627 * cover the secondary 80 MHz, and bits 8-15 cover the secondary 160 MHz. 4628 */ 4629 ATH12K_WMI_DCS_SEG_PRI20 = 0x1, 4630 ATH12K_WMI_DCS_SEG_SEC20 = 0x2, 4631 ATH12K_WMI_DCS_SEG_SEC40_LOW = 0x4, 4632 ATH12K_WMI_DCS_SEG_SEC40_UP = 0x8, 4633 ATH12K_WMI_DCS_SEG_SEC40 = 0xC, 4634 ATH12K_WMI_DCS_SEG_SEC80_LOW = 0x10, 4635 ATH12K_WMI_DCS_SEG_SEC80_LOW_UP = 0x20, 4636 ATH12K_WMI_DCS_SEG_SEC80_UP_LOW = 0x40, 4637 ATH12K_WMI_DCS_SEG_SEC80_UP = 0x80, 4638 ATH12K_WMI_DCS_SEG_SEC80 = 0xF0, 4639 ATH12K_WMI_DCS_SEG_SEC160_LOW = 0x0100, 4640 ATH12K_WMI_DCS_SEG_SEC160_LOW_UP = 0x0200, 4641 ATH12K_WMI_DCS_SEG_SEC160_LOW_UP_UP = 0x0400, 4642 ATH12K_WMI_DCS_SEG_SEC160_LOW_UP_UP_UP = 0x0800, 4643 ATH12K_WMI_DCS_SEG_SEC160_UP_LOW_LOW_LOW = 0x1000, 4644 ATH12K_WMI_DCS_SEG_SEC160_UP_LOW_LOW = 0x2000, 4645 ATH12K_WMI_DCS_SEG_SEC160_UP_LOW = 0x4000, 4646 ATH12K_WMI_DCS_SEG_SEC160_UP = 0x8000, 4647 ATH12K_WMI_DCS_SEG_SEC160 = 0xFF00, 4648 }; 4649 4650 struct wmi_pdev_temperature_event { 4651 /* temperature value in Celsius degree */ 4652 a_sle32 temp; 4653 __le32 pdev_id; 4654 } __packed; 4655 4656 #define WMI_RX_STATUS_OK 0x00 4657 #define WMI_RX_STATUS_ERR_CRC 0x01 4658 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4659 #define WMI_RX_STATUS_ERR_MIC 0x10 4660 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4661 4662 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4663 4664 struct ath12k_wmi_mgmt_rx_arg { 4665 u32 chan_freq; 4666 u32 channel; 4667 u32 snr; 4668 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4669 u32 rate; 4670 enum wmi_phy_mode phy_mode; 4671 u32 buf_len; 4672 int status; 4673 u32 flags; 4674 int rssi; 4675 u32 tsf_delta; 4676 u8 pdev_id; 4677 }; 4678 4679 #define ATH_MAX_ANTENNA 4 4680 4681 struct ath12k_wmi_mgmt_rx_params { 4682 __le32 channel; 4683 __le32 snr; 4684 __le32 rate; 4685 __le32 phy_mode; 4686 __le32 buf_len; 4687 __le32 status; 4688 __le32 rssi_ctl[ATH_MAX_ANTENNA]; 4689 __le32 flags; 4690 a_sle32 rssi; 4691 __le32 tsf_delta; 4692 __le32 rx_tsf_l32; 4693 __le32 rx_tsf_u32; 4694 __le32 pdev_id; 4695 __le32 chan_freq; 4696 } __packed; 4697 4698 #define MAX_ANTENNA_EIGHT 8 4699 4700 struct wmi_mgmt_tx_compl_event { 4701 __le32 desc_id; 4702 __le32 status; 4703 __le32 pdev_id; 4704 __le32 ppdu_id; 4705 __le32 ack_rssi; 4706 } __packed; 4707 4708 struct wmi_scan_event { 4709 __le32 event_type; /* %WMI_SCAN_EVENT_ */ 4710 __le32 reason; /* %WMI_SCAN_REASON_ */ 4711 __le32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4712 __le32 scan_req_id; 4713 __le32 scan_id; 4714 __le32 vdev_id; 4715 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4716 * In case of AP it is TSF of the AP vdev 4717 * In case of STA connected state, this is the TSF of the AP 4718 * In case of STA not connected, it will be the free running HW timer 4719 */ 4720 __le32 tsf_timestamp; 4721 } __packed; 4722 4723 enum wmi_peer_sta_kickout_reason { 4724 WMI_PEER_STA_KICKOUT_REASON_UNSPECIFIED = 0, 4725 WMI_PEER_STA_KICKOUT_REASON_XRETRY = 1, 4726 WMI_PEER_STA_KICKOUT_REASON_INACTIVITY = 2, 4727 WMI_PEER_STA_KICKOUT_REASON_IBSS_DISCONNECT = 3, 4728 WMI_PEER_STA_KICKOUT_REASON_TDLS_DISCONNECT = 4, 4729 WMI_PEER_STA_KICKOUT_REASON_SA_QUERY_TIMEOUT = 5, 4730 WMI_PEER_STA_KICKOUT_REASON_ROAMING_EVENT = 6, 4731 WMI_PEER_STA_KICKOUT_REASON_PMF_ERROR = 7, 4732 }; 4733 4734 struct wmi_peer_sta_kickout_arg { 4735 const u8 *mac_addr; 4736 enum wmi_peer_sta_kickout_reason reason; 4737 u32 rssi; 4738 }; 4739 4740 struct wmi_peer_sta_kickout_event { 4741 struct ath12k_wmi_mac_addr_params peer_macaddr; 4742 __le32 reason; 4743 __le32 rssi; 4744 } __packed; 4745 4746 #define WMI_ROAM_REASON_MASK GENMASK(3, 0) 4747 #define WMI_ROAM_SUBNET_STATUS_MASK GENMASK(5, 4) 4748 4749 enum wmi_roam_reason { 4750 WMI_ROAM_REASON_BETTER_AP = 1, 4751 WMI_ROAM_REASON_BEACON_MISS = 2, 4752 WMI_ROAM_REASON_LOW_RSSI = 3, 4753 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4754 WMI_ROAM_REASON_HO_FAILED = 5, 4755 4756 /* keep last */ 4757 WMI_ROAM_REASON_MAX, 4758 }; 4759 4760 struct wmi_roam_event { 4761 __le32 vdev_id; 4762 __le32 reason; 4763 __le32 rssi; 4764 } __packed; 4765 4766 #define WMI_CHAN_INFO_START_RESP 0 4767 #define WMI_CHAN_INFO_END_RESP 1 4768 4769 struct wmi_chan_info_event { 4770 __le32 err_code; 4771 __le32 freq; 4772 __le32 cmd_flags; 4773 __le32 noise_floor; 4774 __le32 rx_clear_count; 4775 __le32 cycle_count; 4776 __le32 chan_tx_pwr_range; 4777 __le32 chan_tx_pwr_tp; 4778 __le32 rx_frame_count; 4779 __le32 my_bss_rx_cycle_count; 4780 __le32 rx_11b_mode_data_duration; 4781 __le32 tx_frame_cnt; 4782 __le32 mac_clk_mhz; 4783 __le32 vdev_id; 4784 } __packed; 4785 4786 struct ath12k_wmi_target_cap_arg { 4787 u32 phy_capability; 4788 u32 max_frag_entry; 4789 u32 num_rf_chains; 4790 u32 ht_cap_info; 4791 u32 vht_cap_info; 4792 u32 vht_supp_mcs; 4793 u32 hw_min_tx_power; 4794 u32 hw_max_tx_power; 4795 u32 sys_cap_info; 4796 u32 min_pkt_size_enable; 4797 u32 max_bcn_ie_size; 4798 u32 max_num_scan_channels; 4799 u32 max_supported_macs; 4800 u32 wmi_fw_sub_feat_caps; 4801 u32 txrx_chainmask; 4802 u32 default_dbs_hw_mode_index; 4803 u32 num_msdu_desc; 4804 }; 4805 4806 enum wmi_vdev_type { 4807 WMI_VDEV_TYPE_UNSPEC = 0, 4808 WMI_VDEV_TYPE_AP = 1, 4809 WMI_VDEV_TYPE_STA = 2, 4810 WMI_VDEV_TYPE_IBSS = 3, 4811 WMI_VDEV_TYPE_MONITOR = 4, 4812 }; 4813 4814 enum wmi_vdev_subtype { 4815 WMI_VDEV_SUBTYPE_NONE, 4816 WMI_VDEV_SUBTYPE_P2P_DEVICE, 4817 WMI_VDEV_SUBTYPE_P2P_CLIENT, 4818 WMI_VDEV_SUBTYPE_P2P_GO, 4819 WMI_VDEV_SUBTYPE_PROXY_STA, 4820 WMI_VDEV_SUBTYPE_MESH_NON_11S, 4821 WMI_VDEV_SUBTYPE_MESH_11S, 4822 }; 4823 4824 enum wmi_sta_powersave_param { 4825 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 4826 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 4827 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 4828 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 4829 WMI_STA_PS_PARAM_UAPSD = 4, 4830 }; 4831 4832 enum wmi_sta_ps_param_uapsd { 4833 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4834 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4835 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4836 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4837 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4838 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4839 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4840 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4841 }; 4842 4843 enum wmi_sta_ps_param_tx_wake_threshold { 4844 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 4845 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 4846 4847 /* Values greater than one indicate that many TX attempts per beacon 4848 * interval before the STA will wake up 4849 */ 4850 }; 4851 4852 /* The maximum number of PS-Poll frames the FW will send in response to 4853 * traffic advertised in TIM before waking up (by sending a null frame with PS 4854 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 4855 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 4856 * parameter is used when the RX wake policy is 4857 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 4858 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 4859 */ 4860 enum wmi_sta_ps_param_pspoll_count { 4861 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 4862 /* Values greater than 0 indicate the maximum number of PS-Poll frames 4863 * FW will send before waking up. 4864 */ 4865 }; 4866 4867 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 4868 enum wmi_ap_ps_param_uapsd { 4869 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4870 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4871 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4872 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4873 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4874 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4875 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4876 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4877 }; 4878 4879 /* U-APSD maximum service period of peer station */ 4880 enum wmi_ap_ps_peer_param_max_sp { 4881 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 4882 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 4883 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 4884 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 4885 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 4886 }; 4887 4888 enum wmi_ap_ps_peer_param { 4889 /** Set uapsd configuration for a given peer. 4890 * 4891 * This include the delivery and trigger enabled state for each AC. 4892 * The host MLME needs to set this based on AP capability and stations 4893 * request Set in the association request received from the station. 4894 * 4895 * Lower 8 bits of the value specify the UAPSD configuration. 4896 * 4897 * (see enum wmi_ap_ps_param_uapsd) 4898 * The default value is 0. 4899 */ 4900 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 4901 4902 /** 4903 * Set the service period for a UAPSD capable station 4904 * 4905 * The service period from wme ie in the (re)assoc request frame. 4906 * 4907 * (see enum wmi_ap_ps_peer_param_max_sp) 4908 */ 4909 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 4910 4911 /** Time in seconds for aging out buffered frames 4912 * for STA in power save 4913 */ 4914 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 4915 4916 /** Specify frame types that are considered SIFS 4917 * RESP trigger frame 4918 */ 4919 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 4920 4921 /** Specifies the trigger state of TID. 4922 * Valid only for UAPSD frame type 4923 */ 4924 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 4925 4926 /* Specifies the WNM sleep state of a STA */ 4927 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 4928 }; 4929 4930 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 4931 4932 #define WMI_MAX_KEY_INDEX 7 4933 #define WMI_MAX_KEY_LEN 32 4934 4935 enum wmi_key_type { 4936 WMI_KEY_PAIRWISE = 0, 4937 WMI_KEY_GROUP = 1, 4938 }; 4939 4940 enum wmi_cipher_type { 4941 WMI_CIPHER_NONE = 0, /* clear key */ 4942 WMI_CIPHER_WEP = 1, 4943 WMI_CIPHER_TKIP = 2, 4944 WMI_CIPHER_AES_OCB = 3, 4945 WMI_CIPHER_AES_CCM = 4, 4946 WMI_CIPHER_WAPI = 5, 4947 WMI_CIPHER_CKIP = 6, 4948 WMI_CIPHER_AES_CMAC = 7, 4949 WMI_CIPHER_ANY = 8, 4950 WMI_CIPHER_AES_GCM = 9, 4951 WMI_CIPHER_AES_GMAC = 10, 4952 }; 4953 4954 /* Value to disable fixed rate setting */ 4955 #define WMI_FIXED_RATE_NONE (0xffff) 4956 4957 #define ATH12K_RC_VERSION_OFFSET 28 4958 #define ATH12K_RC_PREAMBLE_OFFSET 8 4959 #define ATH12K_RC_NSS_OFFSET 5 4960 4961 #define ATH12K_HW_RATE_CODE(rate, nss, preamble) \ 4962 ((1 << ATH12K_RC_VERSION_OFFSET) | \ 4963 ((nss) << ATH12K_RC_NSS_OFFSET) | \ 4964 ((preamble) << ATH12K_RC_PREAMBLE_OFFSET) | \ 4965 (rate)) 4966 4967 /* Preamble types to be used with VDEV fixed rate configuration */ 4968 enum wmi_rate_preamble { 4969 WMI_RATE_PREAMBLE_OFDM, 4970 WMI_RATE_PREAMBLE_CCK, 4971 WMI_RATE_PREAMBLE_HT, 4972 WMI_RATE_PREAMBLE_VHT, 4973 WMI_RATE_PREAMBLE_HE, 4974 WMI_RATE_PREAMBLE_EHT, 4975 }; 4976 4977 /** 4978 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 4979 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 4980 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 4981 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 4982 */ 4983 enum wmi_rtscts_prot_mode { 4984 WMI_RTS_CTS_DISABLED = 0, 4985 WMI_USE_RTS_CTS = 1, 4986 WMI_USE_CTS2SELF = 2, 4987 }; 4988 4989 /** 4990 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 4991 * protection mode. 4992 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 4993 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 4994 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 4995 * but if there's a sw retry, both the rate 4996 * series will use RTS-CTS. 4997 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 4998 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 4999 */ 5000 enum wmi_rtscts_profile { 5001 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 5002 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 5003 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 5004 WMI_RTSCTS_ERP = 3, 5005 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 5006 }; 5007 5008 #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr) 5009 5010 enum wmi_sta_ps_param_rx_wake_policy { 5011 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 5012 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 5013 }; 5014 5015 /* Do not change existing values! Used by ath12k_frame_mode parameter 5016 * module parameter. 5017 */ 5018 enum ath12k_hw_txrx_mode { 5019 ATH12K_HW_TXRX_RAW = 0, 5020 ATH12K_HW_TXRX_NATIVE_WIFI = 1, 5021 ATH12K_HW_TXRX_ETHERNET = 2, 5022 }; 5023 5024 struct wmi_wmm_params { 5025 __le32 tlv_header; 5026 __le32 cwmin; 5027 __le32 cwmax; 5028 __le32 aifs; 5029 __le32 txoplimit; 5030 __le32 acm; 5031 __le32 no_ack; 5032 } __packed; 5033 5034 struct wmi_wmm_params_arg { 5035 u8 acm; 5036 u8 aifs; 5037 u16 cwmin; 5038 u16 cwmax; 5039 u16 txop; 5040 u8 no_ack; 5041 }; 5042 5043 struct wmi_vdev_set_wmm_params_cmd { 5044 __le32 tlv_header; 5045 __le32 vdev_id; 5046 struct wmi_wmm_params wmm_params[4]; 5047 __le32 wmm_param_type; 5048 } __packed; 5049 5050 struct wmi_wmm_params_all_arg { 5051 struct wmi_wmm_params_arg ac_be; 5052 struct wmi_wmm_params_arg ac_bk; 5053 struct wmi_wmm_params_arg ac_vi; 5054 struct wmi_wmm_params_arg ac_vo; 5055 }; 5056 5057 #define ATH12K_TWT_DEF_STA_CONG_TIMER_MS 5000 5058 #define ATH12K_TWT_DEF_DEFAULT_SLOT_SIZE 10 5059 #define ATH12K_TWT_DEF_CONGESTION_THRESH_SETUP 50 5060 #define ATH12K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 5061 #define ATH12K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 5062 #define ATH12K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 5063 #define ATH12K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 5064 #define ATH12K_TWT_DEF_MIN_NO_STA_SETUP 10 5065 #define ATH12K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 5066 #define ATH12K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 5067 #define ATH12K_TWT_DEF_MIN_NO_TWT_SLOTS 2 5068 #define ATH12K_TWT_DEF_MAX_NO_STA_TWT 500 5069 #define ATH12K_TWT_DEF_MODE_CHECK_INTERVAL 10000 5070 #define ATH12K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 5071 #define ATH12K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 5072 5073 struct wmi_twt_enable_params_cmd { 5074 __le32 tlv_header; 5075 __le32 pdev_id; 5076 __le32 sta_cong_timer_ms; 5077 __le32 mbss_support; 5078 __le32 default_slot_size; 5079 __le32 congestion_thresh_setup; 5080 __le32 congestion_thresh_teardown; 5081 __le32 congestion_thresh_critical; 5082 __le32 interference_thresh_teardown; 5083 __le32 interference_thresh_setup; 5084 __le32 min_no_sta_setup; 5085 __le32 min_no_sta_teardown; 5086 __le32 no_of_bcast_mcast_slots; 5087 __le32 min_no_twt_slots; 5088 __le32 max_no_sta_twt; 5089 __le32 mode_check_interval; 5090 __le32 add_sta_slot_interval; 5091 __le32 remove_sta_slot_interval; 5092 } __packed; 5093 5094 struct wmi_twt_disable_params_cmd { 5095 __le32 tlv_header; 5096 __le32 pdev_id; 5097 } __packed; 5098 5099 struct wmi_obss_spatial_reuse_params_cmd { 5100 __le32 tlv_header; 5101 __le32 pdev_id; 5102 __le32 enable; 5103 a_sle32 obss_min; 5104 a_sle32 obss_max; 5105 __le32 vdev_id; 5106 } __packed; 5107 5108 struct wmi_pdev_obss_pd_bitmap_cmd { 5109 __le32 tlv_header; 5110 __le32 pdev_id; 5111 __le32 bitmap[2]; 5112 } __packed; 5113 5114 #define ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5115 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5116 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION 1 5117 5118 #define ATH12K_BSS_COLOR_STA_PERIODS 10000 5119 #define ATH12K_BSS_COLOR_AP_PERIODS 5000 5120 5121 /** 5122 * enum wmi_bss_color_collision - Event types for BSS color collision handling 5123 * @WMI_BSS_COLOR_COLLISION_DISABLE: Indicates that BSS color collision detection 5124 * is disabled. 5125 * @WMI_BSS_COLOR_COLLISION_DETECTION: Event triggered when a BSS color collision 5126 * is detected. 5127 * @WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY: Event indicating that the timer for waiting 5128 * on a free BSS color slot has expired. 5129 * @WMI_BSS_COLOR_FREE_SLOT_AVAILABLE: Event indicating that a free BSS color slot 5130 * has become available. 5131 */ 5132 enum wmi_bss_color_collision { 5133 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5134 WMI_BSS_COLOR_COLLISION_DETECTION, 5135 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5136 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5137 }; 5138 5139 struct wmi_obss_color_collision_cfg_params_cmd { 5140 __le32 tlv_header; 5141 __le32 vdev_id; 5142 __le32 flags; 5143 __le32 evt_type; 5144 __le32 current_bss_color; 5145 __le32 detection_period_ms; 5146 __le32 scan_period_ms; 5147 __le32 free_slot_expiry_time_ms; 5148 } __packed; 5149 5150 struct wmi_bss_color_change_enable_params_cmd { 5151 __le32 tlv_header; 5152 __le32 vdev_id; 5153 __le32 enable; 5154 } __packed; 5155 5156 struct wmi_obss_color_collision_event { 5157 __le32 vdev_id; 5158 __le32 evt_type; 5159 __le64 obss_color_bitmap; 5160 } __packed; 5161 5162 #define ATH12K_IPV4_TH_SEED_SIZE 5 5163 #define ATH12K_IPV6_TH_SEED_SIZE 11 5164 5165 struct ath12k_wmi_pdev_lro_config_cmd { 5166 __le32 tlv_header; 5167 __le32 lro_enable; 5168 __le32 res; 5169 u32 th_4[ATH12K_IPV4_TH_SEED_SIZE]; 5170 u32 th_6[ATH12K_IPV6_TH_SEED_SIZE]; 5171 __le32 pdev_id; 5172 } __packed; 5173 5174 #define ATH12K_WMI_SPECTRAL_COUNT_DEFAULT 0 5175 #define ATH12K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5176 #define ATH12K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5177 #define ATH12K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5178 #define ATH12K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5179 #define ATH12K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5180 #define ATH12K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5181 #define ATH12K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5182 #define ATH12K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5183 #define ATH12K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5184 #define ATH12K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5185 #define ATH12K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5186 #define ATH12K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5187 #define ATH12K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5188 #define ATH12K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5189 #define ATH12K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5190 #define ATH12K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5191 #define ATH12K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5192 5193 struct ath12k_wmi_vdev_spectral_conf_arg { 5194 u32 vdev_id; 5195 u32 scan_count; 5196 u32 scan_period; 5197 u32 scan_priority; 5198 u32 scan_fft_size; 5199 u32 scan_gc_ena; 5200 u32 scan_restart_ena; 5201 u32 scan_noise_floor_ref; 5202 u32 scan_init_delay; 5203 u32 scan_nb_tone_thr; 5204 u32 scan_str_bin_thr; 5205 u32 scan_wb_rpt_mode; 5206 u32 scan_rssi_rpt_mode; 5207 u32 scan_rssi_thr; 5208 u32 scan_pwr_format; 5209 u32 scan_rpt_mode; 5210 u32 scan_bin_scale; 5211 u32 scan_dbm_adj; 5212 u32 scan_chn_mask; 5213 }; 5214 5215 struct ath12k_wmi_vdev_spectral_conf_cmd { 5216 __le32 tlv_header; 5217 __le32 vdev_id; 5218 __le32 scan_count; 5219 __le32 scan_period; 5220 __le32 scan_priority; 5221 __le32 scan_fft_size; 5222 __le32 scan_gc_ena; 5223 __le32 scan_restart_ena; 5224 __le32 scan_noise_floor_ref; 5225 __le32 scan_init_delay; 5226 __le32 scan_nb_tone_thr; 5227 __le32 scan_str_bin_thr; 5228 __le32 scan_wb_rpt_mode; 5229 __le32 scan_rssi_rpt_mode; 5230 __le32 scan_rssi_thr; 5231 __le32 scan_pwr_format; 5232 __le32 scan_rpt_mode; 5233 __le32 scan_bin_scale; 5234 __le32 scan_dbm_adj; 5235 __le32 scan_chn_mask; 5236 } __packed; 5237 5238 #define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5239 #define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5240 #define ATH12K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5241 #define ATH12K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5242 5243 struct ath12k_wmi_vdev_spectral_enable_cmd { 5244 __le32 tlv_header; 5245 __le32 vdev_id; 5246 __le32 trigger_cmd; 5247 __le32 enable_cmd; 5248 } __packed; 5249 5250 struct ath12k_wmi_pdev_dma_ring_cfg_arg { 5251 u32 tlv_header; 5252 u32 pdev_id; 5253 u32 module_id; 5254 u32 base_paddr_lo; 5255 u32 base_paddr_hi; 5256 u32 head_idx_paddr_lo; 5257 u32 head_idx_paddr_hi; 5258 u32 tail_idx_paddr_lo; 5259 u32 tail_idx_paddr_hi; 5260 u32 num_elems; 5261 u32 buf_size; 5262 u32 num_resp_per_event; 5263 u32 event_timeout_ms; 5264 }; 5265 5266 struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd { 5267 __le32 tlv_header; 5268 __le32 pdev_id; 5269 __le32 module_id; /* see enum wmi_direct_buffer_module */ 5270 __le32 base_paddr_lo; 5271 __le32 base_paddr_hi; 5272 __le32 head_idx_paddr_lo; 5273 __le32 head_idx_paddr_hi; 5274 __le32 tail_idx_paddr_lo; 5275 __le32 tail_idx_paddr_hi; 5276 __le32 num_elems; /* Number of elems in the ring */ 5277 __le32 buf_size; /* size of allocated buffer in bytes */ 5278 5279 /* Number of wmi_dma_buf_release_entry packed together */ 5280 __le32 num_resp_per_event; 5281 5282 /* Target should timeout and send whatever resp 5283 * it has if this time expires, units in milliseconds 5284 */ 5285 __le32 event_timeout_ms; 5286 } __packed; 5287 5288 struct ath12k_wmi_dma_buf_release_fixed_params { 5289 __le32 pdev_id; 5290 __le32 module_id; 5291 __le32 num_buf_release_entry; 5292 __le32 num_meta_data_entry; 5293 } __packed; 5294 5295 struct ath12k_wmi_dma_buf_release_entry_params { 5296 __le32 tlv_header; 5297 __le32 paddr_lo; 5298 5299 /* Bits 11:0: address of data 5300 * Bits 31:12: host context data 5301 */ 5302 __le32 paddr_hi; 5303 } __packed; 5304 5305 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5306 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5307 5308 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5309 5310 struct ath12k_wmi_dma_buf_release_meta_data_params { 5311 __le32 tlv_header; 5312 a_sle32 noise_floor[WMI_MAX_CHAINS]; 5313 __le32 reset_delay; 5314 __le32 freq1; 5315 __le32 freq2; 5316 __le32 ch_width; 5317 } __packed; 5318 5319 enum wmi_fils_discovery_cmd_type { 5320 WMI_FILS_DISCOVERY_CMD, 5321 WMI_UNSOL_BCAST_PROBE_RESP, 5322 }; 5323 5324 struct wmi_fils_discovery_cmd { 5325 __le32 tlv_header; 5326 __le32 vdev_id; 5327 __le32 interval; 5328 __le32 config; /* enum wmi_fils_discovery_cmd_type */ 5329 } __packed; 5330 5331 struct wmi_fils_discovery_tmpl_cmd { 5332 __le32 tlv_header; 5333 __le32 vdev_id; 5334 __le32 buf_len; 5335 } __packed; 5336 5337 struct wmi_probe_tmpl_cmd { 5338 __le32 tlv_header; 5339 __le32 vdev_id; 5340 __le32 buf_len; 5341 } __packed; 5342 5343 #define WMI_MLO_CMD_TIMEOUT_HZ (5 * HZ) 5344 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5345 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5346 5347 struct ath12k_wmi_pdev { 5348 struct ath12k_wmi_base *wmi_ab; 5349 enum ath12k_htc_ep_id eid; 5350 u32 rx_decap_mode; 5351 }; 5352 5353 struct ath12k_hw_mode_freq_range_arg { 5354 u32 low_2ghz_freq; 5355 u32 high_2ghz_freq; 5356 u32 low_5ghz_freq; 5357 u32 high_5ghz_freq; 5358 }; 5359 5360 struct ath12k_svc_ext_mac_phy_info { 5361 enum wmi_host_hw_mode_config_type hw_mode_config_type; 5362 u32 phy_id; 5363 u32 supported_bands; 5364 struct ath12k_hw_mode_freq_range_arg hw_freq_range; 5365 }; 5366 5367 #define ATH12K_MAX_MAC_PHY_CAP 8 5368 5369 struct ath12k_svc_ext_info { 5370 u32 num_hw_modes; 5371 struct ath12k_svc_ext_mac_phy_info mac_phy_info[ATH12K_MAX_MAC_PHY_CAP]; 5372 }; 5373 5374 /** 5375 * enum ath12k_hw_mode - enum for host mode 5376 * @ATH12K_HW_MODE_SMM: Single mac mode 5377 * @ATH12K_HW_MODE_DBS: DBS mode 5378 * @ATH12K_HW_MODE_SBS: SBS mode with either high share or low share 5379 * @ATH12K_HW_MODE_SBS_UPPER_SHARE: Higher 5 GHz shared with 2.4 GHz 5380 * @ATH12K_HW_MODE_SBS_LOWER_SHARE: Lower 5 GHz shared with 2.4 GHz 5381 * @ATH12K_HW_MODE_MAX: Max, used to indicate invalid mode 5382 */ 5383 enum ath12k_hw_mode { 5384 ATH12K_HW_MODE_SMM, 5385 ATH12K_HW_MODE_DBS, 5386 ATH12K_HW_MODE_SBS, 5387 ATH12K_HW_MODE_SBS_UPPER_SHARE, 5388 ATH12K_HW_MODE_SBS_LOWER_SHARE, 5389 ATH12K_HW_MODE_MAX, 5390 }; 5391 5392 struct ath12k_hw_mode_info { 5393 bool support_dbs:1; 5394 bool support_sbs:1; 5395 5396 struct ath12k_hw_mode_freq_range_arg freq_range_caps[ATH12K_HW_MODE_MAX] 5397 [MAX_RADIOS]; 5398 }; 5399 5400 struct ath12k_wmi_base { 5401 struct ath12k_base *ab; 5402 struct ath12k_wmi_pdev wmi[MAX_RADIOS]; 5403 enum ath12k_htc_ep_id wmi_endpoint_id[MAX_RADIOS]; 5404 u32 max_msg_len[MAX_RADIOS]; 5405 5406 struct completion service_ready; 5407 struct completion unified_ready; 5408 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE); 5409 wait_queue_head_t tx_credits_wq; 5410 u32 num_mem_chunks; 5411 u32 rx_decap_mode; 5412 struct ath12k_wmi_host_mem_chunk_arg mem_chunks[WMI_MAX_MEM_REQS]; 5413 5414 enum wmi_host_hw_mode_config_type preferred_hw_mode; 5415 5416 struct ath12k_wmi_target_cap_arg *targ_cap; 5417 5418 struct ath12k_svc_ext_info svc_ext_info; 5419 u32 sbs_lower_band_end_freq; 5420 struct ath12k_hw_mode_info hw_mode_info; 5421 5422 u8 dp_peer_meta_data_ver; 5423 }; 5424 5425 struct wmi_pdev_set_bios_interface_cmd { 5426 __le32 tlv_header; 5427 __le32 pdev_id; 5428 __le32 param_type_id; 5429 __le32 length; 5430 } __packed; 5431 5432 enum wmi_bios_param_type { 5433 WMI_BIOS_PARAM_CCA_THRESHOLD_TYPE = 0, 5434 WMI_BIOS_PARAM_TAS_CONFIG_TYPE = 1, 5435 WMI_BIOS_PARAM_TAS_DATA_TYPE = 2, 5436 5437 /* bandedge control power */ 5438 WMI_BIOS_PARAM_TYPE_BANDEDGE = 3, 5439 5440 WMI_BIOS_PARAM_TYPE_MAX, 5441 }; 5442 5443 struct wmi_pdev_set_bios_sar_table_cmd { 5444 __le32 tlv_header; 5445 __le32 pdev_id; 5446 __le32 sar_len; 5447 __le32 dbs_backoff_len; 5448 } __packed; 5449 5450 struct wmi_pdev_set_bios_geo_table_cmd { 5451 __le32 tlv_header; 5452 __le32 pdev_id; 5453 __le32 geo_len; 5454 } __packed; 5455 5456 #define ATH12K_FW_STATS_BUF_SIZE (1024 * 1024) 5457 5458 enum wmi_sys_cap_info_flags { 5459 WMI_SYS_CAP_INFO_RXTX_LED = BIT(0), 5460 WMI_SYS_CAP_INFO_RFKILL = BIT(1), 5461 }; 5462 5463 #define WMI_RFKILL_CFG_GPIO_PIN_NUM GENMASK(5, 0) 5464 #define WMI_RFKILL_CFG_RADIO_LEVEL BIT(6) 5465 #define WMI_RFKILL_CFG_PIN_AS_GPIO GENMASK(10, 7) 5466 5467 enum wmi_rfkill_enable_radio { 5468 WMI_RFKILL_ENABLE_RADIO_ON = 0, 5469 WMI_RFKILL_ENABLE_RADIO_OFF = 1, 5470 }; 5471 5472 enum wmi_rfkill_radio_state { 5473 WMI_RFKILL_RADIO_STATE_OFF = 1, 5474 WMI_RFKILL_RADIO_STATE_ON = 2, 5475 }; 5476 5477 struct wmi_rfkill_state_change_event { 5478 __le32 gpio_pin_num; 5479 __le32 int_type; 5480 __le32 radio_state; 5481 } __packed; 5482 5483 struct wmi_twt_enable_event { 5484 __le32 pdev_id; 5485 __le32 status; 5486 } __packed; 5487 5488 struct wmi_twt_disable_event { 5489 __le32 pdev_id; 5490 __le32 status; 5491 } __packed; 5492 5493 struct wmi_mlo_setup_cmd { 5494 __le32 tlv_header; 5495 __le32 mld_group_id; 5496 __le32 pdev_id; 5497 } __packed; 5498 5499 struct wmi_mlo_setup_arg { 5500 __le32 group_id; 5501 u8 num_partner_links; 5502 u8 *partner_link_id; 5503 }; 5504 5505 struct wmi_mlo_ready_cmd { 5506 __le32 tlv_header; 5507 __le32 pdev_id; 5508 } __packed; 5509 5510 enum wmi_mlo_tear_down_reason_code_type { 5511 WMI_MLO_TEARDOWN_SSR_REASON, 5512 }; 5513 5514 struct wmi_mlo_teardown_cmd { 5515 __le32 tlv_header; 5516 __le32 pdev_id; 5517 __le32 reason_code; 5518 } __packed; 5519 5520 struct wmi_mlo_setup_complete_event { 5521 __le32 pdev_id; 5522 __le32 status; 5523 } __packed; 5524 5525 struct wmi_mlo_teardown_complete_event { 5526 __le32 pdev_id; 5527 __le32 status; 5528 } __packed; 5529 5530 /* WOW structures */ 5531 enum wmi_wow_wakeup_event { 5532 WOW_BMISS_EVENT = 0, 5533 WOW_BETTER_AP_EVENT, 5534 WOW_DEAUTH_RECVD_EVENT, 5535 WOW_MAGIC_PKT_RECVD_EVENT, 5536 WOW_GTK_ERR_EVENT, 5537 WOW_FOURWAY_HSHAKE_EVENT, 5538 WOW_EAPOL_RECVD_EVENT, 5539 WOW_NLO_DETECTED_EVENT, 5540 WOW_DISASSOC_RECVD_EVENT, 5541 WOW_PATTERN_MATCH_EVENT, 5542 WOW_CSA_IE_EVENT, 5543 WOW_PROBE_REQ_WPS_IE_EVENT, 5544 WOW_AUTH_REQ_EVENT, 5545 WOW_ASSOC_REQ_EVENT, 5546 WOW_HTT_EVENT, 5547 WOW_RA_MATCH_EVENT, 5548 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5549 WOW_IOAC_MAGIC_EVENT, 5550 WOW_IOAC_SHORT_EVENT, 5551 WOW_IOAC_EXTEND_EVENT, 5552 WOW_IOAC_TIMER_EVENT, 5553 WOW_DFS_PHYERR_RADAR_EVENT, 5554 WOW_BEACON_EVENT, 5555 WOW_CLIENT_KICKOUT_EVENT, 5556 WOW_EVENT_MAX, 5557 }; 5558 5559 enum wmi_wow_interface_cfg { 5560 WOW_IFACE_PAUSE_ENABLED, 5561 WOW_IFACE_PAUSE_DISABLED 5562 }; 5563 5564 #define C2S(x) case x: return #x 5565 5566 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5567 { 5568 switch (ev) { 5569 C2S(WOW_BMISS_EVENT); 5570 C2S(WOW_BETTER_AP_EVENT); 5571 C2S(WOW_DEAUTH_RECVD_EVENT); 5572 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5573 C2S(WOW_GTK_ERR_EVENT); 5574 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5575 C2S(WOW_EAPOL_RECVD_EVENT); 5576 C2S(WOW_NLO_DETECTED_EVENT); 5577 C2S(WOW_DISASSOC_RECVD_EVENT); 5578 C2S(WOW_PATTERN_MATCH_EVENT); 5579 C2S(WOW_CSA_IE_EVENT); 5580 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5581 C2S(WOW_AUTH_REQ_EVENT); 5582 C2S(WOW_ASSOC_REQ_EVENT); 5583 C2S(WOW_HTT_EVENT); 5584 C2S(WOW_RA_MATCH_EVENT); 5585 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5586 C2S(WOW_IOAC_MAGIC_EVENT); 5587 C2S(WOW_IOAC_SHORT_EVENT); 5588 C2S(WOW_IOAC_EXTEND_EVENT); 5589 C2S(WOW_IOAC_TIMER_EVENT); 5590 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5591 C2S(WOW_BEACON_EVENT); 5592 C2S(WOW_CLIENT_KICKOUT_EVENT); 5593 C2S(WOW_EVENT_MAX); 5594 default: 5595 return NULL; 5596 } 5597 } 5598 5599 enum wmi_wow_wake_reason { 5600 WOW_REASON_UNSPECIFIED = -1, 5601 WOW_REASON_NLOD = 0, 5602 WOW_REASON_AP_ASSOC_LOST, 5603 WOW_REASON_LOW_RSSI, 5604 WOW_REASON_DEAUTH_RECVD, 5605 WOW_REASON_DISASSOC_RECVD, 5606 WOW_REASON_GTK_HS_ERR, 5607 WOW_REASON_EAP_REQ, 5608 WOW_REASON_FOURWAY_HS_RECV, 5609 WOW_REASON_TIMER_INTR_RECV, 5610 WOW_REASON_PATTERN_MATCH_FOUND, 5611 WOW_REASON_RECV_MAGIC_PATTERN, 5612 WOW_REASON_P2P_DISC, 5613 WOW_REASON_WLAN_HB, 5614 WOW_REASON_CSA_EVENT, 5615 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5616 WOW_REASON_AUTH_REQ_RECV, 5617 WOW_REASON_ASSOC_REQ_RECV, 5618 WOW_REASON_HTT_EVENT, 5619 WOW_REASON_RA_MATCH, 5620 WOW_REASON_HOST_AUTO_SHUTDOWN, 5621 WOW_REASON_IOAC_MAGIC_EVENT, 5622 WOW_REASON_IOAC_SHORT_EVENT, 5623 WOW_REASON_IOAC_EXTEND_EVENT, 5624 WOW_REASON_IOAC_TIMER_EVENT, 5625 WOW_REASON_ROAM_HO, 5626 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5627 WOW_REASON_BEACON_RECV, 5628 WOW_REASON_CLIENT_KICKOUT_EVENT, 5629 WOW_REASON_PAGE_FAULT = 0x3a, 5630 WOW_REASON_DEBUG_TEST = 0xFF, 5631 }; 5632 5633 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5634 { 5635 switch (reason) { 5636 C2S(WOW_REASON_UNSPECIFIED); 5637 C2S(WOW_REASON_NLOD); 5638 C2S(WOW_REASON_AP_ASSOC_LOST); 5639 C2S(WOW_REASON_LOW_RSSI); 5640 C2S(WOW_REASON_DEAUTH_RECVD); 5641 C2S(WOW_REASON_DISASSOC_RECVD); 5642 C2S(WOW_REASON_GTK_HS_ERR); 5643 C2S(WOW_REASON_EAP_REQ); 5644 C2S(WOW_REASON_FOURWAY_HS_RECV); 5645 C2S(WOW_REASON_TIMER_INTR_RECV); 5646 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5647 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5648 C2S(WOW_REASON_P2P_DISC); 5649 C2S(WOW_REASON_WLAN_HB); 5650 C2S(WOW_REASON_CSA_EVENT); 5651 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5652 C2S(WOW_REASON_AUTH_REQ_RECV); 5653 C2S(WOW_REASON_ASSOC_REQ_RECV); 5654 C2S(WOW_REASON_HTT_EVENT); 5655 C2S(WOW_REASON_RA_MATCH); 5656 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5657 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5658 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5659 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5660 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5661 C2S(WOW_REASON_ROAM_HO); 5662 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5663 C2S(WOW_REASON_BEACON_RECV); 5664 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5665 C2S(WOW_REASON_PAGE_FAULT); 5666 C2S(WOW_REASON_DEBUG_TEST); 5667 default: 5668 return NULL; 5669 } 5670 } 5671 5672 #undef C2S 5673 5674 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5675 #define WOW_DEFAULT_BITMASK_SIZE 148 5676 5677 #define WOW_MIN_PATTERN_SIZE 1 5678 #define WOW_MAX_PATTERN_SIZE 148 5679 #define WOW_MAX_PKT_OFFSET 128 5680 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 5681 sizeof(struct rfc1042_hdr)) 5682 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 5683 offsetof(struct ieee80211_hdr_3addr, addr1)) 5684 5685 struct wmi_wow_bitmap_pattern_params { 5686 __le32 tlv_header; 5687 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 5688 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 5689 __le32 pattern_offset; 5690 __le32 pattern_len; 5691 __le32 bitmask_len; 5692 __le32 pattern_id; 5693 } __packed; 5694 5695 struct wmi_wow_add_pattern_cmd { 5696 __le32 tlv_header; 5697 __le32 vdev_id; 5698 __le32 pattern_id; 5699 __le32 pattern_type; 5700 } __packed; 5701 5702 struct wmi_wow_del_pattern_cmd { 5703 __le32 tlv_header; 5704 __le32 vdev_id; 5705 __le32 pattern_id; 5706 __le32 pattern_type; 5707 } __packed; 5708 5709 enum wmi_tlv_pattern_type { 5710 WOW_PATTERN_MIN = 0, 5711 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5712 WOW_IPV4_SYNC_PATTERN, 5713 WOW_IPV6_SYNC_PATTERN, 5714 WOW_WILD_CARD_PATTERN, 5715 WOW_TIMER_PATTERN, 5716 WOW_MAGIC_PATTERN, 5717 WOW_IPV6_RA_PATTERN, 5718 WOW_IOAC_PKT_PATTERN, 5719 WOW_IOAC_TMR_PATTERN, 5720 WOW_PATTERN_MAX 5721 }; 5722 5723 struct wmi_wow_add_del_event_cmd { 5724 __le32 tlv_header; 5725 __le32 vdev_id; 5726 __le32 is_add; 5727 __le32 event_bitmap; 5728 } __packed; 5729 5730 struct wmi_wow_enable_cmd { 5731 __le32 tlv_header; 5732 __le32 enable; 5733 __le32 pause_iface_config; 5734 __le32 flags; 5735 } __packed; 5736 5737 struct wmi_wow_host_wakeup_cmd { 5738 __le32 tlv_header; 5739 __le32 reserved; 5740 } __packed; 5741 5742 struct wmi_wow_ev_param { 5743 __le32 vdev_id; 5744 __le32 flag; 5745 __le32 wake_reason; 5746 __le32 data_len; 5747 } __packed; 5748 5749 struct wmi_wow_ev_pg_fault_param { 5750 __le32 len; 5751 u8 data[]; 5752 } __packed; 5753 5754 struct wmi_wow_ev_arg { 5755 enum wmi_wow_wake_reason wake_reason; 5756 }; 5757 5758 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 5759 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 5760 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 5761 #define WMI_PNO_MAX_NETW_CHANNELS 26 5762 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 5763 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 5764 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 5765 5766 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 5767 #define WMI_PNO_MAX_PB_REQ_SIZE 450 5768 5769 #define WMI_PNO_24GHZ_DEFAULT_CH 1 5770 #define WMI_PNO_5GHZ_DEFAULT_CH 36 5771 5772 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 5773 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 5774 5775 /* SSID broadcast type */ 5776 enum wmi_ssid_bcast_type { 5777 BCAST_UNKNOWN = 0, 5778 BCAST_NORMAL = 1, 5779 BCAST_HIDDEN = 2, 5780 }; 5781 5782 #define WMI_NLO_MAX_SSIDS 16 5783 #define WMI_NLO_MAX_CHAN 48 5784 5785 #define WMI_NLO_CONFIG_STOP BIT(0) 5786 #define WMI_NLO_CONFIG_START BIT(1) 5787 #define WMI_NLO_CONFIG_RESET BIT(2) 5788 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 5789 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 5790 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 5791 5792 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 5793 * Only one of them can be enabled at a given time 5794 */ 5795 #define WMI_NLO_CONFIG_ENLO BIT(7) 5796 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 5797 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 5798 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 5799 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 5800 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 5801 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 5802 5803 struct wmi_nlo_ssid_params { 5804 __le32 valid; 5805 struct ath12k_wmi_ssid_params ssid; 5806 } __packed; 5807 5808 struct wmi_nlo_enc_params { 5809 __le32 valid; 5810 __le32 enc_type; 5811 } __packed; 5812 5813 struct wmi_nlo_auth_params { 5814 __le32 valid; 5815 __le32 auth_type; 5816 } __packed; 5817 5818 struct wmi_nlo_bcast_nw_params { 5819 __le32 valid; 5820 __le32 bcast_nw_type; 5821 } __packed; 5822 5823 struct wmi_nlo_rssi_params { 5824 __le32 valid; 5825 __le32 rssi; 5826 } __packed; 5827 5828 struct nlo_configured_params { 5829 /* TLV tag and len;*/ 5830 __le32 tlv_header; 5831 struct wmi_nlo_ssid_params ssid; 5832 struct wmi_nlo_enc_params enc_type; 5833 struct wmi_nlo_auth_params auth_type; 5834 struct wmi_nlo_rssi_params rssi_cond; 5835 5836 /* indicates if the SSID is hidden or not */ 5837 struct wmi_nlo_bcast_nw_params bcast_nw_type; 5838 } __packed; 5839 5840 struct wmi_network_type_arg { 5841 struct cfg80211_ssid ssid; 5842 u32 authentication; 5843 u32 encryption; 5844 u32 bcast_nw_type; 5845 u8 channel_count; 5846 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 5847 s32 rssi_threshold; 5848 }; 5849 5850 struct wmi_pno_scan_req_arg { 5851 u8 enable; 5852 u8 vdev_id; 5853 u8 uc_networks_count; 5854 struct wmi_network_type_arg a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 5855 u32 fast_scan_period; 5856 u32 slow_scan_period; 5857 u8 fast_scan_max_cycles; 5858 5859 bool do_passive_scan; 5860 5861 u32 delay_start_time; 5862 u32 active_min_time; 5863 u32 active_max_time; 5864 u32 passive_min_time; 5865 u32 passive_max_time; 5866 5867 /* mac address randomization attributes */ 5868 u32 enable_pno_scan_randomization; 5869 u8 mac_addr[ETH_ALEN]; 5870 u8 mac_addr_mask[ETH_ALEN]; 5871 }; 5872 5873 struct wmi_wow_nlo_config_cmd { 5874 __le32 tlv_header; 5875 __le32 flags; 5876 __le32 vdev_id; 5877 __le32 fast_scan_max_cycles; 5878 __le32 active_dwell_time; 5879 __le32 passive_dwell_time; 5880 __le32 probe_bundle_size; 5881 5882 /* ART = IRT */ 5883 __le32 rest_time; 5884 5885 /* max value that can be reached after scan_backoff_multiplier */ 5886 __le32 max_rest_time; 5887 5888 __le32 scan_backoff_multiplier; 5889 __le32 fast_scan_period; 5890 5891 /* specific to windows */ 5892 __le32 slow_scan_period; 5893 5894 __le32 no_of_ssids; 5895 5896 __le32 num_of_channels; 5897 5898 /* NLO scan start delay time in milliseconds */ 5899 __le32 delay_start_time; 5900 5901 /* MAC Address to use in Probe Req as SA */ 5902 struct ath12k_wmi_mac_addr_params mac_addr; 5903 5904 /* Mask on which MAC has to be randomized */ 5905 struct ath12k_wmi_mac_addr_params mac_mask; 5906 5907 /* IE bitmap to use in Probe Req */ 5908 __le32 ie_bitmap[8]; 5909 5910 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 5911 __le32 num_vendor_oui; 5912 5913 /* Number of connected NLO band preferences */ 5914 __le32 num_cnlo_band_pref; 5915 5916 /* The TLVs will follow. 5917 * nlo_configured_params nlo_list[]; 5918 * u32 channel_list[num_of_channels]; 5919 */ 5920 } __packed; 5921 5922 /* Definition of HW data filtering */ 5923 enum hw_data_filter_type { 5924 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5925 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5926 }; 5927 5928 struct wmi_hw_data_filter_cmd { 5929 __le32 tlv_header; 5930 __le32 vdev_id; 5931 __le32 enable; 5932 __le32 hw_filter_bitmap; 5933 } __packed; 5934 5935 struct wmi_hw_data_filter_arg { 5936 u32 vdev_id; 5937 bool enable; 5938 u32 hw_filter_bitmap; 5939 }; 5940 5941 #define WMI_IPV6_UC_TYPE 0 5942 #define WMI_IPV6_AC_TYPE 1 5943 5944 #define WMI_IPV6_MAX_COUNT 16 5945 #define WMI_IPV4_MAX_COUNT 2 5946 5947 struct wmi_arp_ns_offload_arg { 5948 u8 ipv4_addr[WMI_IPV4_MAX_COUNT][4]; 5949 u32 ipv4_count; 5950 u32 ipv6_count; 5951 u8 ipv6_addr[WMI_IPV6_MAX_COUNT][16]; 5952 u8 self_ipv6_addr[WMI_IPV6_MAX_COUNT][16]; 5953 u8 ipv6_type[WMI_IPV6_MAX_COUNT]; 5954 bool ipv6_valid[WMI_IPV6_MAX_COUNT]; 5955 u8 mac_addr[ETH_ALEN]; 5956 }; 5957 5958 #define WMI_MAX_NS_OFFLOADS 2 5959 #define WMI_MAX_ARP_OFFLOADS 2 5960 5961 #define WMI_ARPOL_FLAGS_VALID BIT(0) 5962 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 5963 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 5964 5965 struct wmi_arp_offload_params { 5966 __le32 tlv_header; 5967 __le32 flags; 5968 u8 target_ipaddr[4]; 5969 u8 remote_ipaddr[4]; 5970 struct ath12k_wmi_mac_addr_params target_mac; 5971 } __packed; 5972 5973 #define WMI_NSOL_FLAGS_VALID BIT(0) 5974 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 5975 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 5976 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 5977 5978 #define WMI_NSOL_MAX_TARGET_IPS 2 5979 5980 struct wmi_ns_offload_params { 5981 __le32 tlv_header; 5982 __le32 flags; 5983 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 5984 u8 solicitation_ipaddr[16]; 5985 u8 remote_ipaddr[16]; 5986 struct ath12k_wmi_mac_addr_params target_mac; 5987 } __packed; 5988 5989 struct wmi_set_arp_ns_offload_cmd { 5990 __le32 tlv_header; 5991 __le32 flags; 5992 __le32 vdev_id; 5993 __le32 num_ns_ext_tuples; 5994 /* The TLVs follow: 5995 * wmi_ns_offload_params ns[WMI_MAX_NS_OFFLOADS]; 5996 * wmi_arp_offload_params arp[WMI_MAX_ARP_OFFLOADS]; 5997 * wmi_ns_offload_params ns_ext[num_ns_ext_tuples]; 5998 */ 5999 } __packed; 6000 6001 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 6002 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 6003 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 6004 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 6005 6006 #define GTK_OFFLOAD_KEK_BYTES 16 6007 #define GTK_OFFLOAD_KCK_BYTES 16 6008 #define GTK_REPLAY_COUNTER_BYTES 8 6009 #define WMI_MAX_KEY_LEN 32 6010 #define IGTK_PN_SIZE 6 6011 6012 struct wmi_gtk_offload_status_event { 6013 __le32 vdev_id; 6014 __le32 flags; 6015 __le32 refresh_cnt; 6016 __le64 replay_ctr; 6017 u8 igtk_key_index; 6018 u8 igtk_key_length; 6019 u8 igtk_key_rsc[IGTK_PN_SIZE]; 6020 u8 igtk_key[WMI_MAX_KEY_LEN]; 6021 u8 gtk_key_index; 6022 u8 gtk_key_length; 6023 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 6024 u8 gtk_key[WMI_MAX_KEY_LEN]; 6025 } __packed; 6026 6027 struct wmi_gtk_rekey_offload_cmd { 6028 __le32 tlv_header; 6029 __le32 vdev_id; 6030 __le32 flags; 6031 u8 kek[GTK_OFFLOAD_KEK_BYTES]; 6032 u8 kck[GTK_OFFLOAD_KCK_BYTES]; 6033 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 6034 } __packed; 6035 6036 struct wmi_sta_keepalive_cmd { 6037 __le32 tlv_header; 6038 __le32 vdev_id; 6039 __le32 enabled; 6040 6041 /* WMI_STA_KEEPALIVE_METHOD_ */ 6042 __le32 method; 6043 6044 /* in seconds */ 6045 __le32 interval; 6046 6047 /* following this structure is the TLV for struct 6048 * wmi_sta_keepalive_arp_resp_params 6049 */ 6050 } __packed; 6051 6052 struct wmi_sta_keepalive_arp_resp_params { 6053 __le32 tlv_header; 6054 __le32 src_ip4_addr; 6055 __le32 dest_ip4_addr; 6056 struct ath12k_wmi_mac_addr_params dest_mac_addr; 6057 } __packed; 6058 6059 struct wmi_sta_keepalive_arg { 6060 u32 vdev_id; 6061 u32 enabled; 6062 u32 method; 6063 u32 interval; 6064 u32 src_ip4_addr; 6065 u32 dest_ip4_addr; 6066 const u8 dest_mac_addr[ETH_ALEN]; 6067 }; 6068 6069 enum wmi_sta_keepalive_method { 6070 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 6071 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 6072 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 6073 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 6074 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 6075 }; 6076 6077 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 6078 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 6079 6080 struct wmi_stats_event { 6081 __le32 stats_id; 6082 __le32 num_pdev_stats; 6083 __le32 num_vdev_stats; 6084 __le32 num_peer_stats; 6085 __le32 num_bcnflt_stats; 6086 __le32 num_chan_stats; 6087 __le32 num_mib_stats; 6088 __le32 pdev_id; 6089 __le32 num_bcn_stats; 6090 __le32 num_peer_extd_stats; 6091 __le32 num_peer_extd2_stats; 6092 } __packed; 6093 6094 enum wmi_stats_id { 6095 WMI_REQUEST_PDEV_STAT = BIT(2), 6096 WMI_REQUEST_VDEV_STAT = BIT(3), 6097 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 6098 WMI_REQUEST_BCN_STAT = BIT(11), 6099 }; 6100 6101 struct wmi_request_stats_cmd { 6102 __le32 tlv_header; 6103 __le32 stats_id; 6104 __le32 vdev_id; 6105 struct ath12k_wmi_mac_addr_params peer_macaddr; 6106 __le32 pdev_id; 6107 } __packed; 6108 6109 struct wmi_rssi_stat_params { 6110 __le32 vdev_id; 6111 __le32 rssi_avg_beacon[WMI_MAX_CHAINS]; 6112 __le32 rssi_avg_data[WMI_MAX_CHAINS]; 6113 struct ath12k_wmi_mac_addr_params peer_macaddr; 6114 } __packed; 6115 6116 struct wmi_per_chain_rssi_stat_params { 6117 __le32 num_per_chain_rssi; 6118 } __packed; 6119 6120 #define WLAN_MAX_AC 4 6121 #define MAX_TX_RATE_VALUES 10 6122 6123 struct wmi_vdev_stats_params { 6124 __le32 vdev_id; 6125 __le32 beacon_snr; 6126 __le32 data_snr; 6127 __le32 num_tx_frames[WLAN_MAX_AC]; 6128 __le32 num_rx_frames; 6129 __le32 num_tx_frames_retries[WLAN_MAX_AC]; 6130 __le32 num_tx_frames_failures[WLAN_MAX_AC]; 6131 __le32 num_rts_fail; 6132 __le32 num_rts_success; 6133 __le32 num_rx_err; 6134 __le32 num_rx_discard; 6135 __le32 num_tx_not_acked; 6136 __le32 tx_rate_history[MAX_TX_RATE_VALUES]; 6137 __le32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 6138 } __packed; 6139 6140 struct ath12k_wmi_bcn_stats_params { 6141 __le32 vdev_id; 6142 __le32 tx_bcn_succ_cnt; 6143 __le32 tx_bcn_outage_cnt; 6144 } __packed; 6145 6146 struct ath12k_wmi_pdev_base_stats_params { 6147 a_sle32 chan_nf; 6148 __le32 tx_frame_count; /* Cycles spent transmitting frames */ 6149 __le32 rx_frame_count; /* Cycles spent receiving frames */ 6150 __le32 rx_clear_count; /* Total channel busy time, evidently */ 6151 __le32 cycle_count; /* Total on-channel time */ 6152 __le32 phy_err_count; 6153 __le32 chan_tx_pwr; 6154 } __packed; 6155 6156 struct ath12k_wmi_pdev_tx_stats_params { 6157 a_sle32 comp_queued; 6158 a_sle32 comp_delivered; 6159 a_sle32 msdu_enqued; 6160 a_sle32 mpdu_enqued; 6161 a_sle32 wmm_drop; 6162 a_sle32 local_enqued; 6163 a_sle32 local_freed; 6164 a_sle32 hw_queued; 6165 a_sle32 hw_reaped; 6166 a_sle32 underrun; 6167 a_sle32 tx_abort; 6168 a_sle32 mpdus_requed; 6169 __le32 tx_ko; 6170 __le32 data_rc; 6171 __le32 self_triggers; 6172 __le32 sw_retry_failure; 6173 __le32 illgl_rate_phy_err; 6174 __le32 pdev_cont_xretry; 6175 __le32 pdev_tx_timeout; 6176 __le32 pdev_resets; 6177 __le32 stateless_tid_alloc_failure; 6178 __le32 phy_underrun; 6179 __le32 txop_ovf; 6180 } __packed; 6181 6182 struct ath12k_wmi_pdev_rx_stats_params { 6183 a_sle32 mid_ppdu_route_change; 6184 a_sle32 status_rcvd; 6185 a_sle32 r0_frags; 6186 a_sle32 r1_frags; 6187 a_sle32 r2_frags; 6188 a_sle32 r3_frags; 6189 a_sle32 htt_msdus; 6190 a_sle32 htt_mpdus; 6191 a_sle32 loc_msdus; 6192 a_sle32 loc_mpdus; 6193 a_sle32 oversize_amsdu; 6194 a_sle32 phy_errs; 6195 a_sle32 phy_err_drop; 6196 a_sle32 mpdu_errs; 6197 } __packed; 6198 6199 struct ath12k_wmi_pdev_stats_params { 6200 struct ath12k_wmi_pdev_base_stats_params base; 6201 struct ath12k_wmi_pdev_tx_stats_params tx; 6202 struct ath12k_wmi_pdev_rx_stats_params rx; 6203 } __packed; 6204 6205 struct ath12k_fw_stats_req_params { 6206 u32 stats_id; 6207 u32 vdev_id; 6208 u32 pdev_id; 6209 }; 6210 6211 #define WMI_REQ_CTRL_PATH_PDEV_TX_STAT 1 6212 #define WMI_REQUEST_CTRL_PATH_STAT_GET 1 6213 6214 #define WMI_TPC_CONFIG BIT(1) 6215 #define WMI_TPC_REG_PWR_ALLOWED BIT(2) 6216 #define WMI_TPC_RATES_ARRAY1 BIT(3) 6217 #define WMI_TPC_RATES_ARRAY2 BIT(4) 6218 #define WMI_TPC_RATES_DL_OFDMA_ARRAY BIT(5) 6219 #define WMI_TPC_CTL_PWR_ARRAY BIT(6) 6220 #define WMI_TPC_CONFIG_PARAM 0x1 6221 #define ATH12K_TPC_RATE_ARRAY_MU GENMASK(15, 8) 6222 #define ATH12K_TPC_RATE_ARRAY_SU GENMASK(7, 0) 6223 #define TPC_STATS_REG_PWR_ALLOWED_TYPE 0 6224 6225 enum wmi_halphy_ctrl_path_stats_id { 6226 WMI_HALPHY_PDEV_TX_SU_STATS = 0, 6227 WMI_HALPHY_PDEV_TX_SUTXBF_STATS, 6228 WMI_HALPHY_PDEV_TX_MU_STATS, 6229 WMI_HALPHY_PDEV_TX_MUTXBF_STATS, 6230 WMI_HALPHY_PDEV_TX_STATS_MAX, 6231 }; 6232 6233 enum ath12k_wmi_tpc_stats_rates_array { 6234 ATH12K_TPC_STATS_RATES_ARRAY1, 6235 ATH12K_TPC_STATS_RATES_ARRAY2, 6236 }; 6237 6238 enum ath12k_wmi_tpc_stats_ctl_array { 6239 ATH12K_TPC_STATS_CTL_ARRAY, 6240 ATH12K_TPC_STATS_CTL_160ARRAY, 6241 }; 6242 6243 enum ath12k_wmi_tpc_stats_events { 6244 ATH12K_TPC_STATS_CONFIG_REG_PWR_EVENT, 6245 ATH12K_TPC_STATS_RATES_EVENT1, 6246 ATH12K_TPC_STATS_RATES_EVENT2, 6247 ATH12K_TPC_STATS_CTL_TABLE_EVENT 6248 }; 6249 6250 struct wmi_request_halphy_ctrl_path_stats_cmd_fixed_params { 6251 __le32 tlv_header; 6252 __le32 stats_id_mask; 6253 __le32 request_id; 6254 __le32 action; 6255 __le32 subid; 6256 } __packed; 6257 6258 struct ath12k_wmi_pdev_tpc_stats_event_fixed_params { 6259 __le32 pdev_id; 6260 __le32 end_of_event; 6261 __le32 event_count; 6262 } __packed; 6263 6264 struct wmi_tpc_config_params { 6265 __le32 reg_domain; 6266 __le32 chan_freq; 6267 __le32 phy_mode; 6268 __le32 twice_antenna_reduction; 6269 __le32 twice_max_reg_power; 6270 __le32 twice_antenna_gain; 6271 __le32 power_limit; 6272 __le32 rate_max; 6273 __le32 num_tx_chain; 6274 __le32 ctl; 6275 __le32 flags; 6276 __le32 caps; 6277 } __packed; 6278 6279 struct wmi_max_reg_power_fixed_params { 6280 __le32 reg_power_type; 6281 __le32 reg_array_len; 6282 __le32 d1; 6283 __le32 d2; 6284 __le32 d3; 6285 __le32 d4; 6286 } __packed; 6287 6288 struct wmi_max_reg_power_allowed_arg { 6289 struct wmi_max_reg_power_fixed_params tpc_reg_pwr; 6290 s16 *reg_pwr_array; 6291 }; 6292 6293 struct wmi_tpc_rates_array_fixed_params { 6294 __le32 rate_array_type; 6295 __le32 rate_array_len; 6296 } __packed; 6297 6298 struct wmi_tpc_rates_array_arg { 6299 struct wmi_tpc_rates_array_fixed_params tpc_rates_array; 6300 s16 *rate_array; 6301 }; 6302 6303 struct wmi_tpc_ctl_pwr_fixed_params { 6304 __le32 ctl_array_type; 6305 __le32 ctl_array_len; 6306 __le32 end_of_ctl_pwr; 6307 __le32 ctl_pwr_count; 6308 __le32 d1; 6309 __le32 d2; 6310 __le32 d3; 6311 __le32 d4; 6312 } __packed; 6313 6314 struct wmi_tpc_ctl_pwr_table_arg { 6315 struct wmi_tpc_ctl_pwr_fixed_params tpc_ctl_pwr; 6316 s8 *ctl_pwr_table; 6317 }; 6318 6319 struct wmi_tpc_stats_arg { 6320 u32 pdev_id; 6321 u32 event_count; 6322 u32 end_of_event; 6323 u32 tlvs_rcvd; 6324 struct wmi_max_reg_power_allowed_arg max_reg_allowed_power; 6325 struct wmi_tpc_rates_array_arg rates_array1; 6326 struct wmi_tpc_rates_array_arg rates_array2; 6327 struct wmi_tpc_config_params tpc_config; 6328 struct wmi_tpc_ctl_pwr_table_arg ctl_array; 6329 }; 6330 6331 struct wmi_vdev_ch_power_params { 6332 __le32 tlv_header; 6333 6334 /* Channel center frequency (MHz) */ 6335 __le32 chan_cfreq; 6336 6337 /* Unit: dBm, either PSD/EIRP power for this frequency or 6338 * incremental for non-PSD BW 6339 */ 6340 __le32 tx_power; 6341 } __packed; 6342 6343 struct wmi_vdev_set_tpc_power_cmd { 6344 __le32 tlv_header; 6345 __le32 vdev_id; 6346 6347 /* Value: 0 or 1, is PSD power or not */ 6348 __le32 psd_power; 6349 6350 /* Maximum EIRP power (dBm units), valid only if power is PSD */ 6351 __le32 eirp_power; 6352 6353 /* Type: WMI_6GHZ_REG_TYPE, used for halphy CTL lookup */ 6354 __le32 power_type_6ghz; 6355 6356 /* This fixed_param TLV is followed by the below TLVs: 6357 * num_pwr_levels of wmi_vdev_ch_power_info 6358 * For PSD power, it is the PSD/EIRP power of the frequency (20 MHz chunks). 6359 * For non-PSD power, the power values are for 20, 40, and till 6360 * BSS BW power levels. 6361 * The num_pwr_levels will be checked by sw how many elements present 6362 * in the variable-length array. 6363 */ 6364 } __packed; 6365 6366 #define CRTL_F_DYNC_FORCE_LINK_NUM GENMASK(3, 2) 6367 6368 struct wmi_mlo_link_set_active_cmd { 6369 __le32 tlv_header; 6370 __le32 force_mode; 6371 __le32 reason; 6372 __le32 use_ieee_link_id_bitmap; 6373 struct ath12k_wmi_mac_addr_params ap_mld_mac_addr; 6374 __le32 ctrl_flags; 6375 } __packed; 6376 6377 struct wmi_mlo_set_active_link_number_params { 6378 __le32 tlv_header; 6379 __le32 num_of_link; 6380 __le32 vdev_type; 6381 __le32 vdev_subtype; 6382 __le32 home_freq; 6383 } __packed; 6384 6385 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_1 GENMASK(7, 0) 6386 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_2 GENMASK(15, 8) 6387 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_3 GENMASK(23, 16) 6388 #define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_4 GENMASK(31, 24) 6389 6390 struct wmi_disallowed_mlo_mode_bitmap_params { 6391 __le32 tlv_header; 6392 __le32 disallowed_mode_bitmap; 6393 __le32 ieee_link_id_comb; 6394 } __packed; 6395 6396 enum wmi_mlo_link_force_mode { 6397 WMI_MLO_LINK_FORCE_MODE_ACTIVE = 1, 6398 WMI_MLO_LINK_FORCE_MODE_INACTIVE = 2, 6399 WMI_MLO_LINK_FORCE_MODE_ACTIVE_LINK_NUM = 3, 6400 WMI_MLO_LINK_FORCE_MODE_INACTIVE_LINK_NUM = 4, 6401 WMI_MLO_LINK_FORCE_MODE_NO_FORCE = 5, 6402 WMI_MLO_LINK_FORCE_MODE_ACTIVE_INACTIVE = 6, 6403 WMI_MLO_LINK_FORCE_MODE_NON_FORCE_UPDATE = 7, 6404 }; 6405 6406 enum wmi_mlo_link_force_reason { 6407 WMI_MLO_LINK_FORCE_REASON_NEW_CONNECT = 1, 6408 WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, 6409 WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, 6410 WMI_MLO_LINK_FORCE_REASON_TDLS = 4, 6411 WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, 6412 WMI_MLO_LINK_FORCE_REASON_LINK_DELETE = 6, 6413 WMI_MLO_LINK_FORCE_REASON_SINGLE_LINK_EMLSR_OP = 7, 6414 }; 6415 6416 struct wmi_mlo_link_num_arg { 6417 u32 num_of_link; 6418 u32 vdev_type; 6419 u32 vdev_subtype; 6420 u32 home_freq; 6421 }; 6422 6423 struct wmi_mlo_control_flags_arg { 6424 bool overwrite_force_active_bitmap; 6425 bool overwrite_force_inactive_bitmap; 6426 bool dync_force_link_num; 6427 bool post_re_evaluate; 6428 u8 post_re_evaluate_loops; 6429 bool dont_reschedule_workqueue; 6430 }; 6431 6432 struct wmi_ml_link_force_cmd_arg { 6433 u8 ap_mld_mac_addr[ETH_ALEN]; 6434 u16 ieee_link_id_bitmap; 6435 u16 ieee_link_id_bitmap2; 6436 u8 link_num; 6437 }; 6438 6439 struct wmi_ml_disallow_mode_bmap_arg { 6440 u32 disallowed_mode; 6441 union { 6442 u32 ieee_link_id_comb; 6443 u8 ieee_link_id[4]; 6444 }; 6445 }; 6446 6447 /* maximum size of link number param array 6448 * for MLO link set active command 6449 */ 6450 #define WMI_MLO_LINK_NUM_SZ 2 6451 6452 /* maximum size of vdev bitmap array for 6453 * MLO link set active command 6454 */ 6455 #define WMI_MLO_VDEV_BITMAP_SZ 2 6456 6457 /* Max number of disallowed bitmap combination 6458 * sent to firmware 6459 */ 6460 #define WMI_ML_MAX_DISALLOW_BMAP_COMB 4 6461 6462 struct wmi_mlo_link_set_active_arg { 6463 enum wmi_mlo_link_force_mode force_mode; 6464 enum wmi_mlo_link_force_reason reason; 6465 u32 num_link_entry; 6466 u32 num_vdev_bitmap; 6467 u32 num_inactive_vdev_bitmap; 6468 struct wmi_mlo_link_num_arg link_num[WMI_MLO_LINK_NUM_SZ]; 6469 u32 vdev_bitmap[WMI_MLO_VDEV_BITMAP_SZ]; 6470 u32 inactive_vdev_bitmap[WMI_MLO_VDEV_BITMAP_SZ]; 6471 struct wmi_mlo_control_flags_arg ctrl_flags; 6472 bool use_ieee_link_id; 6473 struct wmi_ml_link_force_cmd_arg force_cmd; 6474 u32 num_disallow_mode_comb; 6475 struct wmi_ml_disallow_mode_bmap_arg disallow_bmap[WMI_ML_MAX_DISALLOW_BMAP_COMB]; 6476 }; 6477 6478 #define ATH12K_MAX_20MHZ_SEGMENTS 16 6479 #define ATH12K_MAX_NUM_ANTENNA 8 6480 #define ATH12K_MAX_NUM_NF_HW_DBM 32 6481 6482 struct ath12k_wmi_rssi_dbm_conv_info_fixed_params { 6483 __le32 pdev_id; 6484 } __packed; 6485 6486 struct ath12k_wmi_rssi_dbm_conv_info_params { 6487 __le32 curr_bw; 6488 __le32 curr_rx_chainmask; 6489 __le32 xbar_config; 6490 a_sle32 xlna_bypass_offset; 6491 a_sle32 xlna_bypass_threshold; 6492 a_sle32 nf_hw_dbm[ATH12K_MAX_NUM_NF_HW_DBM]; 6493 } __packed; 6494 6495 struct ath12k_wmi_rssi_dbm_conv_temp_info_params { 6496 a_sle32 offset; 6497 } __packed; 6498 6499 struct ath12k_wmi_rssi_dbm_conv_param_arg { 6500 u32 curr_bw; 6501 u32 curr_rx_chainmask; 6502 u32 xbar_config; 6503 s32 xlna_bypass_offset; 6504 s32 xlna_bypass_threshold; 6505 s8 nf_hw_dbm[ATH12K_MAX_NUM_ANTENNA][ATH12K_MAX_20MHZ_SEGMENTS]; 6506 }; 6507 6508 struct ath12k_wmi_rssi_dbm_conv_info_arg { 6509 bool temp_offset_present; 6510 s32 temp_offset; 6511 bool nf_dbm_present; 6512 s8 min_nf_dbm; 6513 }; 6514 6515 /* each WMI cmd can hold 58 channel entries at most */ 6516 #define ATH12K_WMI_MAX_NUM_CHAN_PER_CMD 58 6517 6518 #define ATH12K_OBSS_PD_THRESHOLD_IN_DBM BIT(29) 6519 #define ATH12K_OBSS_PD_SRG_EN BIT(30) 6520 #define ATH12K_OBSS_PD_NON_SRG_EN BIT(31) 6521 6522 struct ath12k_wmi_obss_pd_arg { 6523 bool srp_support; 6524 bool srg_enabled; 6525 bool non_srg_enabled; 6526 s8 srg_th; 6527 s8 non_srg_th; 6528 }; 6529 6530 int ath12k_wmi_cmd_send(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb, 6531 u32 cmd_id); 6532 struct sk_buff *ath12k_wmi_alloc_skb(struct ath12k_wmi_base *wmi_sc, u32 len); 6533 int ath12k_wmi_mgmt_send(struct ath12k_link_vif *arvif, u32 buf_id, 6534 struct sk_buff *frame); 6535 int ath12k_wmi_p2p_go_bcn_ie(struct ath12k *ar, u32 vdev_id, 6536 const u8 *p2p_ie); 6537 int ath12k_wmi_bcn_tmpl(struct ath12k_link_vif *arvif, 6538 struct ieee80211_mutable_offsets *offs, 6539 struct sk_buff *bcn, 6540 struct ath12k_wmi_bcn_tmpl_ema_arg *ema_args); 6541 int ath12k_wmi_vdev_down(struct ath12k *ar, u8 vdev_id); 6542 int ath12k_wmi_vdev_up(struct ath12k *ar, struct ath12k_wmi_vdev_up_params *params); 6543 int ath12k_wmi_vdev_stop(struct ath12k *ar, u8 vdev_id); 6544 int ath12k_wmi_vdev_start(struct ath12k *ar, struct wmi_vdev_start_req_arg *arg, 6545 bool restart); 6546 int ath12k_wmi_set_peer_param(struct ath12k *ar, const u8 *peer_addr, 6547 u32 vdev_id, u32 param_id, u32 param_val); 6548 int ath12k_wmi_pdev_set_param(struct ath12k *ar, u32 param_id, 6549 u32 param_value, u8 pdev_id); 6550 int ath12k_wmi_pdev_set_ps_mode(struct ath12k *ar, int vdev_id, u32 enable); 6551 int ath12k_wmi_wait_for_unified_ready(struct ath12k_base *ab); 6552 int ath12k_wmi_cmd_init(struct ath12k_base *ab); 6553 int ath12k_wmi_wait_for_service_ready(struct ath12k_base *ab); 6554 int ath12k_wmi_connect(struct ath12k_base *ab); 6555 int ath12k_wmi_pdev_attach(struct ath12k_base *ab, 6556 u8 pdev_id); 6557 int ath12k_wmi_attach(struct ath12k_base *ab); 6558 void ath12k_wmi_detach(struct ath12k_base *ab); 6559 int ath12k_wmi_vdev_create(struct ath12k *ar, u8 *macaddr, 6560 struct ath12k_wmi_vdev_create_arg *arg); 6561 int ath12k_wmi_send_peer_create_cmd(struct ath12k *ar, 6562 struct ath12k_wmi_peer_create_arg *arg); 6563 int ath12k_wmi_vdev_set_param_cmd(struct ath12k *ar, u32 vdev_id, 6564 u32 param_id, u32 param_value); 6565 6566 int ath12k_wmi_set_sta_ps_param(struct ath12k *ar, u32 vdev_id, 6567 u32 param, u32 param_value); 6568 int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms); 6569 int ath12k_wmi_send_peer_delete_cmd(struct ath12k *ar, 6570 const u8 *peer_addr, u8 vdev_id); 6571 int ath12k_wmi_vdev_delete(struct ath12k *ar, u8 vdev_id); 6572 void ath12k_wmi_start_scan_init(struct ath12k *ar, 6573 struct ath12k_wmi_scan_req_arg *arg); 6574 int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar, 6575 struct ath12k_wmi_scan_req_arg *arg); 6576 int ath12k_wmi_send_scan_stop_cmd(struct ath12k *ar, 6577 struct ath12k_wmi_scan_cancel_arg *arg); 6578 int ath12k_wmi_send_wmm_update_cmd(struct ath12k *ar, u32 vdev_id, 6579 struct wmi_wmm_params_all_arg *param); 6580 int ath12k_wmi_pdev_suspend(struct ath12k *ar, u32 suspend_opt, 6581 u32 pdev_id); 6582 int ath12k_wmi_pdev_resume(struct ath12k *ar, u32 pdev_id); 6583 6584 int ath12k_wmi_send_peer_assoc_cmd(struct ath12k *ar, 6585 struct ath12k_wmi_peer_assoc_arg *arg); 6586 int ath12k_wmi_vdev_install_key(struct ath12k *ar, 6587 struct wmi_vdev_install_key_arg *arg); 6588 int ath12k_wmi_pdev_bss_chan_info_request(struct ath12k *ar, 6589 enum wmi_bss_chan_info_req_type type); 6590 int ath12k_wmi_send_pdev_temperature_cmd(struct ath12k *ar); 6591 int ath12k_wmi_send_peer_flush_tids_cmd(struct ath12k *ar, 6592 u8 peer_addr[ETH_ALEN], 6593 u32 peer_tid_bitmap, 6594 u8 vdev_id); 6595 int ath12k_wmi_send_set_ap_ps_param_cmd(struct ath12k *ar, u8 *peer_addr, 6596 struct ath12k_wmi_ap_ps_arg *arg); 6597 int ath12k_wmi_send_scan_chan_list_cmd(struct ath12k *ar, 6598 struct ath12k_wmi_scan_chan_list_arg *arg); 6599 int ath12k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath12k *ar, 6600 u32 pdev_id); 6601 int ath12k_wmi_addba_clear_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac); 6602 int ath12k_wmi_addba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac, 6603 u32 tid, u32 buf_size); 6604 int ath12k_wmi_addba_set_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac, 6605 u32 tid, u32 status); 6606 int ath12k_wmi_delba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac, 6607 u32 tid, u32 initiator, u32 reason); 6608 int ath12k_wmi_send_bcn_offload_control_cmd(struct ath12k *ar, 6609 u32 vdev_id, u32 bcn_ctrl_op); 6610 int ath12k_wmi_send_init_country_cmd(struct ath12k *ar, 6611 struct ath12k_wmi_init_country_arg *arg); 6612 int 6613 ath12k_wmi_send_set_current_country_cmd(struct ath12k *ar, 6614 struct wmi_set_current_country_arg *arg); 6615 int ath12k_wmi_peer_rx_reorder_queue_setup(struct ath12k *ar, 6616 int vdev_id, const u8 *addr, 6617 dma_addr_t paddr, u8 tid, 6618 u8 ba_window_size_valid, 6619 u32 ba_window_size); 6620 int ath12k_wmi_send_11d_scan_start_cmd(struct ath12k *ar, 6621 struct wmi_11d_scan_start_arg *arg); 6622 int ath12k_wmi_send_11d_scan_stop_cmd(struct ath12k *ar, u32 vdev_id); 6623 int 6624 ath12k_wmi_rx_reord_queue_remove(struct ath12k *ar, 6625 struct ath12k_wmi_rx_reorder_queue_remove_arg *arg); 6626 int ath12k_wmi_send_pdev_set_regdomain(struct ath12k *ar, 6627 struct ath12k_wmi_pdev_set_regdomain_arg *arg); 6628 int ath12k_wmi_simulate_radar(struct ath12k *ar); 6629 int ath12k_wmi_send_twt_enable_cmd(struct ath12k *ar, u32 pdev_id); 6630 int ath12k_wmi_send_twt_disable_cmd(struct ath12k *ar, u32 pdev_id); 6631 int ath12k_wmi_send_obss_spr_cmd(struct ath12k *ar, u32 vdev_id, 6632 struct ieee80211_he_obss_pd *he_obss_pd); 6633 u32 ath12k_wmi_build_obss_pd(const struct ath12k_wmi_obss_pd_arg *arg); 6634 int ath12k_wmi_pdev_set_srg_bss_color_bitmap(struct ath12k *ar, u32 pdev_id, 6635 const u32 *bitmap); 6636 int ath12k_wmi_pdev_set_srg_partial_bssid_bitmap(struct ath12k *ar, u32 pdev_id, 6637 const u32 *bitmap); 6638 int ath12k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath12k *ar, u32 pdev_id, 6639 const u32 *bitmap); 6640 int ath12k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath12k *ar, u32 pdev_id, 6641 const u32 *bitmap); 6642 int ath12k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath12k *ar, u32 pdev_id, 6643 const u32 *bitmap); 6644 int ath12k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath12k *ar, u32 pdev_id, 6645 const u32 *bitmap); 6646 int ath12k_wmi_obss_color_cfg_cmd(struct ath12k *ar, u32 vdev_id, 6647 u8 bss_color, u32 period, 6648 bool enable); 6649 int ath12k_wmi_send_bss_color_change_enable_cmd(struct ath12k *ar, u32 vdev_id, 6650 bool enable); 6651 int ath12k_wmi_pdev_lro_cfg(struct ath12k *ar, int pdev_id); 6652 int ath12k_wmi_pdev_dma_ring_cfg(struct ath12k *ar, 6653 struct ath12k_wmi_pdev_dma_ring_cfg_arg *arg); 6654 int ath12k_wmi_vdev_spectral_enable(struct ath12k *ar, u32 vdev_id, 6655 u32 trigger, u32 enable); 6656 int ath12k_wmi_vdev_spectral_conf(struct ath12k *ar, 6657 struct ath12k_wmi_vdev_spectral_conf_arg *arg); 6658 int ath12k_wmi_fils_discovery_tmpl(struct ath12k *ar, u32 vdev_id, 6659 struct sk_buff *tmpl); 6660 int ath12k_wmi_fils_discovery(struct ath12k *ar, u32 vdev_id, u32 interval, 6661 bool unsol_bcast_probe_resp_enabled); 6662 int ath12k_wmi_probe_resp_tmpl(struct ath12k *ar, u32 vdev_id, 6663 struct sk_buff *tmpl); 6664 int ath12k_wmi_set_hw_mode(struct ath12k_base *ab, 6665 enum wmi_host_hw_mode_config_type mode); 6666 int ath12k_wmi_set_bios_cmd(struct ath12k_base *ab, u32 param_id, 6667 const u8 *buf, size_t buf_len); 6668 int ath12k_wmi_set_bios_sar_cmd(struct ath12k_base *ab, const u8 *psar_table); 6669 int ath12k_wmi_set_bios_geo_cmd(struct ath12k_base *ab, const u8 *pgeo_table); 6670 int ath12k_wmi_send_stats_request_cmd(struct ath12k *ar, u32 stats_id, 6671 u32 vdev_id, u32 pdev_id); 6672 __le32 ath12k_wmi_tlv_hdr(u32 cmd, u32 len); 6673 6674 int ath12k_wmi_send_tpc_stats_request(struct ath12k *ar, 6675 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type); 6676 void ath12k_wmi_free_tpc_stats_mem(struct ath12k *ar); 6677 int ath12k_wmi_send_thermal_mitigation_cmd(struct ath12k *ar, 6678 struct ath12k_wmi_thermal_mitigation_arg *arg); 6679 6680 static inline u32 6681 ath12k_wmi_caps_ext_get_pdev_id(const struct ath12k_wmi_caps_ext_params *param) 6682 { 6683 return le32_get_bits(param->pdev_and_hw_link_ids, WMI_CAPS_PARAMS_PDEV_ID); 6684 } 6685 6686 static inline u32 6687 ath12k_wmi_caps_ext_get_hw_link_id(const struct ath12k_wmi_caps_ext_params *param) 6688 { 6689 return le32_get_bits(param->pdev_and_hw_link_ids, WMI_CAPS_PARAMS_HW_LINK_ID); 6690 } 6691 6692 static inline u32 6693 ath12k_wmi_mac_phy_get_pdev_id(const struct ath12k_wmi_mac_phy_caps_params *param) 6694 { 6695 return le32_get_bits(param->pdev_and_hw_link_ids, 6696 WMI_CAPS_PARAMS_PDEV_ID); 6697 } 6698 6699 static inline u32 6700 ath12k_wmi_mac_phy_get_hw_link_id(const struct ath12k_wmi_mac_phy_caps_params *param) 6701 { 6702 return le32_get_bits(param->pdev_and_hw_link_ids, 6703 WMI_CAPS_PARAMS_HW_LINK_ID); 6704 } 6705 6706 int ath12k_wmi_wow_host_wakeup_ind(struct ath12k *ar); 6707 int ath12k_wmi_wow_enable(struct ath12k *ar); 6708 int ath12k_wmi_wow_del_pattern(struct ath12k *ar, u32 vdev_id, u32 pattern_id); 6709 int ath12k_wmi_wow_add_pattern(struct ath12k *ar, u32 vdev_id, u32 pattern_id, 6710 const u8 *pattern, const u8 *mask, 6711 int pattern_len, int pattern_offset); 6712 int ath12k_wmi_wow_add_wakeup_event(struct ath12k *ar, u32 vdev_id, 6713 enum wmi_wow_wakeup_event event, 6714 u32 enable); 6715 int ath12k_wmi_wow_config_pno(struct ath12k *ar, u32 vdev_id, 6716 struct wmi_pno_scan_req_arg *pno_scan); 6717 int ath12k_wmi_hw_data_filter_cmd(struct ath12k *ar, 6718 struct wmi_hw_data_filter_arg *arg); 6719 int ath12k_wmi_arp_ns_offload(struct ath12k *ar, 6720 struct ath12k_link_vif *arvif, 6721 struct wmi_arp_ns_offload_arg *offload, 6722 bool enable); 6723 int ath12k_wmi_gtk_rekey_offload(struct ath12k *ar, 6724 struct ath12k_link_vif *arvif, bool enable); 6725 int ath12k_wmi_gtk_rekey_getinfo(struct ath12k *ar, 6726 struct ath12k_link_vif *arvif); 6727 int ath12k_wmi_sta_keepalive(struct ath12k *ar, 6728 const struct wmi_sta_keepalive_arg *arg); 6729 int ath12k_wmi_mlo_setup(struct ath12k *ar, struct wmi_mlo_setup_arg *mlo_params); 6730 int ath12k_wmi_mlo_ready(struct ath12k *ar); 6731 int ath12k_wmi_mlo_teardown(struct ath12k *ar); 6732 void ath12k_wmi_fw_stats_dump(struct ath12k *ar, 6733 struct ath12k_fw_stats *fw_stats, u32 stats_id, 6734 char *buf); 6735 bool ath12k_wmi_supports_6ghz_cc_ext(struct ath12k *ar); 6736 int ath12k_wmi_send_vdev_set_tpc_power(struct ath12k *ar, 6737 u32 vdev_id, 6738 struct ath12k_reg_tpc_power_info *param); 6739 int ath12k_wmi_send_mlo_link_set_active_cmd(struct ath12k_base *ab, 6740 struct wmi_mlo_link_set_active_arg *param); 6741 int ath12k_wmi_simulate_incumbent_signal_interference(struct ath12k *ar, 6742 u32 chan_bw_interference_bitmap); 6743 int ath12k_wmi_alloc(void); 6744 void ath12k_wmi_free(void); 6745 6746 #endif 6747