18527d81eSPavankumar Nandeshwar // SPDX-License-Identifier: BSD-3-Clause-Clear 28527d81eSPavankumar Nandeshwar /* 38527d81eSPavankumar Nandeshwar * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 48527d81eSPavankumar Nandeshwar * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 58527d81eSPavankumar Nandeshwar */ 68527d81eSPavankumar Nandeshwar 78527d81eSPavankumar Nandeshwar #include "../core.h" 88527d81eSPavankumar Nandeshwar #include "../debug.h" 98527d81eSPavankumar Nandeshwar #include "../dp_tx.h" 108527d81eSPavankumar Nandeshwar #include "../peer.h" 118527d81eSPavankumar Nandeshwar #include "dp_tx.h" 122bb41934SPavankumar Nandeshwar #include "hal_desc.h" 132bb41934SPavankumar Nandeshwar #include "hal.h" 142bb41934SPavankumar Nandeshwar #include "hal_tx.h" 158527d81eSPavankumar Nandeshwar 16972f34d5SPavankumar Nandeshwar static void 17972f34d5SPavankumar Nandeshwar ath12k_wifi7_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, 18a45d0e81SPavankumar Nandeshwar struct hal_tx_msdu_ext_desc *tcl_ext_cmd, 19a45d0e81SPavankumar Nandeshwar struct hal_tx_info *ti) 20a45d0e81SPavankumar Nandeshwar { 21a45d0e81SPavankumar Nandeshwar tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 22a45d0e81SPavankumar Nandeshwar HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 23a45d0e81SPavankumar Nandeshwar tcl_ext_cmd->info1 = le32_encode_bits(0x0, 24a45d0e81SPavankumar Nandeshwar HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 25a45d0e81SPavankumar Nandeshwar le32_encode_bits(ti->data_len, 26a45d0e81SPavankumar Nandeshwar HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 27a45d0e81SPavankumar Nandeshwar 28a45d0e81SPavankumar Nandeshwar tcl_ext_cmd->info1 |= le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 29a45d0e81SPavankumar Nandeshwar le32_encode_bits(ti->encap_type, 30a45d0e81SPavankumar Nandeshwar HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 31a45d0e81SPavankumar Nandeshwar le32_encode_bits(ti->encrypt_type, 32a45d0e81SPavankumar Nandeshwar HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 33a45d0e81SPavankumar Nandeshwar } 34a45d0e81SPavankumar Nandeshwar 35a45d0e81SPavankumar Nandeshwar #define HTT_META_DATA_ALIGNMENT 0x8 36a45d0e81SPavankumar Nandeshwar 37a45d0e81SPavankumar Nandeshwar /* Preparing HTT Metadata when utilized with ext MSDU */ 38972f34d5SPavankumar Nandeshwar static int ath12k_wifi7_dp_prepare_htt_metadata(struct sk_buff *skb) 39a45d0e81SPavankumar Nandeshwar { 40a45d0e81SPavankumar Nandeshwar struct hal_tx_msdu_metadata *desc_ext; 41a45d0e81SPavankumar Nandeshwar u8 htt_desc_size; 42a45d0e81SPavankumar Nandeshwar /* Size rounded of multiple of 8 bytes */ 43a45d0e81SPavankumar Nandeshwar u8 htt_desc_size_aligned; 44a45d0e81SPavankumar Nandeshwar 45a45d0e81SPavankumar Nandeshwar htt_desc_size = sizeof(struct hal_tx_msdu_metadata); 46a45d0e81SPavankumar Nandeshwar htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); 47a45d0e81SPavankumar Nandeshwar 48a45d0e81SPavankumar Nandeshwar desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned); 49a45d0e81SPavankumar Nandeshwar if (!desc_ext) 50a45d0e81SPavankumar Nandeshwar return -ENOMEM; 51a45d0e81SPavankumar Nandeshwar 52a45d0e81SPavankumar Nandeshwar desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) | 53a45d0e81SPavankumar Nandeshwar le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) | 54a45d0e81SPavankumar Nandeshwar le32_encode_bits(1, 55a45d0e81SPavankumar Nandeshwar HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL); 56a45d0e81SPavankumar Nandeshwar 57a45d0e81SPavankumar Nandeshwar return 0; 58a45d0e81SPavankumar Nandeshwar } 59a45d0e81SPavankumar Nandeshwar 60c26f294fSRipan Deuri /* TODO: Remove the export once this file is built with wifi7 ko */ 619e0ee04fSRipan Deuri int ath12k_wifi7_dp_tx(struct ath12k_pdev_dp *dp_pdev, struct ath12k_link_vif *arvif, 62a45d0e81SPavankumar Nandeshwar struct sk_buff *skb, bool gsn_valid, int mcbc_gsn, 63a45d0e81SPavankumar Nandeshwar bool is_mcast) 64a45d0e81SPavankumar Nandeshwar { 659e0ee04fSRipan Deuri struct ath12k_dp *dp = dp_pdev->dp; 66*96b42732SPavankumar Nandeshwar struct ath12k_hal *hal = dp->hal; 679e0ee04fSRipan Deuri struct ath12k_base *ab = dp->ab; 68a45d0e81SPavankumar Nandeshwar struct hal_tx_info ti = {}; 69a45d0e81SPavankumar Nandeshwar struct ath12k_tx_desc_info *tx_desc; 70a45d0e81SPavankumar Nandeshwar struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 71a45d0e81SPavankumar Nandeshwar struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 72a45d0e81SPavankumar Nandeshwar struct hal_tcl_data_cmd *hal_tcl_desc; 73a45d0e81SPavankumar Nandeshwar struct hal_tx_msdu_ext_desc *msg; 74a45d0e81SPavankumar Nandeshwar struct sk_buff *skb_ext_desc = NULL; 75a45d0e81SPavankumar Nandeshwar struct hal_srng *tcl_ring; 76a45d0e81SPavankumar Nandeshwar struct ieee80211_hdr *hdr = (void *)skb->data; 77a45d0e81SPavankumar Nandeshwar struct ath12k_vif *ahvif = arvif->ahvif; 78af66c764SHarsh Kumar Bijlani struct ath12k_dp_vif *dp_vif = &ahvif->dp_vif; 79af66c764SHarsh Kumar Bijlani struct ath12k_dp_link_vif *dp_link_vif; 80a45d0e81SPavankumar Nandeshwar struct dp_tx_ring *tx_ring; 81a45d0e81SPavankumar Nandeshwar u8 pool_id; 82a45d0e81SPavankumar Nandeshwar u8 hal_ring_id; 83a45d0e81SPavankumar Nandeshwar int ret; 84a45d0e81SPavankumar Nandeshwar u8 ring_selector, ring_map = 0; 85a45d0e81SPavankumar Nandeshwar bool tcl_ring_retry; 86a45d0e81SPavankumar Nandeshwar bool msdu_ext_desc = false; 87a45d0e81SPavankumar Nandeshwar bool add_htt_metadata = false; 88*96b42732SPavankumar Nandeshwar u32 iova_mask = dp->hw_params->iova_mask; 89a45d0e81SPavankumar Nandeshwar bool is_diff_encap = false; 90a45d0e81SPavankumar Nandeshwar bool is_null_frame = false; 91a45d0e81SPavankumar Nandeshwar 929e0ee04fSRipan Deuri if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 93a45d0e81SPavankumar Nandeshwar return -ESHUTDOWN; 94a45d0e81SPavankumar Nandeshwar 95a45d0e81SPavankumar Nandeshwar if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 96a45d0e81SPavankumar Nandeshwar !ieee80211_is_data(hdr->frame_control)) 97a45d0e81SPavankumar Nandeshwar return -EOPNOTSUPP; 98a45d0e81SPavankumar Nandeshwar 99a45d0e81SPavankumar Nandeshwar pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 100a45d0e81SPavankumar Nandeshwar 101a45d0e81SPavankumar Nandeshwar /* Let the default ring selection be based on current processor 102a45d0e81SPavankumar Nandeshwar * number, where one of the 3 tcl rings are selected based on 103a45d0e81SPavankumar Nandeshwar * the smp_processor_id(). In case that ring 104a45d0e81SPavankumar Nandeshwar * is full/busy, we resort to other available rings. 105a45d0e81SPavankumar Nandeshwar * If all rings are full, we drop the packet. 106a45d0e81SPavankumar Nandeshwar * TODO: Add throttling logic when all rings are full 107a45d0e81SPavankumar Nandeshwar */ 108*96b42732SPavankumar Nandeshwar ring_selector = dp->hw_params->hw_ops->get_ring_selector(skb); 109a45d0e81SPavankumar Nandeshwar 110a45d0e81SPavankumar Nandeshwar tcl_ring_sel: 111a45d0e81SPavankumar Nandeshwar tcl_ring_retry = false; 112*96b42732SPavankumar Nandeshwar ti.ring_id = ring_selector % dp->hw_params->max_tx_ring; 113a45d0e81SPavankumar Nandeshwar 114a45d0e81SPavankumar Nandeshwar ring_map |= BIT(ti.ring_id); 115*96b42732SPavankumar Nandeshwar ti.rbm_id = hal->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 116a45d0e81SPavankumar Nandeshwar 117a45d0e81SPavankumar Nandeshwar tx_ring = &dp->tx_ring[ti.ring_id]; 118a45d0e81SPavankumar Nandeshwar 119a45d0e81SPavankumar Nandeshwar tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 120a45d0e81SPavankumar Nandeshwar if (!tx_desc) 121a45d0e81SPavankumar Nandeshwar return -ENOMEM; 122a45d0e81SPavankumar Nandeshwar 123af66c764SHarsh Kumar Bijlani dp_link_vif = ath12k_dp_vif_to_dp_link_vif(&ahvif->dp_vif, arvif->link_id); 124a45d0e81SPavankumar Nandeshwar 125af66c764SHarsh Kumar Bijlani ti.bank_id = dp_link_vif->bank_id; 126af66c764SHarsh Kumar Bijlani ti.meta_data_flags = dp_link_vif->tcl_metadata; 127af66c764SHarsh Kumar Bijlani 128af66c764SHarsh Kumar Bijlani if (dp_vif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 1299e0ee04fSRipan Deuri test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags)) { 130a45d0e81SPavankumar Nandeshwar if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 131a45d0e81SPavankumar Nandeshwar ti.encrypt_type = 132a45d0e81SPavankumar Nandeshwar ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 133a45d0e81SPavankumar Nandeshwar 134a45d0e81SPavankumar Nandeshwar if (ieee80211_has_protected(hdr->frame_control)) 135a45d0e81SPavankumar Nandeshwar skb_put(skb, IEEE80211_CCMP_MIC_LEN); 136a45d0e81SPavankumar Nandeshwar } else { 137a45d0e81SPavankumar Nandeshwar ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 138a45d0e81SPavankumar Nandeshwar } 139a45d0e81SPavankumar Nandeshwar 140a45d0e81SPavankumar Nandeshwar msdu_ext_desc = true; 141a45d0e81SPavankumar Nandeshwar } 142a45d0e81SPavankumar Nandeshwar 143a45d0e81SPavankumar Nandeshwar if (gsn_valid) { 144a45d0e81SPavankumar Nandeshwar /* Reset and Initialize meta_data_flags with Global Sequence 145a45d0e81SPavankumar Nandeshwar * Number (GSN) info. 146a45d0e81SPavankumar Nandeshwar */ 147a45d0e81SPavankumar Nandeshwar ti.meta_data_flags = 148a45d0e81SPavankumar Nandeshwar u32_encode_bits(HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM, 149a45d0e81SPavankumar Nandeshwar HTT_TCL_META_DATA_TYPE) | 150a45d0e81SPavankumar Nandeshwar u32_encode_bits(mcbc_gsn, HTT_TCL_META_DATA_GLOBAL_SEQ_NUM); 151a45d0e81SPavankumar Nandeshwar } 152a45d0e81SPavankumar Nandeshwar 153a45d0e81SPavankumar Nandeshwar ti.encap_type = ath12k_dp_tx_get_encap_type(ab, skb); 154af66c764SHarsh Kumar Bijlani ti.addr_search_flags = dp_link_vif->hal_addr_search_flags; 155af66c764SHarsh Kumar Bijlani ti.search_type = dp_link_vif->search_type; 156a45d0e81SPavankumar Nandeshwar ti.type = HAL_TCL_DESC_TYPE_BUFFER; 157a45d0e81SPavankumar Nandeshwar ti.pkt_offset = 0; 158af66c764SHarsh Kumar Bijlani ti.lmac_id = dp_link_vif->lmac_id; 159a45d0e81SPavankumar Nandeshwar 160af66c764SHarsh Kumar Bijlani ti.vdev_id = dp_link_vif->vdev_id; 161a45d0e81SPavankumar Nandeshwar if (gsn_valid) 162a45d0e81SPavankumar Nandeshwar ti.vdev_id += HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID; 163a45d0e81SPavankumar Nandeshwar 164af66c764SHarsh Kumar Bijlani ti.bss_ast_hash = dp_link_vif->ast_hash; 165af66c764SHarsh Kumar Bijlani ti.bss_ast_idx = dp_link_vif->ast_idx; 166a45d0e81SPavankumar Nandeshwar ti.dscp_tid_tbl_idx = 0; 167a45d0e81SPavankumar Nandeshwar 168a45d0e81SPavankumar Nandeshwar if (skb->ip_summed == CHECKSUM_PARTIAL && 169a45d0e81SPavankumar Nandeshwar ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 170a45d0e81SPavankumar Nandeshwar ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 171a45d0e81SPavankumar Nandeshwar u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 172a45d0e81SPavankumar Nandeshwar u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 173a45d0e81SPavankumar Nandeshwar u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 174a45d0e81SPavankumar Nandeshwar u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 175a45d0e81SPavankumar Nandeshwar } 176a45d0e81SPavankumar Nandeshwar 177a45d0e81SPavankumar Nandeshwar ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 178a45d0e81SPavankumar Nandeshwar 179a45d0e81SPavankumar Nandeshwar ti.tid = ath12k_dp_tx_get_tid(skb); 180a45d0e81SPavankumar Nandeshwar 181a45d0e81SPavankumar Nandeshwar switch (ti.encap_type) { 182a45d0e81SPavankumar Nandeshwar case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 183a45d0e81SPavankumar Nandeshwar is_null_frame = ieee80211_is_nullfunc(hdr->frame_control); 184a45d0e81SPavankumar Nandeshwar if (ahvif->vif->offload_flags & IEEE80211_OFFLOAD_ENCAP_ENABLED) { 185a45d0e81SPavankumar Nandeshwar if (skb->protocol == cpu_to_be16(ETH_P_PAE) || is_null_frame) 186a45d0e81SPavankumar Nandeshwar is_diff_encap = true; 187a45d0e81SPavankumar Nandeshwar 188a45d0e81SPavankumar Nandeshwar /* Firmware expects msdu ext descriptor for nwifi/raw packets 189a45d0e81SPavankumar Nandeshwar * received in ETH mode. Without this, observed tx fail for 190a45d0e81SPavankumar Nandeshwar * Multicast packets in ETH mode. 191a45d0e81SPavankumar Nandeshwar */ 192a45d0e81SPavankumar Nandeshwar msdu_ext_desc = true; 193a45d0e81SPavankumar Nandeshwar } else { 194a45d0e81SPavankumar Nandeshwar ath12k_dp_tx_encap_nwifi(skb); 195a45d0e81SPavankumar Nandeshwar } 196a45d0e81SPavankumar Nandeshwar break; 197a45d0e81SPavankumar Nandeshwar case HAL_TCL_ENCAP_TYPE_RAW: 198a45d0e81SPavankumar Nandeshwar if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 199a45d0e81SPavankumar Nandeshwar ret = -EINVAL; 200a45d0e81SPavankumar Nandeshwar goto fail_remove_tx_buf; 201a45d0e81SPavankumar Nandeshwar } 202a45d0e81SPavankumar Nandeshwar break; 203a45d0e81SPavankumar Nandeshwar case HAL_TCL_ENCAP_TYPE_ETHERNET: 204a45d0e81SPavankumar Nandeshwar /* no need to encap */ 205a45d0e81SPavankumar Nandeshwar break; 206a45d0e81SPavankumar Nandeshwar case HAL_TCL_ENCAP_TYPE_802_3: 207a45d0e81SPavankumar Nandeshwar default: 208a45d0e81SPavankumar Nandeshwar /* TODO: Take care of other encap modes as well */ 209a45d0e81SPavankumar Nandeshwar ret = -EINVAL; 210775fe5acSPavankumar Nandeshwar atomic_inc(&dp->device_stats.tx_err.misc_fail); 211a45d0e81SPavankumar Nandeshwar goto fail_remove_tx_buf; 212a45d0e81SPavankumar Nandeshwar } 213a45d0e81SPavankumar Nandeshwar 214a45d0e81SPavankumar Nandeshwar if (iova_mask && 215a45d0e81SPavankumar Nandeshwar (unsigned long)skb->data & iova_mask) { 216*96b42732SPavankumar Nandeshwar ret = ath12k_dp_tx_align_payload(dp, &skb); 217a45d0e81SPavankumar Nandeshwar if (ret) { 218a45d0e81SPavankumar Nandeshwar ath12k_warn(ab, "failed to align TX buffer %d\n", ret); 219a45d0e81SPavankumar Nandeshwar /* don't bail out, give original buffer 220a45d0e81SPavankumar Nandeshwar * a chance even unaligned. 221a45d0e81SPavankumar Nandeshwar */ 222a45d0e81SPavankumar Nandeshwar goto map; 223a45d0e81SPavankumar Nandeshwar } 224a45d0e81SPavankumar Nandeshwar 225a45d0e81SPavankumar Nandeshwar /* hdr is pointing to a wrong place after alignment, 226a45d0e81SPavankumar Nandeshwar * so refresh it for later use. 227a45d0e81SPavankumar Nandeshwar */ 228a45d0e81SPavankumar Nandeshwar hdr = (void *)skb->data; 229a45d0e81SPavankumar Nandeshwar } 230a45d0e81SPavankumar Nandeshwar map: 231*96b42732SPavankumar Nandeshwar ti.paddr = dma_map_single(dp->dev, skb->data, skb->len, DMA_TO_DEVICE); 232*96b42732SPavankumar Nandeshwar if (dma_mapping_error(dp->dev, ti.paddr)) { 233775fe5acSPavankumar Nandeshwar atomic_inc(&dp->device_stats.tx_err.misc_fail); 234a45d0e81SPavankumar Nandeshwar ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 235a45d0e81SPavankumar Nandeshwar ret = -ENOMEM; 236a45d0e81SPavankumar Nandeshwar goto fail_remove_tx_buf; 237a45d0e81SPavankumar Nandeshwar } 238a45d0e81SPavankumar Nandeshwar 2399e0ee04fSRipan Deuri if ((!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags) && 240a45d0e81SPavankumar Nandeshwar !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && 241a45d0e81SPavankumar Nandeshwar !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) && 242a45d0e81SPavankumar Nandeshwar ieee80211_has_protected(hdr->frame_control)) || 243a45d0e81SPavankumar Nandeshwar is_diff_encap) { 244a45d0e81SPavankumar Nandeshwar /* Firmware is not expecting meta data for qos null 245a45d0e81SPavankumar Nandeshwar * nwifi packet received in ETH encap mode. 246a45d0e81SPavankumar Nandeshwar */ 247a45d0e81SPavankumar Nandeshwar if (is_null_frame && msdu_ext_desc) 248a45d0e81SPavankumar Nandeshwar goto skip_htt_meta; 249a45d0e81SPavankumar Nandeshwar 250a45d0e81SPavankumar Nandeshwar /* Add metadata for sw encrypted vlan group traffic 251a45d0e81SPavankumar Nandeshwar * and EAPOL nwifi packet received in ETH encap mode. 252a45d0e81SPavankumar Nandeshwar */ 253a45d0e81SPavankumar Nandeshwar add_htt_metadata = true; 254a45d0e81SPavankumar Nandeshwar msdu_ext_desc = true; 255a45d0e81SPavankumar Nandeshwar ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT; 256a45d0e81SPavankumar Nandeshwar skip_htt_meta: 257a45d0e81SPavankumar Nandeshwar ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW); 258a45d0e81SPavankumar Nandeshwar ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; 259a45d0e81SPavankumar Nandeshwar ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 260a45d0e81SPavankumar Nandeshwar } 261a45d0e81SPavankumar Nandeshwar 262a45d0e81SPavankumar Nandeshwar tx_desc->skb = skb; 263af66c764SHarsh Kumar Bijlani tx_desc->mac_id = dp_link_vif->pdev_idx; 264a45d0e81SPavankumar Nandeshwar ti.desc_id = tx_desc->desc_id; 265a45d0e81SPavankumar Nandeshwar ti.data_len = skb->len; 266a45d0e81SPavankumar Nandeshwar skb_cb->paddr = ti.paddr; 267a45d0e81SPavankumar Nandeshwar 268a45d0e81SPavankumar Nandeshwar if (msdu_ext_desc) { 269a45d0e81SPavankumar Nandeshwar skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 270a45d0e81SPavankumar Nandeshwar if (!skb_ext_desc) { 271a45d0e81SPavankumar Nandeshwar ret = -ENOMEM; 272a45d0e81SPavankumar Nandeshwar goto fail_unmap_dma; 273a45d0e81SPavankumar Nandeshwar } 274a45d0e81SPavankumar Nandeshwar 275a45d0e81SPavankumar Nandeshwar skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 276a45d0e81SPavankumar Nandeshwar memset(skb_ext_desc->data, 0, skb_ext_desc->len); 277a45d0e81SPavankumar Nandeshwar 278a45d0e81SPavankumar Nandeshwar msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 279972f34d5SPavankumar Nandeshwar ath12k_wifi7_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 280a45d0e81SPavankumar Nandeshwar 281a45d0e81SPavankumar Nandeshwar if (add_htt_metadata) { 282972f34d5SPavankumar Nandeshwar ret = ath12k_wifi7_dp_prepare_htt_metadata(skb_ext_desc); 283a45d0e81SPavankumar Nandeshwar if (ret < 0) { 284a45d0e81SPavankumar Nandeshwar ath12k_dbg(ab, ATH12K_DBG_DP_TX, 285a45d0e81SPavankumar Nandeshwar "Failed to add HTT meta data, dropping packet\n"); 286a45d0e81SPavankumar Nandeshwar goto fail_free_ext_skb; 287a45d0e81SPavankumar Nandeshwar } 288a45d0e81SPavankumar Nandeshwar } 289a45d0e81SPavankumar Nandeshwar 290*96b42732SPavankumar Nandeshwar ti.paddr = dma_map_single(dp->dev, skb_ext_desc->data, 291a45d0e81SPavankumar Nandeshwar skb_ext_desc->len, DMA_TO_DEVICE); 292*96b42732SPavankumar Nandeshwar ret = dma_mapping_error(dp->dev, ti.paddr); 293a45d0e81SPavankumar Nandeshwar if (ret) 294a45d0e81SPavankumar Nandeshwar goto fail_free_ext_skb; 295a45d0e81SPavankumar Nandeshwar 296a45d0e81SPavankumar Nandeshwar ti.data_len = skb_ext_desc->len; 297a45d0e81SPavankumar Nandeshwar ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 298a45d0e81SPavankumar Nandeshwar 299a45d0e81SPavankumar Nandeshwar skb_cb->paddr_ext_desc = ti.paddr; 300a45d0e81SPavankumar Nandeshwar tx_desc->skb_ext_desc = skb_ext_desc; 301a45d0e81SPavankumar Nandeshwar } 302a45d0e81SPavankumar Nandeshwar 303a45d0e81SPavankumar Nandeshwar hal_ring_id = tx_ring->tcl_data_ring.ring_id; 304*96b42732SPavankumar Nandeshwar tcl_ring = &hal->srng_list[hal_ring_id]; 305a45d0e81SPavankumar Nandeshwar 306a45d0e81SPavankumar Nandeshwar spin_lock_bh(&tcl_ring->lock); 307a45d0e81SPavankumar Nandeshwar 308a45d0e81SPavankumar Nandeshwar ath12k_hal_srng_access_begin(ab, tcl_ring); 309a45d0e81SPavankumar Nandeshwar 310a45d0e81SPavankumar Nandeshwar hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 311a45d0e81SPavankumar Nandeshwar if (!hal_tcl_desc) { 312a45d0e81SPavankumar Nandeshwar /* NOTE: It is highly unlikely we'll be running out of tcl_ring 313a45d0e81SPavankumar Nandeshwar * desc because the desc is directly enqueued onto hw queue. 314a45d0e81SPavankumar Nandeshwar */ 315a45d0e81SPavankumar Nandeshwar ath12k_hal_srng_access_end(ab, tcl_ring); 316775fe5acSPavankumar Nandeshwar dp->device_stats.tx_err.desc_na[ti.ring_id]++; 317a45d0e81SPavankumar Nandeshwar spin_unlock_bh(&tcl_ring->lock); 318a45d0e81SPavankumar Nandeshwar ret = -ENOMEM; 319a45d0e81SPavankumar Nandeshwar 320a45d0e81SPavankumar Nandeshwar /* Checking for available tcl descriptors in another ring in 321a45d0e81SPavankumar Nandeshwar * case of failure due to full tcl ring now, is better than 322a45d0e81SPavankumar Nandeshwar * checking this ring earlier for each pkt tx. 323a45d0e81SPavankumar Nandeshwar * Restart ring selection if some rings are not checked yet. 324a45d0e81SPavankumar Nandeshwar */ 325*96b42732SPavankumar Nandeshwar if (ring_map != (BIT(dp->hw_params->max_tx_ring) - 1) && 326*96b42732SPavankumar Nandeshwar dp->hw_params->tcl_ring_retry) { 327a45d0e81SPavankumar Nandeshwar tcl_ring_retry = true; 328a45d0e81SPavankumar Nandeshwar ring_selector++; 329a45d0e81SPavankumar Nandeshwar } 330a45d0e81SPavankumar Nandeshwar 331a45d0e81SPavankumar Nandeshwar goto fail_unmap_dma_ext; 332a45d0e81SPavankumar Nandeshwar } 333a45d0e81SPavankumar Nandeshwar 334a45d0e81SPavankumar Nandeshwar spin_lock_bh(&arvif->link_stats_lock); 335a45d0e81SPavankumar Nandeshwar arvif->link_stats.tx_encap_type[ti.encap_type]++; 336a45d0e81SPavankumar Nandeshwar arvif->link_stats.tx_encrypt_type[ti.encrypt_type]++; 337a45d0e81SPavankumar Nandeshwar arvif->link_stats.tx_desc_type[ti.type]++; 338a45d0e81SPavankumar Nandeshwar 339a45d0e81SPavankumar Nandeshwar if (is_mcast) 340a45d0e81SPavankumar Nandeshwar arvif->link_stats.tx_bcast_mcast++; 341a45d0e81SPavankumar Nandeshwar else 342a45d0e81SPavankumar Nandeshwar arvif->link_stats.tx_enqueued++; 343a45d0e81SPavankumar Nandeshwar spin_unlock_bh(&arvif->link_stats_lock); 344a45d0e81SPavankumar Nandeshwar 345775fe5acSPavankumar Nandeshwar dp->device_stats.tx_enqueued[ti.ring_id]++; 346a45d0e81SPavankumar Nandeshwar 347972f34d5SPavankumar Nandeshwar ath12k_wifi7_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 348a45d0e81SPavankumar Nandeshwar 349a45d0e81SPavankumar Nandeshwar ath12k_hal_srng_access_end(ab, tcl_ring); 350a45d0e81SPavankumar Nandeshwar 351a45d0e81SPavankumar Nandeshwar spin_unlock_bh(&tcl_ring->lock); 352a45d0e81SPavankumar Nandeshwar 353a45d0e81SPavankumar Nandeshwar ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 354a45d0e81SPavankumar Nandeshwar skb->data, skb->len); 355a45d0e81SPavankumar Nandeshwar 3569e0ee04fSRipan Deuri atomic_inc(&dp_pdev->num_tx_pending); 357a45d0e81SPavankumar Nandeshwar 358a45d0e81SPavankumar Nandeshwar return 0; 359a45d0e81SPavankumar Nandeshwar 360a45d0e81SPavankumar Nandeshwar fail_unmap_dma_ext: 361a45d0e81SPavankumar Nandeshwar if (skb_cb->paddr_ext_desc) 362*96b42732SPavankumar Nandeshwar dma_unmap_single(dp->dev, skb_cb->paddr_ext_desc, 363a45d0e81SPavankumar Nandeshwar skb_ext_desc->len, 364a45d0e81SPavankumar Nandeshwar DMA_TO_DEVICE); 365a45d0e81SPavankumar Nandeshwar fail_free_ext_skb: 366a45d0e81SPavankumar Nandeshwar kfree_skb(skb_ext_desc); 367a45d0e81SPavankumar Nandeshwar 368a45d0e81SPavankumar Nandeshwar fail_unmap_dma: 369*96b42732SPavankumar Nandeshwar dma_unmap_single(dp->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 370a45d0e81SPavankumar Nandeshwar 371a45d0e81SPavankumar Nandeshwar fail_remove_tx_buf: 372a45d0e81SPavankumar Nandeshwar ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 373a45d0e81SPavankumar Nandeshwar 374a45d0e81SPavankumar Nandeshwar spin_lock_bh(&arvif->link_stats_lock); 375a45d0e81SPavankumar Nandeshwar arvif->link_stats.tx_dropped++; 376a45d0e81SPavankumar Nandeshwar spin_unlock_bh(&arvif->link_stats_lock); 377a45d0e81SPavankumar Nandeshwar 378a45d0e81SPavankumar Nandeshwar if (tcl_ring_retry) 379a45d0e81SPavankumar Nandeshwar goto tcl_ring_sel; 380a45d0e81SPavankumar Nandeshwar 381a45d0e81SPavankumar Nandeshwar return ret; 382a45d0e81SPavankumar Nandeshwar } 383a45d0e81SPavankumar Nandeshwar 3848527d81eSPavankumar Nandeshwar static void 385*96b42732SPavankumar Nandeshwar ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_dp *dp, 3868527d81eSPavankumar Nandeshwar struct ath12k_tx_desc_params *desc_params, 3878527d81eSPavankumar Nandeshwar struct dp_tx_ring *tx_ring, 3888527d81eSPavankumar Nandeshwar struct ath12k_dp_htt_wbm_tx_status *ts, 3898527d81eSPavankumar Nandeshwar u16 peer_id) 3908527d81eSPavankumar Nandeshwar { 391*96b42732SPavankumar Nandeshwar struct ath12k_base *ab = dp->ab; 3928527d81eSPavankumar Nandeshwar struct ieee80211_tx_info *info; 3938527d81eSPavankumar Nandeshwar struct ath12k_link_vif *arvif; 3948527d81eSPavankumar Nandeshwar struct ath12k_skb_cb *skb_cb; 3958527d81eSPavankumar Nandeshwar struct ieee80211_vif *vif; 3968527d81eSPavankumar Nandeshwar struct ath12k_vif *ahvif; 3978527d81eSPavankumar Nandeshwar struct sk_buff *msdu = desc_params->skb; 3988527d81eSPavankumar Nandeshwar s32 noise_floor; 3998527d81eSPavankumar Nandeshwar struct ieee80211_tx_status status = {}; 4009e0b56a3SHarsh Kumar Bijlani struct ath12k_dp_link_peer *peer; 40111157e09SHarsh Kumar Bijlani struct ath12k_pdev_dp *dp_pdev; 402*96b42732SPavankumar Nandeshwar u8 pdev_id; 4038527d81eSPavankumar Nandeshwar 4048527d81eSPavankumar Nandeshwar skb_cb = ATH12K_SKB_CB(msdu); 4058527d81eSPavankumar Nandeshwar info = IEEE80211_SKB_CB(msdu); 4068527d81eSPavankumar Nandeshwar 407*96b42732SPavankumar Nandeshwar pdev_id = ath12k_hw_mac_id_to_pdev_id(dp->hw_params, desc_params->mac_id); 4088527d81eSPavankumar Nandeshwar 409*96b42732SPavankumar Nandeshwar rcu_read_lock(); 410*96b42732SPavankumar Nandeshwar dp_pdev = ath12k_dp_to_pdev_dp(dp, pdev_id); 411*96b42732SPavankumar Nandeshwar if (!dp_pdev) { 412*96b42732SPavankumar Nandeshwar rcu_read_unlock(); 413*96b42732SPavankumar Nandeshwar return; 414*96b42732SPavankumar Nandeshwar } 4158527d81eSPavankumar Nandeshwar 416*96b42732SPavankumar Nandeshwar dp->device_stats.tx_completed[tx_ring->tcl_data_ring_id]++; 417*96b42732SPavankumar Nandeshwar 418*96b42732SPavankumar Nandeshwar if (atomic_dec_and_test(&dp_pdev->num_tx_pending)) 419*96b42732SPavankumar Nandeshwar wake_up(&dp_pdev->tx_empty_waitq); 420*96b42732SPavankumar Nandeshwar 421*96b42732SPavankumar Nandeshwar dma_unmap_single(dp->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 4228527d81eSPavankumar Nandeshwar if (skb_cb->paddr_ext_desc) { 423*96b42732SPavankumar Nandeshwar dma_unmap_single(dp->dev, skb_cb->paddr_ext_desc, 4248527d81eSPavankumar Nandeshwar desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 4258527d81eSPavankumar Nandeshwar dev_kfree_skb_any(desc_params->skb_ext_desc); 4268527d81eSPavankumar Nandeshwar } 4278527d81eSPavankumar Nandeshwar 4288527d81eSPavankumar Nandeshwar vif = skb_cb->vif; 4298527d81eSPavankumar Nandeshwar if (vif) { 4308527d81eSPavankumar Nandeshwar ahvif = ath12k_vif_to_ahvif(vif); 4318527d81eSPavankumar Nandeshwar arvif = rcu_dereference(ahvif->link[skb_cb->link_id]); 4328527d81eSPavankumar Nandeshwar if (arvif) { 4338527d81eSPavankumar Nandeshwar spin_lock_bh(&arvif->link_stats_lock); 4348527d81eSPavankumar Nandeshwar arvif->link_stats.tx_completed++; 4358527d81eSPavankumar Nandeshwar spin_unlock_bh(&arvif->link_stats_lock); 4368527d81eSPavankumar Nandeshwar } 4378527d81eSPavankumar Nandeshwar } 4388527d81eSPavankumar Nandeshwar 4398527d81eSPavankumar Nandeshwar memset(&info->status, 0, sizeof(info->status)); 4408527d81eSPavankumar Nandeshwar 4418527d81eSPavankumar Nandeshwar if (ts->acked) { 4428527d81eSPavankumar Nandeshwar if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 4438527d81eSPavankumar Nandeshwar info->flags |= IEEE80211_TX_STAT_ACK; 4448527d81eSPavankumar Nandeshwar info->status.ack_signal = ts->ack_rssi; 4458527d81eSPavankumar Nandeshwar 4468527d81eSPavankumar Nandeshwar if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 4478527d81eSPavankumar Nandeshwar ab->wmi_ab.svc_map)) { 448*96b42732SPavankumar Nandeshwar struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); 449*96b42732SPavankumar Nandeshwar 4508527d81eSPavankumar Nandeshwar spin_lock_bh(&ar->data_lock); 4518527d81eSPavankumar Nandeshwar noise_floor = ath12k_pdev_get_noise_floor(ar); 4528527d81eSPavankumar Nandeshwar spin_unlock_bh(&ar->data_lock); 4538527d81eSPavankumar Nandeshwar 4548527d81eSPavankumar Nandeshwar info->status.ack_signal += noise_floor; 4558527d81eSPavankumar Nandeshwar } 4568527d81eSPavankumar Nandeshwar 4578527d81eSPavankumar Nandeshwar info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 4588527d81eSPavankumar Nandeshwar } else { 4598527d81eSPavankumar Nandeshwar info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 4608527d81eSPavankumar Nandeshwar } 4618527d81eSPavankumar Nandeshwar } 462*96b42732SPavankumar Nandeshwar 46311157e09SHarsh Kumar Bijlani peer = ath12k_dp_link_peer_find_by_peerid(dp_pdev, peer_id); 4648527d81eSPavankumar Nandeshwar if (!peer || !peer->sta) { 4658527d81eSPavankumar Nandeshwar ath12k_dbg(ab, ATH12K_DBG_DATA, 4668527d81eSPavankumar Nandeshwar "dp_tx: failed to find the peer with peer_id %d\n", peer_id); 467*96b42732SPavankumar Nandeshwar ieee80211_free_txskb(ath12k_pdev_dp_to_hw(dp_pdev), msdu); 4688527d81eSPavankumar Nandeshwar goto exit; 4698527d81eSPavankumar Nandeshwar } else { 4708527d81eSPavankumar Nandeshwar status.sta = peer->sta; 4718527d81eSPavankumar Nandeshwar } 4728527d81eSPavankumar Nandeshwar 4738527d81eSPavankumar Nandeshwar status.info = info; 4748527d81eSPavankumar Nandeshwar status.skb = msdu; 475*96b42732SPavankumar Nandeshwar ieee80211_tx_status_ext(ath12k_pdev_dp_to_hw(dp_pdev), &status); 4768527d81eSPavankumar Nandeshwar exit: 4778527d81eSPavankumar Nandeshwar rcu_read_unlock(); 4788527d81eSPavankumar Nandeshwar } 4798527d81eSPavankumar Nandeshwar 4808527d81eSPavankumar Nandeshwar static void 481*96b42732SPavankumar Nandeshwar ath12k_dp_tx_process_htt_tx_complete(struct ath12k_dp *dp, void *desc, 4828527d81eSPavankumar Nandeshwar struct dp_tx_ring *tx_ring, 4838527d81eSPavankumar Nandeshwar struct ath12k_tx_desc_params *desc_params) 4848527d81eSPavankumar Nandeshwar { 4858527d81eSPavankumar Nandeshwar struct htt_tx_wbm_completion *status_desc; 4868527d81eSPavankumar Nandeshwar struct ath12k_dp_htt_wbm_tx_status ts = {}; 4878527d81eSPavankumar Nandeshwar enum hal_wbm_htt_tx_comp_status wbm_status; 4888527d81eSPavankumar Nandeshwar u16 peer_id; 4898527d81eSPavankumar Nandeshwar 4908527d81eSPavankumar Nandeshwar status_desc = desc; 4918527d81eSPavankumar Nandeshwar 4928527d81eSPavankumar Nandeshwar wbm_status = le32_get_bits(status_desc->info0, 4938527d81eSPavankumar Nandeshwar HTT_TX_WBM_COMP_INFO0_STATUS); 494775fe5acSPavankumar Nandeshwar dp->device_stats.fw_tx_status[wbm_status]++; 4958527d81eSPavankumar Nandeshwar 4968527d81eSPavankumar Nandeshwar switch (wbm_status) { 4978527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 4988527d81eSPavankumar Nandeshwar ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 4998527d81eSPavankumar Nandeshwar ts.ack_rssi = le32_get_bits(status_desc->info2, 5008527d81eSPavankumar Nandeshwar HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 5018527d81eSPavankumar Nandeshwar 5028527d81eSPavankumar Nandeshwar peer_id = le32_get_bits(((struct hal_wbm_completion_ring_tx *)desc)-> 5038527d81eSPavankumar Nandeshwar info3, HAL_WBM_COMPL_TX_INFO3_PEER_ID); 5048527d81eSPavankumar Nandeshwar 505*96b42732SPavankumar Nandeshwar ath12k_dp_tx_htt_tx_complete_buf(dp, desc_params, tx_ring, &ts, peer_id); 5068527d81eSPavankumar Nandeshwar break; 5078527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 5088527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 5098527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 5108527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 5118527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH: 512*96b42732SPavankumar Nandeshwar ath12k_dp_tx_free_txbuf(dp, tx_ring, desc_params); 5138527d81eSPavankumar Nandeshwar break; 5148527d81eSPavankumar Nandeshwar case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 5158527d81eSPavankumar Nandeshwar /* This event is to be handled only when the driver decides to 5168527d81eSPavankumar Nandeshwar * use WDS offload functionality. 5178527d81eSPavankumar Nandeshwar */ 5188527d81eSPavankumar Nandeshwar break; 5198527d81eSPavankumar Nandeshwar default: 520*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Unknown htt wbm tx status %d\n", wbm_status); 5218527d81eSPavankumar Nandeshwar break; 5228527d81eSPavankumar Nandeshwar } 5238527d81eSPavankumar Nandeshwar } 5248527d81eSPavankumar Nandeshwar 5259e0ee04fSRipan Deuri static void ath12k_wifi7_dp_tx_update_txcompl(struct ath12k_pdev_dp *dp_pdev, 5269e0ee04fSRipan Deuri struct hal_tx_status *ts) 5278527d81eSPavankumar Nandeshwar { 5289e0ee04fSRipan Deuri struct ath12k_dp *dp = dp_pdev->dp; 52935fcf4faSHarsh Kumar Bijlani struct ath12k_dp_link_peer *peer; 5308527d81eSPavankumar Nandeshwar struct ath12k_link_sta *arsta; 5318527d81eSPavankumar Nandeshwar struct rate_info txrate = {}; 53235fcf4faSHarsh Kumar Bijlani struct ieee80211_sta *sta; 53335fcf4faSHarsh Kumar Bijlani struct ath12k_sta *ahsta; 5348527d81eSPavankumar Nandeshwar u16 rate, ru_tones; 5358527d81eSPavankumar Nandeshwar u8 rate_idx = 0; 5368527d81eSPavankumar Nandeshwar int ret; 5378527d81eSPavankumar Nandeshwar 53835fcf4faSHarsh Kumar Bijlani peer = ath12k_dp_link_peer_find_by_peerid(dp_pdev, ts->peer_id); 5398527d81eSPavankumar Nandeshwar if (!peer || !peer->sta) { 540*96b42732SPavankumar Nandeshwar ath12k_dbg(dp->ab, ATH12K_DBG_DP_TX, 5418527d81eSPavankumar Nandeshwar "failed to find the peer by id %u\n", ts->peer_id); 5428527d81eSPavankumar Nandeshwar return; 5438527d81eSPavankumar Nandeshwar } 54435fcf4faSHarsh Kumar Bijlani 54535fcf4faSHarsh Kumar Bijlani spin_lock_bh(&dp->dp_lock); 54635fcf4faSHarsh Kumar Bijlani 5478527d81eSPavankumar Nandeshwar sta = peer->sta; 5488527d81eSPavankumar Nandeshwar ahsta = ath12k_sta_to_ahsta(sta); 5498527d81eSPavankumar Nandeshwar arsta = &ahsta->deflink; 5508527d81eSPavankumar Nandeshwar 55135fcf4faSHarsh Kumar Bijlani spin_unlock_bh(&dp->dp_lock); 55235fcf4faSHarsh Kumar Bijlani 5538527d81eSPavankumar Nandeshwar /* This is to prefer choose the real NSS value arsta->last_txrate.nss, 5548527d81eSPavankumar Nandeshwar * if it is invalid, then choose the NSS value while assoc. 5558527d81eSPavankumar Nandeshwar */ 55635fcf4faSHarsh Kumar Bijlani if (peer->last_txrate.nss) 55735fcf4faSHarsh Kumar Bijlani txrate.nss = peer->last_txrate.nss; 5588527d81eSPavankumar Nandeshwar else 5598527d81eSPavankumar Nandeshwar txrate.nss = arsta->peer_nss; 5608527d81eSPavankumar Nandeshwar 5618527d81eSPavankumar Nandeshwar switch (ts->pkt_type) { 5628527d81eSPavankumar Nandeshwar case HAL_TX_RATE_STATS_PKT_TYPE_11A: 5638527d81eSPavankumar Nandeshwar case HAL_TX_RATE_STATS_PKT_TYPE_11B: 5648527d81eSPavankumar Nandeshwar ret = ath12k_mac_hw_ratecode_to_legacy_rate(ts->mcs, 5658527d81eSPavankumar Nandeshwar ts->pkt_type, 5668527d81eSPavankumar Nandeshwar &rate_idx, 5678527d81eSPavankumar Nandeshwar &rate); 5688527d81eSPavankumar Nandeshwar if (ret < 0) { 569*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Invalid tx legacy rate %d\n", ret); 5708527d81eSPavankumar Nandeshwar return; 5718527d81eSPavankumar Nandeshwar } 5728527d81eSPavankumar Nandeshwar 5738527d81eSPavankumar Nandeshwar txrate.legacy = rate; 5748527d81eSPavankumar Nandeshwar break; 5758527d81eSPavankumar Nandeshwar case HAL_TX_RATE_STATS_PKT_TYPE_11N: 5768527d81eSPavankumar Nandeshwar if (ts->mcs > ATH12K_HT_MCS_MAX) { 577*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Invalid HT mcs index %d\n", ts->mcs); 5788527d81eSPavankumar Nandeshwar return; 5798527d81eSPavankumar Nandeshwar } 5808527d81eSPavankumar Nandeshwar 5818527d81eSPavankumar Nandeshwar if (txrate.nss != 0) 5828527d81eSPavankumar Nandeshwar txrate.mcs = ts->mcs + 8 * (txrate.nss - 1); 5838527d81eSPavankumar Nandeshwar 5848527d81eSPavankumar Nandeshwar txrate.flags = RATE_INFO_FLAGS_MCS; 5858527d81eSPavankumar Nandeshwar 5868527d81eSPavankumar Nandeshwar if (ts->sgi) 5878527d81eSPavankumar Nandeshwar txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 5888527d81eSPavankumar Nandeshwar break; 5898527d81eSPavankumar Nandeshwar case HAL_TX_RATE_STATS_PKT_TYPE_11AC: 5908527d81eSPavankumar Nandeshwar if (ts->mcs > ATH12K_VHT_MCS_MAX) { 591*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Invalid VHT mcs index %d\n", ts->mcs); 5928527d81eSPavankumar Nandeshwar return; 5938527d81eSPavankumar Nandeshwar } 5948527d81eSPavankumar Nandeshwar 5958527d81eSPavankumar Nandeshwar txrate.mcs = ts->mcs; 5968527d81eSPavankumar Nandeshwar txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 5978527d81eSPavankumar Nandeshwar 5988527d81eSPavankumar Nandeshwar if (ts->sgi) 5998527d81eSPavankumar Nandeshwar txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 6008527d81eSPavankumar Nandeshwar break; 6018527d81eSPavankumar Nandeshwar case HAL_TX_RATE_STATS_PKT_TYPE_11AX: 6028527d81eSPavankumar Nandeshwar if (ts->mcs > ATH12K_HE_MCS_MAX) { 603*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Invalid HE mcs index %d\n", ts->mcs); 6048527d81eSPavankumar Nandeshwar return; 6058527d81eSPavankumar Nandeshwar } 6068527d81eSPavankumar Nandeshwar 6078527d81eSPavankumar Nandeshwar txrate.mcs = ts->mcs; 6088527d81eSPavankumar Nandeshwar txrate.flags = RATE_INFO_FLAGS_HE_MCS; 6098527d81eSPavankumar Nandeshwar txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(ts->sgi); 6108527d81eSPavankumar Nandeshwar break; 6118527d81eSPavankumar Nandeshwar case HAL_TX_RATE_STATS_PKT_TYPE_11BE: 6128527d81eSPavankumar Nandeshwar if (ts->mcs > ATH12K_EHT_MCS_MAX) { 613*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Invalid EHT mcs index %d\n", ts->mcs); 6148527d81eSPavankumar Nandeshwar return; 6158527d81eSPavankumar Nandeshwar } 6168527d81eSPavankumar Nandeshwar 6178527d81eSPavankumar Nandeshwar txrate.mcs = ts->mcs; 6188527d81eSPavankumar Nandeshwar txrate.flags = RATE_INFO_FLAGS_EHT_MCS; 6198527d81eSPavankumar Nandeshwar txrate.eht_gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(ts->sgi); 6208527d81eSPavankumar Nandeshwar break; 6218527d81eSPavankumar Nandeshwar default: 622*96b42732SPavankumar Nandeshwar ath12k_warn(dp->ab, "Invalid tx pkt type: %d\n", ts->pkt_type); 6238527d81eSPavankumar Nandeshwar return; 6248527d81eSPavankumar Nandeshwar } 6258527d81eSPavankumar Nandeshwar 6268527d81eSPavankumar Nandeshwar txrate.bw = ath12k_mac_bw_to_mac80211_bw(ts->bw); 6278527d81eSPavankumar Nandeshwar 6288527d81eSPavankumar Nandeshwar if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 6298527d81eSPavankumar Nandeshwar txrate.bw = RATE_INFO_BW_HE_RU; 6308527d81eSPavankumar Nandeshwar ru_tones = ath12k_mac_he_convert_tones_to_ru_tones(ts->tones); 6318527d81eSPavankumar Nandeshwar txrate.he_ru_alloc = 6328527d81eSPavankumar Nandeshwar ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 6338527d81eSPavankumar Nandeshwar } 6348527d81eSPavankumar Nandeshwar 6358527d81eSPavankumar Nandeshwar if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11BE) { 6368527d81eSPavankumar Nandeshwar txrate.bw = RATE_INFO_BW_EHT_RU; 6378527d81eSPavankumar Nandeshwar txrate.eht_ru_alloc = 6388527d81eSPavankumar Nandeshwar ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(ts->tones); 6398527d81eSPavankumar Nandeshwar } 6408527d81eSPavankumar Nandeshwar 64135fcf4faSHarsh Kumar Bijlani spin_lock_bh(&dp->dp_lock); 64235fcf4faSHarsh Kumar Bijlani peer->txrate = txrate; 64335fcf4faSHarsh Kumar Bijlani spin_unlock_bh(&dp->dp_lock); 6448527d81eSPavankumar Nandeshwar } 6458527d81eSPavankumar Nandeshwar 6469e0ee04fSRipan Deuri static void ath12k_wifi7_dp_tx_complete_msdu(struct ath12k_pdev_dp *dp_pdev, 6478527d81eSPavankumar Nandeshwar struct ath12k_tx_desc_params *desc_params, 6488527d81eSPavankumar Nandeshwar struct hal_tx_status *ts, 6498527d81eSPavankumar Nandeshwar int ring) 6508527d81eSPavankumar Nandeshwar { 6519e0ee04fSRipan Deuri struct ath12k_dp *dp = dp_pdev->dp; 6529e0ee04fSRipan Deuri struct ath12k_base *ab = dp->ab; 6538527d81eSPavankumar Nandeshwar struct ieee80211_tx_info *info; 6548527d81eSPavankumar Nandeshwar struct ath12k_link_vif *arvif; 6558527d81eSPavankumar Nandeshwar struct ath12k_skb_cb *skb_cb; 6568527d81eSPavankumar Nandeshwar struct ieee80211_vif *vif; 6578527d81eSPavankumar Nandeshwar struct ath12k_vif *ahvif; 6588527d81eSPavankumar Nandeshwar struct sk_buff *msdu = desc_params->skb; 6598527d81eSPavankumar Nandeshwar s32 noise_floor; 6608527d81eSPavankumar Nandeshwar struct ieee80211_tx_status status = {}; 6618527d81eSPavankumar Nandeshwar struct ieee80211_rate_status status_rate = {}; 66235fcf4faSHarsh Kumar Bijlani struct ath12k_dp_link_peer *peer; 6638527d81eSPavankumar Nandeshwar struct rate_info rate; 6648527d81eSPavankumar Nandeshwar 6658527d81eSPavankumar Nandeshwar if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 6668527d81eSPavankumar Nandeshwar /* Must not happen */ 6678527d81eSPavankumar Nandeshwar return; 6688527d81eSPavankumar Nandeshwar } 6698527d81eSPavankumar Nandeshwar 6708527d81eSPavankumar Nandeshwar skb_cb = ATH12K_SKB_CB(msdu); 671775fe5acSPavankumar Nandeshwar dp->device_stats.tx_completed[ring]++; 6728527d81eSPavankumar Nandeshwar 673*96b42732SPavankumar Nandeshwar dma_unmap_single(dp->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 6748527d81eSPavankumar Nandeshwar if (skb_cb->paddr_ext_desc) { 675*96b42732SPavankumar Nandeshwar dma_unmap_single(dp->dev, skb_cb->paddr_ext_desc, 6768527d81eSPavankumar Nandeshwar desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 6778527d81eSPavankumar Nandeshwar dev_kfree_skb_any(desc_params->skb_ext_desc); 6788527d81eSPavankumar Nandeshwar } 6798527d81eSPavankumar Nandeshwar 6808527d81eSPavankumar Nandeshwar rcu_read_lock(); 6818527d81eSPavankumar Nandeshwar 6829e0ee04fSRipan Deuri if (!rcu_dereference(ab->pdevs_active[dp_pdev->mac_id])) { 6839e0ee04fSRipan Deuri ieee80211_free_txskb(ath12k_pdev_dp_to_hw(dp_pdev), msdu); 6848527d81eSPavankumar Nandeshwar goto exit; 6858527d81eSPavankumar Nandeshwar } 6868527d81eSPavankumar Nandeshwar 6878527d81eSPavankumar Nandeshwar if (!skb_cb->vif) { 6889e0ee04fSRipan Deuri ieee80211_free_txskb(ath12k_pdev_dp_to_hw(dp_pdev), msdu); 6898527d81eSPavankumar Nandeshwar goto exit; 6908527d81eSPavankumar Nandeshwar } 6918527d81eSPavankumar Nandeshwar 6928527d81eSPavankumar Nandeshwar vif = skb_cb->vif; 6938527d81eSPavankumar Nandeshwar if (vif) { 6948527d81eSPavankumar Nandeshwar ahvif = ath12k_vif_to_ahvif(vif); 6958527d81eSPavankumar Nandeshwar arvif = rcu_dereference(ahvif->link[skb_cb->link_id]); 6968527d81eSPavankumar Nandeshwar if (arvif) { 6978527d81eSPavankumar Nandeshwar spin_lock_bh(&arvif->link_stats_lock); 6988527d81eSPavankumar Nandeshwar arvif->link_stats.tx_completed++; 6998527d81eSPavankumar Nandeshwar spin_unlock_bh(&arvif->link_stats_lock); 7008527d81eSPavankumar Nandeshwar } 7018527d81eSPavankumar Nandeshwar } 7028527d81eSPavankumar Nandeshwar 7038527d81eSPavankumar Nandeshwar info = IEEE80211_SKB_CB(msdu); 7048527d81eSPavankumar Nandeshwar memset(&info->status, 0, sizeof(info->status)); 7058527d81eSPavankumar Nandeshwar 7068527d81eSPavankumar Nandeshwar /* skip tx rate update from ieee80211_status*/ 7078527d81eSPavankumar Nandeshwar info->status.rates[0].idx = -1; 7088527d81eSPavankumar Nandeshwar 7098527d81eSPavankumar Nandeshwar switch (ts->status) { 7108527d81eSPavankumar Nandeshwar case HAL_WBM_TQM_REL_REASON_FRAME_ACKED: 7118527d81eSPavankumar Nandeshwar if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 7128527d81eSPavankumar Nandeshwar info->flags |= IEEE80211_TX_STAT_ACK; 7138527d81eSPavankumar Nandeshwar info->status.ack_signal = ts->ack_rssi; 7148527d81eSPavankumar Nandeshwar 7158527d81eSPavankumar Nandeshwar if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 7168527d81eSPavankumar Nandeshwar ab->wmi_ab.svc_map)) { 7179e0ee04fSRipan Deuri struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); 7189e0ee04fSRipan Deuri 7198527d81eSPavankumar Nandeshwar spin_lock_bh(&ar->data_lock); 7208527d81eSPavankumar Nandeshwar noise_floor = ath12k_pdev_get_noise_floor(ar); 7218527d81eSPavankumar Nandeshwar spin_unlock_bh(&ar->data_lock); 7228527d81eSPavankumar Nandeshwar 7238527d81eSPavankumar Nandeshwar info->status.ack_signal += noise_floor; 7248527d81eSPavankumar Nandeshwar } 7258527d81eSPavankumar Nandeshwar 7268527d81eSPavankumar Nandeshwar info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 7278527d81eSPavankumar Nandeshwar } 7288527d81eSPavankumar Nandeshwar break; 7298527d81eSPavankumar Nandeshwar case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: 7308527d81eSPavankumar Nandeshwar if (info->flags & IEEE80211_TX_CTL_NO_ACK) { 7318527d81eSPavankumar Nandeshwar info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 7328527d81eSPavankumar Nandeshwar break; 7338527d81eSPavankumar Nandeshwar } 7348527d81eSPavankumar Nandeshwar fallthrough; 7358527d81eSPavankumar Nandeshwar case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: 7368527d81eSPavankumar Nandeshwar case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: 7378527d81eSPavankumar Nandeshwar case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: 7388527d81eSPavankumar Nandeshwar /* The failure status is due to internal firmware tx failure 7398527d81eSPavankumar Nandeshwar * hence drop the frame; do not update the status of frame to 7408527d81eSPavankumar Nandeshwar * the upper layer 7418527d81eSPavankumar Nandeshwar */ 7429e0ee04fSRipan Deuri ieee80211_free_txskb(ath12k_pdev_dp_to_hw(dp_pdev), msdu); 7438527d81eSPavankumar Nandeshwar goto exit; 7448527d81eSPavankumar Nandeshwar default: 7458527d81eSPavankumar Nandeshwar ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", 7468527d81eSPavankumar Nandeshwar ts->status); 7478527d81eSPavankumar Nandeshwar break; 7488527d81eSPavankumar Nandeshwar } 7498527d81eSPavankumar Nandeshwar 7508527d81eSPavankumar Nandeshwar /* NOTE: Tx rate status reporting. Tx completion status does not have 7518527d81eSPavankumar Nandeshwar * necessary information (for example nss) to build the tx rate. 7528527d81eSPavankumar Nandeshwar * Might end up reporting it out-of-band from HTT stats. 7538527d81eSPavankumar Nandeshwar */ 7548527d81eSPavankumar Nandeshwar 7559e0ee04fSRipan Deuri ath12k_wifi7_dp_tx_update_txcompl(dp_pdev, ts); 7568527d81eSPavankumar Nandeshwar 75735fcf4faSHarsh Kumar Bijlani peer = ath12k_dp_link_peer_find_by_peerid(dp_pdev, ts->peer_id); 7588527d81eSPavankumar Nandeshwar if (!peer || !peer->sta) { 7598527d81eSPavankumar Nandeshwar ath12k_err(ab, 7608527d81eSPavankumar Nandeshwar "dp_tx: failed to find the peer with peer_id %d\n", 7618527d81eSPavankumar Nandeshwar ts->peer_id); 7629e0ee04fSRipan Deuri ieee80211_free_txskb(ath12k_pdev_dp_to_hw(dp_pdev), msdu); 7638527d81eSPavankumar Nandeshwar goto exit; 7648527d81eSPavankumar Nandeshwar } 7658527d81eSPavankumar Nandeshwar 7668527d81eSPavankumar Nandeshwar status.sta = peer->sta; 7678527d81eSPavankumar Nandeshwar status.info = info; 7688527d81eSPavankumar Nandeshwar status.skb = msdu; 76935fcf4faSHarsh Kumar Bijlani rate = peer->last_txrate; 7708527d81eSPavankumar Nandeshwar 7718527d81eSPavankumar Nandeshwar status_rate.rate_idx = rate; 7728527d81eSPavankumar Nandeshwar status_rate.try_count = 1; 7738527d81eSPavankumar Nandeshwar 7748527d81eSPavankumar Nandeshwar status.rates = &status_rate; 7758527d81eSPavankumar Nandeshwar status.n_rates = 1; 7769e0ee04fSRipan Deuri ieee80211_tx_status_ext(ath12k_pdev_dp_to_hw(dp_pdev), &status); 7778527d81eSPavankumar Nandeshwar 7788527d81eSPavankumar Nandeshwar exit: 7798527d81eSPavankumar Nandeshwar rcu_read_unlock(); 7808527d81eSPavankumar Nandeshwar } 7818527d81eSPavankumar Nandeshwar 782972f34d5SPavankumar Nandeshwar static void 783*96b42732SPavankumar Nandeshwar ath12k_wifi7_dp_tx_status_parse(struct ath12k_dp *dp, 7848527d81eSPavankumar Nandeshwar struct hal_wbm_completion_ring_tx *desc, 7858527d81eSPavankumar Nandeshwar struct hal_tx_status *ts) 7868527d81eSPavankumar Nandeshwar { 7878527d81eSPavankumar Nandeshwar u32 info0 = le32_to_cpu(desc->rate_stats.info0); 7888527d81eSPavankumar Nandeshwar 7898527d81eSPavankumar Nandeshwar ts->buf_rel_source = 7908527d81eSPavankumar Nandeshwar le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 7918527d81eSPavankumar Nandeshwar if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 7928527d81eSPavankumar Nandeshwar ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 7938527d81eSPavankumar Nandeshwar return; 7948527d81eSPavankumar Nandeshwar 7958527d81eSPavankumar Nandeshwar if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 7968527d81eSPavankumar Nandeshwar return; 7978527d81eSPavankumar Nandeshwar 7988527d81eSPavankumar Nandeshwar ts->status = le32_get_bits(desc->info0, 7998527d81eSPavankumar Nandeshwar HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 8008527d81eSPavankumar Nandeshwar 8018527d81eSPavankumar Nandeshwar ts->ppdu_id = le32_get_bits(desc->info1, 8028527d81eSPavankumar Nandeshwar HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 8038527d81eSPavankumar Nandeshwar 8048527d81eSPavankumar Nandeshwar ts->peer_id = le32_get_bits(desc->info3, HAL_WBM_COMPL_TX_INFO3_PEER_ID); 8058527d81eSPavankumar Nandeshwar 8068527d81eSPavankumar Nandeshwar ts->ack_rssi = le32_get_bits(desc->info2, 8078527d81eSPavankumar Nandeshwar HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI); 8088527d81eSPavankumar Nandeshwar 8098527d81eSPavankumar Nandeshwar if (info0 & HAL_TX_RATE_STATS_INFO0_VALID) { 8108527d81eSPavankumar Nandeshwar ts->pkt_type = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_PKT_TYPE); 8118527d81eSPavankumar Nandeshwar ts->mcs = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_MCS); 8128527d81eSPavankumar Nandeshwar ts->sgi = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_SGI); 8138527d81eSPavankumar Nandeshwar ts->bw = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_BW); 8148527d81eSPavankumar Nandeshwar ts->tones = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_TONES_IN_RU); 8158527d81eSPavankumar Nandeshwar ts->ofdma = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_OFDMA_TX); 8168527d81eSPavankumar Nandeshwar } 8178527d81eSPavankumar Nandeshwar } 8188527d81eSPavankumar Nandeshwar 819*96b42732SPavankumar Nandeshwar void ath12k_wifi7_dp_tx_completion_handler(struct ath12k_dp *dp, int ring_id) 8208527d81eSPavankumar Nandeshwar { 821*96b42732SPavankumar Nandeshwar struct ath12k_base *ab = dp->ab; 8229e0ee04fSRipan Deuri struct ath12k_pdev_dp *dp_pdev; 8238527d81eSPavankumar Nandeshwar int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 824*96b42732SPavankumar Nandeshwar struct hal_srng *status_ring = &dp->hal->srng_list[hal_ring_id]; 8258527d81eSPavankumar Nandeshwar struct ath12k_tx_desc_info *tx_desc = NULL; 8268527d81eSPavankumar Nandeshwar struct hal_tx_status ts = {}; 8278527d81eSPavankumar Nandeshwar struct ath12k_tx_desc_params desc_params; 8288527d81eSPavankumar Nandeshwar struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 8298527d81eSPavankumar Nandeshwar struct hal_wbm_release_ring *desc; 8309e0ee04fSRipan Deuri u8 pdev_idx; 8318527d81eSPavankumar Nandeshwar u64 desc_va; 8328527d81eSPavankumar Nandeshwar enum hal_wbm_rel_src_module buf_rel_source; 8338527d81eSPavankumar Nandeshwar enum hal_wbm_tqm_rel_reason rel_status; 8348527d81eSPavankumar Nandeshwar 8358527d81eSPavankumar Nandeshwar spin_lock_bh(&status_ring->lock); 8368527d81eSPavankumar Nandeshwar 8378527d81eSPavankumar Nandeshwar ath12k_hal_srng_access_begin(ab, status_ring); 8388527d81eSPavankumar Nandeshwar 8398527d81eSPavankumar Nandeshwar while (ATH12K_TX_COMPL_NEXT(ab, tx_ring->tx_status_head) != 8408527d81eSPavankumar Nandeshwar tx_ring->tx_status_tail) { 8418527d81eSPavankumar Nandeshwar desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 8428527d81eSPavankumar Nandeshwar if (!desc) 8438527d81eSPavankumar Nandeshwar break; 8448527d81eSPavankumar Nandeshwar 8458527d81eSPavankumar Nandeshwar memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 8468527d81eSPavankumar Nandeshwar desc, sizeof(*desc)); 8478527d81eSPavankumar Nandeshwar tx_ring->tx_status_head = 8488527d81eSPavankumar Nandeshwar ATH12K_TX_COMPL_NEXT(ab, tx_ring->tx_status_head); 8498527d81eSPavankumar Nandeshwar } 8508527d81eSPavankumar Nandeshwar 8518527d81eSPavankumar Nandeshwar if (ath12k_hal_srng_dst_peek(ab, status_ring) && 8528527d81eSPavankumar Nandeshwar (ATH12K_TX_COMPL_NEXT(ab, tx_ring->tx_status_head) == 8538527d81eSPavankumar Nandeshwar tx_ring->tx_status_tail)) { 8548527d81eSPavankumar Nandeshwar /* TODO: Process pending tx_status messages when kfifo_is_full() */ 8558527d81eSPavankumar Nandeshwar ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 8568527d81eSPavankumar Nandeshwar } 8578527d81eSPavankumar Nandeshwar 8588527d81eSPavankumar Nandeshwar ath12k_hal_srng_access_end(ab, status_ring); 8598527d81eSPavankumar Nandeshwar 8608527d81eSPavankumar Nandeshwar spin_unlock_bh(&status_ring->lock); 8618527d81eSPavankumar Nandeshwar 8628527d81eSPavankumar Nandeshwar while (ATH12K_TX_COMPL_NEXT(ab, tx_ring->tx_status_tail) != 8638527d81eSPavankumar Nandeshwar tx_ring->tx_status_head) { 8648527d81eSPavankumar Nandeshwar struct hal_wbm_completion_ring_tx *tx_status; 8658527d81eSPavankumar Nandeshwar u32 desc_id; 8668527d81eSPavankumar Nandeshwar 8678527d81eSPavankumar Nandeshwar tx_ring->tx_status_tail = 8688527d81eSPavankumar Nandeshwar ATH12K_TX_COMPL_NEXT(ab, tx_ring->tx_status_tail); 8698527d81eSPavankumar Nandeshwar tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 870*96b42732SPavankumar Nandeshwar ath12k_wifi7_dp_tx_status_parse(dp, tx_status, &ts); 8718527d81eSPavankumar Nandeshwar 8728527d81eSPavankumar Nandeshwar if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 8738527d81eSPavankumar Nandeshwar /* HW done cookie conversion */ 8748527d81eSPavankumar Nandeshwar desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 8758527d81eSPavankumar Nandeshwar le32_to_cpu(tx_status->buf_va_lo)); 8768527d81eSPavankumar Nandeshwar tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 8778527d81eSPavankumar Nandeshwar } else { 8788527d81eSPavankumar Nandeshwar /* SW does cookie conversion to VA */ 8798527d81eSPavankumar Nandeshwar desc_id = le32_get_bits(tx_status->buf_va_hi, 8808527d81eSPavankumar Nandeshwar BUFFER_ADDR_INFO1_SW_COOKIE); 8818527d81eSPavankumar Nandeshwar 882*96b42732SPavankumar Nandeshwar tx_desc = ath12k_dp_get_tx_desc(dp, desc_id); 8838527d81eSPavankumar Nandeshwar } 8848527d81eSPavankumar Nandeshwar if (!tx_desc) { 8858527d81eSPavankumar Nandeshwar ath12k_warn(ab, "unable to retrieve tx_desc!"); 8868527d81eSPavankumar Nandeshwar continue; 8878527d81eSPavankumar Nandeshwar } 8888527d81eSPavankumar Nandeshwar 8898527d81eSPavankumar Nandeshwar desc_params.mac_id = tx_desc->mac_id; 8908527d81eSPavankumar Nandeshwar desc_params.skb = tx_desc->skb; 8918527d81eSPavankumar Nandeshwar desc_params.skb_ext_desc = tx_desc->skb_ext_desc; 8928527d81eSPavankumar Nandeshwar 8938527d81eSPavankumar Nandeshwar /* Find the HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE value */ 8948527d81eSPavankumar Nandeshwar buf_rel_source = le32_get_bits(tx_status->info0, 8958527d81eSPavankumar Nandeshwar HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE); 896775fe5acSPavankumar Nandeshwar dp->device_stats.tx_wbm_rel_source[buf_rel_source]++; 8978527d81eSPavankumar Nandeshwar 8988527d81eSPavankumar Nandeshwar rel_status = le32_get_bits(tx_status->info0, 8998527d81eSPavankumar Nandeshwar HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 900775fe5acSPavankumar Nandeshwar dp->device_stats.tqm_rel_reason[rel_status]++; 9018527d81eSPavankumar Nandeshwar 9028527d81eSPavankumar Nandeshwar /* Release descriptor as soon as extracting necessary info 9038527d81eSPavankumar Nandeshwar * to reduce contention 9048527d81eSPavankumar Nandeshwar */ 9058527d81eSPavankumar Nandeshwar ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 9068527d81eSPavankumar Nandeshwar if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 907*96b42732SPavankumar Nandeshwar ath12k_dp_tx_process_htt_tx_complete(dp, (void *)tx_status, 9088527d81eSPavankumar Nandeshwar tx_ring, &desc_params); 9098527d81eSPavankumar Nandeshwar continue; 9108527d81eSPavankumar Nandeshwar } 9118527d81eSPavankumar Nandeshwar 912*96b42732SPavankumar Nandeshwar pdev_idx = ath12k_hw_mac_id_to_pdev_id(dp->hw_params, desc_params.mac_id); 9138527d81eSPavankumar Nandeshwar 9149e0ee04fSRipan Deuri rcu_read_lock(); 9158527d81eSPavankumar Nandeshwar 9169e0ee04fSRipan Deuri dp_pdev = ath12k_dp_to_pdev_dp(dp, pdev_idx); 9179e0ee04fSRipan Deuri if (!dp_pdev) { 9189e0ee04fSRipan Deuri rcu_read_unlock(); 9199e0ee04fSRipan Deuri continue; 9209e0ee04fSRipan Deuri } 9219e0ee04fSRipan Deuri 9229e0ee04fSRipan Deuri if (atomic_dec_and_test(&dp_pdev->num_tx_pending)) 9239e0ee04fSRipan Deuri wake_up(&dp_pdev->tx_empty_waitq); 9249e0ee04fSRipan Deuri 9259e0ee04fSRipan Deuri ath12k_wifi7_dp_tx_complete_msdu(dp_pdev, &desc_params, &ts, 9268527d81eSPavankumar Nandeshwar tx_ring->tcl_data_ring_id); 9279e0ee04fSRipan Deuri rcu_read_unlock(); 9288527d81eSPavankumar Nandeshwar } 9298527d81eSPavankumar Nandeshwar } 9302bb41934SPavankumar Nandeshwar 9312bb41934SPavankumar Nandeshwar u32 ath12k_wifi7_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, 9322bb41934SPavankumar Nandeshwar struct ath12k_link_vif *arvif) 9332bb41934SPavankumar Nandeshwar { 9342bb41934SPavankumar Nandeshwar u32 bank_config = 0; 9352bb41934SPavankumar Nandeshwar u8 link_id = arvif->link_id; 9362bb41934SPavankumar Nandeshwar struct ath12k_vif *ahvif = arvif->ahvif; 9372bb41934SPavankumar Nandeshwar struct ath12k_dp_vif *dp_vif = &ahvif->dp_vif; 9382bb41934SPavankumar Nandeshwar struct ath12k_dp_link_vif *dp_link_vif; 9392bb41934SPavankumar Nandeshwar 9402bb41934SPavankumar Nandeshwar dp_link_vif = ath12k_dp_vif_to_dp_link_vif(dp_vif, link_id); 9412bb41934SPavankumar Nandeshwar 9422bb41934SPavankumar Nandeshwar /* Only valid for raw frames with HW crypto enabled. 9432bb41934SPavankumar Nandeshwar * With SW crypto, mac80211 sets key per packet 9442bb41934SPavankumar Nandeshwar */ 9452bb41934SPavankumar Nandeshwar if (dp_vif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 9462bb41934SPavankumar Nandeshwar test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags)) 9472bb41934SPavankumar Nandeshwar bank_config |= 9482bb41934SPavankumar Nandeshwar u32_encode_bits(ath12k_dp_tx_get_encrypt_type(dp_vif->key_cipher), 9492bb41934SPavankumar Nandeshwar HAL_TX_BANK_CONFIG_ENCRYPT_TYPE); 9502bb41934SPavankumar Nandeshwar 9512bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(dp_vif->tx_encap_type, 9522bb41934SPavankumar Nandeshwar HAL_TX_BANK_CONFIG_ENCAP_TYPE); 9532bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) | 9542bb41934SPavankumar Nandeshwar u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) | 9552bb41934SPavankumar Nandeshwar u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD); 9562bb41934SPavankumar Nandeshwar 9572bb41934SPavankumar Nandeshwar /* only valid if idx_lookup_override is not set in tcl_data_cmd */ 9582bb41934SPavankumar Nandeshwar if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) 9592bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(1, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); 9602bb41934SPavankumar Nandeshwar else 9612bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); 9622bb41934SPavankumar Nandeshwar 9632bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(dp_link_vif->hal_addr_search_flags & 9642bb41934SPavankumar Nandeshwar HAL_TX_ADDRX_EN, 9652bb41934SPavankumar Nandeshwar HAL_TX_BANK_CONFIG_ADDRX_EN) | 9662bb41934SPavankumar Nandeshwar u32_encode_bits(!!(dp_link_vif->hal_addr_search_flags & 9672bb41934SPavankumar Nandeshwar HAL_TX_ADDRY_EN), 9682bb41934SPavankumar Nandeshwar HAL_TX_BANK_CONFIG_ADDRY_EN); 9692bb41934SPavankumar Nandeshwar 9702bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(ahvif->vif) ? 3 : 0, 9712bb41934SPavankumar Nandeshwar HAL_TX_BANK_CONFIG_MESH_EN) | 9722bb41934SPavankumar Nandeshwar u32_encode_bits(dp_link_vif->vdev_id_check_en, 9732bb41934SPavankumar Nandeshwar HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN); 9742bb41934SPavankumar Nandeshwar 9752bb41934SPavankumar Nandeshwar bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID); 9762bb41934SPavankumar Nandeshwar 9772bb41934SPavankumar Nandeshwar return bank_config; 9782bb41934SPavankumar Nandeshwar } 979