1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 22 23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 24 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332 0x2 25 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 26 #define ATH12K_QMI_RESP_LEN_MAX 8192 27 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 28 #define ATH12K_QMI_CALDB_SIZE 0x480000 29 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 30 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 31 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 32 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 33 34 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 35 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 36 #define QMI_WLFW_FW_READY_IND_V01 0x0038 37 38 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 39 #define ATH12K_FIRMWARE_MODE_OFF 4 40 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 41 42 #define ATH12K_BOARD_ID_DEFAULT 0xFF 43 44 struct ath12k_base; 45 struct ath12k_hw_group; 46 47 enum ath12k_qmi_file_type { 48 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 49 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 50 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 51 ATH12K_QMI_MAX_FILE_TYPE = 4, 52 }; 53 54 enum ath12k_qmi_bdf_type { 55 ATH12K_QMI_BDF_TYPE_BIN = 0, 56 ATH12K_QMI_BDF_TYPE_ELF = 1, 57 ATH12K_QMI_BDF_TYPE_REGDB = 4, 58 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 59 }; 60 61 enum ath12k_qmi_event_type { 62 ATH12K_QMI_EVENT_SERVER_ARRIVE, 63 ATH12K_QMI_EVENT_SERVER_EXIT, 64 ATH12K_QMI_EVENT_REQUEST_MEM, 65 ATH12K_QMI_EVENT_FW_MEM_READY, 66 ATH12K_QMI_EVENT_FW_READY, 67 ATH12K_QMI_EVENT_REGISTER_DRIVER, 68 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 69 ATH12K_QMI_EVENT_RECOVERY, 70 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 71 ATH12K_QMI_EVENT_POWER_UP, 72 ATH12K_QMI_EVENT_POWER_DOWN, 73 ATH12K_QMI_EVENT_HOST_CAP, 74 ATH12K_QMI_EVENT_MAX, 75 }; 76 77 struct ath12k_qmi_driver_event { 78 struct list_head list; 79 enum ath12k_qmi_event_type type; 80 void *data; 81 }; 82 83 struct ath12k_qmi_ce_cfg { 84 const struct ce_pipe_config *tgt_ce; 85 int tgt_ce_len; 86 const struct service_to_pipe *svc_to_ce_map; 87 int svc_to_ce_map_len; 88 const u8 *shadow_reg; 89 int shadow_reg_len; 90 u32 *shadow_reg_v3; 91 int shadow_reg_v3_len; 92 }; 93 94 struct ath12k_qmi_event_msg { 95 struct list_head list; 96 enum ath12k_qmi_event_type type; 97 }; 98 99 struct target_mem_chunk { 100 u32 size; 101 u32 type; 102 u32 prev_size; 103 u32 prev_type; 104 dma_addr_t paddr; 105 union { 106 void __iomem *ioaddr; 107 void *addr; 108 } v; 109 }; 110 111 struct target_info { 112 u32 chip_id; 113 u32 chip_family; 114 u32 board_id; 115 u32 soc_id; 116 u32 fw_version; 117 u32 eeprom_caldata; 118 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 119 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 120 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 121 }; 122 123 struct m3_mem_region { 124 u32 size; 125 dma_addr_t paddr; 126 void *vaddr; 127 }; 128 129 struct dev_mem_info { 130 u64 start; 131 u64 size; 132 }; 133 134 struct ath12k_qmi { 135 struct ath12k_base *ab; 136 struct qmi_handle handle; 137 struct sockaddr_qrtr sq; 138 struct work_struct event_work; 139 struct workqueue_struct *event_wq; 140 struct list_head event_list; 141 spinlock_t event_lock; /* spinlock for qmi event list */ 142 struct ath12k_qmi_ce_cfg ce_cfg; 143 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 144 u32 mem_seg_count; 145 u32 target_mem_mode; 146 bool target_mem_delayed; 147 u8 cal_done; 148 149 /* protected with struct ath12k_qmi::event_lock */ 150 bool block_event; 151 152 u8 num_radios; 153 struct target_info target; 154 struct m3_mem_region m3_mem; 155 unsigned int service_ins_id; 156 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 157 }; 158 159 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 160 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 161 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 162 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 163 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 164 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 165 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 166 167 struct qmi_wlanfw_host_ddr_range { 168 u64 start; 169 u64 size; 170 }; 171 172 enum ath12k_qmi_target_mem { 173 HOST_DDR_REGION_TYPE = 0x1, 174 BDF_MEM_REGION_TYPE = 0x2, 175 M3_DUMP_REGION_TYPE = 0x3, 176 CALDB_MEM_REGION_TYPE = 0x4, 177 MLO_GLOBAL_MEM_REGION_TYPE = 0x8, 178 PAGEABLE_MEM_REGION_TYPE = 0x9, 179 }; 180 181 enum qmi_wlanfw_host_build_type { 182 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 183 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 184 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 185 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 186 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 187 }; 188 189 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 190 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 191 192 struct wlfw_host_mlo_chip_info_s_v01 { 193 u8 chip_id; 194 u8 num_local_links; 195 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 196 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 197 }; 198 199 enum ath12k_qmi_cnss_feature { 200 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 201 CNSS_QDSS_CFG_MISS_V01 = 3, 202 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 203 CNSS_MAX_FEATURE_V01 = 64, 204 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 205 }; 206 207 struct qmi_wlanfw_host_cap_req_msg_v01 { 208 u8 num_clients_valid; 209 u32 num_clients; 210 u8 wake_msi_valid; 211 u32 wake_msi; 212 u8 gpios_valid; 213 u32 gpios_len; 214 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 215 u8 nm_modem_valid; 216 u8 nm_modem; 217 u8 bdf_support_valid; 218 u8 bdf_support; 219 u8 bdf_cache_support_valid; 220 u8 bdf_cache_support; 221 u8 m3_support_valid; 222 u8 m3_support; 223 u8 m3_cache_support_valid; 224 u8 m3_cache_support; 225 u8 cal_filesys_support_valid; 226 u8 cal_filesys_support; 227 u8 cal_cache_support_valid; 228 u8 cal_cache_support; 229 u8 cal_done_valid; 230 u8 cal_done; 231 u8 mem_bucket_valid; 232 u32 mem_bucket; 233 u8 mem_cfg_mode_valid; 234 u8 mem_cfg_mode; 235 u8 cal_duration_valid; 236 u16 cal_duraiton; 237 u8 platform_name_valid; 238 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 239 u8 ddr_range_valid; 240 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 241 u8 host_build_type_valid; 242 enum qmi_wlanfw_host_build_type host_build_type; 243 u8 mlo_capable_valid; 244 u8 mlo_capable; 245 u8 mlo_chip_id_valid; 246 u16 mlo_chip_id; 247 u8 mlo_group_id_valid; 248 u8 mlo_group_id; 249 u8 max_mlo_peer_valid; 250 u16 max_mlo_peer; 251 u8 mlo_num_chips_valid; 252 u8 mlo_num_chips; 253 u8 mlo_chip_info_valid; 254 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 255 u8 feature_list_valid; 256 u64 feature_list; 257 258 }; 259 260 struct qmi_wlanfw_host_cap_resp_msg_v01 { 261 struct qmi_response_type_v01 resp; 262 }; 263 264 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 265 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 266 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 267 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 268 269 struct qmi_wlanfw_phy_cap_req_msg_v01 { 270 }; 271 272 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 273 struct qmi_response_type_v01 resp; 274 u8 num_phy_valid; 275 u8 num_phy; 276 u8 board_id_valid; 277 u32 board_id; 278 u8 single_chip_mlo_support_valid; 279 u8 single_chip_mlo_support; 280 }; 281 282 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 283 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 284 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 285 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 286 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 287 288 struct qmi_wlanfw_ind_register_req_msg_v01 { 289 u8 fw_ready_enable_valid; 290 u8 fw_ready_enable; 291 u8 initiate_cal_download_enable_valid; 292 u8 initiate_cal_download_enable; 293 u8 initiate_cal_update_enable_valid; 294 u8 initiate_cal_update_enable; 295 u8 msa_ready_enable_valid; 296 u8 msa_ready_enable; 297 u8 pin_connect_result_enable_valid; 298 u8 pin_connect_result_enable; 299 u8 client_id_valid; 300 u32 client_id; 301 u8 request_mem_enable_valid; 302 u8 request_mem_enable; 303 u8 fw_mem_ready_enable_valid; 304 u8 fw_mem_ready_enable; 305 u8 fw_init_done_enable_valid; 306 u8 fw_init_done_enable; 307 u8 rejuvenate_enable_valid; 308 u32 rejuvenate_enable; 309 u8 xo_cal_enable_valid; 310 u8 xo_cal_enable; 311 u8 cal_done_enable_valid; 312 u8 cal_done_enable; 313 }; 314 315 struct qmi_wlanfw_ind_register_resp_msg_v01 { 316 struct qmi_response_type_v01 resp; 317 u8 fw_status_valid; 318 u64 fw_status; 319 }; 320 321 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 322 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 323 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 324 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 325 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 326 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 327 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 328 #define QMI_WLANFW_MAX_STR_LEN_V01 16 329 330 struct qmi_wlanfw_mem_cfg_s_v01 { 331 u64 offset; 332 u32 size; 333 u8 secure_flag; 334 }; 335 336 enum qmi_wlanfw_mem_type_enum_v01 { 337 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 338 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 339 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 340 QMI_WLANFW_MEM_BDF_V01 = 2, 341 QMI_WLANFW_MEM_M3_V01 = 3, 342 QMI_WLANFW_MEM_CAL_V01 = 4, 343 QMI_WLANFW_MEM_DPD_V01 = 5, 344 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 345 }; 346 347 struct qmi_wlanfw_mem_seg_s_v01 { 348 u32 size; 349 enum qmi_wlanfw_mem_type_enum_v01 type; 350 u32 mem_cfg_len; 351 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 352 }; 353 354 struct qmi_wlanfw_request_mem_ind_msg_v01 { 355 u32 mem_seg_len; 356 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 357 }; 358 359 struct qmi_wlanfw_mem_seg_resp_s_v01 { 360 u64 addr; 361 u32 size; 362 enum qmi_wlanfw_mem_type_enum_v01 type; 363 u8 restore; 364 }; 365 366 struct qmi_wlanfw_respond_mem_req_msg_v01 { 367 u32 mem_seg_len; 368 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 369 }; 370 371 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 372 struct qmi_response_type_v01 resp; 373 }; 374 375 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 376 char placeholder; 377 }; 378 379 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 380 char placeholder; 381 }; 382 383 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 384 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 385 #define QMI_WLANFW_CAP_REQ_V01 0x0024 386 #define QMI_WLANFW_CAP_RESP_V01 0x0024 387 388 enum qmi_wlanfw_pipedir_enum_v01 { 389 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 390 QMI_WLFW_PIPEDIR_IN_V01 = 1, 391 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 392 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 393 }; 394 395 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 396 __le32 pipe_num; 397 __le32 pipe_dir; 398 __le32 nentries; 399 __le32 nbytes_max; 400 __le32 flags; 401 }; 402 403 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 404 __le32 service_id; 405 __le32 pipe_dir; 406 __le32 pipe_num; 407 }; 408 409 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 410 u16 id; 411 u16 offset; 412 }; 413 414 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 415 u32 addr; 416 }; 417 418 struct qmi_wlanfw_memory_region_info_s_v01 { 419 u64 region_addr; 420 u32 size; 421 u8 secure_flag; 422 }; 423 424 struct qmi_wlanfw_rf_chip_info_s_v01 { 425 u32 chip_id; 426 u32 chip_family; 427 }; 428 429 struct qmi_wlanfw_rf_board_info_s_v01 { 430 u32 board_id; 431 }; 432 433 struct qmi_wlanfw_soc_info_s_v01 { 434 u32 soc_id; 435 }; 436 437 struct qmi_wlanfw_fw_version_info_s_v01 { 438 u32 fw_version; 439 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 440 }; 441 442 struct qmi_wlanfw_dev_mem_info_s_v01 { 443 u64 start; 444 u64 size; 445 }; 446 447 enum qmi_wlanfw_cal_temp_id_enum_v01 { 448 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 449 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 450 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 451 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 452 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 453 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 454 }; 455 456 enum qmi_wlanfw_rd_card_chain_cap_v01 { 457 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 458 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 459 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 460 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 461 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 462 }; 463 464 struct qmi_wlanfw_cap_resp_msg_v01 { 465 struct qmi_response_type_v01 resp; 466 u8 chip_info_valid; 467 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 468 u8 board_info_valid; 469 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 470 u8 soc_info_valid; 471 struct qmi_wlanfw_soc_info_s_v01 soc_info; 472 u8 fw_version_info_valid; 473 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 474 u8 fw_build_id_valid; 475 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 476 u8 num_macs_valid; 477 u8 num_macs; 478 u8 voltage_mv_valid; 479 u32 voltage_mv; 480 u8 time_freq_hz_valid; 481 u32 time_freq_hz; 482 u8 otp_version_valid; 483 u32 otp_version; 484 u8 eeprom_caldata_read_timeout_valid; 485 u32 eeprom_caldata_read_timeout; 486 u8 fw_caps_valid; 487 u64 fw_caps; 488 u8 rd_card_chain_cap_valid; 489 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 490 u8 dev_mem_info_valid; 491 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 492 }; 493 494 struct qmi_wlanfw_cap_req_msg_v01 { 495 char placeholder; 496 }; 497 498 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 499 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 500 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 501 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 502 /* TODO: Need to check with MCL and FW team that data can be pointer and 503 * can be last element in structure 504 */ 505 struct qmi_wlanfw_bdf_download_req_msg_v01 { 506 u8 valid; 507 u8 file_id_valid; 508 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 509 u8 total_size_valid; 510 u32 total_size; 511 u8 seg_id_valid; 512 u32 seg_id; 513 u8 data_valid; 514 u32 data_len; 515 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 516 u8 end_valid; 517 u8 end; 518 u8 bdf_type_valid; 519 u8 bdf_type; 520 521 }; 522 523 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 524 struct qmi_response_type_v01 resp; 525 }; 526 527 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 528 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 529 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 530 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 531 532 struct qmi_wlanfw_m3_info_req_msg_v01 { 533 u64 addr; 534 u32 size; 535 }; 536 537 struct qmi_wlanfw_m3_info_resp_msg_v01 { 538 struct qmi_response_type_v01 resp; 539 }; 540 541 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 542 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 543 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 544 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 545 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 546 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 547 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 548 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 549 #define QMI_WLANFW_MAX_STR_LEN_V01 16 550 #define QMI_WLANFW_MAX_NUM_CE_V01 12 551 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 552 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 553 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 554 555 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 556 u32 mode; 557 u8 hw_debug_valid; 558 u8 hw_debug; 559 }; 560 561 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 562 struct qmi_response_type_v01 resp; 563 }; 564 565 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 566 u8 host_version_valid; 567 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 568 u8 tgt_cfg_valid; 569 u32 tgt_cfg_len; 570 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 571 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 572 u8 svc_cfg_valid; 573 u32 svc_cfg_len; 574 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 575 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 576 u8 shadow_reg_valid; 577 u32 shadow_reg_len; 578 struct qmi_wlanfw_shadow_reg_cfg_s_v01 579 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 580 u8 shadow_reg_v3_valid; 581 u32 shadow_reg_v3_len; 582 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 583 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 584 }; 585 586 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 587 struct qmi_response_type_v01 resp; 588 }; 589 590 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 591 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F 592 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 593 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7 594 595 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 596 /* Must be set to true if enable_fwlog is being passed */ 597 u8 enable_fwlog_valid; 598 u8 enable_fwlog; 599 }; 600 601 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 602 struct qmi_response_type_v01 resp; 603 }; 604 605 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block) 606 { 607 lockdep_assert_held(&qmi->event_lock); 608 609 qmi->block_event = block; 610 } 611 612 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi) 613 { 614 lockdep_assert_held(&qmi->event_lock); 615 616 return qmi->block_event; 617 } 618 619 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 620 u32 mode); 621 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 622 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 623 int ath12k_qmi_init_service(struct ath12k_base *ab); 624 void ath12k_qmi_free_resource(struct ath12k_base *ab); 625 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab); 626 void ath12k_qmi_reset_mlo_mem(struct ath12k_hw_group *ag); 627 628 #endif 629