1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH12K_QMI_WLFW_NODE_ID_BASE 0x07 19 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 20 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 22 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 23 24 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 25 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 26 #define ATH12K_QMI_RESP_LEN_MAX 8192 27 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 28 #define ATH12K_QMI_CALDB_SIZE 0x480000 29 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 30 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 31 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 32 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 33 34 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 35 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 36 #define QMI_WLFW_FW_READY_IND_V01 0x0038 37 38 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 39 #define ATH12K_FIRMWARE_MODE_OFF 4 40 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 41 42 #define ATH12K_BOARD_ID_DEFAULT 0xFF 43 44 struct ath12k_base; 45 46 enum ath12k_qmi_file_type { 47 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 48 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 49 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 50 ATH12K_QMI_MAX_FILE_TYPE = 4, 51 }; 52 53 enum ath12k_qmi_bdf_type { 54 ATH12K_QMI_BDF_TYPE_BIN = 0, 55 ATH12K_QMI_BDF_TYPE_ELF = 1, 56 ATH12K_QMI_BDF_TYPE_REGDB = 4, 57 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 58 }; 59 60 enum ath12k_qmi_event_type { 61 ATH12K_QMI_EVENT_SERVER_ARRIVE, 62 ATH12K_QMI_EVENT_SERVER_EXIT, 63 ATH12K_QMI_EVENT_REQUEST_MEM, 64 ATH12K_QMI_EVENT_FW_MEM_READY, 65 ATH12K_QMI_EVENT_FW_READY, 66 ATH12K_QMI_EVENT_REGISTER_DRIVER, 67 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 68 ATH12K_QMI_EVENT_RECOVERY, 69 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 70 ATH12K_QMI_EVENT_POWER_UP, 71 ATH12K_QMI_EVENT_POWER_DOWN, 72 ATH12K_QMI_EVENT_MAX, 73 }; 74 75 struct ath12k_qmi_driver_event { 76 struct list_head list; 77 enum ath12k_qmi_event_type type; 78 void *data; 79 }; 80 81 struct ath12k_qmi_ce_cfg { 82 const struct ce_pipe_config *tgt_ce; 83 int tgt_ce_len; 84 const struct service_to_pipe *svc_to_ce_map; 85 int svc_to_ce_map_len; 86 const u8 *shadow_reg; 87 int shadow_reg_len; 88 u32 *shadow_reg_v3; 89 int shadow_reg_v3_len; 90 }; 91 92 struct ath12k_qmi_event_msg { 93 struct list_head list; 94 enum ath12k_qmi_event_type type; 95 }; 96 97 struct target_mem_chunk { 98 u32 size; 99 u32 type; 100 dma_addr_t paddr; 101 union { 102 void __iomem *ioaddr; 103 void *addr; 104 } v; 105 }; 106 107 struct target_info { 108 u32 chip_id; 109 u32 chip_family; 110 u32 board_id; 111 u32 soc_id; 112 u32 fw_version; 113 u32 eeprom_caldata; 114 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 115 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 116 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 117 }; 118 119 struct m3_mem_region { 120 u32 size; 121 dma_addr_t paddr; 122 void *vaddr; 123 }; 124 125 struct dev_mem_info { 126 u64 start; 127 u64 size; 128 }; 129 130 struct ath12k_qmi { 131 struct ath12k_base *ab; 132 struct qmi_handle handle; 133 struct sockaddr_qrtr sq; 134 struct work_struct event_work; 135 struct workqueue_struct *event_wq; 136 struct list_head event_list; 137 spinlock_t event_lock; /* spinlock for qmi event list */ 138 struct ath12k_qmi_ce_cfg ce_cfg; 139 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 140 u32 mem_seg_count; 141 u32 target_mem_mode; 142 bool target_mem_delayed; 143 u8 cal_done; 144 u8 num_radios; 145 struct target_info target; 146 struct m3_mem_region m3_mem; 147 unsigned int service_ins_id; 148 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 149 }; 150 151 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 152 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 153 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 154 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 155 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 156 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 157 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 158 159 struct qmi_wlanfw_host_ddr_range { 160 u64 start; 161 u64 size; 162 }; 163 164 enum ath12k_qmi_target_mem { 165 HOST_DDR_REGION_TYPE = 0x1, 166 BDF_MEM_REGION_TYPE = 0x2, 167 M3_DUMP_REGION_TYPE = 0x3, 168 CALDB_MEM_REGION_TYPE = 0x4, 169 PAGEABLE_MEM_REGION_TYPE = 0x9, 170 }; 171 172 enum qmi_wlanfw_host_build_type { 173 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 174 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 175 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 176 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 177 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 178 }; 179 180 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 181 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 182 183 struct wlfw_host_mlo_chip_info_s_v01 { 184 u8 chip_id; 185 u8 num_local_links; 186 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 187 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 188 }; 189 190 enum ath12k_qmi_cnss_feature { 191 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 192 CNSS_QDSS_CFG_MISS_V01 = 3, 193 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 194 CNSS_MAX_FEATURE_V01 = 64, 195 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 196 }; 197 198 struct qmi_wlanfw_host_cap_req_msg_v01 { 199 u8 num_clients_valid; 200 u32 num_clients; 201 u8 wake_msi_valid; 202 u32 wake_msi; 203 u8 gpios_valid; 204 u32 gpios_len; 205 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 206 u8 nm_modem_valid; 207 u8 nm_modem; 208 u8 bdf_support_valid; 209 u8 bdf_support; 210 u8 bdf_cache_support_valid; 211 u8 bdf_cache_support; 212 u8 m3_support_valid; 213 u8 m3_support; 214 u8 m3_cache_support_valid; 215 u8 m3_cache_support; 216 u8 cal_filesys_support_valid; 217 u8 cal_filesys_support; 218 u8 cal_cache_support_valid; 219 u8 cal_cache_support; 220 u8 cal_done_valid; 221 u8 cal_done; 222 u8 mem_bucket_valid; 223 u32 mem_bucket; 224 u8 mem_cfg_mode_valid; 225 u8 mem_cfg_mode; 226 u8 cal_duration_valid; 227 u16 cal_duraiton; 228 u8 platform_name_valid; 229 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 230 u8 ddr_range_valid; 231 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 232 u8 host_build_type_valid; 233 enum qmi_wlanfw_host_build_type host_build_type; 234 u8 mlo_capable_valid; 235 u8 mlo_capable; 236 u8 mlo_chip_id_valid; 237 u16 mlo_chip_id; 238 u8 mlo_group_id_valid; 239 u8 mlo_group_id; 240 u8 max_mlo_peer_valid; 241 u16 max_mlo_peer; 242 u8 mlo_num_chips_valid; 243 u8 mlo_num_chips; 244 u8 mlo_chip_info_valid; 245 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 246 u8 feature_list_valid; 247 u64 feature_list; 248 249 }; 250 251 struct qmi_wlanfw_host_cap_resp_msg_v01 { 252 struct qmi_response_type_v01 resp; 253 }; 254 255 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 256 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 257 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 258 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 259 260 struct qmi_wlanfw_phy_cap_req_msg_v01 { 261 }; 262 263 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 264 struct qmi_response_type_v01 resp; 265 u8 num_phy_valid; 266 u8 num_phy; 267 u8 board_id_valid; 268 u32 board_id; 269 }; 270 271 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 272 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 273 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 274 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 275 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 276 277 struct qmi_wlanfw_ind_register_req_msg_v01 { 278 u8 fw_ready_enable_valid; 279 u8 fw_ready_enable; 280 u8 initiate_cal_download_enable_valid; 281 u8 initiate_cal_download_enable; 282 u8 initiate_cal_update_enable_valid; 283 u8 initiate_cal_update_enable; 284 u8 msa_ready_enable_valid; 285 u8 msa_ready_enable; 286 u8 pin_connect_result_enable_valid; 287 u8 pin_connect_result_enable; 288 u8 client_id_valid; 289 u32 client_id; 290 u8 request_mem_enable_valid; 291 u8 request_mem_enable; 292 u8 fw_mem_ready_enable_valid; 293 u8 fw_mem_ready_enable; 294 u8 fw_init_done_enable_valid; 295 u8 fw_init_done_enable; 296 u8 rejuvenate_enable_valid; 297 u32 rejuvenate_enable; 298 u8 xo_cal_enable_valid; 299 u8 xo_cal_enable; 300 u8 cal_done_enable_valid; 301 u8 cal_done_enable; 302 }; 303 304 struct qmi_wlanfw_ind_register_resp_msg_v01 { 305 struct qmi_response_type_v01 resp; 306 u8 fw_status_valid; 307 u64 fw_status; 308 }; 309 310 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 311 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 312 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 313 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 314 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 315 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 316 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 317 #define QMI_WLANFW_MAX_STR_LEN_V01 16 318 319 struct qmi_wlanfw_mem_cfg_s_v01 { 320 u64 offset; 321 u32 size; 322 u8 secure_flag; 323 }; 324 325 enum qmi_wlanfw_mem_type_enum_v01 { 326 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 327 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 328 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 329 QMI_WLANFW_MEM_BDF_V01 = 2, 330 QMI_WLANFW_MEM_M3_V01 = 3, 331 QMI_WLANFW_MEM_CAL_V01 = 4, 332 QMI_WLANFW_MEM_DPD_V01 = 5, 333 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 334 }; 335 336 struct qmi_wlanfw_mem_seg_s_v01 { 337 u32 size; 338 enum qmi_wlanfw_mem_type_enum_v01 type; 339 u32 mem_cfg_len; 340 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 341 }; 342 343 struct qmi_wlanfw_request_mem_ind_msg_v01 { 344 u32 mem_seg_len; 345 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 346 }; 347 348 struct qmi_wlanfw_mem_seg_resp_s_v01 { 349 u64 addr; 350 u32 size; 351 enum qmi_wlanfw_mem_type_enum_v01 type; 352 u8 restore; 353 }; 354 355 struct qmi_wlanfw_respond_mem_req_msg_v01 { 356 u32 mem_seg_len; 357 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 358 }; 359 360 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 361 struct qmi_response_type_v01 resp; 362 }; 363 364 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 365 char placeholder; 366 }; 367 368 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 369 char placeholder; 370 }; 371 372 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 373 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 374 #define QMI_WLANFW_CAP_REQ_V01 0x0024 375 #define QMI_WLANFW_CAP_RESP_V01 0x0024 376 377 enum qmi_wlanfw_pipedir_enum_v01 { 378 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 379 QMI_WLFW_PIPEDIR_IN_V01 = 1, 380 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 381 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 382 }; 383 384 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 385 __le32 pipe_num; 386 __le32 pipe_dir; 387 __le32 nentries; 388 __le32 nbytes_max; 389 __le32 flags; 390 }; 391 392 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 393 __le32 service_id; 394 __le32 pipe_dir; 395 __le32 pipe_num; 396 }; 397 398 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 399 u16 id; 400 u16 offset; 401 }; 402 403 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 404 u32 addr; 405 }; 406 407 struct qmi_wlanfw_memory_region_info_s_v01 { 408 u64 region_addr; 409 u32 size; 410 u8 secure_flag; 411 }; 412 413 struct qmi_wlanfw_rf_chip_info_s_v01 { 414 u32 chip_id; 415 u32 chip_family; 416 }; 417 418 struct qmi_wlanfw_rf_board_info_s_v01 { 419 u32 board_id; 420 }; 421 422 struct qmi_wlanfw_soc_info_s_v01 { 423 u32 soc_id; 424 }; 425 426 struct qmi_wlanfw_fw_version_info_s_v01 { 427 u32 fw_version; 428 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 429 }; 430 431 struct qmi_wlanfw_dev_mem_info_s_v01 { 432 u64 start; 433 u64 size; 434 }; 435 436 enum qmi_wlanfw_cal_temp_id_enum_v01 { 437 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 438 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 439 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 440 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 441 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 442 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 443 }; 444 445 enum qmi_wlanfw_rd_card_chain_cap_v01 { 446 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 447 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 448 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 449 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 450 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 451 }; 452 453 struct qmi_wlanfw_cap_resp_msg_v01 { 454 struct qmi_response_type_v01 resp; 455 u8 chip_info_valid; 456 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 457 u8 board_info_valid; 458 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 459 u8 soc_info_valid; 460 struct qmi_wlanfw_soc_info_s_v01 soc_info; 461 u8 fw_version_info_valid; 462 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 463 u8 fw_build_id_valid; 464 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 465 u8 num_macs_valid; 466 u8 num_macs; 467 u8 voltage_mv_valid; 468 u32 voltage_mv; 469 u8 time_freq_hz_valid; 470 u32 time_freq_hz; 471 u8 otp_version_valid; 472 u32 otp_version; 473 u8 eeprom_caldata_read_timeout_valid; 474 u32 eeprom_caldata_read_timeout; 475 u8 fw_caps_valid; 476 u64 fw_caps; 477 u8 rd_card_chain_cap_valid; 478 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 479 u8 dev_mem_info_valid; 480 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 481 }; 482 483 struct qmi_wlanfw_cap_req_msg_v01 { 484 char placeholder; 485 }; 486 487 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 488 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 489 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 490 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 491 /* TODO: Need to check with MCL and FW team that data can be pointer and 492 * can be last element in structure 493 */ 494 struct qmi_wlanfw_bdf_download_req_msg_v01 { 495 u8 valid; 496 u8 file_id_valid; 497 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 498 u8 total_size_valid; 499 u32 total_size; 500 u8 seg_id_valid; 501 u32 seg_id; 502 u8 data_valid; 503 u32 data_len; 504 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 505 u8 end_valid; 506 u8 end; 507 u8 bdf_type_valid; 508 u8 bdf_type; 509 510 }; 511 512 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 513 struct qmi_response_type_v01 resp; 514 }; 515 516 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 517 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 518 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 519 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 520 521 struct qmi_wlanfw_m3_info_req_msg_v01 { 522 u64 addr; 523 u32 size; 524 }; 525 526 struct qmi_wlanfw_m3_info_resp_msg_v01 { 527 struct qmi_response_type_v01 resp; 528 }; 529 530 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 531 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 532 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 533 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 534 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 535 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 536 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 537 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 538 #define QMI_WLANFW_MAX_STR_LEN_V01 16 539 #define QMI_WLANFW_MAX_NUM_CE_V01 12 540 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 541 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 542 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 543 544 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 545 u32 mode; 546 u8 hw_debug_valid; 547 u8 hw_debug; 548 }; 549 550 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 551 struct qmi_response_type_v01 resp; 552 }; 553 554 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 555 u8 host_version_valid; 556 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 557 u8 tgt_cfg_valid; 558 u32 tgt_cfg_len; 559 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 560 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 561 u8 svc_cfg_valid; 562 u32 svc_cfg_len; 563 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 564 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 565 u8 shadow_reg_valid; 566 u32 shadow_reg_len; 567 struct qmi_wlanfw_shadow_reg_cfg_s_v01 568 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 569 u8 shadow_reg_v3_valid; 570 u32 shadow_reg_v3_len; 571 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 572 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 573 }; 574 575 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 576 struct qmi_response_type_v01 resp; 577 }; 578 579 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 580 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F 581 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 582 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7 583 584 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 585 /* Must be set to true if enable_fwlog is being passed */ 586 u8 enable_fwlog_valid; 587 u8 enable_fwlog; 588 }; 589 590 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 591 struct qmi_response_type_v01 resp; 592 }; 593 594 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 595 u32 mode); 596 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 597 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 598 int ath12k_qmi_init_service(struct ath12k_base *ab); 599 void ath12k_qmi_free_resource(struct ath12k_base *ab); 600 601 #endif 602