1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 22 23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 24 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332 0x2 25 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 26 #define ATH12K_QMI_RESP_LEN_MAX 8192 27 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 28 #define ATH12K_QMI_CALDB_SIZE 0x480000 29 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 30 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 31 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 32 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 33 34 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 35 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 36 #define QMI_WLFW_FW_READY_IND_V01 0x0038 37 38 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 39 #define ATH12K_FIRMWARE_MODE_OFF 4 40 41 #define ATH12K_BOARD_ID_DEFAULT 0xFF 42 43 struct ath12k_base; 44 struct ath12k_hw_group; 45 46 enum ath12k_qmi_file_type { 47 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 48 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 49 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 50 ATH12K_QMI_MAX_FILE_TYPE = 4, 51 }; 52 53 enum ath12k_qmi_bdf_type { 54 ATH12K_QMI_BDF_TYPE_BIN = 0, 55 ATH12K_QMI_BDF_TYPE_ELF = 1, 56 ATH12K_QMI_BDF_TYPE_REGDB = 4, 57 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 58 }; 59 60 enum ath12k_qmi_event_type { 61 ATH12K_QMI_EVENT_SERVER_ARRIVE, 62 ATH12K_QMI_EVENT_SERVER_EXIT, 63 ATH12K_QMI_EVENT_REQUEST_MEM, 64 ATH12K_QMI_EVENT_FW_MEM_READY, 65 ATH12K_QMI_EVENT_FW_READY, 66 ATH12K_QMI_EVENT_REGISTER_DRIVER, 67 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 68 ATH12K_QMI_EVENT_RECOVERY, 69 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 70 ATH12K_QMI_EVENT_POWER_UP, 71 ATH12K_QMI_EVENT_POWER_DOWN, 72 ATH12K_QMI_EVENT_HOST_CAP, 73 ATH12K_QMI_EVENT_MAX, 74 }; 75 76 struct ath12k_qmi_driver_event { 77 struct list_head list; 78 enum ath12k_qmi_event_type type; 79 void *data; 80 }; 81 82 struct ath12k_qmi_ce_cfg { 83 const struct ce_pipe_config *tgt_ce; 84 int tgt_ce_len; 85 const struct service_to_pipe *svc_to_ce_map; 86 int svc_to_ce_map_len; 87 const u8 *shadow_reg; 88 int shadow_reg_len; 89 u32 *shadow_reg_v3; 90 int shadow_reg_v3_len; 91 }; 92 93 struct ath12k_qmi_event_msg { 94 struct list_head list; 95 enum ath12k_qmi_event_type type; 96 }; 97 98 struct target_mem_chunk { 99 u32 size; 100 u32 type; 101 u32 prev_size; 102 u32 prev_type; 103 dma_addr_t paddr; 104 union { 105 void __iomem *ioaddr; 106 void *addr; 107 } v; 108 }; 109 110 struct target_info { 111 u32 chip_id; 112 u32 chip_family; 113 u32 board_id; 114 u32 soc_id; 115 u32 fw_version; 116 u32 eeprom_caldata; 117 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 118 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 119 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 120 }; 121 122 struct m3_mem_region { 123 u32 size; 124 dma_addr_t paddr; 125 void *vaddr; 126 }; 127 128 struct dev_mem_info { 129 u64 start; 130 u64 size; 131 }; 132 133 struct ath12k_qmi { 134 struct ath12k_base *ab; 135 struct qmi_handle handle; 136 struct sockaddr_qrtr sq; 137 struct work_struct event_work; 138 struct workqueue_struct *event_wq; 139 struct list_head event_list; 140 spinlock_t event_lock; /* spinlock for qmi event list */ 141 struct ath12k_qmi_ce_cfg ce_cfg; 142 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 143 u32 mem_seg_count; 144 u32 target_mem_mode; 145 bool target_mem_delayed; 146 u8 cal_done; 147 148 /* protected with struct ath12k_qmi::event_lock */ 149 bool block_event; 150 151 u8 num_radios; 152 struct target_info target; 153 struct m3_mem_region m3_mem; 154 unsigned int service_ins_id; 155 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 156 }; 157 158 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 159 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 160 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 161 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 162 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 163 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 164 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 165 166 struct qmi_wlanfw_host_ddr_range { 167 u64 start; 168 u64 size; 169 }; 170 171 enum ath12k_qmi_target_mem { 172 HOST_DDR_REGION_TYPE = 0x1, 173 BDF_MEM_REGION_TYPE = 0x2, 174 M3_DUMP_REGION_TYPE = 0x3, 175 CALDB_MEM_REGION_TYPE = 0x4, 176 MLO_GLOBAL_MEM_REGION_TYPE = 0x8, 177 PAGEABLE_MEM_REGION_TYPE = 0x9, 178 }; 179 180 enum qmi_wlanfw_host_build_type { 181 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 182 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 183 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 184 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 185 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 186 }; 187 188 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 189 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 190 191 struct wlfw_host_mlo_chip_info_s_v01 { 192 u8 chip_id; 193 u8 num_local_links; 194 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 195 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 196 }; 197 198 enum ath12k_qmi_cnss_feature { 199 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 200 CNSS_QDSS_CFG_MISS_V01 = 3, 201 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 202 CNSS_MAX_FEATURE_V01 = 64, 203 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 204 }; 205 206 struct qmi_wlanfw_host_cap_req_msg_v01 { 207 u8 num_clients_valid; 208 u32 num_clients; 209 u8 wake_msi_valid; 210 u32 wake_msi; 211 u8 gpios_valid; 212 u32 gpios_len; 213 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 214 u8 nm_modem_valid; 215 u8 nm_modem; 216 u8 bdf_support_valid; 217 u8 bdf_support; 218 u8 bdf_cache_support_valid; 219 u8 bdf_cache_support; 220 u8 m3_support_valid; 221 u8 m3_support; 222 u8 m3_cache_support_valid; 223 u8 m3_cache_support; 224 u8 cal_filesys_support_valid; 225 u8 cal_filesys_support; 226 u8 cal_cache_support_valid; 227 u8 cal_cache_support; 228 u8 cal_done_valid; 229 u8 cal_done; 230 u8 mem_bucket_valid; 231 u32 mem_bucket; 232 u8 mem_cfg_mode_valid; 233 u8 mem_cfg_mode; 234 u8 cal_duration_valid; 235 u16 cal_duraiton; 236 u8 platform_name_valid; 237 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 238 u8 ddr_range_valid; 239 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 240 u8 host_build_type_valid; 241 enum qmi_wlanfw_host_build_type host_build_type; 242 u8 mlo_capable_valid; 243 u8 mlo_capable; 244 u8 mlo_chip_id_valid; 245 u16 mlo_chip_id; 246 u8 mlo_group_id_valid; 247 u8 mlo_group_id; 248 u8 max_mlo_peer_valid; 249 u16 max_mlo_peer; 250 u8 mlo_num_chips_valid; 251 u8 mlo_num_chips; 252 u8 mlo_chip_info_valid; 253 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 254 u8 feature_list_valid; 255 u64 feature_list; 256 257 }; 258 259 struct qmi_wlanfw_host_cap_resp_msg_v01 { 260 struct qmi_response_type_v01 resp; 261 }; 262 263 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 264 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 265 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 266 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 267 268 struct qmi_wlanfw_phy_cap_req_msg_v01 { 269 }; 270 271 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 272 struct qmi_response_type_v01 resp; 273 u8 num_phy_valid; 274 u8 num_phy; 275 u8 board_id_valid; 276 u32 board_id; 277 u8 single_chip_mlo_support_valid; 278 u8 single_chip_mlo_support; 279 }; 280 281 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 282 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 283 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 284 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 285 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 286 287 struct qmi_wlanfw_ind_register_req_msg_v01 { 288 u8 fw_ready_enable_valid; 289 u8 fw_ready_enable; 290 u8 initiate_cal_download_enable_valid; 291 u8 initiate_cal_download_enable; 292 u8 initiate_cal_update_enable_valid; 293 u8 initiate_cal_update_enable; 294 u8 msa_ready_enable_valid; 295 u8 msa_ready_enable; 296 u8 pin_connect_result_enable_valid; 297 u8 pin_connect_result_enable; 298 u8 client_id_valid; 299 u32 client_id; 300 u8 request_mem_enable_valid; 301 u8 request_mem_enable; 302 u8 fw_mem_ready_enable_valid; 303 u8 fw_mem_ready_enable; 304 u8 fw_init_done_enable_valid; 305 u8 fw_init_done_enable; 306 u8 rejuvenate_enable_valid; 307 u32 rejuvenate_enable; 308 u8 xo_cal_enable_valid; 309 u8 xo_cal_enable; 310 u8 cal_done_enable_valid; 311 u8 cal_done_enable; 312 }; 313 314 struct qmi_wlanfw_ind_register_resp_msg_v01 { 315 struct qmi_response_type_v01 resp; 316 u8 fw_status_valid; 317 u64 fw_status; 318 }; 319 320 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 321 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 322 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 323 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 324 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 325 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 326 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 327 #define QMI_WLANFW_MAX_STR_LEN_V01 16 328 329 struct qmi_wlanfw_mem_cfg_s_v01 { 330 u64 offset; 331 u32 size; 332 u8 secure_flag; 333 }; 334 335 enum qmi_wlanfw_mem_type_enum_v01 { 336 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 337 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 338 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 339 QMI_WLANFW_MEM_BDF_V01 = 2, 340 QMI_WLANFW_MEM_M3_V01 = 3, 341 QMI_WLANFW_MEM_CAL_V01 = 4, 342 QMI_WLANFW_MEM_DPD_V01 = 5, 343 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 344 }; 345 346 struct qmi_wlanfw_mem_seg_s_v01 { 347 u32 size; 348 enum qmi_wlanfw_mem_type_enum_v01 type; 349 u32 mem_cfg_len; 350 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 351 }; 352 353 struct qmi_wlanfw_request_mem_ind_msg_v01 { 354 u32 mem_seg_len; 355 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 356 }; 357 358 struct qmi_wlanfw_mem_seg_resp_s_v01 { 359 u64 addr; 360 u32 size; 361 enum qmi_wlanfw_mem_type_enum_v01 type; 362 u8 restore; 363 }; 364 365 struct qmi_wlanfw_respond_mem_req_msg_v01 { 366 u32 mem_seg_len; 367 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 368 }; 369 370 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 371 struct qmi_response_type_v01 resp; 372 }; 373 374 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 375 char placeholder; 376 }; 377 378 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 379 char placeholder; 380 }; 381 382 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 383 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 384 #define QMI_WLANFW_CAP_REQ_V01 0x0024 385 #define QMI_WLANFW_CAP_RESP_V01 0x0024 386 387 enum qmi_wlanfw_pipedir_enum_v01 { 388 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 389 QMI_WLFW_PIPEDIR_IN_V01 = 1, 390 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 391 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 392 }; 393 394 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 395 __le32 pipe_num; 396 __le32 pipe_dir; 397 __le32 nentries; 398 __le32 nbytes_max; 399 __le32 flags; 400 }; 401 402 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 403 __le32 service_id; 404 __le32 pipe_dir; 405 __le32 pipe_num; 406 }; 407 408 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 409 u16 id; 410 u16 offset; 411 }; 412 413 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 414 u32 addr; 415 }; 416 417 struct qmi_wlanfw_memory_region_info_s_v01 { 418 u64 region_addr; 419 u32 size; 420 u8 secure_flag; 421 }; 422 423 struct qmi_wlanfw_rf_chip_info_s_v01 { 424 u32 chip_id; 425 u32 chip_family; 426 }; 427 428 struct qmi_wlanfw_rf_board_info_s_v01 { 429 u32 board_id; 430 }; 431 432 struct qmi_wlanfw_soc_info_s_v01 { 433 u32 soc_id; 434 }; 435 436 struct qmi_wlanfw_fw_version_info_s_v01 { 437 u32 fw_version; 438 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 439 }; 440 441 struct qmi_wlanfw_dev_mem_info_s_v01 { 442 u64 start; 443 u64 size; 444 }; 445 446 enum qmi_wlanfw_cal_temp_id_enum_v01 { 447 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 448 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 449 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 450 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 451 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 452 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 453 }; 454 455 enum qmi_wlanfw_rd_card_chain_cap_v01 { 456 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 457 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 458 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 459 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 460 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 461 }; 462 463 struct qmi_wlanfw_cap_resp_msg_v01 { 464 struct qmi_response_type_v01 resp; 465 u8 chip_info_valid; 466 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 467 u8 board_info_valid; 468 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 469 u8 soc_info_valid; 470 struct qmi_wlanfw_soc_info_s_v01 soc_info; 471 u8 fw_version_info_valid; 472 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 473 u8 fw_build_id_valid; 474 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 475 u8 num_macs_valid; 476 u8 num_macs; 477 u8 voltage_mv_valid; 478 u32 voltage_mv; 479 u8 time_freq_hz_valid; 480 u32 time_freq_hz; 481 u8 otp_version_valid; 482 u32 otp_version; 483 u8 eeprom_caldata_read_timeout_valid; 484 u32 eeprom_caldata_read_timeout; 485 u8 fw_caps_valid; 486 u64 fw_caps; 487 u8 rd_card_chain_cap_valid; 488 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 489 u8 dev_mem_info_valid; 490 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 491 }; 492 493 struct qmi_wlanfw_cap_req_msg_v01 { 494 char placeholder; 495 }; 496 497 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 498 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 499 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 500 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 501 /* TODO: Need to check with MCL and FW team that data can be pointer and 502 * can be last element in structure 503 */ 504 struct qmi_wlanfw_bdf_download_req_msg_v01 { 505 u8 valid; 506 u8 file_id_valid; 507 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 508 u8 total_size_valid; 509 u32 total_size; 510 u8 seg_id_valid; 511 u32 seg_id; 512 u8 data_valid; 513 u32 data_len; 514 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 515 u8 end_valid; 516 u8 end; 517 u8 bdf_type_valid; 518 u8 bdf_type; 519 520 }; 521 522 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 523 struct qmi_response_type_v01 resp; 524 }; 525 526 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 527 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 528 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 529 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 530 531 struct qmi_wlanfw_m3_info_req_msg_v01 { 532 u64 addr; 533 u32 size; 534 }; 535 536 struct qmi_wlanfw_m3_info_resp_msg_v01 { 537 struct qmi_response_type_v01 resp; 538 }; 539 540 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 541 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 542 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 543 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 544 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 545 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 546 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 547 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 548 #define QMI_WLANFW_MAX_STR_LEN_V01 16 549 #define QMI_WLANFW_MAX_NUM_CE_V01 12 550 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 551 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 552 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 553 554 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 555 u32 mode; 556 u8 hw_debug_valid; 557 u8 hw_debug; 558 }; 559 560 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 561 struct qmi_response_type_v01 resp; 562 }; 563 564 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 565 u8 host_version_valid; 566 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 567 u8 tgt_cfg_valid; 568 u32 tgt_cfg_len; 569 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 570 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 571 u8 svc_cfg_valid; 572 u32 svc_cfg_len; 573 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 574 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 575 u8 shadow_reg_valid; 576 u32 shadow_reg_len; 577 struct qmi_wlanfw_shadow_reg_cfg_s_v01 578 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 579 u8 shadow_reg_v3_valid; 580 u32 shadow_reg_v3_len; 581 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 582 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 583 }; 584 585 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 586 struct qmi_response_type_v01 resp; 587 }; 588 589 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 590 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F 591 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 592 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7 593 594 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 595 /* Must be set to true if enable_fwlog is being passed */ 596 u8 enable_fwlog_valid; 597 u8 enable_fwlog; 598 }; 599 600 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 601 struct qmi_response_type_v01 resp; 602 }; 603 604 enum ath12k_qmi_mem_mode { 605 ATH12K_QMI_MEMORY_MODE_DEFAULT = 0, 606 ATH12K_QMI_MEMORY_MODE_LOW_512_M, 607 }; 608 609 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block) 610 { 611 lockdep_assert_held(&qmi->event_lock); 612 613 qmi->block_event = block; 614 } 615 616 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi) 617 { 618 lockdep_assert_held(&qmi->event_lock); 619 620 return qmi->block_event; 621 } 622 623 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 624 u32 mode); 625 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 626 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 627 int ath12k_qmi_init_service(struct ath12k_base *ab); 628 void ath12k_qmi_free_resource(struct ath12k_base *ab); 629 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab); 630 void ath12k_qmi_reset_mlo_mem(struct ath12k_hw_group *ag); 631 632 #endif 633