1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 22 23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 24 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 25 #define ATH12K_QMI_RESP_LEN_MAX 8192 26 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 27 #define ATH12K_QMI_CALDB_SIZE 0x480000 28 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 29 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 30 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 31 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 32 33 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 34 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 35 #define QMI_WLFW_FW_READY_IND_V01 0x0038 36 37 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 38 #define ATH12K_FIRMWARE_MODE_OFF 4 39 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 40 41 #define ATH12K_BOARD_ID_DEFAULT 0xFF 42 43 struct ath12k_base; 44 45 enum ath12k_qmi_file_type { 46 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 47 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 48 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 49 ATH12K_QMI_MAX_FILE_TYPE = 4, 50 }; 51 52 enum ath12k_qmi_bdf_type { 53 ATH12K_QMI_BDF_TYPE_BIN = 0, 54 ATH12K_QMI_BDF_TYPE_ELF = 1, 55 ATH12K_QMI_BDF_TYPE_REGDB = 4, 56 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 57 }; 58 59 enum ath12k_qmi_event_type { 60 ATH12K_QMI_EVENT_SERVER_ARRIVE, 61 ATH12K_QMI_EVENT_SERVER_EXIT, 62 ATH12K_QMI_EVENT_REQUEST_MEM, 63 ATH12K_QMI_EVENT_FW_MEM_READY, 64 ATH12K_QMI_EVENT_FW_READY, 65 ATH12K_QMI_EVENT_REGISTER_DRIVER, 66 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 67 ATH12K_QMI_EVENT_RECOVERY, 68 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 69 ATH12K_QMI_EVENT_POWER_UP, 70 ATH12K_QMI_EVENT_POWER_DOWN, 71 ATH12K_QMI_EVENT_MAX, 72 }; 73 74 struct ath12k_qmi_driver_event { 75 struct list_head list; 76 enum ath12k_qmi_event_type type; 77 void *data; 78 }; 79 80 struct ath12k_qmi_ce_cfg { 81 const struct ce_pipe_config *tgt_ce; 82 int tgt_ce_len; 83 const struct service_to_pipe *svc_to_ce_map; 84 int svc_to_ce_map_len; 85 const u8 *shadow_reg; 86 int shadow_reg_len; 87 u32 *shadow_reg_v3; 88 int shadow_reg_v3_len; 89 }; 90 91 struct ath12k_qmi_event_msg { 92 struct list_head list; 93 enum ath12k_qmi_event_type type; 94 }; 95 96 struct target_mem_chunk { 97 u32 size; 98 u32 type; 99 u32 prev_size; 100 u32 prev_type; 101 dma_addr_t paddr; 102 union { 103 void __iomem *ioaddr; 104 void *addr; 105 } v; 106 }; 107 108 struct target_info { 109 u32 chip_id; 110 u32 chip_family; 111 u32 board_id; 112 u32 soc_id; 113 u32 fw_version; 114 u32 eeprom_caldata; 115 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 116 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 117 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 118 }; 119 120 struct m3_mem_region { 121 u32 size; 122 dma_addr_t paddr; 123 void *vaddr; 124 }; 125 126 struct dev_mem_info { 127 u64 start; 128 u64 size; 129 }; 130 131 struct ath12k_qmi { 132 struct ath12k_base *ab; 133 struct qmi_handle handle; 134 struct sockaddr_qrtr sq; 135 struct work_struct event_work; 136 struct workqueue_struct *event_wq; 137 struct list_head event_list; 138 spinlock_t event_lock; /* spinlock for qmi event list */ 139 struct ath12k_qmi_ce_cfg ce_cfg; 140 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 141 u32 mem_seg_count; 142 u32 target_mem_mode; 143 bool target_mem_delayed; 144 u8 cal_done; 145 u8 num_radios; 146 struct target_info target; 147 struct m3_mem_region m3_mem; 148 unsigned int service_ins_id; 149 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 150 }; 151 152 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 153 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 154 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 155 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 156 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 157 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 158 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 159 160 struct qmi_wlanfw_host_ddr_range { 161 u64 start; 162 u64 size; 163 }; 164 165 enum ath12k_qmi_target_mem { 166 HOST_DDR_REGION_TYPE = 0x1, 167 BDF_MEM_REGION_TYPE = 0x2, 168 M3_DUMP_REGION_TYPE = 0x3, 169 CALDB_MEM_REGION_TYPE = 0x4, 170 PAGEABLE_MEM_REGION_TYPE = 0x9, 171 }; 172 173 enum qmi_wlanfw_host_build_type { 174 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 175 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 176 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 177 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 178 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 179 }; 180 181 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 182 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 183 184 struct wlfw_host_mlo_chip_info_s_v01 { 185 u8 chip_id; 186 u8 num_local_links; 187 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 188 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 189 }; 190 191 enum ath12k_qmi_cnss_feature { 192 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 193 CNSS_QDSS_CFG_MISS_V01 = 3, 194 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 195 CNSS_MAX_FEATURE_V01 = 64, 196 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 197 }; 198 199 struct qmi_wlanfw_host_cap_req_msg_v01 { 200 u8 num_clients_valid; 201 u32 num_clients; 202 u8 wake_msi_valid; 203 u32 wake_msi; 204 u8 gpios_valid; 205 u32 gpios_len; 206 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 207 u8 nm_modem_valid; 208 u8 nm_modem; 209 u8 bdf_support_valid; 210 u8 bdf_support; 211 u8 bdf_cache_support_valid; 212 u8 bdf_cache_support; 213 u8 m3_support_valid; 214 u8 m3_support; 215 u8 m3_cache_support_valid; 216 u8 m3_cache_support; 217 u8 cal_filesys_support_valid; 218 u8 cal_filesys_support; 219 u8 cal_cache_support_valid; 220 u8 cal_cache_support; 221 u8 cal_done_valid; 222 u8 cal_done; 223 u8 mem_bucket_valid; 224 u32 mem_bucket; 225 u8 mem_cfg_mode_valid; 226 u8 mem_cfg_mode; 227 u8 cal_duration_valid; 228 u16 cal_duraiton; 229 u8 platform_name_valid; 230 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 231 u8 ddr_range_valid; 232 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 233 u8 host_build_type_valid; 234 enum qmi_wlanfw_host_build_type host_build_type; 235 u8 mlo_capable_valid; 236 u8 mlo_capable; 237 u8 mlo_chip_id_valid; 238 u16 mlo_chip_id; 239 u8 mlo_group_id_valid; 240 u8 mlo_group_id; 241 u8 max_mlo_peer_valid; 242 u16 max_mlo_peer; 243 u8 mlo_num_chips_valid; 244 u8 mlo_num_chips; 245 u8 mlo_chip_info_valid; 246 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 247 u8 feature_list_valid; 248 u64 feature_list; 249 250 }; 251 252 struct qmi_wlanfw_host_cap_resp_msg_v01 { 253 struct qmi_response_type_v01 resp; 254 }; 255 256 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 257 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 258 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 259 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 260 261 struct qmi_wlanfw_phy_cap_req_msg_v01 { 262 }; 263 264 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 265 struct qmi_response_type_v01 resp; 266 u8 num_phy_valid; 267 u8 num_phy; 268 u8 board_id_valid; 269 u32 board_id; 270 u8 single_chip_mlo_support_valid; 271 u8 single_chip_mlo_support; 272 }; 273 274 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 275 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 276 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 277 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 278 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 279 280 struct qmi_wlanfw_ind_register_req_msg_v01 { 281 u8 fw_ready_enable_valid; 282 u8 fw_ready_enable; 283 u8 initiate_cal_download_enable_valid; 284 u8 initiate_cal_download_enable; 285 u8 initiate_cal_update_enable_valid; 286 u8 initiate_cal_update_enable; 287 u8 msa_ready_enable_valid; 288 u8 msa_ready_enable; 289 u8 pin_connect_result_enable_valid; 290 u8 pin_connect_result_enable; 291 u8 client_id_valid; 292 u32 client_id; 293 u8 request_mem_enable_valid; 294 u8 request_mem_enable; 295 u8 fw_mem_ready_enable_valid; 296 u8 fw_mem_ready_enable; 297 u8 fw_init_done_enable_valid; 298 u8 fw_init_done_enable; 299 u8 rejuvenate_enable_valid; 300 u32 rejuvenate_enable; 301 u8 xo_cal_enable_valid; 302 u8 xo_cal_enable; 303 u8 cal_done_enable_valid; 304 u8 cal_done_enable; 305 }; 306 307 struct qmi_wlanfw_ind_register_resp_msg_v01 { 308 struct qmi_response_type_v01 resp; 309 u8 fw_status_valid; 310 u64 fw_status; 311 }; 312 313 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 314 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 315 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 316 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 317 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 318 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 319 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 320 #define QMI_WLANFW_MAX_STR_LEN_V01 16 321 322 struct qmi_wlanfw_mem_cfg_s_v01 { 323 u64 offset; 324 u32 size; 325 u8 secure_flag; 326 }; 327 328 enum qmi_wlanfw_mem_type_enum_v01 { 329 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 330 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 331 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 332 QMI_WLANFW_MEM_BDF_V01 = 2, 333 QMI_WLANFW_MEM_M3_V01 = 3, 334 QMI_WLANFW_MEM_CAL_V01 = 4, 335 QMI_WLANFW_MEM_DPD_V01 = 5, 336 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 337 }; 338 339 struct qmi_wlanfw_mem_seg_s_v01 { 340 u32 size; 341 enum qmi_wlanfw_mem_type_enum_v01 type; 342 u32 mem_cfg_len; 343 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 344 }; 345 346 struct qmi_wlanfw_request_mem_ind_msg_v01 { 347 u32 mem_seg_len; 348 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 349 }; 350 351 struct qmi_wlanfw_mem_seg_resp_s_v01 { 352 u64 addr; 353 u32 size; 354 enum qmi_wlanfw_mem_type_enum_v01 type; 355 u8 restore; 356 }; 357 358 struct qmi_wlanfw_respond_mem_req_msg_v01 { 359 u32 mem_seg_len; 360 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 361 }; 362 363 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 364 struct qmi_response_type_v01 resp; 365 }; 366 367 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 368 char placeholder; 369 }; 370 371 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 372 char placeholder; 373 }; 374 375 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 376 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 377 #define QMI_WLANFW_CAP_REQ_V01 0x0024 378 #define QMI_WLANFW_CAP_RESP_V01 0x0024 379 380 enum qmi_wlanfw_pipedir_enum_v01 { 381 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 382 QMI_WLFW_PIPEDIR_IN_V01 = 1, 383 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 384 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 385 }; 386 387 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 388 __le32 pipe_num; 389 __le32 pipe_dir; 390 __le32 nentries; 391 __le32 nbytes_max; 392 __le32 flags; 393 }; 394 395 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 396 __le32 service_id; 397 __le32 pipe_dir; 398 __le32 pipe_num; 399 }; 400 401 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 402 u16 id; 403 u16 offset; 404 }; 405 406 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 407 u32 addr; 408 }; 409 410 struct qmi_wlanfw_memory_region_info_s_v01 { 411 u64 region_addr; 412 u32 size; 413 u8 secure_flag; 414 }; 415 416 struct qmi_wlanfw_rf_chip_info_s_v01 { 417 u32 chip_id; 418 u32 chip_family; 419 }; 420 421 struct qmi_wlanfw_rf_board_info_s_v01 { 422 u32 board_id; 423 }; 424 425 struct qmi_wlanfw_soc_info_s_v01 { 426 u32 soc_id; 427 }; 428 429 struct qmi_wlanfw_fw_version_info_s_v01 { 430 u32 fw_version; 431 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 432 }; 433 434 struct qmi_wlanfw_dev_mem_info_s_v01 { 435 u64 start; 436 u64 size; 437 }; 438 439 enum qmi_wlanfw_cal_temp_id_enum_v01 { 440 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 441 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 442 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 443 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 444 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 445 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 446 }; 447 448 enum qmi_wlanfw_rd_card_chain_cap_v01 { 449 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 450 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 451 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 452 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 453 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 454 }; 455 456 struct qmi_wlanfw_cap_resp_msg_v01 { 457 struct qmi_response_type_v01 resp; 458 u8 chip_info_valid; 459 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 460 u8 board_info_valid; 461 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 462 u8 soc_info_valid; 463 struct qmi_wlanfw_soc_info_s_v01 soc_info; 464 u8 fw_version_info_valid; 465 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 466 u8 fw_build_id_valid; 467 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 468 u8 num_macs_valid; 469 u8 num_macs; 470 u8 voltage_mv_valid; 471 u32 voltage_mv; 472 u8 time_freq_hz_valid; 473 u32 time_freq_hz; 474 u8 otp_version_valid; 475 u32 otp_version; 476 u8 eeprom_caldata_read_timeout_valid; 477 u32 eeprom_caldata_read_timeout; 478 u8 fw_caps_valid; 479 u64 fw_caps; 480 u8 rd_card_chain_cap_valid; 481 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 482 u8 dev_mem_info_valid; 483 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 484 }; 485 486 struct qmi_wlanfw_cap_req_msg_v01 { 487 char placeholder; 488 }; 489 490 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 491 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 492 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 493 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 494 /* TODO: Need to check with MCL and FW team that data can be pointer and 495 * can be last element in structure 496 */ 497 struct qmi_wlanfw_bdf_download_req_msg_v01 { 498 u8 valid; 499 u8 file_id_valid; 500 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 501 u8 total_size_valid; 502 u32 total_size; 503 u8 seg_id_valid; 504 u32 seg_id; 505 u8 data_valid; 506 u32 data_len; 507 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 508 u8 end_valid; 509 u8 end; 510 u8 bdf_type_valid; 511 u8 bdf_type; 512 513 }; 514 515 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 516 struct qmi_response_type_v01 resp; 517 }; 518 519 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 520 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 521 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 522 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 523 524 struct qmi_wlanfw_m3_info_req_msg_v01 { 525 u64 addr; 526 u32 size; 527 }; 528 529 struct qmi_wlanfw_m3_info_resp_msg_v01 { 530 struct qmi_response_type_v01 resp; 531 }; 532 533 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 534 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 535 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 536 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 537 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 538 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 539 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 540 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 541 #define QMI_WLANFW_MAX_STR_LEN_V01 16 542 #define QMI_WLANFW_MAX_NUM_CE_V01 12 543 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 544 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 545 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 546 547 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 548 u32 mode; 549 u8 hw_debug_valid; 550 u8 hw_debug; 551 }; 552 553 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 554 struct qmi_response_type_v01 resp; 555 }; 556 557 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 558 u8 host_version_valid; 559 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 560 u8 tgt_cfg_valid; 561 u32 tgt_cfg_len; 562 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 563 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 564 u8 svc_cfg_valid; 565 u32 svc_cfg_len; 566 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 567 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 568 u8 shadow_reg_valid; 569 u32 shadow_reg_len; 570 struct qmi_wlanfw_shadow_reg_cfg_s_v01 571 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 572 u8 shadow_reg_v3_valid; 573 u32 shadow_reg_v3_len; 574 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 575 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 576 }; 577 578 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 579 struct qmi_response_type_v01 resp; 580 }; 581 582 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 583 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F 584 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 585 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7 586 587 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 588 /* Must be set to true if enable_fwlog is being passed */ 589 u8 enable_fwlog_valid; 590 u8 enable_fwlog; 591 }; 592 593 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 594 struct qmi_response_type_v01 resp; 595 }; 596 597 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 598 u32 mode); 599 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 600 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 601 int ath12k_qmi_init_service(struct ath12k_base *ab); 602 void ath12k_qmi_free_resource(struct ath12k_base *ab); 603 604 #endif 605