1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 17 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 18 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 19 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 20 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 22 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332 0x2 23 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 24 #define ATH12K_QMI_RESP_LEN_MAX 8192 25 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 26 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 27 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 28 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 29 30 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 31 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 32 #define QMI_WLFW_FW_READY_IND_V01 0x0038 33 34 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 35 36 #define ATH12K_BOARD_ID_DEFAULT 0xFF 37 38 struct ath12k_base; 39 struct ath12k_hw_group; 40 41 enum ath12k_qmi_file_type { 42 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 43 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 44 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 45 ATH12K_QMI_MAX_FILE_TYPE = 4, 46 }; 47 48 enum ath12k_qmi_bdf_type { 49 ATH12K_QMI_BDF_TYPE_BIN = 0, 50 ATH12K_QMI_BDF_TYPE_ELF = 1, 51 ATH12K_QMI_BDF_TYPE_REGDB = 4, 52 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 53 }; 54 55 enum ath12k_qmi_event_type { 56 ATH12K_QMI_EVENT_SERVER_ARRIVE, 57 ATH12K_QMI_EVENT_SERVER_EXIT, 58 ATH12K_QMI_EVENT_REQUEST_MEM, 59 ATH12K_QMI_EVENT_FW_MEM_READY, 60 ATH12K_QMI_EVENT_FW_READY, 61 ATH12K_QMI_EVENT_REGISTER_DRIVER, 62 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 63 ATH12K_QMI_EVENT_RECOVERY, 64 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 65 ATH12K_QMI_EVENT_POWER_UP, 66 ATH12K_QMI_EVENT_POWER_DOWN, 67 ATH12K_QMI_EVENT_HOST_CAP, 68 ATH12K_QMI_EVENT_MAX, 69 }; 70 71 struct ath12k_qmi_driver_event { 72 struct list_head list; 73 enum ath12k_qmi_event_type type; 74 void *data; 75 }; 76 77 struct ath12k_qmi_ce_cfg { 78 const struct ce_pipe_config *tgt_ce; 79 int tgt_ce_len; 80 const struct service_to_pipe *svc_to_ce_map; 81 int svc_to_ce_map_len; 82 const u8 *shadow_reg; 83 int shadow_reg_len; 84 u32 *shadow_reg_v3; 85 int shadow_reg_v3_len; 86 }; 87 88 struct ath12k_qmi_event_msg { 89 struct list_head list; 90 enum ath12k_qmi_event_type type; 91 }; 92 93 struct target_mem_chunk { 94 u32 size; 95 u32 type; 96 u32 prev_size; 97 u32 prev_type; 98 dma_addr_t paddr; 99 union { 100 void __iomem *ioaddr; 101 void *addr; 102 } v; 103 }; 104 105 struct target_info { 106 u32 chip_id; 107 u32 chip_family; 108 u32 board_id; 109 u32 soc_id; 110 u32 fw_version; 111 u32 eeprom_caldata; 112 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 113 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 114 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 115 }; 116 117 struct m3_mem_region { 118 /* total memory allocated */ 119 u32 total_size; 120 /* actual memory being used */ 121 u32 size; 122 dma_addr_t paddr; 123 void *vaddr; 124 }; 125 126 struct dev_mem_info { 127 u64 start; 128 u64 size; 129 }; 130 131 struct ath12k_qmi { 132 struct ath12k_base *ab; 133 struct qmi_handle handle; 134 struct sockaddr_qrtr sq; 135 struct work_struct event_work; 136 struct workqueue_struct *event_wq; 137 struct list_head event_list; 138 spinlock_t event_lock; /* spinlock for qmi event list */ 139 struct ath12k_qmi_ce_cfg ce_cfg; 140 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 141 u32 mem_seg_count; 142 u32 target_mem_mode; 143 bool target_mem_delayed; 144 u8 cal_done; 145 146 /* protected with struct ath12k_qmi::event_lock */ 147 bool block_event; 148 149 u8 num_radios; 150 struct target_info target; 151 struct m3_mem_region m3_mem; 152 struct m3_mem_region aux_uc_mem; 153 unsigned int service_ins_id; 154 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 155 u8 dynamic_ddr_support; 156 }; 157 158 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 265 159 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 160 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 161 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 162 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 163 164 struct qmi_wlanfw_host_ddr_range { 165 u64 start; 166 u64 size; 167 }; 168 169 enum ath12k_qmi_target_mem { 170 HOST_DDR_REGION_TYPE = 0x1, 171 BDF_MEM_REGION_TYPE = 0x2, 172 M3_DUMP_REGION_TYPE = 0x3, 173 CALDB_MEM_REGION_TYPE = 0x4, 174 MLO_GLOBAL_MEM_REGION_TYPE = 0x8, 175 PAGEABLE_MEM_REGION_TYPE = 0x9, 176 LPASS_SHARED_V01_REGION_TYPE = 0xb, 177 }; 178 179 enum qmi_wlanfw_host_build_type { 180 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 181 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 182 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 183 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 184 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 185 }; 186 187 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 188 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 189 190 struct wlfw_host_mlo_chip_info_s_v01 { 191 u8 chip_id; 192 u8 num_local_links; 193 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 194 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 195 }; 196 197 enum ath12k_qmi_cnss_feature { 198 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 199 CNSS_QDSS_CFG_MISS_V01 = 3, 200 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 201 CNSS_AUX_UC_SUPPORT_V01 = 6, 202 CNSS_MAX_FEATURE_V01 = 64, 203 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 204 }; 205 206 struct qmi_wlanfw_host_cap_req_msg_v01 { 207 u8 num_clients_valid; 208 u32 num_clients; 209 u8 wake_msi_valid; 210 u32 wake_msi; 211 u8 gpios_valid; 212 u32 gpios_len; 213 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 214 u8 nm_modem_valid; 215 u8 nm_modem; 216 u8 bdf_support_valid; 217 u8 bdf_support; 218 u8 bdf_cache_support_valid; 219 u8 bdf_cache_support; 220 u8 m3_support_valid; 221 u8 m3_support; 222 u8 m3_cache_support_valid; 223 u8 m3_cache_support; 224 u8 cal_filesys_support_valid; 225 u8 cal_filesys_support; 226 u8 cal_cache_support_valid; 227 u8 cal_cache_support; 228 u8 cal_done_valid; 229 u8 cal_done; 230 u8 mem_bucket_valid; 231 u32 mem_bucket; 232 u8 mem_cfg_mode_valid; 233 u8 mem_cfg_mode; 234 u8 cal_duration_valid; 235 u16 cal_duraiton; 236 u8 platform_name_valid; 237 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 238 u8 ddr_range_valid; 239 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 240 u8 host_build_type_valid; 241 enum qmi_wlanfw_host_build_type host_build_type; 242 u8 mlo_capable_valid; 243 u8 mlo_capable; 244 u8 mlo_chip_id_valid; 245 u16 mlo_chip_id; 246 u8 mlo_group_id_valid; 247 u8 mlo_group_id; 248 u8 max_mlo_peer_valid; 249 u16 max_mlo_peer; 250 u8 mlo_num_chips_valid; 251 u8 mlo_num_chips; 252 u8 mlo_chip_info_valid; 253 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 254 u8 feature_list_valid; 255 u64 feature_list; 256 u8 dynamic_mem_support_valid; 257 u8 dynamic_mem_support; 258 }; 259 260 struct qmi_wlanfw_host_cap_resp_msg_v01 { 261 struct qmi_response_type_v01 resp; 262 }; 263 264 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 265 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 266 267 struct qmi_wlanfw_phy_cap_req_msg_v01 { 268 }; 269 270 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 271 struct qmi_response_type_v01 resp; 272 u8 num_phy_valid; 273 u8 num_phy; 274 u8 board_id_valid; 275 u32 board_id; 276 u8 single_chip_mlo_support_valid; 277 u8 single_chip_mlo_support; 278 u8 dynamic_ddr_support_valid; 279 u8 dynamic_ddr_support; 280 }; 281 282 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 283 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 284 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 285 286 struct qmi_wlanfw_ind_register_req_msg_v01 { 287 u8 fw_ready_enable_valid; 288 u8 fw_ready_enable; 289 u8 initiate_cal_download_enable_valid; 290 u8 initiate_cal_download_enable; 291 u8 initiate_cal_update_enable_valid; 292 u8 initiate_cal_update_enable; 293 u8 msa_ready_enable_valid; 294 u8 msa_ready_enable; 295 u8 pin_connect_result_enable_valid; 296 u8 pin_connect_result_enable; 297 u8 client_id_valid; 298 u32 client_id; 299 u8 request_mem_enable_valid; 300 u8 request_mem_enable; 301 u8 fw_mem_ready_enable_valid; 302 u8 fw_mem_ready_enable; 303 u8 fw_init_done_enable_valid; 304 u8 fw_init_done_enable; 305 u8 rejuvenate_enable_valid; 306 u32 rejuvenate_enable; 307 u8 xo_cal_enable_valid; 308 u8 xo_cal_enable; 309 u8 cal_done_enable_valid; 310 u8 cal_done_enable; 311 }; 312 313 struct qmi_wlanfw_ind_register_resp_msg_v01 { 314 struct qmi_response_type_v01 resp; 315 u8 fw_status_valid; 316 u64 fw_status; 317 }; 318 319 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 320 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 321 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 322 #define QMI_WLANFW_MAX_STR_LEN_V01 16 323 324 struct qmi_wlanfw_mem_cfg_s_v01 { 325 u64 offset; 326 u32 size; 327 u8 secure_flag; 328 }; 329 330 enum qmi_wlanfw_mem_type_enum_v01 { 331 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 332 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 333 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 334 QMI_WLANFW_MEM_BDF_V01 = 2, 335 QMI_WLANFW_MEM_M3_V01 = 3, 336 QMI_WLANFW_MEM_CAL_V01 = 4, 337 QMI_WLANFW_MEM_DPD_V01 = 5, 338 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 339 }; 340 341 struct qmi_wlanfw_mem_seg_s_v01 { 342 u32 size; 343 enum qmi_wlanfw_mem_type_enum_v01 type; 344 u32 mem_cfg_len; 345 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 346 }; 347 348 struct qmi_wlanfw_request_mem_ind_msg_v01 { 349 u32 mem_seg_len; 350 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 351 }; 352 353 struct qmi_wlanfw_mem_seg_resp_s_v01 { 354 u64 addr; 355 u32 size; 356 enum qmi_wlanfw_mem_type_enum_v01 type; 357 u8 restore; 358 }; 359 360 struct qmi_wlanfw_respond_mem_req_msg_v01 { 361 u32 mem_seg_len; 362 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 363 }; 364 365 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 366 struct qmi_response_type_v01 resp; 367 }; 368 369 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 370 char placeholder; 371 }; 372 373 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 374 char placeholder; 375 }; 376 377 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 378 #define QMI_WLANFW_CAP_REQ_V01 0x0024 379 380 enum qmi_wlanfw_pipedir_enum_v01 { 381 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 382 QMI_WLFW_PIPEDIR_IN_V01 = 1, 383 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 384 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 385 }; 386 387 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 388 u32 pipe_num; 389 u32 pipe_dir; 390 u32 nentries; 391 u32 nbytes_max; 392 u32 flags; 393 }; 394 395 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 396 u32 service_id; 397 u32 pipe_dir; 398 u32 pipe_num; 399 }; 400 401 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 402 u16 id; 403 u16 offset; 404 }; 405 406 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 407 u32 addr; 408 }; 409 410 struct qmi_wlanfw_memory_region_info_s_v01 { 411 u64 region_addr; 412 u32 size; 413 u8 secure_flag; 414 }; 415 416 struct qmi_wlanfw_rf_chip_info_s_v01 { 417 u32 chip_id; 418 u32 chip_family; 419 }; 420 421 struct qmi_wlanfw_rf_board_info_s_v01 { 422 u32 board_id; 423 }; 424 425 struct qmi_wlanfw_soc_info_s_v01 { 426 u32 soc_id; 427 }; 428 429 struct qmi_wlanfw_fw_version_info_s_v01 { 430 u32 fw_version; 431 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 432 }; 433 434 struct qmi_wlanfw_dev_mem_info_s_v01 { 435 u64 start; 436 u64 size; 437 }; 438 439 enum qmi_wlanfw_cal_temp_id_enum_v01 { 440 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 441 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 442 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 443 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 444 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 445 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 446 }; 447 448 enum qmi_wlanfw_rd_card_chain_cap_v01 { 449 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 450 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 451 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 452 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 453 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 454 }; 455 456 struct qmi_wlanfw_cap_resp_msg_v01 { 457 struct qmi_response_type_v01 resp; 458 u8 chip_info_valid; 459 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 460 u8 board_info_valid; 461 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 462 u8 soc_info_valid; 463 struct qmi_wlanfw_soc_info_s_v01 soc_info; 464 u8 fw_version_info_valid; 465 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 466 u8 fw_build_id_valid; 467 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 468 u8 num_macs_valid; 469 u8 num_macs; 470 u8 voltage_mv_valid; 471 u32 voltage_mv; 472 u8 time_freq_hz_valid; 473 u32 time_freq_hz; 474 u8 otp_version_valid; 475 u32 otp_version; 476 u8 eeprom_caldata_read_timeout_valid; 477 u32 eeprom_caldata_read_timeout; 478 u8 fw_caps_valid; 479 u64 fw_caps; 480 u8 rd_card_chain_cap_valid; 481 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 482 u8 dev_mem_info_valid; 483 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 484 }; 485 486 struct qmi_wlanfw_cap_req_msg_v01 { 487 char placeholder; 488 }; 489 490 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 491 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 492 /* TODO: Need to check with MCL and FW team that data can be pointer and 493 * can be last element in structure 494 */ 495 struct qmi_wlanfw_bdf_download_req_msg_v01 { 496 u8 valid; 497 u8 file_id_valid; 498 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 499 u8 total_size_valid; 500 u32 total_size; 501 u8 seg_id_valid; 502 u32 seg_id; 503 u8 data_valid; 504 u32 data_len; 505 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 506 u8 end_valid; 507 u8 end; 508 u8 bdf_type_valid; 509 u8 bdf_type; 510 511 }; 512 513 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 514 struct qmi_response_type_v01 resp; 515 }; 516 517 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 518 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 519 520 struct qmi_wlanfw_m3_info_req_msg_v01 { 521 u64 addr; 522 u32 size; 523 }; 524 525 struct qmi_wlanfw_m3_info_resp_msg_v01 { 526 struct qmi_response_type_v01 resp; 527 }; 528 529 #define QMI_WLANFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 530 #define QMI_WLANFW_AUX_UC_INFO_REQ_V01 0x005A 531 532 struct qmi_wlanfw_aux_uc_info_req_msg_v01 { 533 u64 addr; 534 u32 size; 535 }; 536 537 struct qmi_wlanfw_aux_uc_info_resp_msg_v01 { 538 struct qmi_response_type_v01 resp; 539 }; 540 541 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 542 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 543 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 544 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 545 #define QMI_WLANFW_MAX_STR_LEN_V01 16 546 #define QMI_WLANFW_MAX_NUM_CE_V01 12 547 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 548 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 549 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 550 551 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 552 u32 mode; 553 u8 hw_debug_valid; 554 u8 hw_debug; 555 }; 556 557 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 558 struct qmi_response_type_v01 resp; 559 }; 560 561 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 562 u8 host_version_valid; 563 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 564 u8 tgt_cfg_valid; 565 u32 tgt_cfg_len; 566 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 567 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 568 u8 svc_cfg_valid; 569 u32 svc_cfg_len; 570 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 571 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 572 u8 shadow_reg_valid; 573 u32 shadow_reg_len; 574 struct qmi_wlanfw_shadow_reg_cfg_s_v01 575 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 576 u8 shadow_reg_v3_valid; 577 u32 shadow_reg_v3_len; 578 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 579 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 580 }; 581 582 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 583 struct qmi_response_type_v01 resp; 584 }; 585 586 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 587 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 588 589 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 590 /* Must be set to true if enable_fwlog is being passed */ 591 u8 enable_fwlog_valid; 592 u8 enable_fwlog; 593 }; 594 595 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 596 struct qmi_response_type_v01 resp; 597 }; 598 599 enum ath12k_qmi_mem_mode { 600 ATH12K_QMI_MEMORY_MODE_DEFAULT = 0, 601 ATH12K_QMI_MEMORY_MODE_LOW_512_M, 602 }; 603 604 enum ath12k_qmi_firmware_mode { 605 /* the default mode, standard 802.11 functionality */ 606 ATH12K_QMI_FIRMWARE_MODE_NORMAL, 607 608 /* factory tests etc */ 609 ATH12K_QMI_FIRMWARE_MODE_FTM, 610 611 /* firmware offline; values 2-3 reserved by firmware ABI */ 612 ATH12K_QMI_FIRMWARE_MODE_OFF = 4, 613 }; 614 615 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block) 616 { 617 lockdep_assert_held(&qmi->event_lock); 618 619 qmi->block_event = block; 620 } 621 622 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi) 623 { 624 lockdep_assert_held(&qmi->event_lock); 625 626 return qmi->block_event; 627 } 628 629 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 630 enum ath12k_qmi_firmware_mode mode); 631 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 632 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 633 int ath12k_qmi_init_service(struct ath12k_base *ab); 634 void ath12k_qmi_free_resource(struct ath12k_base *ab); 635 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab); 636 void ath12k_qmi_reset_mlo_mem(struct ath12k_hw_group *ag); 637 638 #endif 639