1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 22 23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 24 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 25 #define ATH12K_QMI_RESP_LEN_MAX 8192 26 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 27 #define ATH12K_QMI_CALDB_SIZE 0x480000 28 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 29 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 30 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 31 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 32 33 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 34 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 35 #define QMI_WLFW_FW_READY_IND_V01 0x0038 36 37 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 38 #define ATH12K_FIRMWARE_MODE_OFF 4 39 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 40 41 #define ATH12K_BOARD_ID_DEFAULT 0xFF 42 43 struct ath12k_base; 44 45 enum ath12k_qmi_file_type { 46 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 47 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 48 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 49 ATH12K_QMI_MAX_FILE_TYPE = 4, 50 }; 51 52 enum ath12k_qmi_bdf_type { 53 ATH12K_QMI_BDF_TYPE_BIN = 0, 54 ATH12K_QMI_BDF_TYPE_ELF = 1, 55 ATH12K_QMI_BDF_TYPE_REGDB = 4, 56 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 57 }; 58 59 enum ath12k_qmi_event_type { 60 ATH12K_QMI_EVENT_SERVER_ARRIVE, 61 ATH12K_QMI_EVENT_SERVER_EXIT, 62 ATH12K_QMI_EVENT_REQUEST_MEM, 63 ATH12K_QMI_EVENT_FW_MEM_READY, 64 ATH12K_QMI_EVENT_FW_READY, 65 ATH12K_QMI_EVENT_REGISTER_DRIVER, 66 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 67 ATH12K_QMI_EVENT_RECOVERY, 68 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 69 ATH12K_QMI_EVENT_POWER_UP, 70 ATH12K_QMI_EVENT_POWER_DOWN, 71 ATH12K_QMI_EVENT_HOST_CAP, 72 ATH12K_QMI_EVENT_MAX, 73 }; 74 75 struct ath12k_qmi_driver_event { 76 struct list_head list; 77 enum ath12k_qmi_event_type type; 78 void *data; 79 }; 80 81 struct ath12k_qmi_ce_cfg { 82 const struct ce_pipe_config *tgt_ce; 83 int tgt_ce_len; 84 const struct service_to_pipe *svc_to_ce_map; 85 int svc_to_ce_map_len; 86 const u8 *shadow_reg; 87 int shadow_reg_len; 88 u32 *shadow_reg_v3; 89 int shadow_reg_v3_len; 90 }; 91 92 struct ath12k_qmi_event_msg { 93 struct list_head list; 94 enum ath12k_qmi_event_type type; 95 }; 96 97 struct target_mem_chunk { 98 u32 size; 99 u32 type; 100 u32 prev_size; 101 u32 prev_type; 102 dma_addr_t paddr; 103 union { 104 void __iomem *ioaddr; 105 void *addr; 106 } v; 107 }; 108 109 struct target_info { 110 u32 chip_id; 111 u32 chip_family; 112 u32 board_id; 113 u32 soc_id; 114 u32 fw_version; 115 u32 eeprom_caldata; 116 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 117 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 118 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 119 }; 120 121 struct m3_mem_region { 122 u32 size; 123 dma_addr_t paddr; 124 void *vaddr; 125 }; 126 127 struct dev_mem_info { 128 u64 start; 129 u64 size; 130 }; 131 132 struct ath12k_qmi { 133 struct ath12k_base *ab; 134 struct qmi_handle handle; 135 struct sockaddr_qrtr sq; 136 struct work_struct event_work; 137 struct workqueue_struct *event_wq; 138 struct list_head event_list; 139 spinlock_t event_lock; /* spinlock for qmi event list */ 140 struct ath12k_qmi_ce_cfg ce_cfg; 141 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 142 u32 mem_seg_count; 143 u32 target_mem_mode; 144 bool target_mem_delayed; 145 u8 cal_done; 146 147 /* protected with struct ath12k_qmi::event_lock */ 148 bool block_event; 149 150 u8 num_radios; 151 struct target_info target; 152 struct m3_mem_region m3_mem; 153 unsigned int service_ins_id; 154 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 155 }; 156 157 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 158 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 159 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 160 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 161 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 162 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 163 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 164 165 struct qmi_wlanfw_host_ddr_range { 166 u64 start; 167 u64 size; 168 }; 169 170 enum ath12k_qmi_target_mem { 171 HOST_DDR_REGION_TYPE = 0x1, 172 BDF_MEM_REGION_TYPE = 0x2, 173 M3_DUMP_REGION_TYPE = 0x3, 174 CALDB_MEM_REGION_TYPE = 0x4, 175 PAGEABLE_MEM_REGION_TYPE = 0x9, 176 }; 177 178 enum qmi_wlanfw_host_build_type { 179 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 180 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 181 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 182 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 183 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 184 }; 185 186 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 187 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 188 189 struct wlfw_host_mlo_chip_info_s_v01 { 190 u8 chip_id; 191 u8 num_local_links; 192 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 193 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 194 }; 195 196 enum ath12k_qmi_cnss_feature { 197 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 198 CNSS_QDSS_CFG_MISS_V01 = 3, 199 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 200 CNSS_MAX_FEATURE_V01 = 64, 201 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 202 }; 203 204 struct qmi_wlanfw_host_cap_req_msg_v01 { 205 u8 num_clients_valid; 206 u32 num_clients; 207 u8 wake_msi_valid; 208 u32 wake_msi; 209 u8 gpios_valid; 210 u32 gpios_len; 211 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 212 u8 nm_modem_valid; 213 u8 nm_modem; 214 u8 bdf_support_valid; 215 u8 bdf_support; 216 u8 bdf_cache_support_valid; 217 u8 bdf_cache_support; 218 u8 m3_support_valid; 219 u8 m3_support; 220 u8 m3_cache_support_valid; 221 u8 m3_cache_support; 222 u8 cal_filesys_support_valid; 223 u8 cal_filesys_support; 224 u8 cal_cache_support_valid; 225 u8 cal_cache_support; 226 u8 cal_done_valid; 227 u8 cal_done; 228 u8 mem_bucket_valid; 229 u32 mem_bucket; 230 u8 mem_cfg_mode_valid; 231 u8 mem_cfg_mode; 232 u8 cal_duration_valid; 233 u16 cal_duraiton; 234 u8 platform_name_valid; 235 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 236 u8 ddr_range_valid; 237 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 238 u8 host_build_type_valid; 239 enum qmi_wlanfw_host_build_type host_build_type; 240 u8 mlo_capable_valid; 241 u8 mlo_capable; 242 u8 mlo_chip_id_valid; 243 u16 mlo_chip_id; 244 u8 mlo_group_id_valid; 245 u8 mlo_group_id; 246 u8 max_mlo_peer_valid; 247 u16 max_mlo_peer; 248 u8 mlo_num_chips_valid; 249 u8 mlo_num_chips; 250 u8 mlo_chip_info_valid; 251 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 252 u8 feature_list_valid; 253 u64 feature_list; 254 255 }; 256 257 struct qmi_wlanfw_host_cap_resp_msg_v01 { 258 struct qmi_response_type_v01 resp; 259 }; 260 261 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 262 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 263 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 264 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 265 266 struct qmi_wlanfw_phy_cap_req_msg_v01 { 267 }; 268 269 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 270 struct qmi_response_type_v01 resp; 271 u8 num_phy_valid; 272 u8 num_phy; 273 u8 board_id_valid; 274 u32 board_id; 275 u8 single_chip_mlo_support_valid; 276 u8 single_chip_mlo_support; 277 }; 278 279 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 280 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 281 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 282 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 283 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 284 285 struct qmi_wlanfw_ind_register_req_msg_v01 { 286 u8 fw_ready_enable_valid; 287 u8 fw_ready_enable; 288 u8 initiate_cal_download_enable_valid; 289 u8 initiate_cal_download_enable; 290 u8 initiate_cal_update_enable_valid; 291 u8 initiate_cal_update_enable; 292 u8 msa_ready_enable_valid; 293 u8 msa_ready_enable; 294 u8 pin_connect_result_enable_valid; 295 u8 pin_connect_result_enable; 296 u8 client_id_valid; 297 u32 client_id; 298 u8 request_mem_enable_valid; 299 u8 request_mem_enable; 300 u8 fw_mem_ready_enable_valid; 301 u8 fw_mem_ready_enable; 302 u8 fw_init_done_enable_valid; 303 u8 fw_init_done_enable; 304 u8 rejuvenate_enable_valid; 305 u32 rejuvenate_enable; 306 u8 xo_cal_enable_valid; 307 u8 xo_cal_enable; 308 u8 cal_done_enable_valid; 309 u8 cal_done_enable; 310 }; 311 312 struct qmi_wlanfw_ind_register_resp_msg_v01 { 313 struct qmi_response_type_v01 resp; 314 u8 fw_status_valid; 315 u64 fw_status; 316 }; 317 318 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 319 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 320 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 321 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 322 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 323 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 324 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 325 #define QMI_WLANFW_MAX_STR_LEN_V01 16 326 327 struct qmi_wlanfw_mem_cfg_s_v01 { 328 u64 offset; 329 u32 size; 330 u8 secure_flag; 331 }; 332 333 enum qmi_wlanfw_mem_type_enum_v01 { 334 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 335 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 336 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 337 QMI_WLANFW_MEM_BDF_V01 = 2, 338 QMI_WLANFW_MEM_M3_V01 = 3, 339 QMI_WLANFW_MEM_CAL_V01 = 4, 340 QMI_WLANFW_MEM_DPD_V01 = 5, 341 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 342 }; 343 344 struct qmi_wlanfw_mem_seg_s_v01 { 345 u32 size; 346 enum qmi_wlanfw_mem_type_enum_v01 type; 347 u32 mem_cfg_len; 348 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 349 }; 350 351 struct qmi_wlanfw_request_mem_ind_msg_v01 { 352 u32 mem_seg_len; 353 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 354 }; 355 356 struct qmi_wlanfw_mem_seg_resp_s_v01 { 357 u64 addr; 358 u32 size; 359 enum qmi_wlanfw_mem_type_enum_v01 type; 360 u8 restore; 361 }; 362 363 struct qmi_wlanfw_respond_mem_req_msg_v01 { 364 u32 mem_seg_len; 365 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 366 }; 367 368 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 369 struct qmi_response_type_v01 resp; 370 }; 371 372 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 373 char placeholder; 374 }; 375 376 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 377 char placeholder; 378 }; 379 380 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 381 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 382 #define QMI_WLANFW_CAP_REQ_V01 0x0024 383 #define QMI_WLANFW_CAP_RESP_V01 0x0024 384 385 enum qmi_wlanfw_pipedir_enum_v01 { 386 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 387 QMI_WLFW_PIPEDIR_IN_V01 = 1, 388 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 389 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 390 }; 391 392 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 393 __le32 pipe_num; 394 __le32 pipe_dir; 395 __le32 nentries; 396 __le32 nbytes_max; 397 __le32 flags; 398 }; 399 400 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 401 __le32 service_id; 402 __le32 pipe_dir; 403 __le32 pipe_num; 404 }; 405 406 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 407 u16 id; 408 u16 offset; 409 }; 410 411 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 412 u32 addr; 413 }; 414 415 struct qmi_wlanfw_memory_region_info_s_v01 { 416 u64 region_addr; 417 u32 size; 418 u8 secure_flag; 419 }; 420 421 struct qmi_wlanfw_rf_chip_info_s_v01 { 422 u32 chip_id; 423 u32 chip_family; 424 }; 425 426 struct qmi_wlanfw_rf_board_info_s_v01 { 427 u32 board_id; 428 }; 429 430 struct qmi_wlanfw_soc_info_s_v01 { 431 u32 soc_id; 432 }; 433 434 struct qmi_wlanfw_fw_version_info_s_v01 { 435 u32 fw_version; 436 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 437 }; 438 439 struct qmi_wlanfw_dev_mem_info_s_v01 { 440 u64 start; 441 u64 size; 442 }; 443 444 enum qmi_wlanfw_cal_temp_id_enum_v01 { 445 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 446 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 447 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 448 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 449 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 450 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 451 }; 452 453 enum qmi_wlanfw_rd_card_chain_cap_v01 { 454 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 455 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 456 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 457 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 458 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 459 }; 460 461 struct qmi_wlanfw_cap_resp_msg_v01 { 462 struct qmi_response_type_v01 resp; 463 u8 chip_info_valid; 464 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 465 u8 board_info_valid; 466 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 467 u8 soc_info_valid; 468 struct qmi_wlanfw_soc_info_s_v01 soc_info; 469 u8 fw_version_info_valid; 470 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 471 u8 fw_build_id_valid; 472 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 473 u8 num_macs_valid; 474 u8 num_macs; 475 u8 voltage_mv_valid; 476 u32 voltage_mv; 477 u8 time_freq_hz_valid; 478 u32 time_freq_hz; 479 u8 otp_version_valid; 480 u32 otp_version; 481 u8 eeprom_caldata_read_timeout_valid; 482 u32 eeprom_caldata_read_timeout; 483 u8 fw_caps_valid; 484 u64 fw_caps; 485 u8 rd_card_chain_cap_valid; 486 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 487 u8 dev_mem_info_valid; 488 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 489 }; 490 491 struct qmi_wlanfw_cap_req_msg_v01 { 492 char placeholder; 493 }; 494 495 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 496 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 497 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 498 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 499 /* TODO: Need to check with MCL and FW team that data can be pointer and 500 * can be last element in structure 501 */ 502 struct qmi_wlanfw_bdf_download_req_msg_v01 { 503 u8 valid; 504 u8 file_id_valid; 505 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 506 u8 total_size_valid; 507 u32 total_size; 508 u8 seg_id_valid; 509 u32 seg_id; 510 u8 data_valid; 511 u32 data_len; 512 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 513 u8 end_valid; 514 u8 end; 515 u8 bdf_type_valid; 516 u8 bdf_type; 517 518 }; 519 520 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 521 struct qmi_response_type_v01 resp; 522 }; 523 524 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 525 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 526 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 527 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 528 529 struct qmi_wlanfw_m3_info_req_msg_v01 { 530 u64 addr; 531 u32 size; 532 }; 533 534 struct qmi_wlanfw_m3_info_resp_msg_v01 { 535 struct qmi_response_type_v01 resp; 536 }; 537 538 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 539 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 540 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 541 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 542 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 543 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 544 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 545 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 546 #define QMI_WLANFW_MAX_STR_LEN_V01 16 547 #define QMI_WLANFW_MAX_NUM_CE_V01 12 548 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 549 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 550 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 551 552 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 553 u32 mode; 554 u8 hw_debug_valid; 555 u8 hw_debug; 556 }; 557 558 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 559 struct qmi_response_type_v01 resp; 560 }; 561 562 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 563 u8 host_version_valid; 564 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 565 u8 tgt_cfg_valid; 566 u32 tgt_cfg_len; 567 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 568 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 569 u8 svc_cfg_valid; 570 u32 svc_cfg_len; 571 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 572 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 573 u8 shadow_reg_valid; 574 u32 shadow_reg_len; 575 struct qmi_wlanfw_shadow_reg_cfg_s_v01 576 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 577 u8 shadow_reg_v3_valid; 578 u32 shadow_reg_v3_len; 579 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 580 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 581 }; 582 583 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 584 struct qmi_response_type_v01 resp; 585 }; 586 587 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 588 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F 589 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 590 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7 591 592 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 593 /* Must be set to true if enable_fwlog is being passed */ 594 u8 enable_fwlog_valid; 595 u8 enable_fwlog; 596 }; 597 598 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 599 struct qmi_response_type_v01 resp; 600 }; 601 602 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block) 603 { 604 lockdep_assert_held(&qmi->event_lock); 605 606 qmi->block_event = block; 607 } 608 609 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi) 610 { 611 lockdep_assert_held(&qmi->event_lock); 612 613 return qmi->block_event; 614 } 615 616 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 617 u32 mode); 618 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 619 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 620 int ath12k_qmi_init_service(struct ath12k_base *ab); 621 void ath12k_qmi_free_resource(struct ath12k_base *ab); 622 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab); 623 624 #endif 625