1d8899132SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2d8899132SKalle Valo /* 3d8899132SKalle Valo * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4d8899132SKalle Valo * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5d8899132SKalle Valo */ 6d8899132SKalle Valo 7d8899132SKalle Valo #ifndef ATH12K_QMI_H 8d8899132SKalle Valo #define ATH12K_QMI_H 9d8899132SKalle Valo 10d8899132SKalle Valo #include <linux/mutex.h> 11d8899132SKalle Valo #include <linux/soc/qcom/qmi.h> 12d8899132SKalle Valo 13d8899132SKalle Valo #define ATH12K_HOST_VERSION_STRING "WIN" 14d8899132SKalle Valo #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15d8899132SKalle Valo #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16d8899132SKalle Valo #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 17d8899132SKalle Valo #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18d8899132SKalle Valo #define ATH12K_QMI_WLFW_NODE_ID_BASE 0x07 19d8899132SKalle Valo #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 20d8899132SKalle Valo #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 21d8899132SKalle Valo #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 22d8899132SKalle Valo #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 23d8899132SKalle Valo 24d8899132SKalle Valo #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 25d8899132SKalle Valo #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 26d8899132SKalle Valo #define ATH12K_QMI_RESP_LEN_MAX 8192 27d8899132SKalle Valo #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 28d8899132SKalle Valo #define ATH12K_QMI_CALDB_SIZE 0x480000 29d8899132SKalle Valo #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 30d8899132SKalle Valo #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 31d8899132SKalle Valo #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 32d8899132SKalle Valo #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 33d8899132SKalle Valo 34d8899132SKalle Valo #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 35d8899132SKalle Valo #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 36d8899132SKalle Valo #define QMI_WLFW_FW_READY_IND_V01 0x0038 37d8899132SKalle Valo 38d8899132SKalle Valo #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 39d8899132SKalle Valo #define ATH12K_FIRMWARE_MODE_OFF 4 40d8899132SKalle Valo #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 41d8899132SKalle Valo 42d8899132SKalle Valo #define ATH12K_BOARD_ID_DEFAULT 0xFF 43d8899132SKalle Valo 44d8899132SKalle Valo struct ath12k_base; 45d8899132SKalle Valo 46d8899132SKalle Valo enum ath12k_qmi_file_type { 4727d7e348SDinesh Karthikeyan ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 4827d7e348SDinesh Karthikeyan ATH12K_QMI_FILE_TYPE_CALDATA = 2, 4927d7e348SDinesh Karthikeyan ATH12K_QMI_FILE_TYPE_EEPROM = 3, 5027d7e348SDinesh Karthikeyan ATH12K_QMI_MAX_FILE_TYPE = 4, 51d8899132SKalle Valo }; 52d8899132SKalle Valo 53d8899132SKalle Valo enum ath12k_qmi_bdf_type { 54d8899132SKalle Valo ATH12K_QMI_BDF_TYPE_BIN = 0, 55d8899132SKalle Valo ATH12K_QMI_BDF_TYPE_ELF = 1, 56d8899132SKalle Valo ATH12K_QMI_BDF_TYPE_REGDB = 4, 5742982259SDinesh Karthikeyan ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 58d8899132SKalle Valo }; 59d8899132SKalle Valo 60d8899132SKalle Valo enum ath12k_qmi_event_type { 61d8899132SKalle Valo ATH12K_QMI_EVENT_SERVER_ARRIVE, 62d8899132SKalle Valo ATH12K_QMI_EVENT_SERVER_EXIT, 63d8899132SKalle Valo ATH12K_QMI_EVENT_REQUEST_MEM, 64d8899132SKalle Valo ATH12K_QMI_EVENT_FW_MEM_READY, 65d8899132SKalle Valo ATH12K_QMI_EVENT_FW_READY, 66d8899132SKalle Valo ATH12K_QMI_EVENT_REGISTER_DRIVER, 67d8899132SKalle Valo ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 68d8899132SKalle Valo ATH12K_QMI_EVENT_RECOVERY, 69d8899132SKalle Valo ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 70d8899132SKalle Valo ATH12K_QMI_EVENT_POWER_UP, 71d8899132SKalle Valo ATH12K_QMI_EVENT_POWER_DOWN, 72d8899132SKalle Valo ATH12K_QMI_EVENT_MAX, 73d8899132SKalle Valo }; 74d8899132SKalle Valo 75d8899132SKalle Valo struct ath12k_qmi_driver_event { 76d8899132SKalle Valo struct list_head list; 77d8899132SKalle Valo enum ath12k_qmi_event_type type; 78d8899132SKalle Valo void *data; 79d8899132SKalle Valo }; 80d8899132SKalle Valo 81d8899132SKalle Valo struct ath12k_qmi_ce_cfg { 82d8899132SKalle Valo const struct ce_pipe_config *tgt_ce; 83d8899132SKalle Valo int tgt_ce_len; 84d8899132SKalle Valo const struct service_to_pipe *svc_to_ce_map; 85d8899132SKalle Valo int svc_to_ce_map_len; 86d8899132SKalle Valo const u8 *shadow_reg; 87d8899132SKalle Valo int shadow_reg_len; 88d8899132SKalle Valo u32 *shadow_reg_v3; 89d8899132SKalle Valo int shadow_reg_v3_len; 90d8899132SKalle Valo }; 91d8899132SKalle Valo 92d8899132SKalle Valo struct ath12k_qmi_event_msg { 93d8899132SKalle Valo struct list_head list; 94d8899132SKalle Valo enum ath12k_qmi_event_type type; 95d8899132SKalle Valo }; 96d8899132SKalle Valo 97d8899132SKalle Valo struct target_mem_chunk { 98d8899132SKalle Valo u32 size; 99d8899132SKalle Valo u32 type; 100d8899132SKalle Valo dma_addr_t paddr; 101d8899132SKalle Valo union { 102d8899132SKalle Valo void __iomem *ioaddr; 103d8899132SKalle Valo void *addr; 104d8899132SKalle Valo } v; 105d8899132SKalle Valo }; 106d8899132SKalle Valo 107d8899132SKalle Valo struct target_info { 108d8899132SKalle Valo u32 chip_id; 109d8899132SKalle Valo u32 chip_family; 110d8899132SKalle Valo u32 board_id; 111d8899132SKalle Valo u32 soc_id; 112d8899132SKalle Valo u32 fw_version; 113d8899132SKalle Valo u32 eeprom_caldata; 114d8899132SKalle Valo char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 115d8899132SKalle Valo char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 116d8899132SKalle Valo char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 117d8899132SKalle Valo }; 118d8899132SKalle Valo 119d8899132SKalle Valo struct m3_mem_region { 120d8899132SKalle Valo u32 size; 121d8899132SKalle Valo dma_addr_t paddr; 122d8899132SKalle Valo void *vaddr; 123d8899132SKalle Valo }; 124d8899132SKalle Valo 125d8899132SKalle Valo struct dev_mem_info { 126d8899132SKalle Valo u64 start; 127d8899132SKalle Valo u64 size; 128d8899132SKalle Valo }; 129d8899132SKalle Valo 130d8899132SKalle Valo struct ath12k_qmi { 131d8899132SKalle Valo struct ath12k_base *ab; 132d8899132SKalle Valo struct qmi_handle handle; 133d8899132SKalle Valo struct sockaddr_qrtr sq; 134d8899132SKalle Valo struct work_struct event_work; 135d8899132SKalle Valo struct workqueue_struct *event_wq; 136d8899132SKalle Valo struct list_head event_list; 137d8899132SKalle Valo spinlock_t event_lock; /* spinlock for qmi event list */ 138d8899132SKalle Valo struct ath12k_qmi_ce_cfg ce_cfg; 139d8899132SKalle Valo struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 140d8899132SKalle Valo u32 mem_seg_count; 141d8899132SKalle Valo u32 target_mem_mode; 142d8899132SKalle Valo bool target_mem_delayed; 143d8899132SKalle Valo u8 cal_done; 144d8899132SKalle Valo struct target_info target; 145d8899132SKalle Valo struct m3_mem_region m3_mem; 146d8899132SKalle Valo unsigned int service_ins_id; 147d8899132SKalle Valo struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 148d8899132SKalle Valo }; 149d8899132SKalle Valo 150d8899132SKalle Valo #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 151d8899132SKalle Valo #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 152d8899132SKalle Valo #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 153d8899132SKalle Valo #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 154d8899132SKalle Valo #define QMI_WLFW_MAX_NUM_GPIO_V01 32 155d8899132SKalle Valo #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 156d8899132SKalle Valo #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 157d8899132SKalle Valo 158d8899132SKalle Valo struct qmi_wlanfw_host_ddr_range { 159d8899132SKalle Valo u64 start; 160d8899132SKalle Valo u64 size; 161d8899132SKalle Valo }; 162d8899132SKalle Valo 163d8899132SKalle Valo enum ath12k_qmi_target_mem { 164d8899132SKalle Valo HOST_DDR_REGION_TYPE = 0x1, 165d8899132SKalle Valo BDF_MEM_REGION_TYPE = 0x2, 166d8899132SKalle Valo M3_DUMP_REGION_TYPE = 0x3, 167d8899132SKalle Valo CALDB_MEM_REGION_TYPE = 0x4, 168d8899132SKalle Valo PAGEABLE_MEM_REGION_TYPE = 0x9, 169d8899132SKalle Valo }; 170d8899132SKalle Valo 171d8899132SKalle Valo enum qmi_wlanfw_host_build_type { 172d8899132SKalle Valo WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 173d8899132SKalle Valo QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 174d8899132SKalle Valo QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 175d8899132SKalle Valo QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 176d8899132SKalle Valo WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 177d8899132SKalle Valo }; 178d8899132SKalle Valo 179d8899132SKalle Valo #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 180d8899132SKalle Valo #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 181d8899132SKalle Valo 182d8899132SKalle Valo struct wlfw_host_mlo_chip_info_s_v01 { 183d8899132SKalle Valo u8 chip_id; 184d8899132SKalle Valo u8 num_local_links; 185d8899132SKalle Valo u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 186d8899132SKalle Valo u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 187d8899132SKalle Valo }; 188d8899132SKalle Valo 189d8899132SKalle Valo enum ath12k_qmi_cnss_feature { 190d8899132SKalle Valo CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 191d8899132SKalle Valo CNSS_QDSS_CFG_MISS_V01 = 3, 19234c5625aSCarl Huang CNSS_PCIE_PERST_NO_PULL_V01 = 4, 193d8899132SKalle Valo CNSS_MAX_FEATURE_V01 = 64, 194d8899132SKalle Valo CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 195d8899132SKalle Valo }; 196d8899132SKalle Valo 197d8899132SKalle Valo struct qmi_wlanfw_host_cap_req_msg_v01 { 198d8899132SKalle Valo u8 num_clients_valid; 199d8899132SKalle Valo u32 num_clients; 200d8899132SKalle Valo u8 wake_msi_valid; 201d8899132SKalle Valo u32 wake_msi; 202d8899132SKalle Valo u8 gpios_valid; 203d8899132SKalle Valo u32 gpios_len; 204d8899132SKalle Valo u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 205d8899132SKalle Valo u8 nm_modem_valid; 206d8899132SKalle Valo u8 nm_modem; 207d8899132SKalle Valo u8 bdf_support_valid; 208d8899132SKalle Valo u8 bdf_support; 209d8899132SKalle Valo u8 bdf_cache_support_valid; 210d8899132SKalle Valo u8 bdf_cache_support; 211d8899132SKalle Valo u8 m3_support_valid; 212d8899132SKalle Valo u8 m3_support; 213d8899132SKalle Valo u8 m3_cache_support_valid; 214d8899132SKalle Valo u8 m3_cache_support; 215d8899132SKalle Valo u8 cal_filesys_support_valid; 216d8899132SKalle Valo u8 cal_filesys_support; 217d8899132SKalle Valo u8 cal_cache_support_valid; 218d8899132SKalle Valo u8 cal_cache_support; 219d8899132SKalle Valo u8 cal_done_valid; 220d8899132SKalle Valo u8 cal_done; 221d8899132SKalle Valo u8 mem_bucket_valid; 222d8899132SKalle Valo u32 mem_bucket; 223d8899132SKalle Valo u8 mem_cfg_mode_valid; 224d8899132SKalle Valo u8 mem_cfg_mode; 225d8899132SKalle Valo u8 cal_duration_valid; 226d8899132SKalle Valo u16 cal_duraiton; 227d8899132SKalle Valo u8 platform_name_valid; 228d8899132SKalle Valo char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 229d8899132SKalle Valo u8 ddr_range_valid; 230d8899132SKalle Valo struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 231d8899132SKalle Valo u8 host_build_type_valid; 232d8899132SKalle Valo enum qmi_wlanfw_host_build_type host_build_type; 233d8899132SKalle Valo u8 mlo_capable_valid; 234d8899132SKalle Valo u8 mlo_capable; 235d8899132SKalle Valo u8 mlo_chip_id_valid; 236d8899132SKalle Valo u16 mlo_chip_id; 237d8899132SKalle Valo u8 mlo_group_id_valid; 238d8899132SKalle Valo u8 mlo_group_id; 239d8899132SKalle Valo u8 max_mlo_peer_valid; 240d8899132SKalle Valo u16 max_mlo_peer; 241d8899132SKalle Valo u8 mlo_num_chips_valid; 242d8899132SKalle Valo u8 mlo_num_chips; 243d8899132SKalle Valo u8 mlo_chip_info_valid; 244d8899132SKalle Valo struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 245d8899132SKalle Valo u8 feature_list_valid; 246d8899132SKalle Valo u64 feature_list; 247d8899132SKalle Valo 248d8899132SKalle Valo }; 249d8899132SKalle Valo 250d8899132SKalle Valo struct qmi_wlanfw_host_cap_resp_msg_v01 { 251d8899132SKalle Valo struct qmi_response_type_v01 resp; 252d8899132SKalle Valo }; 253d8899132SKalle Valo 254d8899132SKalle Valo #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 255d8899132SKalle Valo #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 256d8899132SKalle Valo #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 257d8899132SKalle Valo #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 258d8899132SKalle Valo #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 259d8899132SKalle Valo 260d8899132SKalle Valo struct qmi_wlanfw_ind_register_req_msg_v01 { 261d8899132SKalle Valo u8 fw_ready_enable_valid; 262d8899132SKalle Valo u8 fw_ready_enable; 263d8899132SKalle Valo u8 initiate_cal_download_enable_valid; 264d8899132SKalle Valo u8 initiate_cal_download_enable; 265d8899132SKalle Valo u8 initiate_cal_update_enable_valid; 266d8899132SKalle Valo u8 initiate_cal_update_enable; 267d8899132SKalle Valo u8 msa_ready_enable_valid; 268d8899132SKalle Valo u8 msa_ready_enable; 269d8899132SKalle Valo u8 pin_connect_result_enable_valid; 270d8899132SKalle Valo u8 pin_connect_result_enable; 271d8899132SKalle Valo u8 client_id_valid; 272d8899132SKalle Valo u32 client_id; 273d8899132SKalle Valo u8 request_mem_enable_valid; 274d8899132SKalle Valo u8 request_mem_enable; 275d8899132SKalle Valo u8 fw_mem_ready_enable_valid; 276d8899132SKalle Valo u8 fw_mem_ready_enable; 277d8899132SKalle Valo u8 fw_init_done_enable_valid; 278d8899132SKalle Valo u8 fw_init_done_enable; 279d8899132SKalle Valo u8 rejuvenate_enable_valid; 280d8899132SKalle Valo u32 rejuvenate_enable; 281d8899132SKalle Valo u8 xo_cal_enable_valid; 282d8899132SKalle Valo u8 xo_cal_enable; 283d8899132SKalle Valo u8 cal_done_enable_valid; 284d8899132SKalle Valo u8 cal_done_enable; 285d8899132SKalle Valo }; 286d8899132SKalle Valo 287d8899132SKalle Valo struct qmi_wlanfw_ind_register_resp_msg_v01 { 288d8899132SKalle Valo struct qmi_response_type_v01 resp; 289d8899132SKalle Valo u8 fw_status_valid; 290d8899132SKalle Valo u64 fw_status; 291d8899132SKalle Valo }; 292d8899132SKalle Valo 293d8899132SKalle Valo #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 294d8899132SKalle Valo #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 295d8899132SKalle Valo #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 296d8899132SKalle Valo #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 297d8899132SKalle Valo #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 298d8899132SKalle Valo #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 299d8899132SKalle Valo #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 300d8899132SKalle Valo #define QMI_WLANFW_MAX_STR_LEN_V01 16 301d8899132SKalle Valo 302d8899132SKalle Valo struct qmi_wlanfw_mem_cfg_s_v01 { 303d8899132SKalle Valo u64 offset; 304d8899132SKalle Valo u32 size; 305d8899132SKalle Valo u8 secure_flag; 306d8899132SKalle Valo }; 307d8899132SKalle Valo 308d8899132SKalle Valo enum qmi_wlanfw_mem_type_enum_v01 { 309d8899132SKalle Valo WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 310d8899132SKalle Valo QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 311d8899132SKalle Valo QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 312d8899132SKalle Valo QMI_WLANFW_MEM_BDF_V01 = 2, 313d8899132SKalle Valo QMI_WLANFW_MEM_M3_V01 = 3, 314d8899132SKalle Valo QMI_WLANFW_MEM_CAL_V01 = 4, 315d8899132SKalle Valo QMI_WLANFW_MEM_DPD_V01 = 5, 316d8899132SKalle Valo WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 317d8899132SKalle Valo }; 318d8899132SKalle Valo 319d8899132SKalle Valo struct qmi_wlanfw_mem_seg_s_v01 { 320d8899132SKalle Valo u32 size; 321d8899132SKalle Valo enum qmi_wlanfw_mem_type_enum_v01 type; 322d8899132SKalle Valo u32 mem_cfg_len; 323d8899132SKalle Valo struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 324d8899132SKalle Valo }; 325d8899132SKalle Valo 326d8899132SKalle Valo struct qmi_wlanfw_request_mem_ind_msg_v01 { 327d8899132SKalle Valo u32 mem_seg_len; 328d8899132SKalle Valo struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 329d8899132SKalle Valo }; 330d8899132SKalle Valo 331d8899132SKalle Valo struct qmi_wlanfw_mem_seg_resp_s_v01 { 332d8899132SKalle Valo u64 addr; 333d8899132SKalle Valo u32 size; 334d8899132SKalle Valo enum qmi_wlanfw_mem_type_enum_v01 type; 335d8899132SKalle Valo u8 restore; 336d8899132SKalle Valo }; 337d8899132SKalle Valo 338d8899132SKalle Valo struct qmi_wlanfw_respond_mem_req_msg_v01 { 339d8899132SKalle Valo u32 mem_seg_len; 340d8899132SKalle Valo struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 341d8899132SKalle Valo }; 342d8899132SKalle Valo 343d8899132SKalle Valo struct qmi_wlanfw_respond_mem_resp_msg_v01 { 344d8899132SKalle Valo struct qmi_response_type_v01 resp; 345d8899132SKalle Valo }; 346d8899132SKalle Valo 347d8899132SKalle Valo struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 348d8899132SKalle Valo char placeholder; 349d8899132SKalle Valo }; 350d8899132SKalle Valo 351d8899132SKalle Valo struct qmi_wlanfw_fw_ready_ind_msg_v01 { 352d8899132SKalle Valo char placeholder; 353d8899132SKalle Valo }; 354d8899132SKalle Valo 355d8899132SKalle Valo #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 356d8899132SKalle Valo #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 357d8899132SKalle Valo #define QMI_WLANFW_CAP_REQ_V01 0x0024 358d8899132SKalle Valo #define QMI_WLANFW_CAP_RESP_V01 0x0024 359d8899132SKalle Valo 360d8899132SKalle Valo enum qmi_wlanfw_pipedir_enum_v01 { 361d8899132SKalle Valo QMI_WLFW_PIPEDIR_NONE_V01 = 0, 362d8899132SKalle Valo QMI_WLFW_PIPEDIR_IN_V01 = 1, 363d8899132SKalle Valo QMI_WLFW_PIPEDIR_OUT_V01 = 2, 364d8899132SKalle Valo QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 365d8899132SKalle Valo }; 366d8899132SKalle Valo 367d8899132SKalle Valo struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 368d8899132SKalle Valo __le32 pipe_num; 369d8899132SKalle Valo __le32 pipe_dir; 370d8899132SKalle Valo __le32 nentries; 371d8899132SKalle Valo __le32 nbytes_max; 372d8899132SKalle Valo __le32 flags; 373d8899132SKalle Valo }; 374d8899132SKalle Valo 375d8899132SKalle Valo struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 376d8899132SKalle Valo __le32 service_id; 377d8899132SKalle Valo __le32 pipe_dir; 378d8899132SKalle Valo __le32 pipe_num; 379d8899132SKalle Valo }; 380d8899132SKalle Valo 381d8899132SKalle Valo struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 382d8899132SKalle Valo u16 id; 383d8899132SKalle Valo u16 offset; 384d8899132SKalle Valo }; 385d8899132SKalle Valo 386d8899132SKalle Valo struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 387d8899132SKalle Valo u32 addr; 388d8899132SKalle Valo }; 389d8899132SKalle Valo 390d8899132SKalle Valo struct qmi_wlanfw_memory_region_info_s_v01 { 391d8899132SKalle Valo u64 region_addr; 392d8899132SKalle Valo u32 size; 393d8899132SKalle Valo u8 secure_flag; 394d8899132SKalle Valo }; 395d8899132SKalle Valo 396d8899132SKalle Valo struct qmi_wlanfw_rf_chip_info_s_v01 { 397d8899132SKalle Valo u32 chip_id; 398d8899132SKalle Valo u32 chip_family; 399d8899132SKalle Valo }; 400d8899132SKalle Valo 401d8899132SKalle Valo struct qmi_wlanfw_rf_board_info_s_v01 { 402d8899132SKalle Valo u32 board_id; 403d8899132SKalle Valo }; 404d8899132SKalle Valo 405d8899132SKalle Valo struct qmi_wlanfw_soc_info_s_v01 { 406d8899132SKalle Valo u32 soc_id; 407d8899132SKalle Valo }; 408d8899132SKalle Valo 409d8899132SKalle Valo struct qmi_wlanfw_fw_version_info_s_v01 { 410d8899132SKalle Valo u32 fw_version; 411d8899132SKalle Valo char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 412d8899132SKalle Valo }; 413d8899132SKalle Valo 414d8899132SKalle Valo struct qmi_wlanfw_dev_mem_info_s_v01 { 415d8899132SKalle Valo u64 start; 416d8899132SKalle Valo u64 size; 417d8899132SKalle Valo }; 418d8899132SKalle Valo 419d8899132SKalle Valo enum qmi_wlanfw_cal_temp_id_enum_v01 { 420d8899132SKalle Valo QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 421d8899132SKalle Valo QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 422d8899132SKalle Valo QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 423d8899132SKalle Valo QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 424d8899132SKalle Valo QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 425d8899132SKalle Valo QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 426d8899132SKalle Valo }; 427d8899132SKalle Valo 428d8899132SKalle Valo enum qmi_wlanfw_rd_card_chain_cap_v01 { 429d8899132SKalle Valo WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 430d8899132SKalle Valo WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 431d8899132SKalle Valo WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 432d8899132SKalle Valo WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 433d8899132SKalle Valo WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 434d8899132SKalle Valo }; 435d8899132SKalle Valo 436d8899132SKalle Valo struct qmi_wlanfw_cap_resp_msg_v01 { 437d8899132SKalle Valo struct qmi_response_type_v01 resp; 438d8899132SKalle Valo u8 chip_info_valid; 439d8899132SKalle Valo struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 440d8899132SKalle Valo u8 board_info_valid; 441d8899132SKalle Valo struct qmi_wlanfw_rf_board_info_s_v01 board_info; 442d8899132SKalle Valo u8 soc_info_valid; 443d8899132SKalle Valo struct qmi_wlanfw_soc_info_s_v01 soc_info; 444d8899132SKalle Valo u8 fw_version_info_valid; 445d8899132SKalle Valo struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 446d8899132SKalle Valo u8 fw_build_id_valid; 447d8899132SKalle Valo char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 448d8899132SKalle Valo u8 num_macs_valid; 449d8899132SKalle Valo u8 num_macs; 450d8899132SKalle Valo u8 voltage_mv_valid; 451d8899132SKalle Valo u32 voltage_mv; 452d8899132SKalle Valo u8 time_freq_hz_valid; 453d8899132SKalle Valo u32 time_freq_hz; 454d8899132SKalle Valo u8 otp_version_valid; 455d8899132SKalle Valo u32 otp_version; 456d8899132SKalle Valo u8 eeprom_caldata_read_timeout_valid; 457d8899132SKalle Valo u32 eeprom_caldata_read_timeout; 458d8899132SKalle Valo u8 fw_caps_valid; 459d8899132SKalle Valo u64 fw_caps; 460d8899132SKalle Valo u8 rd_card_chain_cap_valid; 461d8899132SKalle Valo enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 462d8899132SKalle Valo u8 dev_mem_info_valid; 463d8899132SKalle Valo struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 464d8899132SKalle Valo }; 465d8899132SKalle Valo 466d8899132SKalle Valo struct qmi_wlanfw_cap_req_msg_v01 { 467d8899132SKalle Valo char placeholder; 468d8899132SKalle Valo }; 469d8899132SKalle Valo 470d8899132SKalle Valo #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 471d8899132SKalle Valo #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 472d8899132SKalle Valo #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 473d8899132SKalle Valo #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 474d8899132SKalle Valo /* TODO: Need to check with MCL and FW team that data can be pointer and 475d8899132SKalle Valo * can be last element in structure 476d8899132SKalle Valo */ 477d8899132SKalle Valo struct qmi_wlanfw_bdf_download_req_msg_v01 { 478d8899132SKalle Valo u8 valid; 479d8899132SKalle Valo u8 file_id_valid; 480d8899132SKalle Valo enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 481d8899132SKalle Valo u8 total_size_valid; 482d8899132SKalle Valo u32 total_size; 483d8899132SKalle Valo u8 seg_id_valid; 484d8899132SKalle Valo u32 seg_id; 485d8899132SKalle Valo u8 data_valid; 486d8899132SKalle Valo u32 data_len; 487d8899132SKalle Valo u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 488d8899132SKalle Valo u8 end_valid; 489d8899132SKalle Valo u8 end; 490d8899132SKalle Valo u8 bdf_type_valid; 491d8899132SKalle Valo u8 bdf_type; 492d8899132SKalle Valo 493d8899132SKalle Valo }; 494d8899132SKalle Valo 495d8899132SKalle Valo struct qmi_wlanfw_bdf_download_resp_msg_v01 { 496d8899132SKalle Valo struct qmi_response_type_v01 resp; 497d8899132SKalle Valo }; 498d8899132SKalle Valo 499d8899132SKalle Valo #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 500d8899132SKalle Valo #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 501d8899132SKalle Valo #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 502d8899132SKalle Valo #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 503d8899132SKalle Valo 504d8899132SKalle Valo struct qmi_wlanfw_m3_info_req_msg_v01 { 505d8899132SKalle Valo u64 addr; 506d8899132SKalle Valo u32 size; 507d8899132SKalle Valo }; 508d8899132SKalle Valo 509d8899132SKalle Valo struct qmi_wlanfw_m3_info_resp_msg_v01 { 510d8899132SKalle Valo struct qmi_response_type_v01 resp; 511d8899132SKalle Valo }; 512d8899132SKalle Valo 513d8899132SKalle Valo #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 514d8899132SKalle Valo #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 515d8899132SKalle Valo #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 516d8899132SKalle Valo #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 517d8899132SKalle Valo #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 518d8899132SKalle Valo #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 519d8899132SKalle Valo #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 520d8899132SKalle Valo #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 521d8899132SKalle Valo #define QMI_WLANFW_MAX_STR_LEN_V01 16 522d8899132SKalle Valo #define QMI_WLANFW_MAX_NUM_CE_V01 12 523d8899132SKalle Valo #define QMI_WLANFW_MAX_NUM_SVC_V01 24 524d8899132SKalle Valo #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 525d8899132SKalle Valo #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 526d8899132SKalle Valo 527d8899132SKalle Valo struct qmi_wlanfw_wlan_mode_req_msg_v01 { 528d8899132SKalle Valo u32 mode; 529d8899132SKalle Valo u8 hw_debug_valid; 530d8899132SKalle Valo u8 hw_debug; 531d8899132SKalle Valo }; 532d8899132SKalle Valo 533d8899132SKalle Valo struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 534d8899132SKalle Valo struct qmi_response_type_v01 resp; 535d8899132SKalle Valo }; 536d8899132SKalle Valo 537d8899132SKalle Valo struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 538d8899132SKalle Valo u8 host_version_valid; 539d8899132SKalle Valo char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 540d8899132SKalle Valo u8 tgt_cfg_valid; 541d8899132SKalle Valo u32 tgt_cfg_len; 542d8899132SKalle Valo struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 543d8899132SKalle Valo tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 544d8899132SKalle Valo u8 svc_cfg_valid; 545d8899132SKalle Valo u32 svc_cfg_len; 546d8899132SKalle Valo struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 547d8899132SKalle Valo svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 548d8899132SKalle Valo u8 shadow_reg_valid; 549d8899132SKalle Valo u32 shadow_reg_len; 550d8899132SKalle Valo struct qmi_wlanfw_shadow_reg_cfg_s_v01 551d8899132SKalle Valo shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 552d8899132SKalle Valo u8 shadow_reg_v3_valid; 553d8899132SKalle Valo u32 shadow_reg_v3_len; 554d8899132SKalle Valo struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 555d8899132SKalle Valo shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 556d8899132SKalle Valo }; 557d8899132SKalle Valo 558d8899132SKalle Valo struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 559d8899132SKalle Valo struct qmi_response_type_v01 resp; 560d8899132SKalle Valo }; 561d8899132SKalle Valo 562d8899132SKalle Valo int ath12k_qmi_firmware_start(struct ath12k_base *ab, 563d8899132SKalle Valo u32 mode); 564d8899132SKalle Valo void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 565d8899132SKalle Valo void ath12k_qmi_deinit_service(struct ath12k_base *ab); 566d8899132SKalle Valo int ath12k_qmi_init_service(struct ath12k_base *ab); 567*92448f87SWen Gong void ath12k_qmi_free_resource(struct ath12k_base *ab); 568d8899132SKalle Valo 569d8899132SKalle Valo #endif 570