1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 #ifndef ATH12K_PCI_H 7 #define ATH12K_PCI_H 8 9 #include <linux/mhi.h> 10 11 #include "core.h" 12 13 #define PCIE_SOC_GLOBAL_RESET 0x3008 14 #define PCIE_SOC_GLOBAL_RESET_V 1 15 16 #define WLAON_WARM_SW_ENTRY 0x1f80504 17 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 18 19 #define PCIE_Q6_COOKIE_ADDR 0x01f80500 20 #define PCIE_Q6_COOKIE_DATA 0xc0000000 21 22 /* register to wake the UMAC from power collapse */ 23 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 24 25 /* register used for handshake mechanism to validate UMAC is awake */ 26 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 27 28 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 29 #define PARM_LTSSM_VALUE 0x111 30 31 #define GCC_GCC_PCIE_HOT_RST(ab) \ 32 ((ab)->hw_params->regs->gcc_gcc_pcie_hot_rst) 33 34 #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 35 36 #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 37 #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 38 #define PCIE_INT_CLEAR_ALL 0xffffffff 39 40 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab) \ 41 ((ab)->hw_params->regs->pcie_qserdes_sysclk_en_sel) 42 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 43 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff 44 #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab) \ 45 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base) 46 #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02 47 #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab) \ 48 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0x4) 49 #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52 50 #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab) \ 51 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0xc) 52 #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff 53 #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff 54 55 #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c 56 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 57 58 #define QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB 0x1E20338 59 #define OTP_BOARD_ID_MASK GENMASK(15, 0) 60 61 #define PCI_BAR_WINDOW0_BASE 0x1E00000 62 #define PCI_BAR_WINDOW0_END 0x1E7FFFC 63 #define PCI_SOC_RANGE_MASK 0x3FFF 64 #define PCI_SOC_PCI_REG_BASE 0x1E04000 65 #define PCI_SOC_PCI_REG_END 0x1E07FFC 66 #define PCI_PARF_BASE 0x1E08000 67 #define PCI_PARF_END 0x1E0BFFC 68 #define PCI_MHIREGLEN_REG 0x1E0E100 69 #define PCI_MHI_REGION_END 0x1E0EFFC 70 #define QRTR_PCI_DOMAIN_NR_MASK GENMASK(7, 4) 71 #define QRTR_PCI_BUS_NUMBER_MASK GENMASK(3, 0) 72 73 #define ATH12K_PCI_SOC_HW_VERSION_1 1 74 #define ATH12K_PCI_SOC_HW_VERSION_2 2 75 76 struct ath12k_msi_user { 77 const char *name; 78 int num_vectors; 79 u32 base_vector; 80 }; 81 82 struct ath12k_msi_config { 83 int total_vectors; 84 int total_users; 85 const struct ath12k_msi_user *users; 86 }; 87 88 enum ath12k_pci_flags { 89 ATH12K_PCI_FLAG_INIT_DONE, 90 ATH12K_PCI_FLAG_IS_MSI_64, 91 ATH12K_PCI_ASPM_RESTORE, 92 ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, 93 }; 94 95 struct ath12k_pci_ops { 96 int (*wakeup)(struct ath12k_base *ab); 97 void (*release)(struct ath12k_base *ab); 98 }; 99 100 struct ath12k_pci { 101 struct pci_dev *pdev; 102 struct ath12k_base *ab; 103 u16 dev_id; 104 char amss_path[100]; 105 u32 msi_ep_base_data; 106 struct mhi_controller *mhi_ctrl; 107 const struct ath12k_msi_config *msi_config; 108 unsigned long mhi_state; 109 enum mhi_callback mhi_pre_cb; 110 u32 register_window; 111 112 /* protects register_window above */ 113 spinlock_t window_lock; 114 115 /* enum ath12k_pci_flags */ 116 unsigned long flags; 117 u16 link_ctl; 118 unsigned long irq_flags; 119 const struct ath12k_pci_ops *pci_ops; 120 u32 qmi_instance; 121 u64 dma_mask; 122 }; 123 124 static inline struct ath12k_pci *ath12k_pci_priv(struct ath12k_base *ab) 125 { 126 return (struct ath12k_pci *)ab->drv_priv; 127 } 128 129 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 130 int *num_vectors, u32 *user_base_data, 131 u32 *base_vector); 132 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector); 133 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value); 134 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset); 135 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 136 u8 *ul_pipe, u8 *dl_pipe); 137 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 138 u32 *msi_addr_hi); 139 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 140 u32 *msi_idx); 141 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab); 142 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab); 143 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab); 144 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab); 145 int ath12k_pci_hif_suspend(struct ath12k_base *ab); 146 int ath12k_pci_hif_resume(struct ath12k_base *ab); 147 void ath12k_pci_stop(struct ath12k_base *ab); 148 int ath12k_pci_start(struct ath12k_base *ab); 149 int ath12k_pci_power_up(struct ath12k_base *ab); 150 void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend); 151 int ath12k_pci_init(void); 152 void ath12k_pci_exit(void); 153 #endif /* ATH12K_PCI_H */ 154