1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 #include <linux/time.h> 11 #include <linux/vmalloc.h> 12 13 #include "pci.h" 14 #include "core.h" 15 #include "hif.h" 16 #include "mhi.h" 17 #include "debug.h" 18 19 #define ATH12K_PCI_BAR_NUM 0 20 #define ATH12K_PCI_DMA_MASK 36 21 22 #define ATH12K_PCI_IRQ_CE0_OFFSET 3 23 24 #define WINDOW_ENABLE_BIT 0x40000000 25 #define WINDOW_REG_ADDRESS 0x310c 26 #define WINDOW_VALUE_MASK GENMASK(24, 19) 27 #define WINDOW_START 0x80000 28 #define WINDOW_RANGE_MASK GENMASK(18, 0) 29 #define WINDOW_STATIC_MASK GENMASK(31, 6) 30 31 #define TCSR_SOC_HW_VERSION 0x1B00000 32 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 33 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4) 34 35 /* BAR0 + 4k is always accessible, and no 36 * need to force wakeup. 37 * 4K - 32 = 0xFE0 38 */ 39 #define ACCESS_ALWAYS_OFF 0xFE0 40 41 #define QCN9274_DEVICE_ID 0x1109 42 #define WCN7850_DEVICE_ID 0x1107 43 44 #define PCIE_LOCAL_REG_QRTR_NODE_ID 0x1E03164 45 #define DOMAIN_NUMBER_MASK GENMASK(7, 4) 46 #define BUS_NUMBER_MASK GENMASK(3, 0) 47 48 static const struct pci_device_id ath12k_pci_id_table[] = { 49 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) }, 50 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) }, 51 {0} 52 }; 53 54 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table); 55 56 /* TODO: revisit IRQ mapping for new SRNG's */ 57 static const struct ath12k_msi_config ath12k_msi_config[] = { 58 { 59 .total_vectors = 16, 60 .total_users = 3, 61 .users = (struct ath12k_msi_user[]) { 62 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 63 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 64 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 65 }, 66 }, 67 }; 68 69 static const struct ath12k_msi_config msi_config_one_msi = { 70 .total_vectors = 1, 71 .total_users = 4, 72 .users = (struct ath12k_msi_user[]) { 73 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 74 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 75 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 76 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 77 }, 78 }; 79 80 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { 81 "bhi", 82 "mhi-er0", 83 "mhi-er1", 84 "ce0", 85 "ce1", 86 "ce2", 87 "ce3", 88 "ce4", 89 "ce5", 90 "ce6", 91 "ce7", 92 "ce8", 93 "ce9", 94 "ce10", 95 "ce11", 96 "ce12", 97 "ce13", 98 "ce14", 99 "ce15", 100 "host2wbm-desc-feed", 101 "host2reo-re-injection", 102 "host2reo-command", 103 "host2rxdma-monitor-ring3", 104 "host2rxdma-monitor-ring2", 105 "host2rxdma-monitor-ring1", 106 "reo2ost-exception", 107 "wbm2host-rx-release", 108 "reo2host-status", 109 "reo2host-destination-ring4", 110 "reo2host-destination-ring3", 111 "reo2host-destination-ring2", 112 "reo2host-destination-ring1", 113 "rxdma2host-monitor-destination-mac3", 114 "rxdma2host-monitor-destination-mac2", 115 "rxdma2host-monitor-destination-mac1", 116 "ppdu-end-interrupts-mac3", 117 "ppdu-end-interrupts-mac2", 118 "ppdu-end-interrupts-mac1", 119 "rxdma2host-monitor-status-ring-mac3", 120 "rxdma2host-monitor-status-ring-mac2", 121 "rxdma2host-monitor-status-ring-mac1", 122 "host2rxdma-host-buf-ring-mac3", 123 "host2rxdma-host-buf-ring-mac2", 124 "host2rxdma-host-buf-ring-mac1", 125 "rxdma2host-destination-ring-mac3", 126 "rxdma2host-destination-ring-mac2", 127 "rxdma2host-destination-ring-mac1", 128 "host2tcl-input-ring4", 129 "host2tcl-input-ring3", 130 "host2tcl-input-ring2", 131 "host2tcl-input-ring1", 132 "wbm2host-tx-completions-ring4", 133 "wbm2host-tx-completions-ring3", 134 "wbm2host-tx-completions-ring2", 135 "wbm2host-tx-completions-ring1", 136 "tcl2host-status-ring", 137 }; 138 139 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab) 140 { 141 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 142 143 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 144 } 145 146 static void ath12k_pci_bus_release(struct ath12k_base *ab) 147 { 148 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 149 150 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 151 } 152 153 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = { 154 .wakeup = NULL, 155 .release = NULL, 156 }; 157 158 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = { 159 .wakeup = ath12k_pci_bus_wake_up, 160 .release = ath12k_pci_bus_release, 161 }; 162 163 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset) 164 { 165 struct ath12k_base *ab = ab_pci->ab; 166 167 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK); 168 u32 static_window; 169 170 lockdep_assert_held(&ab_pci->window_lock); 171 172 /* Preserve the static window configuration and reset only dynamic window */ 173 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; 174 window |= static_window; 175 176 if (window != ab_pci->register_window) { 177 iowrite32(WINDOW_ENABLE_BIT | window, 178 ab->mem + WINDOW_REG_ADDRESS); 179 ioread32(ab->mem + WINDOW_REG_ADDRESS); 180 ab_pci->register_window = window; 181 } 182 } 183 184 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci) 185 { 186 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK); 187 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK); 188 u32 window; 189 190 window = (umac_window << 12) | (ce_window << 6); 191 192 spin_lock_bh(&ab_pci->window_lock); 193 ab_pci->register_window = window; 194 spin_unlock_bh(&ab_pci->window_lock); 195 196 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 197 } 198 199 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab, 200 u32 offset) 201 { 202 u32 window_start; 203 204 /* If offset lies within DP register range, use 3rd window */ 205 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 206 window_start = 3 * WINDOW_START; 207 /* If offset lies within CE register range, use 2nd window */ 208 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 209 window_start = 2 * WINDOW_START; 210 else 211 window_start = WINDOW_START; 212 213 return window_start; 214 } 215 216 static inline bool ath12k_pci_is_offset_within_mhi_region(u32 offset) 217 { 218 return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END); 219 } 220 221 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) 222 { 223 u32 val, delay; 224 225 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 226 227 val |= PCIE_SOC_GLOBAL_RESET_V; 228 229 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 230 231 /* TODO: exact time to sleep is uncertain */ 232 delay = 10; 233 mdelay(delay); 234 235 /* Need to toggle V bit back otherwise stuck in reset status */ 236 val &= ~PCIE_SOC_GLOBAL_RESET_V; 237 238 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 239 240 mdelay(delay); 241 242 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 243 if (val == 0xffffffff) 244 ath12k_warn(ab, "link down error during global reset\n"); 245 } 246 247 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab) 248 { 249 u32 val; 250 251 /* read cookie */ 252 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 253 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val); 254 255 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 256 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 257 258 /* TODO: exact time to sleep is uncertain */ 259 mdelay(10); 260 261 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 262 * continuing warm path and entering dead loop. 263 */ 264 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 265 mdelay(10); 266 267 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 268 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 269 270 /* A read clear register. clear the register to prevent 271 * Q6 from entering wrong code path. 272 */ 273 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 274 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val); 275 } 276 277 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab) 278 { 279 u32 val; 280 int i; 281 282 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 283 284 /* PCIE link seems very unstable after the Hot Reset*/ 285 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 286 if (val == 0xffffffff) 287 mdelay(5); 288 289 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 290 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 291 } 292 293 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val); 294 295 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 296 val |= GCC_GCC_PCIE_HOT_RST_VAL; 297 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 298 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 299 300 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 301 302 mdelay(5); 303 } 304 305 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab) 306 { 307 /* This is a WAR for PCIE Hotreset. 308 * When target receive Hotreset, but will set the interrupt. 309 * So when download SBL again, SBL will open Interrupt and 310 * receive it, and crash immediately. 311 */ 312 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 313 } 314 315 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab) 316 { 317 u32 val; 318 319 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 320 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 321 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 322 } 323 324 static void ath12k_pci_force_wake(struct ath12k_base *ab) 325 { 326 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 327 mdelay(5); 328 } 329 330 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) 331 { 332 if (power_on) { 333 ath12k_pci_enable_ltssm(ab); 334 ath12k_pci_clear_all_intrs(ab); 335 ath12k_pci_set_wlaon_pwr_ctrl(ab); 336 } 337 338 ath12k_mhi_clear_vector(ab); 339 ath12k_pci_clear_dbg_registers(ab); 340 ath12k_pci_soc_global_reset(ab); 341 ath12k_mhi_set_mhictrl_reset(ab); 342 } 343 344 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab) 345 { 346 int i, j; 347 348 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 349 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 350 351 for (j = 0; j < irq_grp->num_irq; j++) 352 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 353 354 netif_napi_del(&irq_grp->napi); 355 free_netdev(irq_grp->napi_ndev); 356 } 357 } 358 359 static void ath12k_pci_free_irq(struct ath12k_base *ab) 360 { 361 int i, irq_idx; 362 363 for (i = 0; i < ab->hw_params->ce_count; i++) { 364 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 365 continue; 366 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 367 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 368 } 369 370 ath12k_pci_free_ext_irq(ab); 371 } 372 373 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) 374 { 375 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 376 u32 irq_idx; 377 378 /* In case of one MSI vector, we handle irq enable/disable in a 379 * uniform way since we only have one irq 380 */ 381 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 382 return; 383 384 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 385 enable_irq(ab->irq_num[irq_idx]); 386 } 387 388 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) 389 { 390 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 391 u32 irq_idx; 392 393 /* In case of one MSI vector, we handle irq enable/disable in a 394 * uniform way since we only have one irq 395 */ 396 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 397 return; 398 399 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 400 disable_irq_nosync(ab->irq_num[irq_idx]); 401 } 402 403 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab) 404 { 405 int i; 406 407 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 408 409 for (i = 0; i < ab->hw_params->ce_count; i++) { 410 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 411 continue; 412 ath12k_pci_ce_irq_disable(ab, i); 413 } 414 } 415 416 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) 417 { 418 int i; 419 int irq_idx; 420 421 for (i = 0; i < ab->hw_params->ce_count; i++) { 422 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 423 continue; 424 425 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 426 synchronize_irq(ab->irq_num[irq_idx]); 427 } 428 } 429 430 static void ath12k_pci_ce_workqueue(struct work_struct *work) 431 { 432 struct ath12k_ce_pipe *ce_pipe = from_work(ce_pipe, work, intr_wq); 433 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 434 435 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 436 437 enable_irq(ce_pipe->ab->irq_num[irq_idx]); 438 } 439 440 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg) 441 { 442 struct ath12k_ce_pipe *ce_pipe = arg; 443 struct ath12k_base *ab = ce_pipe->ab; 444 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 445 446 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) 447 return IRQ_HANDLED; 448 449 /* last interrupt received for this CE */ 450 ce_pipe->timestamp = jiffies; 451 452 disable_irq_nosync(ab->irq_num[irq_idx]); 453 454 queue_work(system_bh_wq, &ce_pipe->intr_wq); 455 456 return IRQ_HANDLED; 457 } 458 459 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) 460 { 461 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 462 int i; 463 464 /* In case of one MSI vector, we handle irq enable/disable 465 * in a uniform way since we only have one irq 466 */ 467 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 468 return; 469 470 for (i = 0; i < irq_grp->num_irq; i++) 471 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 472 } 473 474 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 475 { 476 int i; 477 478 if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 479 return; 480 481 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 482 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 483 484 ath12k_pci_ext_grp_disable(irq_grp); 485 486 if (irq_grp->napi_enabled) { 487 napi_synchronize(&irq_grp->napi); 488 napi_disable(&irq_grp->napi); 489 irq_grp->napi_enabled = false; 490 } 491 } 492 } 493 494 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) 495 { 496 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 497 int i; 498 499 /* In case of one MSI vector, we handle irq enable/disable in a 500 * uniform way since we only have one irq 501 */ 502 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 503 return; 504 505 for (i = 0; i < irq_grp->num_irq; i++) 506 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 507 } 508 509 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab) 510 { 511 int i, j, irq_idx; 512 513 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 514 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 515 516 for (j = 0; j < irq_grp->num_irq; j++) { 517 irq_idx = irq_grp->irqs[j]; 518 synchronize_irq(ab->irq_num[irq_idx]); 519 } 520 } 521 } 522 523 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 524 { 525 struct ath12k_ext_irq_grp *irq_grp = container_of(napi, 526 struct ath12k_ext_irq_grp, 527 napi); 528 struct ath12k_base *ab = irq_grp->ab; 529 int work_done; 530 int i; 531 532 work_done = ath12k_dp_service_srng(ab, irq_grp, budget); 533 if (work_done < budget) { 534 napi_complete_done(napi, work_done); 535 for (i = 0; i < irq_grp->num_irq; i++) 536 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 537 } 538 539 if (work_done > budget) 540 work_done = budget; 541 542 return work_done; 543 } 544 545 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg) 546 { 547 struct ath12k_ext_irq_grp *irq_grp = arg; 548 struct ath12k_base *ab = irq_grp->ab; 549 int i; 550 551 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 552 return IRQ_HANDLED; 553 554 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); 555 556 /* last interrupt received for this group */ 557 irq_grp->timestamp = jiffies; 558 559 for (i = 0; i < irq_grp->num_irq; i++) 560 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 561 562 napi_schedule(&irq_grp->napi); 563 564 return IRQ_HANDLED; 565 } 566 567 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) 568 { 569 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 570 int i, j, n, ret, num_vectors = 0; 571 u32 user_base_data = 0, base_vector = 0, base_idx; 572 struct ath12k_ext_irq_grp *irq_grp; 573 574 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 575 ret = ath12k_pci_get_user_msi_assignment(ab, "DP", 576 &num_vectors, 577 &user_base_data, 578 &base_vector); 579 if (ret < 0) 580 return ret; 581 582 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 583 irq_grp = &ab->ext_irq_grp[i]; 584 u32 num_irq = 0; 585 586 irq_grp->ab = ab; 587 irq_grp->grp_id = i; 588 irq_grp->napi_ndev = alloc_netdev_dummy(0); 589 if (!irq_grp->napi_ndev) { 590 ret = -ENOMEM; 591 goto fail_allocate; 592 } 593 594 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi, 595 ath12k_pci_ext_grp_napi_poll); 596 597 if (ab->hw_params->ring_mask->tx[i] || 598 ab->hw_params->ring_mask->rx[i] || 599 ab->hw_params->ring_mask->rx_err[i] || 600 ab->hw_params->ring_mask->rx_wbm_rel[i] || 601 ab->hw_params->ring_mask->reo_status[i] || 602 ab->hw_params->ring_mask->host2rxdma[i] || 603 ab->hw_params->ring_mask->rx_mon_dest[i]) { 604 num_irq = 1; 605 } 606 607 irq_grp->num_irq = num_irq; 608 irq_grp->irqs[0] = base_idx + i; 609 610 for (j = 0; j < irq_grp->num_irq; j++) { 611 int irq_idx = irq_grp->irqs[j]; 612 int vector = (i % num_vectors) + base_vector; 613 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); 614 615 ab->irq_num[irq_idx] = irq; 616 617 ath12k_dbg(ab, ATH12K_DBG_PCI, 618 "irq:%d group:%d\n", irq, i); 619 620 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 621 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler, 622 ab_pci->irq_flags, 623 "DP_EXT_IRQ", irq_grp); 624 if (ret) { 625 ath12k_err(ab, "failed request irq %d: %d\n", 626 vector, ret); 627 goto fail_request; 628 } 629 } 630 ath12k_pci_ext_grp_disable(irq_grp); 631 } 632 633 return 0; 634 635 fail_request: 636 /* i ->napi_ndev was properly allocated. Free it also */ 637 i += 1; 638 fail_allocate: 639 for (n = 0; n < i; n++) { 640 irq_grp = &ab->ext_irq_grp[n]; 641 free_netdev(irq_grp->napi_ndev); 642 } 643 return ret; 644 } 645 646 static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci, 647 const struct cpumask *m) 648 { 649 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 650 return 0; 651 652 return irq_set_affinity_and_hint(ab_pci->pdev->irq, m); 653 } 654 655 static int ath12k_pci_config_irq(struct ath12k_base *ab) 656 { 657 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 658 struct ath12k_ce_pipe *ce_pipe; 659 u32 msi_data_start; 660 u32 msi_data_count, msi_data_idx; 661 u32 msi_irq_start; 662 unsigned int msi_data; 663 int irq, i, ret, irq_idx; 664 665 ret = ath12k_pci_get_user_msi_assignment(ab, 666 "CE", &msi_data_count, 667 &msi_data_start, &msi_irq_start); 668 if (ret) 669 return ret; 670 671 /* Configure CE irqs */ 672 673 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 674 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 675 continue; 676 677 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 678 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); 679 ce_pipe = &ab->ce.ce_pipe[i]; 680 681 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 682 683 INIT_WORK(&ce_pipe->intr_wq, ath12k_pci_ce_workqueue); 684 685 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler, 686 ab_pci->irq_flags, irq_name[irq_idx], 687 ce_pipe); 688 if (ret) { 689 ath12k_err(ab, "failed to request irq %d: %d\n", 690 irq_idx, ret); 691 return ret; 692 } 693 694 ab->irq_num[irq_idx] = irq; 695 msi_data_idx++; 696 697 ath12k_pci_ce_irq_disable(ab, i); 698 } 699 700 ret = ath12k_pci_ext_irq_config(ab); 701 if (ret) 702 return ret; 703 704 return 0; 705 } 706 707 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab) 708 { 709 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 710 711 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 712 struct pci_bus *bus = ab_pci->pdev->bus; 713 714 cfg->tgt_ce = ab->hw_params->target_ce_config; 715 cfg->tgt_ce_len = ab->hw_params->target_ce_count; 716 717 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; 718 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; 719 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; 720 721 if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID)) { 722 ab_pci->qmi_instance = 723 u32_encode_bits(pci_domain_nr(bus), DOMAIN_NUMBER_MASK) | 724 u32_encode_bits(bus->number, BUS_NUMBER_MASK); 725 ab->qmi.service_ins_id += ab_pci->qmi_instance; 726 } 727 } 728 729 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab) 730 { 731 int i; 732 733 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 734 735 for (i = 0; i < ab->hw_params->ce_count; i++) { 736 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 737 continue; 738 ath12k_pci_ce_irq_enable(ab, i); 739 } 740 } 741 742 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable) 743 { 744 struct pci_dev *dev = ab_pci->pdev; 745 u16 control; 746 747 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 748 749 if (enable) 750 control |= PCI_MSI_FLAGS_ENABLE; 751 else 752 control &= ~PCI_MSI_FLAGS_ENABLE; 753 754 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 755 } 756 757 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci) 758 { 759 ath12k_pci_msi_config(ab_pci, true); 760 } 761 762 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci) 763 { 764 ath12k_pci_msi_config(ab_pci, false); 765 } 766 767 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci) 768 { 769 struct ath12k_base *ab = ab_pci->ab; 770 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 771 struct msi_desc *msi_desc; 772 int num_vectors; 773 int ret; 774 775 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 776 msi_config->total_vectors, 777 msi_config->total_vectors, 778 PCI_IRQ_MSI); 779 780 if (num_vectors == msi_config->total_vectors) { 781 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 782 ab_pci->irq_flags = IRQF_SHARED; 783 } else { 784 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 785 1, 786 1, 787 PCI_IRQ_MSI); 788 if (num_vectors < 0) { 789 ret = -EINVAL; 790 goto reset_msi_config; 791 } 792 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 793 ab_pci->msi_config = &msi_config_one_msi; 794 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 795 ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n"); 796 } 797 798 ath12k_info(ab, "MSI vectors: %d\n", num_vectors); 799 800 ath12k_pci_msi_disable(ab_pci); 801 802 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 803 if (!msi_desc) { 804 ath12k_err(ab, "msi_desc is NULL!\n"); 805 ret = -EINVAL; 806 goto free_msi_vector; 807 } 808 809 ab_pci->msi_ep_base_data = msi_desc->msg.data; 810 if (msi_desc->pci.msi_attrib.is_64) 811 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 812 813 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 814 815 return 0; 816 817 free_msi_vector: 818 pci_free_irq_vectors(ab_pci->pdev); 819 820 reset_msi_config: 821 return ret; 822 } 823 824 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci) 825 { 826 pci_free_irq_vectors(ab_pci->pdev); 827 } 828 829 static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci) 830 { 831 struct msi_desc *msi_desc; 832 833 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 834 if (!msi_desc) { 835 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n"); 836 pci_free_irq_vectors(ab_pci->pdev); 837 return -EINVAL; 838 } 839 840 ab_pci->msi_ep_base_data = msi_desc->msg.data; 841 842 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 843 ab_pci->msi_ep_base_data); 844 845 return 0; 846 } 847 848 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev) 849 { 850 struct ath12k_base *ab = ab_pci->ab; 851 u16 device_id; 852 int ret = 0; 853 854 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 855 if (device_id != ab_pci->dev_id) { 856 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 857 device_id, ab_pci->dev_id); 858 ret = -EIO; 859 goto out; 860 } 861 862 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM); 863 if (ret) { 864 ath12k_err(ab, "failed to assign pci resource: %d\n", ret); 865 goto out; 866 } 867 868 ret = pci_enable_device(pdev); 869 if (ret) { 870 ath12k_err(ab, "failed to enable pci device: %d\n", ret); 871 goto out; 872 } 873 874 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci"); 875 if (ret) { 876 ath12k_err(ab, "failed to request pci region: %d\n", ret); 877 goto disable_device; 878 } 879 880 ab_pci->dma_mask = DMA_BIT_MASK(ATH12K_PCI_DMA_MASK); 881 dma_set_mask(&pdev->dev, ab_pci->dma_mask); 882 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 883 884 pci_set_master(pdev); 885 886 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); 887 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); 888 if (!ab->mem) { 889 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM); 890 ret = -EIO; 891 goto release_region; 892 } 893 894 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%p\n", ab->mem); 895 return 0; 896 897 release_region: 898 pci_release_region(pdev, ATH12K_PCI_BAR_NUM); 899 disable_device: 900 pci_disable_device(pdev); 901 out: 902 return ret; 903 } 904 905 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci) 906 { 907 struct ath12k_base *ab = ab_pci->ab; 908 struct pci_dev *pci_dev = ab_pci->pdev; 909 910 pci_iounmap(pci_dev, ab->mem); 911 ab->mem = NULL; 912 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM); 913 if (pci_is_enabled(pci_dev)) 914 pci_disable_device(pci_dev); 915 } 916 917 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci) 918 { 919 struct ath12k_base *ab = ab_pci->ab; 920 921 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 922 &ab_pci->link_ctl); 923 924 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 925 ab_pci->link_ctl, 926 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 927 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 928 929 /* disable L0s and L1 */ 930 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 931 PCI_EXP_LNKCTL_ASPMC); 932 933 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); 934 } 935 936 static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab) 937 { 938 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 939 u32 reg; 940 941 /* On platforms with two or more identical mhi devices, qmi service run 942 * with identical qrtr-node-id. Because of this identical ID qrtr-lookup 943 * cannot register more than one qmi service with identical node ID. 944 * 945 * This generates a unique instance ID from PCIe domain number and bus number, 946 * writes to the given register, it is available for firmware when the QMI service 947 * is spawned. 948 */ 949 reg = PCIE_LOCAL_REG_QRTR_NODE_ID & WINDOW_RANGE_MASK; 950 ath12k_pci_write32(ab, reg, ab_pci->qmi_instance); 951 952 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n", 953 reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg)); 954 } 955 956 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) 957 { 958 if (ab_pci->ab->hw_params->supports_aspm && 959 test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) 960 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 961 PCI_EXP_LNKCTL_ASPMC, 962 ab_pci->link_ctl & 963 PCI_EXP_LNKCTL_ASPMC); 964 } 965 966 static void ath12k_pci_cancel_workqueue(struct ath12k_base *ab) 967 { 968 int i; 969 970 for (i = 0; i < ab->hw_params->ce_count; i++) { 971 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 972 973 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 974 continue; 975 976 cancel_work_sync(&ce_pipe->intr_wq); 977 } 978 } 979 980 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab) 981 { 982 ath12k_pci_ce_irqs_disable(ab); 983 ath12k_pci_sync_ce_irqs(ab); 984 ath12k_pci_cancel_workqueue(ab); 985 } 986 987 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 988 u8 *ul_pipe, u8 *dl_pipe) 989 { 990 const struct service_to_pipe *entry; 991 bool ul_set = false, dl_set = false; 992 int i; 993 994 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { 995 entry = &ab->hw_params->svc_to_ce_map[i]; 996 997 if (__le32_to_cpu(entry->service_id) != service_id) 998 continue; 999 1000 switch (__le32_to_cpu(entry->pipedir)) { 1001 case PIPEDIR_NONE: 1002 break; 1003 case PIPEDIR_IN: 1004 WARN_ON(dl_set); 1005 *dl_pipe = __le32_to_cpu(entry->pipenum); 1006 dl_set = true; 1007 break; 1008 case PIPEDIR_OUT: 1009 WARN_ON(ul_set); 1010 *ul_pipe = __le32_to_cpu(entry->pipenum); 1011 ul_set = true; 1012 break; 1013 case PIPEDIR_INOUT: 1014 WARN_ON(dl_set); 1015 WARN_ON(ul_set); 1016 *dl_pipe = __le32_to_cpu(entry->pipenum); 1017 *ul_pipe = __le32_to_cpu(entry->pipenum); 1018 dl_set = true; 1019 ul_set = true; 1020 break; 1021 } 1022 } 1023 1024 if (WARN_ON(!ul_set || !dl_set)) 1025 return -ENOENT; 1026 1027 return 0; 1028 } 1029 1030 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector) 1031 { 1032 struct pci_dev *pci_dev = to_pci_dev(dev); 1033 1034 return pci_irq_vector(pci_dev, vector); 1035 } 1036 1037 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 1038 int *num_vectors, u32 *user_base_data, 1039 u32 *base_vector) 1040 { 1041 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1042 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 1043 int idx; 1044 1045 for (idx = 0; idx < msi_config->total_users; idx++) { 1046 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 1047 *num_vectors = msi_config->users[idx].num_vectors; 1048 *base_vector = msi_config->users[idx].base_vector; 1049 *user_base_data = *base_vector + ab_pci->msi_ep_base_data; 1050 1051 ath12k_dbg(ab, ATH12K_DBG_PCI, 1052 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 1053 user_name, *num_vectors, *user_base_data, 1054 *base_vector); 1055 1056 return 0; 1057 } 1058 } 1059 1060 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 1061 1062 return -EINVAL; 1063 } 1064 1065 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 1066 u32 *msi_addr_hi) 1067 { 1068 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1069 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 1070 1071 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 1072 msi_addr_lo); 1073 1074 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 1075 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 1076 msi_addr_hi); 1077 } else { 1078 *msi_addr_hi = 0; 1079 } 1080 } 1081 1082 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 1083 u32 *msi_idx) 1084 { 1085 u32 i, msi_data_idx; 1086 1087 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 1088 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1089 continue; 1090 1091 if (ce_id == i) 1092 break; 1093 1094 msi_data_idx++; 1095 } 1096 *msi_idx = msi_data_idx; 1097 } 1098 1099 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab) 1100 { 1101 ath12k_pci_ce_irqs_enable(ab); 1102 } 1103 1104 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab) 1105 { 1106 ath12k_pci_ce_irq_disable_sync(ab); 1107 } 1108 1109 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) 1110 { 1111 int i; 1112 1113 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 1114 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 1115 1116 if (!irq_grp->napi_enabled) { 1117 napi_enable(&irq_grp->napi); 1118 irq_grp->napi_enabled = true; 1119 } 1120 1121 ath12k_pci_ext_grp_enable(irq_grp); 1122 } 1123 1124 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); 1125 } 1126 1127 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 1128 { 1129 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 1130 return; 1131 1132 __ath12k_pci_ext_irq_disable(ab); 1133 ath12k_pci_sync_ext_irqs(ab); 1134 } 1135 1136 int ath12k_pci_hif_suspend(struct ath12k_base *ab) 1137 { 1138 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1139 1140 ath12k_mhi_suspend(ar_pci); 1141 1142 return 0; 1143 } 1144 1145 int ath12k_pci_hif_resume(struct ath12k_base *ab) 1146 { 1147 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1148 1149 ath12k_mhi_resume(ar_pci); 1150 1151 return 0; 1152 } 1153 1154 void ath12k_pci_stop(struct ath12k_base *ab) 1155 { 1156 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1157 1158 if (!test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags)) 1159 return; 1160 1161 ath12k_pci_ce_irq_disable_sync(ab); 1162 ath12k_ce_cleanup_pipes(ab); 1163 } 1164 1165 int ath12k_pci_start(struct ath12k_base *ab) 1166 { 1167 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1168 1169 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1170 1171 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 1172 ath12k_pci_aspm_restore(ab_pci); 1173 else 1174 ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 1175 1176 ath12k_pci_ce_irqs_enable(ab); 1177 ath12k_ce_rx_post_buf(ab); 1178 1179 return 0; 1180 } 1181 1182 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) 1183 { 1184 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1185 u32 val, window_start; 1186 int ret = 0; 1187 1188 /* for offset beyond BAR + 4K - 32, may 1189 * need to wakeup MHI to access. 1190 */ 1191 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1192 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1193 ret = ab_pci->pci_ops->wakeup(ab); 1194 1195 if (offset < WINDOW_START) { 1196 val = ioread32(ab->mem + offset); 1197 } else { 1198 if (ab->static_window_map) 1199 window_start = ath12k_pci_get_window_start(ab, offset); 1200 else 1201 window_start = WINDOW_START; 1202 1203 if (window_start == WINDOW_START) { 1204 spin_lock_bh(&ab_pci->window_lock); 1205 ath12k_pci_select_window(ab_pci, offset); 1206 1207 if (ath12k_pci_is_offset_within_mhi_region(offset)) { 1208 offset = offset - PCI_MHIREGLEN_REG; 1209 val = ioread32(ab->mem + 1210 (offset & WINDOW_RANGE_MASK)); 1211 } else { 1212 val = ioread32(ab->mem + window_start + 1213 (offset & WINDOW_RANGE_MASK)); 1214 } 1215 spin_unlock_bh(&ab_pci->window_lock); 1216 } else { 1217 val = ioread32(ab->mem + window_start + 1218 (offset & WINDOW_RANGE_MASK)); 1219 } 1220 } 1221 1222 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1223 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1224 !ret) 1225 ab_pci->pci_ops->release(ab); 1226 return val; 1227 } 1228 1229 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value) 1230 { 1231 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1232 u32 window_start; 1233 int ret = 0; 1234 1235 /* for offset beyond BAR + 4K - 32, may 1236 * need to wakeup MHI to access. 1237 */ 1238 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1239 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1240 ret = ab_pci->pci_ops->wakeup(ab); 1241 1242 if (offset < WINDOW_START) { 1243 iowrite32(value, ab->mem + offset); 1244 } else { 1245 if (ab->static_window_map) 1246 window_start = ath12k_pci_get_window_start(ab, offset); 1247 else 1248 window_start = WINDOW_START; 1249 1250 if (window_start == WINDOW_START) { 1251 spin_lock_bh(&ab_pci->window_lock); 1252 ath12k_pci_select_window(ab_pci, offset); 1253 1254 if (ath12k_pci_is_offset_within_mhi_region(offset)) { 1255 offset = offset - PCI_MHIREGLEN_REG; 1256 iowrite32(value, ab->mem + 1257 (offset & WINDOW_RANGE_MASK)); 1258 } else { 1259 iowrite32(value, ab->mem + window_start + 1260 (offset & WINDOW_RANGE_MASK)); 1261 } 1262 spin_unlock_bh(&ab_pci->window_lock); 1263 } else { 1264 iowrite32(value, ab->mem + window_start + 1265 (offset & WINDOW_RANGE_MASK)); 1266 } 1267 } 1268 1269 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1270 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1271 !ret) 1272 ab_pci->pci_ops->release(ab); 1273 } 1274 1275 #ifdef CONFIG_ATH12K_COREDUMP 1276 static int ath12k_pci_coredump_calculate_size(struct ath12k_base *ab, u32 *dump_seg_sz) 1277 { 1278 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1279 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 1280 struct image_info *rddm_img, *fw_img; 1281 struct ath12k_tlv_dump_data *dump_tlv; 1282 enum ath12k_fw_crash_dump_type mem_type; 1283 u32 len = 0, rddm_tlv_sz = 0, paging_tlv_sz = 0; 1284 struct ath12k_dump_file_data *file_data; 1285 int i; 1286 1287 rddm_img = mhi_ctrl->rddm_image; 1288 if (!rddm_img) { 1289 ath12k_err(ab, "No RDDM dump found\n"); 1290 return 0; 1291 } 1292 1293 fw_img = mhi_ctrl->fbc_image; 1294 1295 for (i = 0; i < fw_img->entries ; i++) { 1296 if (!fw_img->mhi_buf[i].buf) 1297 continue; 1298 1299 paging_tlv_sz += fw_img->mhi_buf[i].len; 1300 } 1301 dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA] = paging_tlv_sz; 1302 1303 for (i = 0; i < rddm_img->entries; i++) { 1304 if (!rddm_img->mhi_buf[i].buf) 1305 continue; 1306 1307 rddm_tlv_sz += rddm_img->mhi_buf[i].len; 1308 } 1309 dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA] = rddm_tlv_sz; 1310 1311 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 1312 mem_type = ath12k_coredump_get_dump_type(ab->qmi.target_mem[i].type); 1313 1314 if (mem_type == FW_CRASH_DUMP_NONE) 1315 continue; 1316 1317 if (mem_type == FW_CRASH_DUMP_TYPE_MAX) { 1318 ath12k_dbg(ab, ATH12K_DBG_PCI, 1319 "target mem region type %d not supported", 1320 ab->qmi.target_mem[i].type); 1321 continue; 1322 } 1323 1324 if (!ab->qmi.target_mem[i].paddr) 1325 continue; 1326 1327 dump_seg_sz[mem_type] += ab->qmi.target_mem[i].size; 1328 } 1329 1330 for (i = 0; i < FW_CRASH_DUMP_TYPE_MAX; i++) { 1331 if (!dump_seg_sz[i]) 1332 continue; 1333 1334 len += sizeof(*dump_tlv) + dump_seg_sz[i]; 1335 } 1336 1337 if (len) 1338 len += sizeof(*file_data); 1339 1340 return len; 1341 } 1342 1343 static void ath12k_pci_coredump_download(struct ath12k_base *ab) 1344 { 1345 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1346 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 1347 struct image_info *rddm_img, *fw_img; 1348 struct timespec64 timestamp; 1349 int i, len, mem_idx; 1350 enum ath12k_fw_crash_dump_type mem_type; 1351 struct ath12k_dump_file_data *file_data; 1352 struct ath12k_tlv_dump_data *dump_tlv; 1353 size_t hdr_len = sizeof(*file_data); 1354 void *buf; 1355 u32 dump_seg_sz[FW_CRASH_DUMP_TYPE_MAX] = { 0 }; 1356 1357 ath12k_mhi_coredump(mhi_ctrl, false); 1358 1359 len = ath12k_pci_coredump_calculate_size(ab, dump_seg_sz); 1360 if (!len) { 1361 ath12k_warn(ab, "No crash dump data found for devcoredump"); 1362 return; 1363 } 1364 1365 rddm_img = mhi_ctrl->rddm_image; 1366 fw_img = mhi_ctrl->fbc_image; 1367 1368 /* dev_coredumpv() requires vmalloc data */ 1369 buf = vzalloc(len); 1370 if (!buf) 1371 return; 1372 1373 ab->dump_data = buf; 1374 ab->ath12k_coredump_len = len; 1375 file_data = ab->dump_data; 1376 strscpy(file_data->df_magic, "ATH12K-FW-DUMP", sizeof(file_data->df_magic)); 1377 file_data->len = cpu_to_le32(len); 1378 file_data->version = cpu_to_le32(ATH12K_FW_CRASH_DUMP_V2); 1379 file_data->chip_id = cpu_to_le32(ab_pci->dev_id); 1380 file_data->qrtr_id = cpu_to_le32(ab_pci->ab->qmi.service_ins_id); 1381 file_data->bus_id = cpu_to_le32(pci_domain_nr(ab_pci->pdev->bus)); 1382 guid_gen(&file_data->guid); 1383 ktime_get_real_ts64(×tamp); 1384 file_data->tv_sec = cpu_to_le64(timestamp.tv_sec); 1385 file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec); 1386 buf += hdr_len; 1387 dump_tlv = buf; 1388 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_PAGING_DATA); 1389 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA]); 1390 buf += COREDUMP_TLV_HDR_SIZE; 1391 1392 /* append all segments together as they are all part of a single contiguous 1393 * block of memory 1394 */ 1395 for (i = 0; i < fw_img->entries ; i++) { 1396 if (!fw_img->mhi_buf[i].buf) 1397 continue; 1398 1399 memcpy_fromio(buf, (void const __iomem *)fw_img->mhi_buf[i].buf, 1400 fw_img->mhi_buf[i].len); 1401 buf += fw_img->mhi_buf[i].len; 1402 } 1403 1404 dump_tlv = buf; 1405 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_RDDM_DATA); 1406 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA]); 1407 buf += COREDUMP_TLV_HDR_SIZE; 1408 1409 /* append all segments together as they are all part of a single contiguous 1410 * block of memory 1411 */ 1412 for (i = 0; i < rddm_img->entries; i++) { 1413 if (!rddm_img->mhi_buf[i].buf) 1414 continue; 1415 1416 memcpy_fromio(buf, (void const __iomem *)rddm_img->mhi_buf[i].buf, 1417 rddm_img->mhi_buf[i].len); 1418 buf += rddm_img->mhi_buf[i].len; 1419 } 1420 1421 mem_idx = FW_CRASH_DUMP_REMOTE_MEM_DATA; 1422 for (; mem_idx < FW_CRASH_DUMP_TYPE_MAX; mem_idx++) { 1423 if (!dump_seg_sz[mem_idx] || mem_idx == FW_CRASH_DUMP_NONE) 1424 continue; 1425 1426 dump_tlv = buf; 1427 dump_tlv->type = cpu_to_le32(mem_idx); 1428 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[mem_idx]); 1429 buf += COREDUMP_TLV_HDR_SIZE; 1430 1431 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 1432 mem_type = ath12k_coredump_get_dump_type 1433 (ab->qmi.target_mem[i].type); 1434 1435 if (mem_type != mem_idx) 1436 continue; 1437 1438 if (!ab->qmi.target_mem[i].paddr) { 1439 ath12k_dbg(ab, ATH12K_DBG_PCI, 1440 "Skipping mem region type %d", 1441 ab->qmi.target_mem[i].type); 1442 continue; 1443 } 1444 1445 memcpy_fromio(buf, ab->qmi.target_mem[i].v.ioaddr, 1446 ab->qmi.target_mem[i].size); 1447 buf += ab->qmi.target_mem[i].size; 1448 } 1449 } 1450 1451 queue_work(ab->workqueue, &ab->dump_work); 1452 } 1453 #endif 1454 1455 int ath12k_pci_power_up(struct ath12k_base *ab) 1456 { 1457 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1458 int ret; 1459 1460 ab_pci->register_window = 0; 1461 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1462 ath12k_pci_sw_reset(ab_pci->ab, true); 1463 1464 /* Disable ASPM during firmware download due to problems switching 1465 * to AMSS state. 1466 */ 1467 ath12k_pci_aspm_disable(ab_pci); 1468 1469 ath12k_pci_msi_enable(ab_pci); 1470 1471 if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID)) 1472 ath12k_pci_update_qrtr_node_id(ab); 1473 1474 ret = ath12k_mhi_start(ab_pci); 1475 if (ret) { 1476 ath12k_err(ab, "failed to start mhi: %d\n", ret); 1477 return ret; 1478 } 1479 1480 if (ab->static_window_map) 1481 ath12k_pci_select_static_window(ab_pci); 1482 1483 return 0; 1484 } 1485 1486 void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend) 1487 { 1488 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1489 1490 if (!test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags)) 1491 return; 1492 1493 /* restore aspm in case firmware bootup fails */ 1494 ath12k_pci_aspm_restore(ab_pci); 1495 1496 ath12k_pci_force_wake(ab_pci->ab); 1497 ath12k_pci_msi_disable(ab_pci); 1498 ath12k_mhi_stop(ab_pci, is_suspend); 1499 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1500 ath12k_pci_sw_reset(ab_pci->ab, false); 1501 } 1502 1503 static int ath12k_pci_panic_handler(struct ath12k_base *ab) 1504 { 1505 ath12k_pci_sw_reset(ab, false); 1506 1507 return NOTIFY_OK; 1508 } 1509 1510 static const struct ath12k_hif_ops ath12k_pci_hif_ops = { 1511 .start = ath12k_pci_start, 1512 .stop = ath12k_pci_stop, 1513 .read32 = ath12k_pci_read32, 1514 .write32 = ath12k_pci_write32, 1515 .power_down = ath12k_pci_power_down, 1516 .power_up = ath12k_pci_power_up, 1517 .suspend = ath12k_pci_hif_suspend, 1518 .resume = ath12k_pci_hif_resume, 1519 .irq_enable = ath12k_pci_ext_irq_enable, 1520 .irq_disable = ath12k_pci_ext_irq_disable, 1521 .get_msi_address = ath12k_pci_get_msi_address, 1522 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment, 1523 .map_service_to_pipe = ath12k_pci_map_service_to_pipe, 1524 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, 1525 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, 1526 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, 1527 .panic_handler = ath12k_pci_panic_handler, 1528 #ifdef CONFIG_ATH12K_COREDUMP 1529 .coredump_download = ath12k_pci_coredump_download, 1530 #endif 1531 }; 1532 1533 static 1534 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor) 1535 { 1536 u32 soc_hw_version; 1537 1538 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1539 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1540 soc_hw_version); 1541 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1542 soc_hw_version); 1543 1544 ath12k_dbg(ab, ATH12K_DBG_PCI, 1545 "pci tcsr_soc_hw_version major %d minor %d\n", 1546 *major, *minor); 1547 } 1548 1549 static int ath12k_pci_probe(struct pci_dev *pdev, 1550 const struct pci_device_id *pci_dev) 1551 { 1552 struct ath12k_base *ab; 1553 struct ath12k_pci *ab_pci; 1554 u32 soc_hw_version_major, soc_hw_version_minor; 1555 int ret; 1556 1557 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); 1558 if (!ab) { 1559 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); 1560 return -ENOMEM; 1561 } 1562 1563 ab->dev = &pdev->dev; 1564 pci_set_drvdata(pdev, ab); 1565 ab_pci = ath12k_pci_priv(ab); 1566 ab_pci->dev_id = pci_dev->device; 1567 ab_pci->ab = ab; 1568 ab_pci->pdev = pdev; 1569 ab->hif.ops = &ath12k_pci_hif_ops; 1570 ab->fw_mode = ATH12K_FIRMWARE_MODE_NORMAL; 1571 pci_set_drvdata(pdev, ab); 1572 spin_lock_init(&ab_pci->window_lock); 1573 1574 ret = ath12k_pci_claim(ab_pci, pdev); 1575 if (ret) { 1576 ath12k_err(ab, "failed to claim device: %d\n", ret); 1577 goto err_free_core; 1578 } 1579 1580 ath12k_dbg(ab, ATH12K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 1581 pdev->vendor, pdev->device, 1582 pdev->subsystem_vendor, pdev->subsystem_device); 1583 1584 ab->id.vendor = pdev->vendor; 1585 ab->id.device = pdev->device; 1586 ab->id.subsystem_vendor = pdev->subsystem_vendor; 1587 ab->id.subsystem_device = pdev->subsystem_device; 1588 1589 switch (pci_dev->device) { 1590 case QCN9274_DEVICE_ID: 1591 ab_pci->msi_config = &ath12k_msi_config[0]; 1592 ab->static_window_map = true; 1593 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; 1594 ab->hal_rx_ops = &hal_rx_qcn9274_ops; 1595 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1596 &soc_hw_version_minor); 1597 switch (soc_hw_version_major) { 1598 case ATH12K_PCI_SOC_HW_VERSION_2: 1599 ab->hw_rev = ATH12K_HW_QCN9274_HW20; 1600 break; 1601 case ATH12K_PCI_SOC_HW_VERSION_1: 1602 ab->hw_rev = ATH12K_HW_QCN9274_HW10; 1603 break; 1604 default: 1605 dev_err(&pdev->dev, 1606 "Unknown hardware version found for QCN9274: 0x%x\n", 1607 soc_hw_version_major); 1608 ret = -EOPNOTSUPP; 1609 goto err_pci_free_region; 1610 } 1611 break; 1612 case WCN7850_DEVICE_ID: 1613 ab->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD; 1614 ab_pci->msi_config = &ath12k_msi_config[0]; 1615 ab->static_window_map = false; 1616 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; 1617 ab->hal_rx_ops = &hal_rx_wcn7850_ops; 1618 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1619 &soc_hw_version_minor); 1620 switch (soc_hw_version_major) { 1621 case ATH12K_PCI_SOC_HW_VERSION_2: 1622 ab->hw_rev = ATH12K_HW_WCN7850_HW20; 1623 break; 1624 default: 1625 dev_err(&pdev->dev, 1626 "Unknown hardware version found for WCN7850: 0x%x\n", 1627 soc_hw_version_major); 1628 ret = -EOPNOTSUPP; 1629 goto err_pci_free_region; 1630 } 1631 break; 1632 1633 default: 1634 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1635 pci_dev->device); 1636 ret = -EOPNOTSUPP; 1637 goto err_pci_free_region; 1638 } 1639 1640 ret = ath12k_pci_msi_alloc(ab_pci); 1641 if (ret) { 1642 ath12k_err(ab, "failed to alloc msi: %d\n", ret); 1643 goto err_pci_free_region; 1644 } 1645 1646 ret = ath12k_core_pre_init(ab); 1647 if (ret) 1648 goto err_pci_msi_free; 1649 1650 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 1651 if (ret) { 1652 ath12k_err(ab, "failed to set irq affinity %d\n", ret); 1653 goto err_pci_msi_free; 1654 } 1655 1656 ret = ath12k_mhi_register(ab_pci); 1657 if (ret) { 1658 ath12k_err(ab, "failed to register mhi: %d\n", ret); 1659 goto err_irq_affinity_cleanup; 1660 } 1661 1662 ret = ath12k_hal_srng_init(ab); 1663 if (ret) 1664 goto err_mhi_unregister; 1665 1666 ret = ath12k_ce_alloc_pipes(ab); 1667 if (ret) { 1668 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1669 goto err_hal_srng_deinit; 1670 } 1671 1672 ath12k_pci_init_qmi_ce_config(ab); 1673 1674 ret = ath12k_pci_config_irq(ab); 1675 if (ret) { 1676 ath12k_err(ab, "failed to config irq: %d\n", ret); 1677 goto err_ce_free; 1678 } 1679 1680 /* kernel may allocate a dummy vector before request_irq and 1681 * then allocate a real vector when request_irq is called. 1682 * So get msi_data here again to avoid spurious interrupt 1683 * as msi_data will configured to srngs. 1684 */ 1685 ret = ath12k_pci_config_msi_data(ab_pci); 1686 if (ret) { 1687 ath12k_err(ab, "failed to config msi_data: %d\n", ret); 1688 goto err_free_irq; 1689 } 1690 1691 ret = ath12k_core_init(ab); 1692 if (ret) { 1693 ath12k_err(ab, "failed to init core: %d\n", ret); 1694 goto err_free_irq; 1695 } 1696 return 0; 1697 1698 err_free_irq: 1699 /* __free_irq() expects the caller to have cleared the affinity hint */ 1700 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1701 ath12k_pci_free_irq(ab); 1702 1703 err_ce_free: 1704 ath12k_ce_free_pipes(ab); 1705 1706 err_hal_srng_deinit: 1707 ath12k_hal_srng_deinit(ab); 1708 1709 err_mhi_unregister: 1710 ath12k_mhi_unregister(ab_pci); 1711 1712 err_irq_affinity_cleanup: 1713 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1714 1715 err_pci_msi_free: 1716 ath12k_pci_msi_free(ab_pci); 1717 1718 err_pci_free_region: 1719 ath12k_pci_free_region(ab_pci); 1720 1721 err_free_core: 1722 ath12k_core_free(ab); 1723 1724 return ret; 1725 } 1726 1727 static void ath12k_pci_remove(struct pci_dev *pdev) 1728 { 1729 struct ath12k_base *ab = pci_get_drvdata(pdev); 1730 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1731 1732 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1733 1734 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1735 ath12k_pci_power_down(ab, false); 1736 ath12k_qmi_deinit_service(ab); 1737 ath12k_core_hw_group_unassign(ab); 1738 goto qmi_fail; 1739 } 1740 1741 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); 1742 1743 cancel_work_sync(&ab->reset_work); 1744 cancel_work_sync(&ab->dump_work); 1745 ath12k_core_deinit(ab); 1746 1747 qmi_fail: 1748 ath12k_fw_unmap(ab); 1749 ath12k_mhi_unregister(ab_pci); 1750 1751 ath12k_pci_free_irq(ab); 1752 ath12k_pci_msi_free(ab_pci); 1753 ath12k_pci_free_region(ab_pci); 1754 1755 ath12k_hal_srng_deinit(ab); 1756 ath12k_ce_free_pipes(ab); 1757 ath12k_core_free(ab); 1758 } 1759 1760 static void ath12k_pci_hw_group_power_down(struct ath12k_hw_group *ag) 1761 { 1762 struct ath12k_base *ab; 1763 int i; 1764 1765 if (!ag) 1766 return; 1767 1768 mutex_lock(&ag->mutex); 1769 1770 for (i = 0; i < ag->num_devices; i++) { 1771 ab = ag->ab[i]; 1772 if (!ab) 1773 continue; 1774 1775 ath12k_pci_power_down(ab, false); 1776 } 1777 1778 mutex_unlock(&ag->mutex); 1779 } 1780 1781 static void ath12k_pci_shutdown(struct pci_dev *pdev) 1782 { 1783 struct ath12k_base *ab = pci_get_drvdata(pdev); 1784 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1785 1786 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1787 ath12k_pci_hw_group_power_down(ab->ag); 1788 } 1789 1790 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev) 1791 { 1792 struct ath12k_base *ab = dev_get_drvdata(dev); 1793 int ret; 1794 1795 ret = ath12k_core_suspend(ab); 1796 if (ret) 1797 ath12k_warn(ab, "failed to suspend core: %d\n", ret); 1798 1799 return ret; 1800 } 1801 1802 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev) 1803 { 1804 struct ath12k_base *ab = dev_get_drvdata(dev); 1805 int ret; 1806 1807 ret = ath12k_core_resume(ab); 1808 if (ret) 1809 ath12k_warn(ab, "failed to resume core: %d\n", ret); 1810 1811 return ret; 1812 } 1813 1814 static __maybe_unused int ath12k_pci_pm_suspend_late(struct device *dev) 1815 { 1816 struct ath12k_base *ab = dev_get_drvdata(dev); 1817 int ret; 1818 1819 ret = ath12k_core_suspend_late(ab); 1820 if (ret) 1821 ath12k_warn(ab, "failed to late suspend core: %d\n", ret); 1822 1823 return ret; 1824 } 1825 1826 static __maybe_unused int ath12k_pci_pm_resume_early(struct device *dev) 1827 { 1828 struct ath12k_base *ab = dev_get_drvdata(dev); 1829 int ret; 1830 1831 ret = ath12k_core_resume_early(ab); 1832 if (ret) 1833 ath12k_warn(ab, "failed to early resume core: %d\n", ret); 1834 1835 return ret; 1836 } 1837 1838 static const struct dev_pm_ops __maybe_unused ath12k_pci_pm_ops = { 1839 SET_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend, 1840 ath12k_pci_pm_resume) 1841 SET_LATE_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend_late, 1842 ath12k_pci_pm_resume_early) 1843 }; 1844 1845 static struct pci_driver ath12k_pci_driver = { 1846 .name = "ath12k_pci", 1847 .id_table = ath12k_pci_id_table, 1848 .probe = ath12k_pci_probe, 1849 .remove = ath12k_pci_remove, 1850 .shutdown = ath12k_pci_shutdown, 1851 .driver.pm = &ath12k_pci_pm_ops, 1852 }; 1853 1854 int ath12k_pci_init(void) 1855 { 1856 int ret; 1857 1858 ret = pci_register_driver(&ath12k_pci_driver); 1859 if (ret) { 1860 pr_err("failed to register ath12k pci driver: %d\n", 1861 ret); 1862 return ret; 1863 } 1864 1865 return 0; 1866 } 1867 1868 void ath12k_pci_exit(void) 1869 { 1870 pci_unregister_driver(&ath12k_pci_driver); 1871 } 1872