1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 #include <linux/time.h> 11 #include <linux/vmalloc.h> 12 13 #include "pci.h" 14 #include "core.h" 15 #include "hif.h" 16 #include "mhi.h" 17 #include "debug.h" 18 19 #define ATH12K_PCI_BAR_NUM 0 20 #define ATH12K_PCI_DMA_MASK 36 21 22 #define ATH12K_PCI_IRQ_CE0_OFFSET 3 23 24 #define WINDOW_ENABLE_BIT 0x40000000 25 #define WINDOW_REG_ADDRESS 0x310c 26 #define WINDOW_VALUE_MASK GENMASK(24, 19) 27 #define WINDOW_START 0x80000 28 #define WINDOW_RANGE_MASK GENMASK(18, 0) 29 #define WINDOW_STATIC_MASK GENMASK(31, 6) 30 31 #define TCSR_SOC_HW_VERSION 0x1B00000 32 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 33 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4) 34 35 /* BAR0 + 4k is always accessible, and no 36 * need to force wakeup. 37 * 4K - 32 = 0xFE0 38 */ 39 #define ACCESS_ALWAYS_OFF 0xFE0 40 41 #define QCN9274_DEVICE_ID 0x1109 42 #define WCN7850_DEVICE_ID 0x1107 43 44 #define PCIE_LOCAL_REG_QRTR_NODE_ID 0x1E03164 45 #define DOMAIN_NUMBER_MASK GENMASK(7, 4) 46 #define BUS_NUMBER_MASK GENMASK(3, 0) 47 48 static const struct pci_device_id ath12k_pci_id_table[] = { 49 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) }, 50 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) }, 51 {0} 52 }; 53 54 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table); 55 56 /* TODO: revisit IRQ mapping for new SRNG's */ 57 static const struct ath12k_msi_config ath12k_msi_config[] = { 58 { 59 .total_vectors = 16, 60 .total_users = 3, 61 .users = (struct ath12k_msi_user[]) { 62 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 63 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 64 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 65 }, 66 }, 67 }; 68 69 static const struct ath12k_msi_config msi_config_one_msi = { 70 .total_vectors = 1, 71 .total_users = 4, 72 .users = (struct ath12k_msi_user[]) { 73 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 74 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 75 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 76 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 77 }, 78 }; 79 80 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { 81 "bhi", 82 "mhi-er0", 83 "mhi-er1", 84 "ce0", 85 "ce1", 86 "ce2", 87 "ce3", 88 "ce4", 89 "ce5", 90 "ce6", 91 "ce7", 92 "ce8", 93 "ce9", 94 "ce10", 95 "ce11", 96 "ce12", 97 "ce13", 98 "ce14", 99 "ce15", 100 "host2wbm-desc-feed", 101 "host2reo-re-injection", 102 "host2reo-command", 103 "host2rxdma-monitor-ring3", 104 "host2rxdma-monitor-ring2", 105 "host2rxdma-monitor-ring1", 106 "reo2ost-exception", 107 "wbm2host-rx-release", 108 "reo2host-status", 109 "reo2host-destination-ring4", 110 "reo2host-destination-ring3", 111 "reo2host-destination-ring2", 112 "reo2host-destination-ring1", 113 "rxdma2host-monitor-destination-mac3", 114 "rxdma2host-monitor-destination-mac2", 115 "rxdma2host-monitor-destination-mac1", 116 "ppdu-end-interrupts-mac3", 117 "ppdu-end-interrupts-mac2", 118 "ppdu-end-interrupts-mac1", 119 "rxdma2host-monitor-status-ring-mac3", 120 "rxdma2host-monitor-status-ring-mac2", 121 "rxdma2host-monitor-status-ring-mac1", 122 "host2rxdma-host-buf-ring-mac3", 123 "host2rxdma-host-buf-ring-mac2", 124 "host2rxdma-host-buf-ring-mac1", 125 "rxdma2host-destination-ring-mac3", 126 "rxdma2host-destination-ring-mac2", 127 "rxdma2host-destination-ring-mac1", 128 "host2tcl-input-ring4", 129 "host2tcl-input-ring3", 130 "host2tcl-input-ring2", 131 "host2tcl-input-ring1", 132 "wbm2host-tx-completions-ring4", 133 "wbm2host-tx-completions-ring3", 134 "wbm2host-tx-completions-ring2", 135 "wbm2host-tx-completions-ring1", 136 "tcl2host-status-ring", 137 }; 138 139 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab) 140 { 141 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 142 143 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 144 } 145 146 static void ath12k_pci_bus_release(struct ath12k_base *ab) 147 { 148 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 149 150 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 151 } 152 153 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = { 154 .wakeup = NULL, 155 .release = NULL, 156 }; 157 158 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = { 159 .wakeup = ath12k_pci_bus_wake_up, 160 .release = ath12k_pci_bus_release, 161 }; 162 163 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset) 164 { 165 struct ath12k_base *ab = ab_pci->ab; 166 167 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK); 168 u32 static_window; 169 170 lockdep_assert_held(&ab_pci->window_lock); 171 172 /* Preserve the static window configuration and reset only dynamic window */ 173 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; 174 window |= static_window; 175 176 if (window != ab_pci->register_window) { 177 iowrite32(WINDOW_ENABLE_BIT | window, 178 ab->mem + WINDOW_REG_ADDRESS); 179 ioread32(ab->mem + WINDOW_REG_ADDRESS); 180 ab_pci->register_window = window; 181 } 182 } 183 184 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci) 185 { 186 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK); 187 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK); 188 u32 window; 189 190 window = (umac_window << 12) | (ce_window << 6); 191 192 spin_lock_bh(&ab_pci->window_lock); 193 ab_pci->register_window = window; 194 spin_unlock_bh(&ab_pci->window_lock); 195 196 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 197 } 198 199 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab, 200 u32 offset) 201 { 202 u32 window_start; 203 204 /* If offset lies within DP register range, use 3rd window */ 205 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 206 window_start = 3 * WINDOW_START; 207 /* If offset lies within CE register range, use 2nd window */ 208 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 209 window_start = 2 * WINDOW_START; 210 else 211 window_start = WINDOW_START; 212 213 return window_start; 214 } 215 216 static inline bool ath12k_pci_is_offset_within_mhi_region(u32 offset) 217 { 218 return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END); 219 } 220 221 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) 222 { 223 u32 val, delay; 224 225 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 226 227 val |= PCIE_SOC_GLOBAL_RESET_V; 228 229 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 230 231 /* TODO: exact time to sleep is uncertain */ 232 delay = 10; 233 mdelay(delay); 234 235 /* Need to toggle V bit back otherwise stuck in reset status */ 236 val &= ~PCIE_SOC_GLOBAL_RESET_V; 237 238 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 239 240 mdelay(delay); 241 242 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 243 if (val == 0xffffffff) 244 ath12k_warn(ab, "link down error during global reset\n"); 245 } 246 247 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab) 248 { 249 u32 val; 250 251 /* read cookie */ 252 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 253 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val); 254 255 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 256 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 257 258 /* TODO: exact time to sleep is uncertain */ 259 mdelay(10); 260 261 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 262 * continuing warm path and entering dead loop. 263 */ 264 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 265 mdelay(10); 266 267 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 268 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 269 270 /* A read clear register. clear the register to prevent 271 * Q6 from entering wrong code path. 272 */ 273 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 274 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val); 275 } 276 277 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab) 278 { 279 u32 val; 280 int i; 281 282 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 283 284 /* PCIE link seems very unstable after the Hot Reset*/ 285 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 286 if (val == 0xffffffff) 287 mdelay(5); 288 289 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 290 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 291 } 292 293 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val); 294 295 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab)); 296 val |= GCC_GCC_PCIE_HOT_RST_VAL; 297 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST(ab), val); 298 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab)); 299 300 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 301 302 mdelay(5); 303 } 304 305 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab) 306 { 307 /* This is a WAR for PCIE Hotreset. 308 * When target receive Hotreset, but will set the interrupt. 309 * So when download SBL again, SBL will open Interrupt and 310 * receive it, and crash immediately. 311 */ 312 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 313 } 314 315 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab) 316 { 317 u32 val; 318 319 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 320 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 321 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 322 } 323 324 static void ath12k_pci_force_wake(struct ath12k_base *ab) 325 { 326 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 327 mdelay(5); 328 } 329 330 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) 331 { 332 if (power_on) { 333 ath12k_pci_enable_ltssm(ab); 334 ath12k_pci_clear_all_intrs(ab); 335 ath12k_pci_set_wlaon_pwr_ctrl(ab); 336 } 337 338 ath12k_mhi_clear_vector(ab); 339 ath12k_pci_clear_dbg_registers(ab); 340 ath12k_pci_soc_global_reset(ab); 341 ath12k_mhi_set_mhictrl_reset(ab); 342 } 343 344 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab) 345 { 346 int i, j; 347 348 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 349 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 350 351 for (j = 0; j < irq_grp->num_irq; j++) 352 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 353 354 netif_napi_del(&irq_grp->napi); 355 free_netdev(irq_grp->napi_ndev); 356 } 357 } 358 359 static void ath12k_pci_free_irq(struct ath12k_base *ab) 360 { 361 int i, irq_idx; 362 363 for (i = 0; i < ab->hw_params->ce_count; i++) { 364 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 365 continue; 366 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 367 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 368 } 369 370 ath12k_pci_free_ext_irq(ab); 371 } 372 373 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) 374 { 375 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 376 u32 irq_idx; 377 378 /* In case of one MSI vector, we handle irq enable/disable in a 379 * uniform way since we only have one irq 380 */ 381 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 382 return; 383 384 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 385 enable_irq(ab->irq_num[irq_idx]); 386 } 387 388 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) 389 { 390 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 391 u32 irq_idx; 392 393 /* In case of one MSI vector, we handle irq enable/disable in a 394 * uniform way since we only have one irq 395 */ 396 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 397 return; 398 399 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 400 disable_irq_nosync(ab->irq_num[irq_idx]); 401 } 402 403 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab) 404 { 405 int i; 406 407 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 408 409 for (i = 0; i < ab->hw_params->ce_count; i++) { 410 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 411 continue; 412 ath12k_pci_ce_irq_disable(ab, i); 413 } 414 } 415 416 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) 417 { 418 int i; 419 int irq_idx; 420 421 for (i = 0; i < ab->hw_params->ce_count; i++) { 422 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 423 continue; 424 425 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 426 synchronize_irq(ab->irq_num[irq_idx]); 427 } 428 } 429 430 static void ath12k_pci_ce_workqueue(struct work_struct *work) 431 { 432 struct ath12k_ce_pipe *ce_pipe = from_work(ce_pipe, work, intr_wq); 433 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 434 435 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 436 437 enable_irq(ce_pipe->ab->irq_num[irq_idx]); 438 } 439 440 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg) 441 { 442 struct ath12k_ce_pipe *ce_pipe = arg; 443 struct ath12k_base *ab = ce_pipe->ab; 444 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 445 446 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) 447 return IRQ_HANDLED; 448 449 /* last interrupt received for this CE */ 450 ce_pipe->timestamp = jiffies; 451 452 disable_irq_nosync(ab->irq_num[irq_idx]); 453 454 queue_work(system_bh_wq, &ce_pipe->intr_wq); 455 456 return IRQ_HANDLED; 457 } 458 459 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) 460 { 461 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 462 int i; 463 464 /* In case of one MSI vector, we handle irq enable/disable 465 * in a uniform way since we only have one irq 466 */ 467 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 468 return; 469 470 for (i = 0; i < irq_grp->num_irq; i++) 471 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 472 } 473 474 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 475 { 476 int i; 477 478 if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 479 return; 480 481 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 482 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 483 484 ath12k_pci_ext_grp_disable(irq_grp); 485 486 if (irq_grp->napi_enabled) { 487 napi_synchronize(&irq_grp->napi); 488 napi_disable(&irq_grp->napi); 489 irq_grp->napi_enabled = false; 490 } 491 } 492 } 493 494 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) 495 { 496 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 497 int i; 498 499 /* In case of one MSI vector, we handle irq enable/disable in a 500 * uniform way since we only have one irq 501 */ 502 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 503 return; 504 505 for (i = 0; i < irq_grp->num_irq; i++) 506 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 507 } 508 509 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab) 510 { 511 int i, j, irq_idx; 512 513 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 514 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 515 516 for (j = 0; j < irq_grp->num_irq; j++) { 517 irq_idx = irq_grp->irqs[j]; 518 synchronize_irq(ab->irq_num[irq_idx]); 519 } 520 } 521 } 522 523 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 524 { 525 struct ath12k_ext_irq_grp *irq_grp = container_of(napi, 526 struct ath12k_ext_irq_grp, 527 napi); 528 struct ath12k_base *ab = irq_grp->ab; 529 int work_done; 530 int i; 531 532 work_done = ath12k_dp_service_srng(ab, irq_grp, budget); 533 if (work_done < budget) { 534 napi_complete_done(napi, work_done); 535 for (i = 0; i < irq_grp->num_irq; i++) 536 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 537 } 538 539 if (work_done > budget) 540 work_done = budget; 541 542 return work_done; 543 } 544 545 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg) 546 { 547 struct ath12k_ext_irq_grp *irq_grp = arg; 548 struct ath12k_base *ab = irq_grp->ab; 549 int i; 550 551 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 552 return IRQ_HANDLED; 553 554 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); 555 556 /* last interrupt received for this group */ 557 irq_grp->timestamp = jiffies; 558 559 for (i = 0; i < irq_grp->num_irq; i++) 560 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 561 562 napi_schedule(&irq_grp->napi); 563 564 return IRQ_HANDLED; 565 } 566 567 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) 568 { 569 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 570 int i, j, n, ret, num_vectors = 0; 571 u32 user_base_data = 0, base_vector = 0, base_idx; 572 struct ath12k_ext_irq_grp *irq_grp; 573 574 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 575 ret = ath12k_pci_get_user_msi_assignment(ab, "DP", 576 &num_vectors, 577 &user_base_data, 578 &base_vector); 579 if (ret < 0) 580 return ret; 581 582 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 583 irq_grp = &ab->ext_irq_grp[i]; 584 u32 num_irq = 0; 585 586 irq_grp->ab = ab; 587 irq_grp->grp_id = i; 588 irq_grp->napi_ndev = alloc_netdev_dummy(0); 589 if (!irq_grp->napi_ndev) { 590 ret = -ENOMEM; 591 goto fail_allocate; 592 } 593 594 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi, 595 ath12k_pci_ext_grp_napi_poll); 596 597 if (ab->hw_params->ring_mask->tx[i] || 598 ab->hw_params->ring_mask->rx[i] || 599 ab->hw_params->ring_mask->rx_err[i] || 600 ab->hw_params->ring_mask->rx_wbm_rel[i] || 601 ab->hw_params->ring_mask->reo_status[i] || 602 ab->hw_params->ring_mask->host2rxdma[i] || 603 ab->hw_params->ring_mask->rx_mon_dest[i] || 604 ab->hw_params->ring_mask->rx_mon_status[i]) { 605 num_irq = 1; 606 } 607 608 irq_grp->num_irq = num_irq; 609 irq_grp->irqs[0] = base_idx + i; 610 611 for (j = 0; j < irq_grp->num_irq; j++) { 612 int irq_idx = irq_grp->irqs[j]; 613 int vector = (i % num_vectors) + base_vector; 614 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); 615 616 ab->irq_num[irq_idx] = irq; 617 618 ath12k_dbg(ab, ATH12K_DBG_PCI, 619 "irq:%d group:%d\n", irq, i); 620 621 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 622 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler, 623 ab_pci->irq_flags, 624 "DP_EXT_IRQ", irq_grp); 625 if (ret) { 626 ath12k_err(ab, "failed request irq %d: %d\n", 627 vector, ret); 628 goto fail_request; 629 } 630 } 631 ath12k_pci_ext_grp_disable(irq_grp); 632 } 633 634 return 0; 635 636 fail_request: 637 /* i ->napi_ndev was properly allocated. Free it also */ 638 i += 1; 639 fail_allocate: 640 for (n = 0; n < i; n++) { 641 irq_grp = &ab->ext_irq_grp[n]; 642 free_netdev(irq_grp->napi_ndev); 643 } 644 return ret; 645 } 646 647 static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci, 648 const struct cpumask *m) 649 { 650 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 651 return 0; 652 653 return irq_set_affinity_and_hint(ab_pci->pdev->irq, m); 654 } 655 656 static int ath12k_pci_config_irq(struct ath12k_base *ab) 657 { 658 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 659 struct ath12k_ce_pipe *ce_pipe; 660 u32 msi_data_start; 661 u32 msi_data_count, msi_data_idx; 662 u32 msi_irq_start; 663 unsigned int msi_data; 664 int irq, i, ret, irq_idx; 665 666 ret = ath12k_pci_get_user_msi_assignment(ab, 667 "CE", &msi_data_count, 668 &msi_data_start, &msi_irq_start); 669 if (ret) 670 return ret; 671 672 /* Configure CE irqs */ 673 674 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 675 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 676 continue; 677 678 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 679 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); 680 ce_pipe = &ab->ce.ce_pipe[i]; 681 682 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 683 684 INIT_WORK(&ce_pipe->intr_wq, ath12k_pci_ce_workqueue); 685 686 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler, 687 ab_pci->irq_flags, irq_name[irq_idx], 688 ce_pipe); 689 if (ret) { 690 ath12k_err(ab, "failed to request irq %d: %d\n", 691 irq_idx, ret); 692 return ret; 693 } 694 695 ab->irq_num[irq_idx] = irq; 696 msi_data_idx++; 697 698 ath12k_pci_ce_irq_disable(ab, i); 699 } 700 701 ret = ath12k_pci_ext_irq_config(ab); 702 if (ret) 703 return ret; 704 705 return 0; 706 } 707 708 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab) 709 { 710 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 711 712 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 713 struct pci_bus *bus = ab_pci->pdev->bus; 714 715 cfg->tgt_ce = ab->hw_params->target_ce_config; 716 cfg->tgt_ce_len = ab->hw_params->target_ce_count; 717 718 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; 719 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; 720 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; 721 722 if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID)) { 723 ab_pci->qmi_instance = 724 u32_encode_bits(pci_domain_nr(bus), DOMAIN_NUMBER_MASK) | 725 u32_encode_bits(bus->number, BUS_NUMBER_MASK); 726 ab->qmi.service_ins_id += ab_pci->qmi_instance; 727 } 728 } 729 730 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab) 731 { 732 int i; 733 734 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 735 736 for (i = 0; i < ab->hw_params->ce_count; i++) { 737 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 738 continue; 739 ath12k_pci_ce_irq_enable(ab, i); 740 } 741 } 742 743 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable) 744 { 745 struct pci_dev *dev = ab_pci->pdev; 746 u16 control; 747 748 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 749 750 if (enable) 751 control |= PCI_MSI_FLAGS_ENABLE; 752 else 753 control &= ~PCI_MSI_FLAGS_ENABLE; 754 755 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 756 } 757 758 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci) 759 { 760 ath12k_pci_msi_config(ab_pci, true); 761 } 762 763 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci) 764 { 765 ath12k_pci_msi_config(ab_pci, false); 766 } 767 768 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci) 769 { 770 struct ath12k_base *ab = ab_pci->ab; 771 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 772 struct msi_desc *msi_desc; 773 int num_vectors; 774 int ret; 775 776 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 777 msi_config->total_vectors, 778 msi_config->total_vectors, 779 PCI_IRQ_MSI); 780 781 if (num_vectors == msi_config->total_vectors) { 782 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 783 ab_pci->irq_flags = IRQF_SHARED; 784 } else { 785 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 786 1, 787 1, 788 PCI_IRQ_MSI); 789 if (num_vectors < 0) { 790 ret = -EINVAL; 791 goto reset_msi_config; 792 } 793 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 794 ab_pci->msi_config = &msi_config_one_msi; 795 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 796 ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n"); 797 } 798 799 ath12k_info(ab, "MSI vectors: %d\n", num_vectors); 800 801 ath12k_pci_msi_disable(ab_pci); 802 803 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 804 if (!msi_desc) { 805 ath12k_err(ab, "msi_desc is NULL!\n"); 806 ret = -EINVAL; 807 goto free_msi_vector; 808 } 809 810 ab_pci->msi_ep_base_data = msi_desc->msg.data; 811 if (msi_desc->pci.msi_attrib.is_64) 812 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 813 814 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 815 816 return 0; 817 818 free_msi_vector: 819 pci_free_irq_vectors(ab_pci->pdev); 820 821 reset_msi_config: 822 return ret; 823 } 824 825 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci) 826 { 827 pci_free_irq_vectors(ab_pci->pdev); 828 } 829 830 static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci) 831 { 832 struct msi_desc *msi_desc; 833 834 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 835 if (!msi_desc) { 836 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n"); 837 pci_free_irq_vectors(ab_pci->pdev); 838 return -EINVAL; 839 } 840 841 ab_pci->msi_ep_base_data = msi_desc->msg.data; 842 843 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 844 ab_pci->msi_ep_base_data); 845 846 return 0; 847 } 848 849 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev) 850 { 851 struct ath12k_base *ab = ab_pci->ab; 852 u16 device_id; 853 int ret = 0; 854 855 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 856 if (device_id != ab_pci->dev_id) { 857 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 858 device_id, ab_pci->dev_id); 859 ret = -EIO; 860 goto out; 861 } 862 863 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM); 864 if (ret) { 865 ath12k_err(ab, "failed to assign pci resource: %d\n", ret); 866 goto out; 867 } 868 869 ret = pci_enable_device(pdev); 870 if (ret) { 871 ath12k_err(ab, "failed to enable pci device: %d\n", ret); 872 goto out; 873 } 874 875 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci"); 876 if (ret) { 877 ath12k_err(ab, "failed to request pci region: %d\n", ret); 878 goto disable_device; 879 } 880 881 ab_pci->dma_mask = DMA_BIT_MASK(ATH12K_PCI_DMA_MASK); 882 dma_set_mask(&pdev->dev, ab_pci->dma_mask); 883 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 884 885 pci_set_master(pdev); 886 887 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); 888 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); 889 if (!ab->mem) { 890 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM); 891 ret = -EIO; 892 goto release_region; 893 } 894 895 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%p\n", ab->mem); 896 return 0; 897 898 release_region: 899 pci_release_region(pdev, ATH12K_PCI_BAR_NUM); 900 disable_device: 901 pci_disable_device(pdev); 902 out: 903 return ret; 904 } 905 906 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci) 907 { 908 struct ath12k_base *ab = ab_pci->ab; 909 struct pci_dev *pci_dev = ab_pci->pdev; 910 911 pci_iounmap(pci_dev, ab->mem); 912 ab->mem = NULL; 913 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM); 914 if (pci_is_enabled(pci_dev)) 915 pci_disable_device(pci_dev); 916 } 917 918 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci) 919 { 920 struct ath12k_base *ab = ab_pci->ab; 921 922 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 923 &ab_pci->link_ctl); 924 925 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 926 ab_pci->link_ctl, 927 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 928 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 929 930 /* disable L0s and L1 */ 931 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 932 PCI_EXP_LNKCTL_ASPMC); 933 934 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); 935 } 936 937 static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab) 938 { 939 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 940 u32 reg; 941 942 /* On platforms with two or more identical mhi devices, qmi service run 943 * with identical qrtr-node-id. Because of this identical ID qrtr-lookup 944 * cannot register more than one qmi service with identical node ID. 945 * 946 * This generates a unique instance ID from PCIe domain number and bus number, 947 * writes to the given register, it is available for firmware when the QMI service 948 * is spawned. 949 */ 950 reg = PCIE_LOCAL_REG_QRTR_NODE_ID & WINDOW_RANGE_MASK; 951 ath12k_pci_write32(ab, reg, ab_pci->qmi_instance); 952 953 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n", 954 reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg)); 955 } 956 957 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) 958 { 959 if (ab_pci->ab->hw_params->supports_aspm && 960 test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) 961 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 962 PCI_EXP_LNKCTL_ASPMC, 963 ab_pci->link_ctl & 964 PCI_EXP_LNKCTL_ASPMC); 965 } 966 967 static void ath12k_pci_cancel_workqueue(struct ath12k_base *ab) 968 { 969 int i; 970 971 for (i = 0; i < ab->hw_params->ce_count; i++) { 972 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 973 974 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 975 continue; 976 977 cancel_work_sync(&ce_pipe->intr_wq); 978 } 979 } 980 981 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab) 982 { 983 ath12k_pci_ce_irqs_disable(ab); 984 ath12k_pci_sync_ce_irqs(ab); 985 ath12k_pci_cancel_workqueue(ab); 986 } 987 988 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 989 u8 *ul_pipe, u8 *dl_pipe) 990 { 991 const struct service_to_pipe *entry; 992 bool ul_set = false, dl_set = false; 993 int i; 994 995 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { 996 entry = &ab->hw_params->svc_to_ce_map[i]; 997 998 if (__le32_to_cpu(entry->service_id) != service_id) 999 continue; 1000 1001 switch (__le32_to_cpu(entry->pipedir)) { 1002 case PIPEDIR_NONE: 1003 break; 1004 case PIPEDIR_IN: 1005 WARN_ON(dl_set); 1006 *dl_pipe = __le32_to_cpu(entry->pipenum); 1007 dl_set = true; 1008 break; 1009 case PIPEDIR_OUT: 1010 WARN_ON(ul_set); 1011 *ul_pipe = __le32_to_cpu(entry->pipenum); 1012 ul_set = true; 1013 break; 1014 case PIPEDIR_INOUT: 1015 WARN_ON(dl_set); 1016 WARN_ON(ul_set); 1017 *dl_pipe = __le32_to_cpu(entry->pipenum); 1018 *ul_pipe = __le32_to_cpu(entry->pipenum); 1019 dl_set = true; 1020 ul_set = true; 1021 break; 1022 } 1023 } 1024 1025 if (WARN_ON(!ul_set || !dl_set)) 1026 return -ENOENT; 1027 1028 return 0; 1029 } 1030 1031 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector) 1032 { 1033 struct pci_dev *pci_dev = to_pci_dev(dev); 1034 1035 return pci_irq_vector(pci_dev, vector); 1036 } 1037 1038 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 1039 int *num_vectors, u32 *user_base_data, 1040 u32 *base_vector) 1041 { 1042 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1043 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 1044 int idx; 1045 1046 for (idx = 0; idx < msi_config->total_users; idx++) { 1047 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 1048 *num_vectors = msi_config->users[idx].num_vectors; 1049 *base_vector = msi_config->users[idx].base_vector; 1050 *user_base_data = *base_vector + ab_pci->msi_ep_base_data; 1051 1052 ath12k_dbg(ab, ATH12K_DBG_PCI, 1053 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 1054 user_name, *num_vectors, *user_base_data, 1055 *base_vector); 1056 1057 return 0; 1058 } 1059 } 1060 1061 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 1062 1063 return -EINVAL; 1064 } 1065 1066 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 1067 u32 *msi_addr_hi) 1068 { 1069 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1070 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 1071 1072 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 1073 msi_addr_lo); 1074 1075 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 1076 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 1077 msi_addr_hi); 1078 } else { 1079 *msi_addr_hi = 0; 1080 } 1081 } 1082 1083 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 1084 u32 *msi_idx) 1085 { 1086 u32 i, msi_data_idx; 1087 1088 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 1089 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1090 continue; 1091 1092 if (ce_id == i) 1093 break; 1094 1095 msi_data_idx++; 1096 } 1097 *msi_idx = msi_data_idx; 1098 } 1099 1100 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab) 1101 { 1102 ath12k_pci_ce_irqs_enable(ab); 1103 } 1104 1105 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab) 1106 { 1107 ath12k_pci_ce_irq_disable_sync(ab); 1108 } 1109 1110 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) 1111 { 1112 int i; 1113 1114 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 1115 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 1116 1117 if (!irq_grp->napi_enabled) { 1118 napi_enable(&irq_grp->napi); 1119 irq_grp->napi_enabled = true; 1120 } 1121 1122 ath12k_pci_ext_grp_enable(irq_grp); 1123 } 1124 1125 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); 1126 } 1127 1128 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 1129 { 1130 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 1131 return; 1132 1133 __ath12k_pci_ext_irq_disable(ab); 1134 ath12k_pci_sync_ext_irqs(ab); 1135 } 1136 1137 int ath12k_pci_hif_suspend(struct ath12k_base *ab) 1138 { 1139 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1140 1141 ath12k_mhi_suspend(ar_pci); 1142 1143 return 0; 1144 } 1145 1146 int ath12k_pci_hif_resume(struct ath12k_base *ab) 1147 { 1148 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1149 1150 ath12k_mhi_resume(ar_pci); 1151 1152 return 0; 1153 } 1154 1155 void ath12k_pci_stop(struct ath12k_base *ab) 1156 { 1157 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1158 1159 if (!test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags)) 1160 return; 1161 1162 ath12k_pci_ce_irq_disable_sync(ab); 1163 ath12k_ce_cleanup_pipes(ab); 1164 } 1165 1166 int ath12k_pci_start(struct ath12k_base *ab) 1167 { 1168 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1169 1170 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1171 1172 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 1173 ath12k_pci_aspm_restore(ab_pci); 1174 else 1175 ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 1176 1177 ath12k_pci_ce_irqs_enable(ab); 1178 ath12k_ce_rx_post_buf(ab); 1179 1180 return 0; 1181 } 1182 1183 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) 1184 { 1185 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1186 u32 val, window_start; 1187 int ret = 0; 1188 1189 /* for offset beyond BAR + 4K - 32, may 1190 * need to wakeup MHI to access. 1191 */ 1192 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1193 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1194 ret = ab_pci->pci_ops->wakeup(ab); 1195 1196 if (offset < WINDOW_START) { 1197 val = ioread32(ab->mem + offset); 1198 } else { 1199 if (ab->static_window_map) 1200 window_start = ath12k_pci_get_window_start(ab, offset); 1201 else 1202 window_start = WINDOW_START; 1203 1204 if (window_start == WINDOW_START) { 1205 spin_lock_bh(&ab_pci->window_lock); 1206 ath12k_pci_select_window(ab_pci, offset); 1207 1208 if (ath12k_pci_is_offset_within_mhi_region(offset)) { 1209 offset = offset - PCI_MHIREGLEN_REG; 1210 val = ioread32(ab->mem + 1211 (offset & WINDOW_RANGE_MASK)); 1212 } else { 1213 val = ioread32(ab->mem + window_start + 1214 (offset & WINDOW_RANGE_MASK)); 1215 } 1216 spin_unlock_bh(&ab_pci->window_lock); 1217 } else { 1218 val = ioread32(ab->mem + window_start + 1219 (offset & WINDOW_RANGE_MASK)); 1220 } 1221 } 1222 1223 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1224 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1225 !ret) 1226 ab_pci->pci_ops->release(ab); 1227 return val; 1228 } 1229 1230 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value) 1231 { 1232 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1233 u32 window_start; 1234 int ret = 0; 1235 1236 /* for offset beyond BAR + 4K - 32, may 1237 * need to wakeup MHI to access. 1238 */ 1239 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1240 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1241 ret = ab_pci->pci_ops->wakeup(ab); 1242 1243 if (offset < WINDOW_START) { 1244 iowrite32(value, ab->mem + offset); 1245 } else { 1246 if (ab->static_window_map) 1247 window_start = ath12k_pci_get_window_start(ab, offset); 1248 else 1249 window_start = WINDOW_START; 1250 1251 if (window_start == WINDOW_START) { 1252 spin_lock_bh(&ab_pci->window_lock); 1253 ath12k_pci_select_window(ab_pci, offset); 1254 1255 if (ath12k_pci_is_offset_within_mhi_region(offset)) { 1256 offset = offset - PCI_MHIREGLEN_REG; 1257 iowrite32(value, ab->mem + 1258 (offset & WINDOW_RANGE_MASK)); 1259 } else { 1260 iowrite32(value, ab->mem + window_start + 1261 (offset & WINDOW_RANGE_MASK)); 1262 } 1263 spin_unlock_bh(&ab_pci->window_lock); 1264 } else { 1265 iowrite32(value, ab->mem + window_start + 1266 (offset & WINDOW_RANGE_MASK)); 1267 } 1268 } 1269 1270 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1271 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1272 !ret) 1273 ab_pci->pci_ops->release(ab); 1274 } 1275 1276 #ifdef CONFIG_ATH12K_COREDUMP 1277 static int ath12k_pci_coredump_calculate_size(struct ath12k_base *ab, u32 *dump_seg_sz) 1278 { 1279 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1280 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 1281 struct image_info *rddm_img, *fw_img; 1282 struct ath12k_tlv_dump_data *dump_tlv; 1283 enum ath12k_fw_crash_dump_type mem_type; 1284 u32 len = 0, rddm_tlv_sz = 0, paging_tlv_sz = 0; 1285 struct ath12k_dump_file_data *file_data; 1286 int i; 1287 1288 rddm_img = mhi_ctrl->rddm_image; 1289 if (!rddm_img) { 1290 ath12k_err(ab, "No RDDM dump found\n"); 1291 return 0; 1292 } 1293 1294 fw_img = mhi_ctrl->fbc_image; 1295 1296 for (i = 0; i < fw_img->entries ; i++) { 1297 if (!fw_img->mhi_buf[i].buf) 1298 continue; 1299 1300 paging_tlv_sz += fw_img->mhi_buf[i].len; 1301 } 1302 dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA] = paging_tlv_sz; 1303 1304 for (i = 0; i < rddm_img->entries; i++) { 1305 if (!rddm_img->mhi_buf[i].buf) 1306 continue; 1307 1308 rddm_tlv_sz += rddm_img->mhi_buf[i].len; 1309 } 1310 dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA] = rddm_tlv_sz; 1311 1312 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 1313 mem_type = ath12k_coredump_get_dump_type(ab->qmi.target_mem[i].type); 1314 1315 if (mem_type == FW_CRASH_DUMP_NONE) 1316 continue; 1317 1318 if (mem_type == FW_CRASH_DUMP_TYPE_MAX) { 1319 ath12k_dbg(ab, ATH12K_DBG_PCI, 1320 "target mem region type %d not supported", 1321 ab->qmi.target_mem[i].type); 1322 continue; 1323 } 1324 1325 if (!ab->qmi.target_mem[i].paddr) 1326 continue; 1327 1328 dump_seg_sz[mem_type] += ab->qmi.target_mem[i].size; 1329 } 1330 1331 for (i = 0; i < FW_CRASH_DUMP_TYPE_MAX; i++) { 1332 if (!dump_seg_sz[i]) 1333 continue; 1334 1335 len += sizeof(*dump_tlv) + dump_seg_sz[i]; 1336 } 1337 1338 if (len) 1339 len += sizeof(*file_data); 1340 1341 return len; 1342 } 1343 1344 static void ath12k_pci_coredump_download(struct ath12k_base *ab) 1345 { 1346 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1347 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 1348 struct image_info *rddm_img, *fw_img; 1349 struct timespec64 timestamp; 1350 int i, len, mem_idx; 1351 enum ath12k_fw_crash_dump_type mem_type; 1352 struct ath12k_dump_file_data *file_data; 1353 struct ath12k_tlv_dump_data *dump_tlv; 1354 size_t hdr_len = sizeof(*file_data); 1355 void *buf; 1356 u32 dump_seg_sz[FW_CRASH_DUMP_TYPE_MAX] = { 0 }; 1357 1358 ath12k_mhi_coredump(mhi_ctrl, false); 1359 1360 len = ath12k_pci_coredump_calculate_size(ab, dump_seg_sz); 1361 if (!len) { 1362 ath12k_warn(ab, "No crash dump data found for devcoredump"); 1363 return; 1364 } 1365 1366 rddm_img = mhi_ctrl->rddm_image; 1367 fw_img = mhi_ctrl->fbc_image; 1368 1369 /* dev_coredumpv() requires vmalloc data */ 1370 buf = vzalloc(len); 1371 if (!buf) 1372 return; 1373 1374 ab->dump_data = buf; 1375 ab->ath12k_coredump_len = len; 1376 file_data = ab->dump_data; 1377 strscpy(file_data->df_magic, "ATH12K-FW-DUMP", sizeof(file_data->df_magic)); 1378 file_data->len = cpu_to_le32(len); 1379 file_data->version = cpu_to_le32(ATH12K_FW_CRASH_DUMP_V2); 1380 file_data->chip_id = cpu_to_le32(ab_pci->dev_id); 1381 file_data->qrtr_id = cpu_to_le32(ab_pci->ab->qmi.service_ins_id); 1382 file_data->bus_id = cpu_to_le32(pci_domain_nr(ab_pci->pdev->bus)); 1383 guid_gen(&file_data->guid); 1384 ktime_get_real_ts64(×tamp); 1385 file_data->tv_sec = cpu_to_le64(timestamp.tv_sec); 1386 file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec); 1387 buf += hdr_len; 1388 dump_tlv = buf; 1389 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_PAGING_DATA); 1390 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA]); 1391 buf += COREDUMP_TLV_HDR_SIZE; 1392 1393 /* append all segments together as they are all part of a single contiguous 1394 * block of memory 1395 */ 1396 for (i = 0; i < fw_img->entries ; i++) { 1397 if (!fw_img->mhi_buf[i].buf) 1398 continue; 1399 1400 memcpy_fromio(buf, (void const __iomem *)fw_img->mhi_buf[i].buf, 1401 fw_img->mhi_buf[i].len); 1402 buf += fw_img->mhi_buf[i].len; 1403 } 1404 1405 dump_tlv = buf; 1406 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_RDDM_DATA); 1407 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA]); 1408 buf += COREDUMP_TLV_HDR_SIZE; 1409 1410 /* append all segments together as they are all part of a single contiguous 1411 * block of memory 1412 */ 1413 for (i = 0; i < rddm_img->entries; i++) { 1414 if (!rddm_img->mhi_buf[i].buf) 1415 continue; 1416 1417 memcpy_fromio(buf, (void const __iomem *)rddm_img->mhi_buf[i].buf, 1418 rddm_img->mhi_buf[i].len); 1419 buf += rddm_img->mhi_buf[i].len; 1420 } 1421 1422 mem_idx = FW_CRASH_DUMP_REMOTE_MEM_DATA; 1423 for (; mem_idx < FW_CRASH_DUMP_TYPE_MAX; mem_idx++) { 1424 if (!dump_seg_sz[mem_idx] || mem_idx == FW_CRASH_DUMP_NONE) 1425 continue; 1426 1427 dump_tlv = buf; 1428 dump_tlv->type = cpu_to_le32(mem_idx); 1429 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[mem_idx]); 1430 buf += COREDUMP_TLV_HDR_SIZE; 1431 1432 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 1433 mem_type = ath12k_coredump_get_dump_type 1434 (ab->qmi.target_mem[i].type); 1435 1436 if (mem_type != mem_idx) 1437 continue; 1438 1439 if (!ab->qmi.target_mem[i].paddr) { 1440 ath12k_dbg(ab, ATH12K_DBG_PCI, 1441 "Skipping mem region type %d", 1442 ab->qmi.target_mem[i].type); 1443 continue; 1444 } 1445 1446 memcpy_fromio(buf, ab->qmi.target_mem[i].v.ioaddr, 1447 ab->qmi.target_mem[i].size); 1448 buf += ab->qmi.target_mem[i].size; 1449 } 1450 } 1451 1452 queue_work(ab->workqueue, &ab->dump_work); 1453 } 1454 #endif 1455 1456 int ath12k_pci_power_up(struct ath12k_base *ab) 1457 { 1458 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1459 int ret; 1460 1461 ab_pci->register_window = 0; 1462 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1463 ath12k_pci_sw_reset(ab_pci->ab, true); 1464 1465 /* Disable ASPM during firmware download due to problems switching 1466 * to AMSS state. 1467 */ 1468 ath12k_pci_aspm_disable(ab_pci); 1469 1470 ath12k_pci_msi_enable(ab_pci); 1471 1472 if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID)) 1473 ath12k_pci_update_qrtr_node_id(ab); 1474 1475 ret = ath12k_mhi_start(ab_pci); 1476 if (ret) { 1477 ath12k_err(ab, "failed to start mhi: %d\n", ret); 1478 return ret; 1479 } 1480 1481 if (ab->static_window_map) 1482 ath12k_pci_select_static_window(ab_pci); 1483 1484 return 0; 1485 } 1486 1487 void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend) 1488 { 1489 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1490 1491 if (!test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags)) 1492 return; 1493 1494 /* restore aspm in case firmware bootup fails */ 1495 ath12k_pci_aspm_restore(ab_pci); 1496 1497 ath12k_pci_force_wake(ab_pci->ab); 1498 ath12k_pci_msi_disable(ab_pci); 1499 ath12k_mhi_stop(ab_pci, is_suspend); 1500 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1501 ath12k_pci_sw_reset(ab_pci->ab, false); 1502 } 1503 1504 static int ath12k_pci_panic_handler(struct ath12k_base *ab) 1505 { 1506 ath12k_pci_sw_reset(ab, false); 1507 1508 return NOTIFY_OK; 1509 } 1510 1511 static const struct ath12k_hif_ops ath12k_pci_hif_ops = { 1512 .start = ath12k_pci_start, 1513 .stop = ath12k_pci_stop, 1514 .read32 = ath12k_pci_read32, 1515 .write32 = ath12k_pci_write32, 1516 .power_down = ath12k_pci_power_down, 1517 .power_up = ath12k_pci_power_up, 1518 .suspend = ath12k_pci_hif_suspend, 1519 .resume = ath12k_pci_hif_resume, 1520 .irq_enable = ath12k_pci_ext_irq_enable, 1521 .irq_disable = ath12k_pci_ext_irq_disable, 1522 .get_msi_address = ath12k_pci_get_msi_address, 1523 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment, 1524 .map_service_to_pipe = ath12k_pci_map_service_to_pipe, 1525 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, 1526 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, 1527 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, 1528 .panic_handler = ath12k_pci_panic_handler, 1529 #ifdef CONFIG_ATH12K_COREDUMP 1530 .coredump_download = ath12k_pci_coredump_download, 1531 #endif 1532 }; 1533 1534 static 1535 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor) 1536 { 1537 u32 soc_hw_version; 1538 1539 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1540 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1541 soc_hw_version); 1542 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1543 soc_hw_version); 1544 1545 ath12k_dbg(ab, ATH12K_DBG_PCI, 1546 "pci tcsr_soc_hw_version major %d minor %d\n", 1547 *major, *minor); 1548 } 1549 1550 static int ath12k_pci_probe(struct pci_dev *pdev, 1551 const struct pci_device_id *pci_dev) 1552 { 1553 struct ath12k_base *ab; 1554 struct ath12k_pci *ab_pci; 1555 u32 soc_hw_version_major, soc_hw_version_minor; 1556 int ret; 1557 1558 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); 1559 if (!ab) { 1560 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); 1561 return -ENOMEM; 1562 } 1563 1564 ab->dev = &pdev->dev; 1565 pci_set_drvdata(pdev, ab); 1566 ab_pci = ath12k_pci_priv(ab); 1567 ab_pci->dev_id = pci_dev->device; 1568 ab_pci->ab = ab; 1569 ab_pci->pdev = pdev; 1570 ab->hif.ops = &ath12k_pci_hif_ops; 1571 ab->fw_mode = ATH12K_FIRMWARE_MODE_NORMAL; 1572 pci_set_drvdata(pdev, ab); 1573 spin_lock_init(&ab_pci->window_lock); 1574 1575 ret = ath12k_pci_claim(ab_pci, pdev); 1576 if (ret) { 1577 ath12k_err(ab, "failed to claim device: %d\n", ret); 1578 goto err_free_core; 1579 } 1580 1581 ath12k_dbg(ab, ATH12K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 1582 pdev->vendor, pdev->device, 1583 pdev->subsystem_vendor, pdev->subsystem_device); 1584 1585 ab->id.vendor = pdev->vendor; 1586 ab->id.device = pdev->device; 1587 ab->id.subsystem_vendor = pdev->subsystem_vendor; 1588 ab->id.subsystem_device = pdev->subsystem_device; 1589 1590 switch (pci_dev->device) { 1591 case QCN9274_DEVICE_ID: 1592 ab_pci->msi_config = &ath12k_msi_config[0]; 1593 ab->static_window_map = true; 1594 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; 1595 ab->hal_rx_ops = &hal_rx_qcn9274_ops; 1596 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1597 &soc_hw_version_minor); 1598 ab->target_mem_mode = ath12k_core_get_memory_mode(ab); 1599 switch (soc_hw_version_major) { 1600 case ATH12K_PCI_SOC_HW_VERSION_2: 1601 ab->hw_rev = ATH12K_HW_QCN9274_HW20; 1602 break; 1603 case ATH12K_PCI_SOC_HW_VERSION_1: 1604 ab->hw_rev = ATH12K_HW_QCN9274_HW10; 1605 break; 1606 default: 1607 dev_err(&pdev->dev, 1608 "Unknown hardware version found for QCN9274: 0x%x\n", 1609 soc_hw_version_major); 1610 ret = -EOPNOTSUPP; 1611 goto err_pci_free_region; 1612 } 1613 break; 1614 case WCN7850_DEVICE_ID: 1615 ab->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD; 1616 ab_pci->msi_config = &ath12k_msi_config[0]; 1617 ab->static_window_map = false; 1618 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; 1619 ab->hal_rx_ops = &hal_rx_wcn7850_ops; 1620 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1621 &soc_hw_version_minor); 1622 ab->target_mem_mode = ATH12K_QMI_MEMORY_MODE_DEFAULT; 1623 switch (soc_hw_version_major) { 1624 case ATH12K_PCI_SOC_HW_VERSION_2: 1625 ab->hw_rev = ATH12K_HW_WCN7850_HW20; 1626 break; 1627 default: 1628 dev_err(&pdev->dev, 1629 "Unknown hardware version found for WCN7850: 0x%x\n", 1630 soc_hw_version_major); 1631 ret = -EOPNOTSUPP; 1632 goto err_pci_free_region; 1633 } 1634 break; 1635 1636 default: 1637 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1638 pci_dev->device); 1639 ret = -EOPNOTSUPP; 1640 goto err_pci_free_region; 1641 } 1642 1643 ret = ath12k_pci_msi_alloc(ab_pci); 1644 if (ret) { 1645 ath12k_err(ab, "failed to alloc msi: %d\n", ret); 1646 goto err_pci_free_region; 1647 } 1648 1649 ret = ath12k_core_pre_init(ab); 1650 if (ret) 1651 goto err_pci_msi_free; 1652 1653 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 1654 if (ret) { 1655 ath12k_err(ab, "failed to set irq affinity %d\n", ret); 1656 goto err_pci_msi_free; 1657 } 1658 1659 ret = ath12k_mhi_register(ab_pci); 1660 if (ret) { 1661 ath12k_err(ab, "failed to register mhi: %d\n", ret); 1662 goto err_irq_affinity_cleanup; 1663 } 1664 1665 ret = ath12k_hal_srng_init(ab); 1666 if (ret) 1667 goto err_mhi_unregister; 1668 1669 ret = ath12k_ce_alloc_pipes(ab); 1670 if (ret) { 1671 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1672 goto err_hal_srng_deinit; 1673 } 1674 1675 ath12k_pci_init_qmi_ce_config(ab); 1676 1677 ret = ath12k_pci_config_irq(ab); 1678 if (ret) { 1679 ath12k_err(ab, "failed to config irq: %d\n", ret); 1680 goto err_ce_free; 1681 } 1682 1683 /* kernel may allocate a dummy vector before request_irq and 1684 * then allocate a real vector when request_irq is called. 1685 * So get msi_data here again to avoid spurious interrupt 1686 * as msi_data will configured to srngs. 1687 */ 1688 ret = ath12k_pci_config_msi_data(ab_pci); 1689 if (ret) { 1690 ath12k_err(ab, "failed to config msi_data: %d\n", ret); 1691 goto err_free_irq; 1692 } 1693 1694 ret = ath12k_core_init(ab); 1695 if (ret) { 1696 ath12k_err(ab, "failed to init core: %d\n", ret); 1697 goto err_free_irq; 1698 } 1699 return 0; 1700 1701 err_free_irq: 1702 /* __free_irq() expects the caller to have cleared the affinity hint */ 1703 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1704 ath12k_pci_free_irq(ab); 1705 1706 err_ce_free: 1707 ath12k_ce_free_pipes(ab); 1708 1709 err_hal_srng_deinit: 1710 ath12k_hal_srng_deinit(ab); 1711 1712 err_mhi_unregister: 1713 ath12k_mhi_unregister(ab_pci); 1714 1715 err_irq_affinity_cleanup: 1716 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1717 1718 err_pci_msi_free: 1719 ath12k_pci_msi_free(ab_pci); 1720 1721 err_pci_free_region: 1722 ath12k_pci_free_region(ab_pci); 1723 1724 err_free_core: 1725 ath12k_core_free(ab); 1726 1727 return ret; 1728 } 1729 1730 static void ath12k_pci_remove(struct pci_dev *pdev) 1731 { 1732 struct ath12k_base *ab = pci_get_drvdata(pdev); 1733 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1734 1735 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1736 1737 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1738 ath12k_pci_power_down(ab, false); 1739 goto qmi_fail; 1740 } 1741 1742 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); 1743 1744 cancel_work_sync(&ab->reset_work); 1745 cancel_work_sync(&ab->dump_work); 1746 ath12k_core_hw_group_cleanup(ab->ag); 1747 1748 qmi_fail: 1749 ath12k_core_deinit(ab); 1750 ath12k_fw_unmap(ab); 1751 ath12k_mhi_unregister(ab_pci); 1752 1753 ath12k_pci_free_irq(ab); 1754 ath12k_pci_msi_free(ab_pci); 1755 ath12k_pci_free_region(ab_pci); 1756 1757 ath12k_hal_srng_deinit(ab); 1758 ath12k_ce_free_pipes(ab); 1759 ath12k_core_free(ab); 1760 } 1761 1762 static void ath12k_pci_hw_group_power_down(struct ath12k_hw_group *ag) 1763 { 1764 struct ath12k_base *ab; 1765 int i; 1766 1767 if (!ag) 1768 return; 1769 1770 mutex_lock(&ag->mutex); 1771 1772 for (i = 0; i < ag->num_devices; i++) { 1773 ab = ag->ab[i]; 1774 if (!ab) 1775 continue; 1776 1777 ath12k_pci_power_down(ab, false); 1778 } 1779 1780 mutex_unlock(&ag->mutex); 1781 } 1782 1783 static void ath12k_pci_shutdown(struct pci_dev *pdev) 1784 { 1785 struct ath12k_base *ab = pci_get_drvdata(pdev); 1786 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1787 1788 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1789 ath12k_pci_hw_group_power_down(ab->ag); 1790 } 1791 1792 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev) 1793 { 1794 struct ath12k_base *ab = dev_get_drvdata(dev); 1795 int ret; 1796 1797 ret = ath12k_core_suspend(ab); 1798 if (ret) 1799 ath12k_warn(ab, "failed to suspend core: %d\n", ret); 1800 1801 return ret; 1802 } 1803 1804 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev) 1805 { 1806 struct ath12k_base *ab = dev_get_drvdata(dev); 1807 int ret; 1808 1809 ret = ath12k_core_resume(ab); 1810 if (ret) 1811 ath12k_warn(ab, "failed to resume core: %d\n", ret); 1812 1813 return ret; 1814 } 1815 1816 static __maybe_unused int ath12k_pci_pm_suspend_late(struct device *dev) 1817 { 1818 struct ath12k_base *ab = dev_get_drvdata(dev); 1819 int ret; 1820 1821 ret = ath12k_core_suspend_late(ab); 1822 if (ret) 1823 ath12k_warn(ab, "failed to late suspend core: %d\n", ret); 1824 1825 return ret; 1826 } 1827 1828 static __maybe_unused int ath12k_pci_pm_resume_early(struct device *dev) 1829 { 1830 struct ath12k_base *ab = dev_get_drvdata(dev); 1831 int ret; 1832 1833 ret = ath12k_core_resume_early(ab); 1834 if (ret) 1835 ath12k_warn(ab, "failed to early resume core: %d\n", ret); 1836 1837 return ret; 1838 } 1839 1840 static const struct dev_pm_ops __maybe_unused ath12k_pci_pm_ops = { 1841 SET_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend, 1842 ath12k_pci_pm_resume) 1843 SET_LATE_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend_late, 1844 ath12k_pci_pm_resume_early) 1845 }; 1846 1847 static struct pci_driver ath12k_pci_driver = { 1848 .name = "ath12k_pci", 1849 .id_table = ath12k_pci_id_table, 1850 .probe = ath12k_pci_probe, 1851 .remove = ath12k_pci_remove, 1852 .shutdown = ath12k_pci_shutdown, 1853 .driver.pm = &ath12k_pci_pm_ops, 1854 }; 1855 1856 int ath12k_pci_init(void) 1857 { 1858 int ret; 1859 1860 ret = pci_register_driver(&ath12k_pci_driver); 1861 if (ret) { 1862 pr_err("failed to register ath12k pci driver: %d\n", 1863 ret); 1864 return ret; 1865 } 1866 1867 return 0; 1868 } 1869 1870 void ath12k_pci_exit(void) 1871 { 1872 pci_unregister_driver(&ath12k_pci_driver); 1873 } 1874