1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/msi.h> 10 #include <linux/pci.h> 11 #include <linux/time.h> 12 #include <linux/vmalloc.h> 13 14 #include "pci.h" 15 #include "core.h" 16 #include "hif.h" 17 #include "mhi.h" 18 #include "debug.h" 19 #include "hal.h" 20 #include "qmi.h" 21 22 #define ATH12K_PCI_BAR_NUM 0 23 #define ATH12K_PCI_DMA_MASK 36 24 25 #define ATH12K_PCI_IRQ_CE0_OFFSET 3 26 27 #define WINDOW_ENABLE_BIT 0x40000000 28 #define WINDOW_VALUE_MASK GENMASK(24, 19) 29 #define WINDOW_START 0x80000 30 #define WINDOW_RANGE_MASK GENMASK(18, 0) 31 #define WINDOW_STATIC_MASK GENMASK(31, 6) 32 33 /* BAR0 + 4k is always accessible, and no 34 * need to force wakeup. 35 * 4K - 32 = 0xFE0 36 */ 37 #define ACCESS_ALWAYS_OFF 0xFE0 38 39 static struct ath12k_pci_driver *ath12k_pci_family_drivers[ATH12K_DEVICE_FAMILY_MAX]; 40 static const struct ath12k_msi_config msi_config_one_msi = { 41 .total_vectors = 1, 42 .total_users = 4, 43 .users = (struct ath12k_msi_user[]) { 44 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 45 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 46 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 47 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 48 }, 49 }; 50 51 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { 52 "bhi", 53 "mhi-er0", 54 "mhi-er1", 55 "ce0", 56 "ce1", 57 "ce2", 58 "ce3", 59 "ce4", 60 "ce5", 61 "ce6", 62 "ce7", 63 "ce8", 64 "ce9", 65 "ce10", 66 "ce11", 67 "ce12", 68 "ce13", 69 "ce14", 70 "ce15", 71 "host2wbm-desc-feed", 72 "host2reo-re-injection", 73 "host2reo-command", 74 "host2rxdma-monitor-ring3", 75 "host2rxdma-monitor-ring2", 76 "host2rxdma-monitor-ring1", 77 "reo2ost-exception", 78 "wbm2host-rx-release", 79 "reo2host-status", 80 "reo2host-destination-ring4", 81 "reo2host-destination-ring3", 82 "reo2host-destination-ring2", 83 "reo2host-destination-ring1", 84 "rxdma2host-monitor-destination-mac3", 85 "rxdma2host-monitor-destination-mac2", 86 "rxdma2host-monitor-destination-mac1", 87 "ppdu-end-interrupts-mac3", 88 "ppdu-end-interrupts-mac2", 89 "ppdu-end-interrupts-mac1", 90 "rxdma2host-monitor-status-ring-mac3", 91 "rxdma2host-monitor-status-ring-mac2", 92 "rxdma2host-monitor-status-ring-mac1", 93 "host2rxdma-host-buf-ring-mac3", 94 "host2rxdma-host-buf-ring-mac2", 95 "host2rxdma-host-buf-ring-mac1", 96 "rxdma2host-destination-ring-mac3", 97 "rxdma2host-destination-ring-mac2", 98 "rxdma2host-destination-ring-mac1", 99 "host2tcl-input-ring4", 100 "host2tcl-input-ring3", 101 "host2tcl-input-ring2", 102 "host2tcl-input-ring1", 103 "wbm2host-tx-completions-ring4", 104 "wbm2host-tx-completions-ring3", 105 "wbm2host-tx-completions-ring2", 106 "wbm2host-tx-completions-ring1", 107 "tcl2host-status-ring", 108 }; 109 110 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset) 111 { 112 struct ath12k_base *ab = ab_pci->ab; 113 114 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK); 115 u32 static_window; 116 117 lockdep_assert_held(&ab_pci->window_lock); 118 119 /* Preserve the static window configuration and reset only dynamic window */ 120 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; 121 window |= static_window; 122 123 if (window != ab_pci->register_window) { 124 iowrite32(WINDOW_ENABLE_BIT | window, 125 ab->mem + ab_pci->window_reg_addr); 126 ioread32(ab->mem + ab_pci->window_reg_addr); 127 ab_pci->register_window = window; 128 } 129 } 130 131 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci) 132 { 133 u32 umac_window; 134 u32 ce_window; 135 u32 window; 136 137 umac_window = u32_get_bits(ab_pci->reg_base->umac_base, WINDOW_VALUE_MASK); 138 ce_window = u32_get_bits(ab_pci->reg_base->ce_reg_base, WINDOW_VALUE_MASK); 139 window = (umac_window << 12) | (ce_window << 6); 140 141 spin_lock_bh(&ab_pci->window_lock); 142 ab_pci->register_window = window; 143 spin_unlock_bh(&ab_pci->window_lock); 144 145 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + ab_pci->window_reg_addr); 146 } 147 148 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab, 149 u32 offset) 150 { 151 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 152 u32 window_start; 153 154 /* If offset lies within DP register range, use 3rd window */ 155 if ((offset ^ ab_pci->reg_base->umac_base) < WINDOW_RANGE_MASK) 156 window_start = 3 * WINDOW_START; 157 /* If offset lies within CE register range, use 2nd window */ 158 else if ((offset ^ ab_pci->reg_base->ce_reg_base) < WINDOW_RANGE_MASK) 159 window_start = 2 * WINDOW_START; 160 else 161 window_start = WINDOW_START; 162 163 return window_start; 164 } 165 166 static inline bool ath12k_pci_is_offset_within_mhi_region(u32 offset) 167 { 168 return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END); 169 } 170 171 static void ath12k_pci_restore_window(struct ath12k_base *ab) 172 { 173 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 174 175 spin_lock_bh(&ab_pci->window_lock); 176 177 iowrite32(WINDOW_ENABLE_BIT | ab_pci->register_window, 178 ab->mem + ab_pci->window_reg_addr); 179 ioread32(ab->mem + ab_pci->window_reg_addr); 180 181 spin_unlock_bh(&ab_pci->window_lock); 182 } 183 184 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) 185 { 186 u32 val, delay; 187 188 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 189 190 val |= PCIE_SOC_GLOBAL_RESET_V; 191 192 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 193 /* Flush the posted write to the device */ 194 ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 195 196 /* TODO: exact time to sleep is uncertain */ 197 delay = 10; 198 mdelay(delay); 199 200 /* Need to toggle V bit back otherwise stuck in reset status */ 201 val &= ~PCIE_SOC_GLOBAL_RESET_V; 202 203 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 204 /* Flush the posted write to the device */ 205 ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 206 207 mdelay(delay); 208 209 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 210 if (val == 0xffffffff) 211 ath12k_warn(ab, "link down error during global reset\n"); 212 213 /* Restore window register as its content is cleared during 214 * hardware global reset, such that it aligns with host cache. 215 */ 216 ath12k_pci_restore_window(ab); 217 } 218 219 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab) 220 { 221 u32 val; 222 223 /* read cookie */ 224 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 225 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val); 226 227 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 228 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 229 230 /* TODO: exact time to sleep is uncertain */ 231 mdelay(10); 232 233 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 234 * continuing warm path and entering dead loop. 235 */ 236 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 237 mdelay(10); 238 239 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 240 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 241 242 /* A read clear register. clear the register to prevent 243 * Q6 from entering wrong code path. 244 */ 245 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 246 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val); 247 } 248 249 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab) 250 { 251 u32 val; 252 int i; 253 254 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 255 256 /* PCIE link seems very unstable after the Hot Reset*/ 257 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 258 if (val == 0xffffffff) 259 mdelay(5); 260 261 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 262 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 263 } 264 265 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val); 266 267 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab)); 268 val |= GCC_GCC_PCIE_HOT_RST_VAL; 269 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST(ab), val); 270 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab)); 271 272 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 273 274 mdelay(5); 275 } 276 277 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab) 278 { 279 /* This is a WAR for PCIE Hotreset. 280 * When target receive Hotreset, but will set the interrupt. 281 * So when download SBL again, SBL will open Interrupt and 282 * receive it, and crash immediately. 283 */ 284 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 285 } 286 287 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab) 288 { 289 u32 val; 290 291 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 292 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 293 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 294 } 295 296 static void ath12k_pci_force_wake(struct ath12k_base *ab) 297 { 298 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 299 mdelay(5); 300 } 301 302 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) 303 { 304 if (power_on) { 305 ath12k_pci_enable_ltssm(ab); 306 ath12k_pci_clear_all_intrs(ab); 307 ath12k_pci_set_wlaon_pwr_ctrl(ab); 308 } 309 310 ath12k_mhi_clear_vector(ab); 311 ath12k_pci_clear_dbg_registers(ab); 312 ath12k_pci_soc_global_reset(ab); 313 ath12k_mhi_set_mhictrl_reset(ab); 314 } 315 316 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab) 317 { 318 int i, j; 319 320 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 321 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 322 323 for (j = 0; j < irq_grp->num_irq; j++) 324 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 325 326 netif_napi_del(&irq_grp->napi); 327 free_netdev(irq_grp->napi_ndev); 328 } 329 } 330 331 static void ath12k_pci_free_irq(struct ath12k_base *ab) 332 { 333 int i, irq_idx; 334 335 for (i = 0; i < ab->hw_params->ce_count; i++) { 336 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 337 continue; 338 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 339 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 340 } 341 342 ath12k_pci_free_ext_irq(ab); 343 } 344 345 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) 346 { 347 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 348 u32 irq_idx; 349 350 /* In case of one MSI vector, we handle irq enable/disable in a 351 * uniform way since we only have one irq 352 */ 353 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 354 return; 355 356 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 357 enable_irq(ab->irq_num[irq_idx]); 358 } 359 360 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) 361 { 362 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 363 u32 irq_idx; 364 365 /* In case of one MSI vector, we handle irq enable/disable in a 366 * uniform way since we only have one irq 367 */ 368 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 369 return; 370 371 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 372 disable_irq_nosync(ab->irq_num[irq_idx]); 373 } 374 375 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab) 376 { 377 int i; 378 379 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 380 381 for (i = 0; i < ab->hw_params->ce_count; i++) { 382 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 383 continue; 384 ath12k_pci_ce_irq_disable(ab, i); 385 } 386 } 387 388 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) 389 { 390 int i; 391 int irq_idx; 392 393 for (i = 0; i < ab->hw_params->ce_count; i++) { 394 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 395 continue; 396 397 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 398 synchronize_irq(ab->irq_num[irq_idx]); 399 } 400 } 401 402 static void ath12k_pci_ce_workqueue(struct work_struct *work) 403 { 404 struct ath12k_ce_pipe *ce_pipe = from_work(ce_pipe, work, intr_wq); 405 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 406 407 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 408 409 enable_irq(ce_pipe->ab->irq_num[irq_idx]); 410 } 411 412 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg) 413 { 414 struct ath12k_ce_pipe *ce_pipe = arg; 415 struct ath12k_base *ab = ce_pipe->ab; 416 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 417 418 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) 419 return IRQ_HANDLED; 420 421 /* last interrupt received for this CE */ 422 ce_pipe->timestamp = jiffies; 423 424 disable_irq_nosync(ab->irq_num[irq_idx]); 425 426 queue_work(system_bh_wq, &ce_pipe->intr_wq); 427 428 return IRQ_HANDLED; 429 } 430 431 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) 432 { 433 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 434 int i; 435 436 /* In case of one MSI vector, we handle irq enable/disable 437 * in a uniform way since we only have one irq 438 */ 439 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 440 return; 441 442 for (i = 0; i < irq_grp->num_irq; i++) 443 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 444 } 445 446 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 447 { 448 int i; 449 450 if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 451 return; 452 453 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 454 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 455 456 ath12k_pci_ext_grp_disable(irq_grp); 457 458 if (irq_grp->napi_enabled) { 459 napi_synchronize(&irq_grp->napi); 460 napi_disable(&irq_grp->napi); 461 irq_grp->napi_enabled = false; 462 } 463 } 464 } 465 466 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) 467 { 468 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 469 int i; 470 471 /* In case of one MSI vector, we handle irq enable/disable in a 472 * uniform way since we only have one irq 473 */ 474 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 475 return; 476 477 for (i = 0; i < irq_grp->num_irq; i++) 478 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 479 } 480 481 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab) 482 { 483 int i, j, irq_idx; 484 485 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 486 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 487 488 for (j = 0; j < irq_grp->num_irq; j++) { 489 irq_idx = irq_grp->irqs[j]; 490 synchronize_irq(ab->irq_num[irq_idx]); 491 } 492 } 493 } 494 495 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 496 { 497 struct ath12k_ext_irq_grp *irq_grp = container_of(napi, 498 struct ath12k_ext_irq_grp, 499 napi); 500 struct ath12k_base *ab = irq_grp->ab; 501 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 502 int work_done; 503 int i; 504 505 work_done = ath12k_dp_service_srng(dp, irq_grp, budget); 506 if (work_done < budget) { 507 napi_complete_done(napi, work_done); 508 for (i = 0; i < irq_grp->num_irq; i++) 509 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 510 } 511 512 if (work_done > budget) 513 work_done = budget; 514 515 return work_done; 516 } 517 518 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg) 519 { 520 struct ath12k_ext_irq_grp *irq_grp = arg; 521 struct ath12k_base *ab = irq_grp->ab; 522 int i; 523 524 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 525 return IRQ_HANDLED; 526 527 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); 528 529 /* last interrupt received for this group */ 530 irq_grp->timestamp = jiffies; 531 532 for (i = 0; i < irq_grp->num_irq; i++) 533 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 534 535 napi_schedule(&irq_grp->napi); 536 537 return IRQ_HANDLED; 538 } 539 540 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) 541 { 542 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 543 int i, j, n, ret, num_vectors = 0; 544 u32 user_base_data = 0, base_vector = 0, base_idx; 545 struct ath12k_ext_irq_grp *irq_grp; 546 bool threaded_napi = false; 547 int irq; 548 549 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 550 ret = ath12k_pci_get_user_msi_assignment(ab, "DP", 551 &num_vectors, 552 &user_base_data, 553 &base_vector); 554 if (ret < 0) 555 return ret; 556 557 irq = ath12k_pci_get_msi_irq(ab->dev, base_vector); 558 if (irq >= 0) 559 threaded_napi = !irq_can_set_affinity(irq); 560 561 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 562 irq_grp = &ab->ext_irq_grp[i]; 563 u32 num_irq = 0; 564 565 irq_grp->ab = ab; 566 irq_grp->grp_id = i; 567 irq_grp->napi_ndev = alloc_netdev_dummy(0); 568 if (!irq_grp->napi_ndev) { 569 ret = -ENOMEM; 570 goto fail_allocate; 571 } 572 573 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi, 574 ath12k_pci_ext_grp_napi_poll); 575 if (threaded_napi) 576 netif_threaded_enable(irq_grp->napi_ndev); 577 578 if (ab->hw_params->ring_mask->tx[i] || 579 ab->hw_params->ring_mask->rx[i] || 580 ab->hw_params->ring_mask->rx_err[i] || 581 ab->hw_params->ring_mask->rx_wbm_rel[i] || 582 ab->hw_params->ring_mask->reo_status[i] || 583 ab->hw_params->ring_mask->host2rxdma[i] || 584 ab->hw_params->ring_mask->rx_mon_dest[i] || 585 ab->hw_params->ring_mask->rx_mon_status[i]) { 586 num_irq = 1; 587 } 588 589 irq_grp->num_irq = num_irq; 590 irq_grp->irqs[0] = base_idx + i; 591 592 for (j = 0; j < irq_grp->num_irq; j++) { 593 int irq_idx = irq_grp->irqs[j]; 594 int vector = (i % num_vectors) + base_vector; 595 596 irq = ath12k_pci_get_msi_irq(ab->dev, vector); 597 598 ab->irq_num[irq_idx] = irq; 599 600 ath12k_dbg(ab, ATH12K_DBG_PCI, 601 "irq:%d group:%d\n", irq, i); 602 603 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 604 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler, 605 ab_pci->irq_flags, 606 "DP_EXT_IRQ", irq_grp); 607 if (ret) { 608 ath12k_err(ab, "failed request irq %d: %d\n", 609 vector, ret); 610 goto fail_request; 611 } 612 } 613 ath12k_pci_ext_grp_disable(irq_grp); 614 } 615 616 return 0; 617 618 fail_request: 619 /* i ->napi_ndev was properly allocated. Free it also */ 620 i += 1; 621 fail_allocate: 622 for (n = 0; n < i; n++) { 623 irq_grp = &ab->ext_irq_grp[n]; 624 free_netdev(irq_grp->napi_ndev); 625 } 626 return ret; 627 } 628 629 static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci, 630 const struct cpumask *m) 631 { 632 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 633 return 0; 634 635 return irq_set_affinity_and_hint(ab_pci->pdev->irq, m); 636 } 637 638 static int ath12k_pci_config_irq(struct ath12k_base *ab) 639 { 640 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 641 struct ath12k_ce_pipe *ce_pipe; 642 u32 msi_data_start; 643 u32 msi_data_count, msi_data_idx; 644 u32 msi_irq_start; 645 unsigned int msi_data; 646 int irq, i, ret, irq_idx; 647 648 ret = ath12k_pci_get_user_msi_assignment(ab, 649 "CE", &msi_data_count, 650 &msi_data_start, &msi_irq_start); 651 if (ret) 652 return ret; 653 654 /* Configure CE irqs */ 655 656 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 657 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 658 continue; 659 660 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 661 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); 662 ce_pipe = &ab->ce.ce_pipe[i]; 663 664 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 665 666 INIT_WORK(&ce_pipe->intr_wq, ath12k_pci_ce_workqueue); 667 668 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler, 669 ab_pci->irq_flags, irq_name[irq_idx], 670 ce_pipe); 671 if (ret) { 672 ath12k_err(ab, "failed to request irq %d: %d\n", 673 irq_idx, ret); 674 return ret; 675 } 676 677 ab->irq_num[irq_idx] = irq; 678 msi_data_idx++; 679 680 ath12k_pci_ce_irq_disable(ab, i); 681 } 682 683 ret = ath12k_pci_ext_irq_config(ab); 684 if (ret) 685 return ret; 686 687 return 0; 688 } 689 690 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab) 691 { 692 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 693 694 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 695 struct pci_bus *bus = ab_pci->pdev->bus; 696 697 cfg->tgt_ce = ab->hw_params->target_ce_config; 698 cfg->tgt_ce_len = ab->hw_params->target_ce_count; 699 700 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; 701 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; 702 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; 703 704 if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID)) { 705 ab_pci->qmi_instance = 706 u32_encode_bits(pci_domain_nr(bus), DOMAIN_NUMBER_MASK) | 707 u32_encode_bits(bus->number, BUS_NUMBER_MASK); 708 ab->qmi.service_ins_id += ab_pci->qmi_instance; 709 } 710 } 711 712 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab) 713 { 714 int i; 715 716 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 717 718 for (i = 0; i < ab->hw_params->ce_count; i++) { 719 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 720 continue; 721 ath12k_pci_ce_irq_enable(ab, i); 722 } 723 } 724 725 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable) 726 { 727 struct pci_dev *dev = ab_pci->pdev; 728 u16 control; 729 730 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 731 732 if (enable) 733 control |= PCI_MSI_FLAGS_ENABLE; 734 else 735 control &= ~PCI_MSI_FLAGS_ENABLE; 736 737 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 738 } 739 740 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci) 741 { 742 ath12k_pci_msi_config(ab_pci, true); 743 } 744 745 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci) 746 { 747 ath12k_pci_msi_config(ab_pci, false); 748 } 749 750 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci) 751 { 752 struct ath12k_base *ab = ab_pci->ab; 753 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 754 struct msi_desc *msi_desc; 755 int num_vectors; 756 int ret; 757 758 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 759 msi_config->total_vectors, 760 msi_config->total_vectors, 761 PCI_IRQ_MSI); 762 763 if (num_vectors == msi_config->total_vectors) { 764 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 765 ab_pci->irq_flags = IRQF_SHARED; 766 } else { 767 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 768 1, 769 1, 770 PCI_IRQ_MSI); 771 if (num_vectors < 0) { 772 ret = -EINVAL; 773 goto reset_msi_config; 774 } 775 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 776 ab_pci->msi_config = &msi_config_one_msi; 777 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 778 ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n"); 779 } 780 781 ath12k_info(ab, "MSI vectors: %d\n", num_vectors); 782 783 ath12k_pci_msi_disable(ab_pci); 784 785 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 786 if (!msi_desc) { 787 ath12k_err(ab, "msi_desc is NULL!\n"); 788 ret = -EINVAL; 789 goto free_msi_vector; 790 } 791 792 ab_pci->msi_ep_base_data = msi_desc->msg.data; 793 if (msi_desc->pci.msi_attrib.is_64) 794 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 795 796 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 797 798 return 0; 799 800 free_msi_vector: 801 pci_free_irq_vectors(ab_pci->pdev); 802 803 reset_msi_config: 804 return ret; 805 } 806 807 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci) 808 { 809 pci_free_irq_vectors(ab_pci->pdev); 810 } 811 812 static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci) 813 { 814 struct msi_desc *msi_desc; 815 816 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 817 if (!msi_desc) { 818 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n"); 819 pci_free_irq_vectors(ab_pci->pdev); 820 return -EINVAL; 821 } 822 823 ab_pci->msi_ep_base_data = msi_desc->msg.data; 824 825 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 826 ab_pci->msi_ep_base_data); 827 828 return 0; 829 } 830 831 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev) 832 { 833 struct ath12k_base *ab = ab_pci->ab; 834 u16 device_id; 835 int ret = 0; 836 837 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 838 if (device_id != ab_pci->dev_id) { 839 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 840 device_id, ab_pci->dev_id); 841 ret = -EIO; 842 goto out; 843 } 844 845 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM); 846 if (ret) { 847 ath12k_err(ab, "failed to assign pci resource: %d\n", ret); 848 goto out; 849 } 850 851 ret = pci_enable_device(pdev); 852 if (ret) { 853 ath12k_err(ab, "failed to enable pci device: %d\n", ret); 854 goto out; 855 } 856 857 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci"); 858 if (ret) { 859 ath12k_err(ab, "failed to request pci region: %d\n", ret); 860 goto disable_device; 861 } 862 863 ab_pci->dma_mask = DMA_BIT_MASK(ATH12K_PCI_DMA_MASK); 864 dma_set_mask(&pdev->dev, ab_pci->dma_mask); 865 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 866 867 pci_set_master(pdev); 868 869 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); 870 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); 871 if (!ab->mem) { 872 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM); 873 ret = -EIO; 874 goto release_region; 875 } 876 877 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%p\n", ab->mem); 878 return 0; 879 880 release_region: 881 pci_release_region(pdev, ATH12K_PCI_BAR_NUM); 882 disable_device: 883 pci_disable_device(pdev); 884 out: 885 return ret; 886 } 887 888 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci) 889 { 890 struct ath12k_base *ab = ab_pci->ab; 891 struct pci_dev *pci_dev = ab_pci->pdev; 892 893 pci_iounmap(pci_dev, ab->mem); 894 ab->mem = NULL; 895 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM); 896 if (pci_is_enabled(pci_dev)) 897 pci_disable_device(pci_dev); 898 } 899 900 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci) 901 { 902 struct ath12k_base *ab = ab_pci->ab; 903 904 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 905 &ab_pci->link_ctl); 906 907 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 908 ab_pci->link_ctl, 909 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 910 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 911 912 /* disable L0s and L1 */ 913 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 914 PCI_EXP_LNKCTL_ASPMC); 915 916 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); 917 } 918 919 static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab) 920 { 921 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 922 u32 reg; 923 924 /* On platforms with two or more identical mhi devices, qmi service run 925 * with identical qrtr-node-id. Because of this identical ID qrtr-lookup 926 * cannot register more than one qmi service with identical node ID. 927 * 928 * This generates a unique instance ID from PCIe domain number and bus number, 929 * writes to the given register, it is available for firmware when the QMI service 930 * is spawned. 931 */ 932 reg = PCIE_LOCAL_REG_QRTR_NODE_ID(ab) & WINDOW_RANGE_MASK; 933 ath12k_pci_write32(ab, reg, ab_pci->qmi_instance); 934 935 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n", 936 reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg)); 937 } 938 939 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) 940 { 941 if (ab_pci->ab->hw_params->supports_aspm && 942 test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) 943 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 944 PCI_EXP_LNKCTL_ASPMC, 945 ab_pci->link_ctl & 946 PCI_EXP_LNKCTL_ASPMC); 947 } 948 949 static void ath12k_pci_cancel_workqueue(struct ath12k_base *ab) 950 { 951 int i; 952 953 for (i = 0; i < ab->hw_params->ce_count; i++) { 954 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 955 956 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 957 continue; 958 959 cancel_work_sync(&ce_pipe->intr_wq); 960 } 961 } 962 963 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab) 964 { 965 ath12k_pci_ce_irqs_disable(ab); 966 ath12k_pci_sync_ce_irqs(ab); 967 ath12k_pci_cancel_workqueue(ab); 968 } 969 970 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 971 u8 *ul_pipe, u8 *dl_pipe) 972 { 973 const struct service_to_pipe *entry; 974 bool ul_set = false, dl_set = false; 975 int i; 976 977 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { 978 entry = &ab->hw_params->svc_to_ce_map[i]; 979 980 if (__le32_to_cpu(entry->service_id) != service_id) 981 continue; 982 983 switch (__le32_to_cpu(entry->pipedir)) { 984 case PIPEDIR_NONE: 985 break; 986 case PIPEDIR_IN: 987 WARN_ON(dl_set); 988 *dl_pipe = __le32_to_cpu(entry->pipenum); 989 dl_set = true; 990 break; 991 case PIPEDIR_OUT: 992 WARN_ON(ul_set); 993 *ul_pipe = __le32_to_cpu(entry->pipenum); 994 ul_set = true; 995 break; 996 case PIPEDIR_INOUT: 997 WARN_ON(dl_set); 998 WARN_ON(ul_set); 999 *dl_pipe = __le32_to_cpu(entry->pipenum); 1000 *ul_pipe = __le32_to_cpu(entry->pipenum); 1001 dl_set = true; 1002 ul_set = true; 1003 break; 1004 } 1005 } 1006 1007 if (WARN_ON(!ul_set || !dl_set)) 1008 return -ENOENT; 1009 1010 return 0; 1011 } 1012 1013 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector) 1014 { 1015 struct pci_dev *pci_dev = to_pci_dev(dev); 1016 1017 return pci_irq_vector(pci_dev, vector); 1018 } 1019 1020 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 1021 int *num_vectors, u32 *user_base_data, 1022 u32 *base_vector) 1023 { 1024 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1025 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 1026 int idx; 1027 1028 for (idx = 0; idx < msi_config->total_users; idx++) { 1029 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 1030 *num_vectors = msi_config->users[idx].num_vectors; 1031 *base_vector = msi_config->users[idx].base_vector; 1032 *user_base_data = *base_vector + ab_pci->msi_ep_base_data; 1033 1034 ath12k_dbg(ab, ATH12K_DBG_PCI, 1035 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 1036 user_name, *num_vectors, *user_base_data, 1037 *base_vector); 1038 1039 return 0; 1040 } 1041 } 1042 1043 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 1044 1045 return -EINVAL; 1046 } 1047 1048 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 1049 u32 *msi_addr_hi) 1050 { 1051 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1052 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 1053 1054 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 1055 msi_addr_lo); 1056 1057 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 1058 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 1059 msi_addr_hi); 1060 } else { 1061 *msi_addr_hi = 0; 1062 } 1063 } 1064 1065 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 1066 u32 *msi_idx) 1067 { 1068 u32 i, msi_data_idx; 1069 1070 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 1071 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1072 continue; 1073 1074 if (ce_id == i) 1075 break; 1076 1077 msi_data_idx++; 1078 } 1079 *msi_idx = msi_data_idx; 1080 } 1081 1082 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab) 1083 { 1084 ath12k_pci_ce_irqs_enable(ab); 1085 } 1086 1087 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab) 1088 { 1089 ath12k_pci_ce_irq_disable_sync(ab); 1090 } 1091 1092 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) 1093 { 1094 int i; 1095 1096 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 1097 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 1098 1099 if (!irq_grp->napi_enabled) { 1100 napi_enable(&irq_grp->napi); 1101 irq_grp->napi_enabled = true; 1102 } 1103 1104 ath12k_pci_ext_grp_enable(irq_grp); 1105 } 1106 1107 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); 1108 } 1109 1110 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 1111 { 1112 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 1113 return; 1114 1115 __ath12k_pci_ext_irq_disable(ab); 1116 ath12k_pci_sync_ext_irqs(ab); 1117 } 1118 1119 int ath12k_pci_hif_suspend(struct ath12k_base *ab) 1120 { 1121 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1122 1123 ath12k_mhi_suspend(ar_pci); 1124 1125 return 0; 1126 } 1127 1128 int ath12k_pci_hif_resume(struct ath12k_base *ab) 1129 { 1130 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1131 1132 ath12k_mhi_resume(ar_pci); 1133 1134 return 0; 1135 } 1136 1137 void ath12k_pci_stop(struct ath12k_base *ab) 1138 { 1139 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1140 1141 if (!test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags)) 1142 return; 1143 1144 ath12k_pci_ce_irq_disable_sync(ab); 1145 ath12k_ce_cleanup_pipes(ab); 1146 } 1147 1148 int ath12k_pci_start(struct ath12k_base *ab) 1149 { 1150 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1151 1152 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1153 1154 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 1155 ath12k_pci_aspm_restore(ab_pci); 1156 else 1157 ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 1158 1159 ath12k_pci_ce_irqs_enable(ab); 1160 ath12k_ce_rx_post_buf(ab); 1161 1162 return 0; 1163 } 1164 1165 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) 1166 { 1167 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1168 u32 val, window_start; 1169 int ret = 0; 1170 1171 /* for offset beyond BAR + 4K - 32, may 1172 * need to wakeup MHI to access. 1173 */ 1174 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1175 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1176 ret = ab_pci->pci_ops->wakeup(ab); 1177 1178 if (offset < WINDOW_START) { 1179 val = ioread32(ab->mem + offset); 1180 } else { 1181 if (ab->static_window_map) 1182 window_start = ath12k_pci_get_window_start(ab, offset); 1183 else 1184 window_start = WINDOW_START; 1185 1186 if (window_start == WINDOW_START) { 1187 spin_lock_bh(&ab_pci->window_lock); 1188 ath12k_pci_select_window(ab_pci, offset); 1189 1190 if (ath12k_pci_is_offset_within_mhi_region(offset)) { 1191 offset = offset - PCI_MHIREGLEN_REG; 1192 val = ioread32(ab->mem + 1193 (offset & WINDOW_RANGE_MASK)); 1194 } else { 1195 val = ioread32(ab->mem + window_start + 1196 (offset & WINDOW_RANGE_MASK)); 1197 } 1198 spin_unlock_bh(&ab_pci->window_lock); 1199 } else { 1200 val = ioread32(ab->mem + window_start + 1201 (offset & WINDOW_RANGE_MASK)); 1202 } 1203 } 1204 1205 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1206 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1207 !ret) 1208 ab_pci->pci_ops->release(ab); 1209 return val; 1210 } 1211 EXPORT_SYMBOL(ath12k_pci_read32); 1212 1213 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value) 1214 { 1215 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1216 u32 window_start; 1217 int ret = 0; 1218 1219 /* for offset beyond BAR + 4K - 32, may 1220 * need to wakeup MHI to access. 1221 */ 1222 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1223 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1224 ret = ab_pci->pci_ops->wakeup(ab); 1225 1226 if (offset < WINDOW_START) { 1227 iowrite32(value, ab->mem + offset); 1228 } else { 1229 if (ab->static_window_map) 1230 window_start = ath12k_pci_get_window_start(ab, offset); 1231 else 1232 window_start = WINDOW_START; 1233 1234 if (window_start == WINDOW_START) { 1235 spin_lock_bh(&ab_pci->window_lock); 1236 ath12k_pci_select_window(ab_pci, offset); 1237 1238 if (ath12k_pci_is_offset_within_mhi_region(offset)) { 1239 offset = offset - PCI_MHIREGLEN_REG; 1240 iowrite32(value, ab->mem + 1241 (offset & WINDOW_RANGE_MASK)); 1242 } else { 1243 iowrite32(value, ab->mem + window_start + 1244 (offset & WINDOW_RANGE_MASK)); 1245 } 1246 spin_unlock_bh(&ab_pci->window_lock); 1247 } else { 1248 iowrite32(value, ab->mem + window_start + 1249 (offset & WINDOW_RANGE_MASK)); 1250 } 1251 } 1252 1253 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1254 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1255 !ret) 1256 ab_pci->pci_ops->release(ab); 1257 } 1258 1259 #ifdef CONFIG_ATH12K_COREDUMP 1260 static int ath12k_pci_coredump_calculate_size(struct ath12k_base *ab, u32 *dump_seg_sz) 1261 { 1262 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1263 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 1264 struct image_info *rddm_img, *fw_img; 1265 struct ath12k_tlv_dump_data *dump_tlv; 1266 enum ath12k_fw_crash_dump_type mem_type; 1267 u32 len = 0, rddm_tlv_sz = 0, paging_tlv_sz = 0; 1268 struct ath12k_dump_file_data *file_data; 1269 int i; 1270 1271 rddm_img = mhi_ctrl->rddm_image; 1272 if (!rddm_img) { 1273 ath12k_err(ab, "No RDDM dump found\n"); 1274 return 0; 1275 } 1276 1277 fw_img = mhi_ctrl->fbc_image; 1278 1279 for (i = 0; i < fw_img->entries ; i++) { 1280 if (!fw_img->mhi_buf[i].buf) 1281 continue; 1282 1283 paging_tlv_sz += fw_img->mhi_buf[i].len; 1284 } 1285 dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA] = paging_tlv_sz; 1286 1287 for (i = 0; i < rddm_img->entries; i++) { 1288 if (!rddm_img->mhi_buf[i].buf) 1289 continue; 1290 1291 rddm_tlv_sz += rddm_img->mhi_buf[i].len; 1292 } 1293 dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA] = rddm_tlv_sz; 1294 1295 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 1296 mem_type = ath12k_coredump_get_dump_type(ab->qmi.target_mem[i].type); 1297 1298 if (mem_type == FW_CRASH_DUMP_NONE) 1299 continue; 1300 1301 if (mem_type == FW_CRASH_DUMP_TYPE_MAX) { 1302 ath12k_dbg(ab, ATH12K_DBG_PCI, 1303 "target mem region type %d not supported", 1304 ab->qmi.target_mem[i].type); 1305 continue; 1306 } 1307 1308 if (!ab->qmi.target_mem[i].paddr) 1309 continue; 1310 1311 dump_seg_sz[mem_type] += ab->qmi.target_mem[i].size; 1312 } 1313 1314 for (i = 0; i < FW_CRASH_DUMP_TYPE_MAX; i++) { 1315 if (!dump_seg_sz[i]) 1316 continue; 1317 1318 len += sizeof(*dump_tlv) + dump_seg_sz[i]; 1319 } 1320 1321 if (len) 1322 len += sizeof(*file_data); 1323 1324 return len; 1325 } 1326 1327 static void ath12k_pci_coredump_download(struct ath12k_base *ab) 1328 { 1329 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1330 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 1331 struct image_info *rddm_img, *fw_img; 1332 struct timespec64 timestamp; 1333 int i, len, mem_idx; 1334 enum ath12k_fw_crash_dump_type mem_type; 1335 struct ath12k_dump_file_data *file_data; 1336 struct ath12k_tlv_dump_data *dump_tlv; 1337 size_t hdr_len = sizeof(*file_data); 1338 void *buf; 1339 u32 dump_seg_sz[FW_CRASH_DUMP_TYPE_MAX] = {}; 1340 1341 ath12k_mhi_coredump(mhi_ctrl, false); 1342 1343 len = ath12k_pci_coredump_calculate_size(ab, dump_seg_sz); 1344 if (!len) { 1345 ath12k_warn(ab, "No crash dump data found for devcoredump"); 1346 return; 1347 } 1348 1349 rddm_img = mhi_ctrl->rddm_image; 1350 fw_img = mhi_ctrl->fbc_image; 1351 1352 /* dev_coredumpv() requires vmalloc data */ 1353 buf = vzalloc(len); 1354 if (!buf) 1355 return; 1356 1357 ab->dump_data = buf; 1358 ab->ath12k_coredump_len = len; 1359 file_data = ab->dump_data; 1360 strscpy(file_data->df_magic, "ATH12K-FW-DUMP", sizeof(file_data->df_magic)); 1361 file_data->len = cpu_to_le32(len); 1362 file_data->version = cpu_to_le32(ATH12K_FW_CRASH_DUMP_V2); 1363 file_data->chip_id = cpu_to_le32(ab_pci->dev_id); 1364 file_data->qrtr_id = cpu_to_le32(ab_pci->ab->qmi.service_ins_id); 1365 file_data->bus_id = cpu_to_le32(pci_domain_nr(ab_pci->pdev->bus)); 1366 guid_gen(&file_data->guid); 1367 ktime_get_real_ts64(×tamp); 1368 file_data->tv_sec = cpu_to_le64(timestamp.tv_sec); 1369 file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec); 1370 buf += hdr_len; 1371 dump_tlv = buf; 1372 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_PAGING_DATA); 1373 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA]); 1374 buf += COREDUMP_TLV_HDR_SIZE; 1375 1376 /* append all segments together as they are all part of a single contiguous 1377 * block of memory 1378 */ 1379 for (i = 0; i < fw_img->entries ; i++) { 1380 if (!fw_img->mhi_buf[i].buf) 1381 continue; 1382 1383 memcpy_fromio(buf, (void const __iomem *)fw_img->mhi_buf[i].buf, 1384 fw_img->mhi_buf[i].len); 1385 buf += fw_img->mhi_buf[i].len; 1386 } 1387 1388 dump_tlv = buf; 1389 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_RDDM_DATA); 1390 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA]); 1391 buf += COREDUMP_TLV_HDR_SIZE; 1392 1393 /* append all segments together as they are all part of a single contiguous 1394 * block of memory 1395 */ 1396 for (i = 0; i < rddm_img->entries; i++) { 1397 if (!rddm_img->mhi_buf[i].buf) 1398 continue; 1399 1400 memcpy_fromio(buf, (void const __iomem *)rddm_img->mhi_buf[i].buf, 1401 rddm_img->mhi_buf[i].len); 1402 buf += rddm_img->mhi_buf[i].len; 1403 } 1404 1405 mem_idx = FW_CRASH_DUMP_REMOTE_MEM_DATA; 1406 for (; mem_idx < FW_CRASH_DUMP_TYPE_MAX; mem_idx++) { 1407 if (!dump_seg_sz[mem_idx] || mem_idx == FW_CRASH_DUMP_NONE) 1408 continue; 1409 1410 dump_tlv = buf; 1411 dump_tlv->type = cpu_to_le32(mem_idx); 1412 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[mem_idx]); 1413 buf += COREDUMP_TLV_HDR_SIZE; 1414 1415 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 1416 mem_type = ath12k_coredump_get_dump_type 1417 (ab->qmi.target_mem[i].type); 1418 1419 if (mem_type != mem_idx) 1420 continue; 1421 1422 if (!ab->qmi.target_mem[i].paddr) { 1423 ath12k_dbg(ab, ATH12K_DBG_PCI, 1424 "Skipping mem region type %d", 1425 ab->qmi.target_mem[i].type); 1426 continue; 1427 } 1428 1429 memcpy_fromio(buf, ab->qmi.target_mem[i].v.ioaddr, 1430 ab->qmi.target_mem[i].size); 1431 buf += ab->qmi.target_mem[i].size; 1432 } 1433 } 1434 1435 queue_work(ab->workqueue, &ab->dump_work); 1436 } 1437 #endif 1438 1439 int ath12k_pci_power_up(struct ath12k_base *ab) 1440 { 1441 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1442 int ret; 1443 1444 ab_pci->register_window = 0; 1445 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1446 ath12k_pci_sw_reset(ab_pci->ab, true); 1447 1448 /* Disable ASPM during firmware download due to problems switching 1449 * to AMSS state. 1450 */ 1451 ath12k_pci_aspm_disable(ab_pci); 1452 1453 ath12k_pci_msi_enable(ab_pci); 1454 1455 if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID)) 1456 ath12k_pci_update_qrtr_node_id(ab); 1457 1458 ret = ath12k_mhi_start(ab_pci); 1459 if (ret) { 1460 ath12k_err(ab, "failed to start mhi: %d\n", ret); 1461 return ret; 1462 } 1463 1464 if (ab->static_window_map) 1465 ath12k_pci_select_static_window(ab_pci); 1466 1467 return 0; 1468 } 1469 1470 void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend) 1471 { 1472 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1473 1474 if (!test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags)) 1475 return; 1476 1477 /* restore aspm in case firmware bootup fails */ 1478 ath12k_pci_aspm_restore(ab_pci); 1479 1480 ath12k_pci_force_wake(ab_pci->ab); 1481 ath12k_pci_msi_disable(ab_pci); 1482 ath12k_mhi_stop(ab_pci, is_suspend); 1483 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1484 ath12k_pci_sw_reset(ab_pci->ab, false); 1485 } 1486 1487 static int ath12k_pci_panic_handler(struct ath12k_base *ab) 1488 { 1489 ath12k_pci_sw_reset(ab, false); 1490 1491 return NOTIFY_OK; 1492 } 1493 1494 static const struct ath12k_hif_ops ath12k_pci_hif_ops = { 1495 .start = ath12k_pci_start, 1496 .stop = ath12k_pci_stop, 1497 .read32 = ath12k_pci_read32, 1498 .write32 = ath12k_pci_write32, 1499 .power_down = ath12k_pci_power_down, 1500 .power_up = ath12k_pci_power_up, 1501 .suspend = ath12k_pci_hif_suspend, 1502 .resume = ath12k_pci_hif_resume, 1503 .irq_enable = ath12k_pci_ext_irq_enable, 1504 .irq_disable = ath12k_pci_ext_irq_disable, 1505 .get_msi_address = ath12k_pci_get_msi_address, 1506 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment, 1507 .map_service_to_pipe = ath12k_pci_map_service_to_pipe, 1508 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, 1509 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, 1510 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, 1511 .panic_handler = ath12k_pci_panic_handler, 1512 #ifdef CONFIG_ATH12K_COREDUMP 1513 .coredump_download = ath12k_pci_coredump_download, 1514 #endif 1515 }; 1516 1517 static enum ath12k_device_family 1518 ath12k_get_device_family(const struct pci_device_id *pci_dev) 1519 { 1520 enum ath12k_device_family device_family_id; 1521 const struct pci_device_id *id; 1522 1523 for (device_family_id = ATH12K_DEVICE_FAMILY_START; 1524 device_family_id < ATH12K_DEVICE_FAMILY_MAX; device_family_id++) { 1525 if (!ath12k_pci_family_drivers[device_family_id]) 1526 continue; 1527 1528 id = ath12k_pci_family_drivers[device_family_id]->id_table; 1529 while (id->device) { 1530 if (id->device == pci_dev->device) 1531 return device_family_id; 1532 id += 1; 1533 } 1534 } 1535 1536 return ATH12K_DEVICE_FAMILY_MAX; 1537 } 1538 1539 static int ath12k_pci_probe(struct pci_dev *pdev, 1540 const struct pci_device_id *pci_dev) 1541 { 1542 enum ath12k_device_family device_id; 1543 struct ath12k_pci *ab_pci; 1544 struct ath12k_base *ab; 1545 int ret; 1546 1547 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); 1548 if (!ab) { 1549 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); 1550 return -ENOMEM; 1551 } 1552 1553 ab->dev = &pdev->dev; 1554 ab_pci = ath12k_pci_priv(ab); 1555 ab_pci->dev_id = pci_dev->device; 1556 ab_pci->ab = ab; 1557 ab_pci->pdev = pdev; 1558 ab->hif.ops = &ath12k_pci_hif_ops; 1559 ab->fw_mode = ATH12K_QMI_FIRMWARE_MODE_NORMAL; 1560 pci_set_drvdata(pdev, ab); 1561 spin_lock_init(&ab_pci->window_lock); 1562 1563 ret = ath12k_pci_claim(ab_pci, pdev); 1564 if (ret) { 1565 ath12k_err(ab, "failed to claim device: %d\n", ret); 1566 goto err_free_core; 1567 } 1568 1569 ath12k_dbg(ab, ATH12K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 1570 pdev->vendor, pdev->device, 1571 pdev->subsystem_vendor, pdev->subsystem_device); 1572 1573 ab->id.vendor = pdev->vendor; 1574 ab->id.device = pdev->device; 1575 ab->id.subsystem_vendor = pdev->subsystem_vendor; 1576 ab->id.subsystem_device = pdev->subsystem_device; 1577 1578 device_id = ath12k_get_device_family(pci_dev); 1579 if (device_id >= ATH12K_DEVICE_FAMILY_MAX) { 1580 ath12k_err(ab, "failed to get device family id\n"); 1581 ret = -EINVAL; 1582 goto err_pci_free_region; 1583 } 1584 1585 ath12k_dbg(ab, ATH12K_DBG_PCI, "PCI device family id: %d\n", device_id); 1586 1587 ab_pci->device_family_ops = &ath12k_pci_family_drivers[device_id]->ops; 1588 ab_pci->reg_base = ath12k_pci_family_drivers[device_id]->reg_base; 1589 1590 /* Call device specific probe. This is the callback that can 1591 * be used to override any ops in future 1592 * probe is validated for NULL during registration. 1593 */ 1594 ret = ab_pci->device_family_ops->probe(pdev, pci_dev); 1595 if (ret) { 1596 ath12k_err(ab, "failed to probe device: %d\n", ret); 1597 goto err_pci_free_region; 1598 } 1599 1600 ret = ath12k_pci_msi_alloc(ab_pci); 1601 if (ret) { 1602 ath12k_err(ab, "failed to alloc msi: %d\n", ret); 1603 goto err_pci_free_region; 1604 } 1605 1606 ret = ath12k_core_pre_init(ab); 1607 if (ret) 1608 goto err_pci_msi_free; 1609 1610 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 1611 if (ret) { 1612 ath12k_err(ab, "failed to set irq affinity %d\n", ret); 1613 goto err_pci_msi_free; 1614 } 1615 1616 ret = ath12k_mhi_register(ab_pci); 1617 if (ret) { 1618 ath12k_err(ab, "failed to register mhi: %d\n", ret); 1619 goto err_irq_affinity_cleanup; 1620 } 1621 1622 ret = ath12k_hal_srng_init(ab); 1623 if (ret) 1624 goto err_mhi_unregister; 1625 1626 ret = ath12k_ce_alloc_pipes(ab); 1627 if (ret) { 1628 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1629 goto err_hal_srng_deinit; 1630 } 1631 1632 ath12k_pci_init_qmi_ce_config(ab); 1633 1634 ret = ath12k_pci_config_irq(ab); 1635 if (ret) { 1636 ath12k_err(ab, "failed to config irq: %d\n", ret); 1637 goto err_ce_free; 1638 } 1639 1640 /* kernel may allocate a dummy vector before request_irq and 1641 * then allocate a real vector when request_irq is called. 1642 * So get msi_data here again to avoid spurious interrupt 1643 * as msi_data will configured to srngs. 1644 */ 1645 ret = ath12k_pci_config_msi_data(ab_pci); 1646 if (ret) { 1647 ath12k_err(ab, "failed to config msi_data: %d\n", ret); 1648 goto err_free_irq; 1649 } 1650 1651 /* Invoke arch_init here so that arch-specific init operations 1652 * can utilize already initialized ab fields, such as HAL SRNGs. 1653 */ 1654 ret = ab_pci->device_family_ops->arch_init(ab); 1655 if (ret) { 1656 ath12k_err(ab, "PCI arch_init failed %d\n", ret); 1657 goto err_free_irq; 1658 } 1659 1660 ret = ath12k_core_init(ab); 1661 if (ret) { 1662 ath12k_err(ab, "failed to init core: %d\n", ret); 1663 goto err_deinit_arch; 1664 } 1665 return 0; 1666 1667 err_deinit_arch: 1668 ab_pci->device_family_ops->arch_deinit(ab); 1669 1670 err_free_irq: 1671 /* __free_irq() expects the caller to have cleared the affinity hint */ 1672 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1673 ath12k_pci_free_irq(ab); 1674 1675 err_ce_free: 1676 ath12k_ce_free_pipes(ab); 1677 1678 err_hal_srng_deinit: 1679 ath12k_hal_srng_deinit(ab); 1680 1681 err_mhi_unregister: 1682 ath12k_mhi_unregister(ab_pci); 1683 1684 err_irq_affinity_cleanup: 1685 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1686 1687 err_pci_msi_free: 1688 ath12k_pci_msi_free(ab_pci); 1689 1690 err_pci_free_region: 1691 ath12k_pci_free_region(ab_pci); 1692 1693 err_free_core: 1694 ath12k_core_free(ab); 1695 1696 return ret; 1697 } 1698 1699 static void ath12k_pci_remove(struct pci_dev *pdev) 1700 { 1701 struct ath12k_base *ab = pci_get_drvdata(pdev); 1702 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1703 1704 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1705 1706 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1707 ath12k_pci_power_down(ab, false); 1708 goto qmi_fail; 1709 } 1710 1711 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); 1712 1713 cancel_work_sync(&ab->reset_work); 1714 cancel_work_sync(&ab->dump_work); 1715 ath12k_core_hw_group_cleanup(ab->ag); 1716 1717 qmi_fail: 1718 ath12k_core_deinit(ab); 1719 ath12k_fw_unmap(ab); 1720 ath12k_mhi_unregister(ab_pci); 1721 1722 ath12k_pci_free_irq(ab); 1723 ath12k_pci_msi_free(ab_pci); 1724 ath12k_pci_free_region(ab_pci); 1725 1726 ath12k_hal_srng_deinit(ab); 1727 ath12k_ce_free_pipes(ab); 1728 1729 ab_pci->device_family_ops->arch_deinit(ab); 1730 1731 ath12k_core_free(ab); 1732 } 1733 1734 static void ath12k_pci_hw_group_power_down(struct ath12k_hw_group *ag) 1735 { 1736 struct ath12k_base *ab; 1737 int i; 1738 1739 if (!ag) 1740 return; 1741 1742 mutex_lock(&ag->mutex); 1743 1744 for (i = 0; i < ag->num_devices; i++) { 1745 ab = ag->ab[i]; 1746 if (!ab) 1747 continue; 1748 1749 ath12k_pci_power_down(ab, false); 1750 } 1751 1752 mutex_unlock(&ag->mutex); 1753 } 1754 1755 static void ath12k_pci_shutdown(struct pci_dev *pdev) 1756 { 1757 struct ath12k_base *ab = pci_get_drvdata(pdev); 1758 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1759 1760 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1761 ath12k_pci_hw_group_power_down(ab->ag); 1762 } 1763 1764 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev) 1765 { 1766 struct ath12k_base *ab = dev_get_drvdata(dev); 1767 int ret; 1768 1769 ret = ath12k_core_suspend(ab); 1770 if (ret) 1771 ath12k_warn(ab, "failed to suspend core: %d\n", ret); 1772 1773 return ret; 1774 } 1775 1776 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev) 1777 { 1778 struct ath12k_base *ab = dev_get_drvdata(dev); 1779 int ret; 1780 1781 ret = ath12k_core_resume(ab); 1782 if (ret) 1783 ath12k_warn(ab, "failed to resume core: %d\n", ret); 1784 1785 return ret; 1786 } 1787 1788 static __maybe_unused int ath12k_pci_pm_suspend_late(struct device *dev) 1789 { 1790 struct ath12k_base *ab = dev_get_drvdata(dev); 1791 int ret; 1792 1793 ret = ath12k_core_suspend_late(ab); 1794 if (ret) 1795 ath12k_warn(ab, "failed to late suspend core: %d\n", ret); 1796 1797 return ret; 1798 } 1799 1800 static __maybe_unused int ath12k_pci_pm_resume_early(struct device *dev) 1801 { 1802 struct ath12k_base *ab = dev_get_drvdata(dev); 1803 int ret; 1804 1805 ret = ath12k_core_resume_early(ab); 1806 if (ret) 1807 ath12k_warn(ab, "failed to early resume core: %d\n", ret); 1808 1809 return ret; 1810 } 1811 1812 static const struct dev_pm_ops __maybe_unused ath12k_pci_pm_ops = { 1813 SET_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend, 1814 ath12k_pci_pm_resume) 1815 SET_LATE_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend_late, 1816 ath12k_pci_pm_resume_early) 1817 }; 1818 1819 int ath12k_pci_register_driver(const enum ath12k_device_family device_id, 1820 struct ath12k_pci_driver *driver) 1821 { 1822 struct pci_driver *pci_driver; 1823 1824 if (device_id >= ATH12K_DEVICE_FAMILY_MAX) 1825 return -EINVAL; 1826 1827 if (!driver || !driver->ops.probe || 1828 !driver->ops.arch_init || !driver->ops.arch_deinit) 1829 return -EINVAL; 1830 1831 if (ath12k_pci_family_drivers[device_id]) { 1832 pr_err("Driver already registered for %d\n", device_id); 1833 return -EALREADY; 1834 } 1835 1836 ath12k_pci_family_drivers[device_id] = driver; 1837 1838 pci_driver = &ath12k_pci_family_drivers[device_id]->driver; 1839 pci_driver->name = driver->name; 1840 pci_driver->id_table = driver->id_table; 1841 pci_driver->probe = ath12k_pci_probe; 1842 pci_driver->remove = ath12k_pci_remove; 1843 pci_driver->shutdown = ath12k_pci_shutdown; 1844 pci_driver->driver.pm = &ath12k_pci_pm_ops; 1845 1846 return pci_register_driver(pci_driver); 1847 } 1848 EXPORT_SYMBOL(ath12k_pci_register_driver); 1849 1850 void ath12k_pci_unregister_driver(const enum ath12k_device_family device_id) 1851 { 1852 if (device_id >= ATH12K_DEVICE_FAMILY_MAX || 1853 !ath12k_pci_family_drivers[device_id]) 1854 return; 1855 1856 pci_unregister_driver(&ath12k_pci_family_drivers[device_id]->driver); 1857 ath12k_pci_family_drivers[device_id] = NULL; 1858 } 1859 EXPORT_SYMBOL(ath12k_pci_unregister_driver); 1860 1861 /* firmware files */ 1862 MODULE_FIRMWARE(ATH12K_FW_DIR "/QCN9274/hw2.0/*"); 1863 MODULE_FIRMWARE(ATH12K_FW_DIR "/WCN7850/hw2.0/*"); 1864