1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 #include <linux/firmware.h> 10 11 #include "core.h" 12 #include "debug.h" 13 #include "mhi.h" 14 #include "pci.h" 15 16 #define MHI_TIMEOUT_DEFAULT_MS 90000 17 #define OTP_INVALID_BOARD_ID 0xFFFF 18 #define OTP_VALID_DUALMAC_BOARD_ID_MASK 0x1000 19 #define MHI_CB_INVALID 0xff 20 21 static const struct mhi_channel_config ath12k_mhi_channels_qcn9274[] = { 22 { 23 .num = 20, 24 .name = "IPCR", 25 .num_elements = 32, 26 .event_ring = 1, 27 .dir = DMA_TO_DEVICE, 28 .ee_mask = 0x4, 29 .pollcfg = 0, 30 .doorbell = MHI_DB_BRST_DISABLE, 31 .lpm_notify = false, 32 .offload_channel = false, 33 .doorbell_mode_switch = false, 34 .auto_queue = false, 35 }, 36 { 37 .num = 21, 38 .name = "IPCR", 39 .num_elements = 32, 40 .event_ring = 1, 41 .dir = DMA_FROM_DEVICE, 42 .ee_mask = 0x4, 43 .pollcfg = 0, 44 .doorbell = MHI_DB_BRST_DISABLE, 45 .lpm_notify = false, 46 .offload_channel = false, 47 .doorbell_mode_switch = false, 48 .auto_queue = true, 49 }, 50 }; 51 52 static struct mhi_event_config ath12k_mhi_events_qcn9274[] = { 53 { 54 .num_elements = 32, 55 .irq_moderation_ms = 0, 56 .irq = 1, 57 .data_type = MHI_ER_CTRL, 58 .mode = MHI_DB_BRST_DISABLE, 59 .hardware_event = false, 60 .client_managed = false, 61 .offload_channel = false, 62 }, 63 { 64 .num_elements = 256, 65 .irq_moderation_ms = 1, 66 .irq = 2, 67 .mode = MHI_DB_BRST_DISABLE, 68 .priority = 1, 69 .hardware_event = false, 70 .client_managed = false, 71 .offload_channel = false, 72 }, 73 }; 74 75 const struct mhi_controller_config ath12k_mhi_config_qcn9274 = { 76 .max_channels = 30, 77 .timeout_ms = 10000, 78 .use_bounce_buf = false, 79 .buf_len = 0, 80 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_qcn9274), 81 .ch_cfg = ath12k_mhi_channels_qcn9274, 82 .num_events = ARRAY_SIZE(ath12k_mhi_events_qcn9274), 83 .event_cfg = ath12k_mhi_events_qcn9274, 84 }; 85 86 static const struct mhi_channel_config ath12k_mhi_channels_wcn7850[] = { 87 { 88 .num = 20, 89 .name = "IPCR", 90 .num_elements = 64, 91 .event_ring = 1, 92 .dir = DMA_TO_DEVICE, 93 .ee_mask = 0x4, 94 .pollcfg = 0, 95 .doorbell = MHI_DB_BRST_DISABLE, 96 .lpm_notify = false, 97 .offload_channel = false, 98 .doorbell_mode_switch = false, 99 .auto_queue = false, 100 }, 101 { 102 .num = 21, 103 .name = "IPCR", 104 .num_elements = 64, 105 .event_ring = 1, 106 .dir = DMA_FROM_DEVICE, 107 .ee_mask = 0x4, 108 .pollcfg = 0, 109 .doorbell = MHI_DB_BRST_DISABLE, 110 .lpm_notify = false, 111 .offload_channel = false, 112 .doorbell_mode_switch = false, 113 .auto_queue = true, 114 }, 115 }; 116 117 static struct mhi_event_config ath12k_mhi_events_wcn7850[] = { 118 { 119 .num_elements = 32, 120 .irq_moderation_ms = 0, 121 .irq = 1, 122 .mode = MHI_DB_BRST_DISABLE, 123 .data_type = MHI_ER_CTRL, 124 .hardware_event = false, 125 .client_managed = false, 126 .offload_channel = false, 127 }, 128 { 129 .num_elements = 256, 130 .irq_moderation_ms = 1, 131 .irq = 2, 132 .mode = MHI_DB_BRST_DISABLE, 133 .priority = 1, 134 .hardware_event = false, 135 .client_managed = false, 136 .offload_channel = false, 137 }, 138 }; 139 140 const struct mhi_controller_config ath12k_mhi_config_wcn7850 = { 141 .max_channels = 128, 142 .timeout_ms = 2000, 143 .use_bounce_buf = false, 144 .buf_len = 8192, 145 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_wcn7850), 146 .ch_cfg = ath12k_mhi_channels_wcn7850, 147 .num_events = ARRAY_SIZE(ath12k_mhi_events_wcn7850), 148 .event_cfg = ath12k_mhi_events_wcn7850, 149 }; 150 151 void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab) 152 { 153 u32 val; 154 155 val = ath12k_pci_read32(ab, MHISTATUS); 156 157 ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val); 158 159 /* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS 160 * has SYSERR bit set and thus need to set MHICTRL_RESET 161 * to clear SYSERR. 162 */ 163 ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 164 165 mdelay(10); 166 } 167 168 static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab) 169 { 170 ath12k_pci_write32(ab, PCIE_TXVECDB, 0); 171 } 172 173 static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab) 174 { 175 ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 176 } 177 178 static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab) 179 { 180 ath12k_pci_write32(ab, PCIE_RXVECDB, 0); 181 } 182 183 static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab) 184 { 185 ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 186 } 187 188 void ath12k_mhi_clear_vector(struct ath12k_base *ab) 189 { 190 ath12k_mhi_reset_txvecdb(ab); 191 ath12k_mhi_reset_txvecstatus(ab); 192 ath12k_mhi_reset_rxvecdb(ab); 193 ath12k_mhi_reset_rxvecstatus(ab); 194 } 195 196 static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci) 197 { 198 struct ath12k_base *ab = ab_pci->ab; 199 u32 user_base_data, base_vector; 200 int ret, num_vectors, i; 201 int *irq; 202 unsigned int msi_data; 203 204 ret = ath12k_pci_get_user_msi_assignment(ab, 205 "MHI", &num_vectors, 206 &user_base_data, &base_vector); 207 if (ret) 208 return ret; 209 210 ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 211 num_vectors, base_vector); 212 213 irq = kcalloc(num_vectors, sizeof(*irq), GFP_KERNEL); 214 if (!irq) 215 return -ENOMEM; 216 217 msi_data = base_vector; 218 for (i = 0; i < num_vectors; i++) { 219 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 220 irq[i] = ath12k_pci_get_msi_irq(ab->dev, 221 msi_data++); 222 else 223 irq[i] = ath12k_pci_get_msi_irq(ab->dev, 224 msi_data); 225 } 226 227 ab_pci->mhi_ctrl->irq = irq; 228 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 229 230 return 0; 231 } 232 233 static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 234 { 235 return 0; 236 } 237 238 static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 239 { 240 } 241 242 static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason) 243 { 244 switch (reason) { 245 case MHI_CB_IDLE: 246 return "MHI_CB_IDLE"; 247 case MHI_CB_PENDING_DATA: 248 return "MHI_CB_PENDING_DATA"; 249 case MHI_CB_LPM_ENTER: 250 return "MHI_CB_LPM_ENTER"; 251 case MHI_CB_LPM_EXIT: 252 return "MHI_CB_LPM_EXIT"; 253 case MHI_CB_EE_RDDM: 254 return "MHI_CB_EE_RDDM"; 255 case MHI_CB_EE_MISSION_MODE: 256 return "MHI_CB_EE_MISSION_MODE"; 257 case MHI_CB_SYS_ERROR: 258 return "MHI_CB_SYS_ERROR"; 259 case MHI_CB_FATAL_ERROR: 260 return "MHI_CB_FATAL_ERROR"; 261 case MHI_CB_BW_REQ: 262 return "MHI_CB_BW_REQ"; 263 default: 264 return "UNKNOWN"; 265 } 266 } 267 268 static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 269 enum mhi_callback cb) 270 { 271 struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 272 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 273 274 ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n", 275 ath12k_mhi_op_callback_to_str(cb)); 276 277 switch (cb) { 278 case MHI_CB_SYS_ERROR: 279 ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 280 break; 281 case MHI_CB_EE_RDDM: 282 if (ab_pci->mhi_pre_cb == MHI_CB_EE_RDDM) { 283 ath12k_dbg(ab, ATH12K_DBG_BOOT, 284 "do not queue again for consecutive RDDM event\n"); 285 break; 286 } 287 288 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) { 289 set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); 290 set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); 291 queue_work(ab->workqueue_aux, &ab->reset_work); 292 } 293 break; 294 default: 295 break; 296 } 297 298 ab_pci->mhi_pre_cb = cb; 299 } 300 301 static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 302 void __iomem *addr, 303 u32 *out) 304 { 305 *out = readl(addr); 306 307 return 0; 308 } 309 310 static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 311 void __iomem *addr, 312 u32 val) 313 { 314 writel(val, addr); 315 } 316 317 int ath12k_mhi_register(struct ath12k_pci *ab_pci) 318 { 319 struct ath12k_base *ab = ab_pci->ab; 320 struct mhi_controller *mhi_ctrl; 321 unsigned int board_id; 322 int ret; 323 bool dualmac = false; 324 325 mhi_ctrl = mhi_alloc_controller(); 326 if (!mhi_ctrl) 327 return -ENOMEM; 328 329 ab_pci->mhi_pre_cb = MHI_CB_INVALID; 330 ab_pci->mhi_ctrl = mhi_ctrl; 331 mhi_ctrl->cntrl_dev = ab->dev; 332 mhi_ctrl->regs = ab->mem; 333 mhi_ctrl->reg_len = ab->mem_len; 334 mhi_ctrl->rddm_size = ab->hw_params->rddm_size; 335 336 if (ab->hw_params->otp_board_id_register) { 337 board_id = 338 ath12k_pci_read32(ab, ab->hw_params->otp_board_id_register); 339 board_id = u32_get_bits(board_id, OTP_BOARD_ID_MASK); 340 341 if (!board_id || (board_id == OTP_INVALID_BOARD_ID)) { 342 ath12k_dbg(ab, ATH12K_DBG_BOOT, 343 "failed to read board id\n"); 344 } else if (board_id & OTP_VALID_DUALMAC_BOARD_ID_MASK) { 345 dualmac = true; 346 ath12k_dbg(ab, ATH12K_DBG_BOOT, 347 "dualmac fw selected for board id: %x\n", board_id); 348 } 349 } 350 351 if (dualmac) { 352 if (ab->fw.amss_dualmac_data && ab->fw.amss_dualmac_len > 0) { 353 /* use MHI firmware file from firmware-N.bin */ 354 mhi_ctrl->fw_data = ab->fw.amss_dualmac_data; 355 mhi_ctrl->fw_sz = ab->fw.amss_dualmac_len; 356 } else { 357 ath12k_warn(ab, "dualmac firmware IE not present in firmware-N.bin\n"); 358 ret = -ENOENT; 359 goto free_controller; 360 } 361 } else { 362 if (ab->fw.amss_data && ab->fw.amss_len > 0) { 363 /* use MHI firmware file from firmware-N.bin */ 364 mhi_ctrl->fw_data = ab->fw.amss_data; 365 mhi_ctrl->fw_sz = ab->fw.amss_len; 366 } else { 367 /* use the old separate mhi.bin MHI firmware file */ 368 ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE, 369 ab_pci->amss_path, 370 sizeof(ab_pci->amss_path)); 371 mhi_ctrl->fw_image = ab_pci->amss_path; 372 } 373 } 374 375 ret = ath12k_mhi_get_msi(ab_pci); 376 if (ret) { 377 ath12k_err(ab, "failed to get msi for mhi\n"); 378 goto free_controller; 379 } 380 381 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 382 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 383 384 mhi_ctrl->iova_start = 0; 385 mhi_ctrl->iova_stop = ab_pci->dma_mask; 386 mhi_ctrl->sbl_size = SZ_512K; 387 mhi_ctrl->seg_len = SZ_512K; 388 mhi_ctrl->fbc_download = true; 389 mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get; 390 mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put; 391 mhi_ctrl->status_cb = ath12k_mhi_op_status_cb; 392 mhi_ctrl->read_reg = ath12k_mhi_op_read_reg; 393 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg; 394 395 ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config); 396 if (ret) { 397 ath12k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 398 goto free_controller; 399 } 400 401 return 0; 402 403 free_controller: 404 mhi_free_controller(mhi_ctrl); 405 ab_pci->mhi_ctrl = NULL; 406 return ret; 407 } 408 409 void ath12k_mhi_unregister(struct ath12k_pci *ab_pci) 410 { 411 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 412 413 mhi_unregister_controller(mhi_ctrl); 414 kfree(mhi_ctrl->irq); 415 mhi_free_controller(mhi_ctrl); 416 ab_pci->mhi_ctrl = NULL; 417 } 418 419 static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state) 420 { 421 switch (mhi_state) { 422 case ATH12K_MHI_INIT: 423 return "INIT"; 424 case ATH12K_MHI_DEINIT: 425 return "DEINIT"; 426 case ATH12K_MHI_POWER_ON: 427 return "POWER_ON"; 428 case ATH12K_MHI_POWER_OFF: 429 return "POWER_OFF"; 430 case ATH12K_MHI_POWER_OFF_KEEP_DEV: 431 return "POWER_OFF_KEEP_DEV"; 432 case ATH12K_MHI_FORCE_POWER_OFF: 433 return "FORCE_POWER_OFF"; 434 case ATH12K_MHI_SUSPEND: 435 return "SUSPEND"; 436 case ATH12K_MHI_RESUME: 437 return "RESUME"; 438 case ATH12K_MHI_TRIGGER_RDDM: 439 return "TRIGGER_RDDM"; 440 case ATH12K_MHI_RDDM_DONE: 441 return "RDDM_DONE"; 442 default: 443 return "UNKNOWN"; 444 } 445 }; 446 447 static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci, 448 enum ath12k_mhi_state mhi_state) 449 { 450 struct ath12k_base *ab = ab_pci->ab; 451 452 switch (mhi_state) { 453 case ATH12K_MHI_INIT: 454 set_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state); 455 break; 456 case ATH12K_MHI_DEINIT: 457 clear_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state); 458 break; 459 case ATH12K_MHI_POWER_ON: 460 set_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state); 461 break; 462 case ATH12K_MHI_POWER_OFF: 463 case ATH12K_MHI_POWER_OFF_KEEP_DEV: 464 case ATH12K_MHI_FORCE_POWER_OFF: 465 clear_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state); 466 clear_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 467 clear_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state); 468 break; 469 case ATH12K_MHI_SUSPEND: 470 set_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state); 471 break; 472 case ATH12K_MHI_RESUME: 473 clear_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state); 474 break; 475 case ATH12K_MHI_TRIGGER_RDDM: 476 set_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 477 break; 478 case ATH12K_MHI_RDDM_DONE: 479 set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state); 480 break; 481 default: 482 ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 483 } 484 } 485 486 static int ath12k_mhi_check_state_bit(struct ath12k_pci *ab_pci, 487 enum ath12k_mhi_state mhi_state) 488 { 489 struct ath12k_base *ab = ab_pci->ab; 490 491 switch (mhi_state) { 492 case ATH12K_MHI_INIT: 493 if (!test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state)) 494 return 0; 495 break; 496 case ATH12K_MHI_DEINIT: 497 case ATH12K_MHI_POWER_ON: 498 if (test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state) && 499 !test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state)) 500 return 0; 501 break; 502 case ATH12K_MHI_FORCE_POWER_OFF: 503 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state)) 504 return 0; 505 break; 506 case ATH12K_MHI_POWER_OFF: 507 case ATH12K_MHI_POWER_OFF_KEEP_DEV: 508 case ATH12K_MHI_SUSPEND: 509 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) && 510 !test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state)) 511 return 0; 512 break; 513 case ATH12K_MHI_RESUME: 514 if (test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state)) 515 return 0; 516 break; 517 case ATH12K_MHI_TRIGGER_RDDM: 518 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) && 519 !test_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 520 return 0; 521 break; 522 case ATH12K_MHI_RDDM_DONE: 523 return 0; 524 default: 525 ath12k_err(ab, "unhandled mhi state: %s(%d)\n", 526 ath12k_mhi_state_to_str(mhi_state), mhi_state); 527 } 528 529 ath12k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 530 ath12k_mhi_state_to_str(mhi_state), mhi_state, 531 ab_pci->mhi_state); 532 533 return -EINVAL; 534 } 535 536 static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci, 537 enum ath12k_mhi_state mhi_state) 538 { 539 struct ath12k_base *ab = ab_pci->ab; 540 int ret; 541 542 ret = ath12k_mhi_check_state_bit(ab_pci, mhi_state); 543 if (ret) 544 goto out; 545 546 ath12k_dbg(ab, ATH12K_DBG_PCI, "setting mhi state: %s(%d)\n", 547 ath12k_mhi_state_to_str(mhi_state), mhi_state); 548 549 switch (mhi_state) { 550 case ATH12K_MHI_INIT: 551 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 552 break; 553 case ATH12K_MHI_DEINIT: 554 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 555 ret = 0; 556 break; 557 case ATH12K_MHI_POWER_ON: 558 /* In case of resume, QRTR's resume_early() is called 559 * right after ath12k' resume_early(). Since QRTR requires 560 * MHI mission mode state when preparing IPCR channels 561 * (see ee_mask of that channel), we need to use the 'sync' 562 * version here to make sure MHI is in that state when we 563 * return. Or QRTR might resume before that state comes, 564 * and as a result it fails. 565 * 566 * The 'sync' version works for non-resume (normal power on) 567 * case as well. 568 */ 569 ret = mhi_sync_power_up(ab_pci->mhi_ctrl); 570 break; 571 case ATH12K_MHI_POWER_OFF: 572 mhi_power_down(ab_pci->mhi_ctrl, true); 573 ret = 0; 574 break; 575 case ATH12K_MHI_POWER_OFF_KEEP_DEV: 576 mhi_power_down_keep_dev(ab_pci->mhi_ctrl, true); 577 ret = 0; 578 break; 579 case ATH12K_MHI_FORCE_POWER_OFF: 580 mhi_power_down(ab_pci->mhi_ctrl, false); 581 ret = 0; 582 break; 583 case ATH12K_MHI_SUSPEND: 584 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 585 break; 586 case ATH12K_MHI_RESUME: 587 ret = mhi_pm_resume(ab_pci->mhi_ctrl); 588 break; 589 case ATH12K_MHI_TRIGGER_RDDM: 590 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 591 break; 592 case ATH12K_MHI_RDDM_DONE: 593 break; 594 default: 595 ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 596 ret = -EINVAL; 597 } 598 599 if (ret) 600 goto out; 601 602 ath12k_mhi_set_state_bit(ab_pci, mhi_state); 603 604 return 0; 605 606 out: 607 ath12k_err(ab, "failed to set mhi state: %s(%d)\n", 608 ath12k_mhi_state_to_str(mhi_state), mhi_state); 609 return ret; 610 } 611 612 int ath12k_mhi_start(struct ath12k_pci *ab_pci) 613 { 614 int ret; 615 616 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 617 618 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_INIT); 619 if (ret) 620 goto out; 621 622 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_ON); 623 if (ret) 624 goto out; 625 626 return 0; 627 628 out: 629 return ret; 630 } 631 632 void ath12k_mhi_stop(struct ath12k_pci *ab_pci, bool is_suspend) 633 { 634 /* During suspend we need to use mhi_power_down_keep_dev() 635 * workaround, otherwise ath12k_core_resume() will timeout 636 * during resume. 637 */ 638 if (is_suspend) 639 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF_KEEP_DEV); 640 else 641 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF); 642 643 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_DEINIT); 644 } 645 646 void ath12k_mhi_suspend(struct ath12k_pci *ab_pci) 647 { 648 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SUSPEND); 649 } 650 651 void ath12k_mhi_resume(struct ath12k_pci *ab_pci) 652 { 653 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME); 654 } 655 656 void ath12k_mhi_coredump(struct mhi_controller *mhi_ctrl, bool in_panic) 657 { 658 mhi_download_rddm_image(mhi_ctrl, in_panic); 659 } 660