1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 10 #include "core.h" 11 #include "debug.h" 12 #include "mhi.h" 13 #include "pci.h" 14 15 #define MHI_TIMEOUT_DEFAULT_MS 90000 16 17 static const struct mhi_channel_config ath12k_mhi_channels_qcn9274[] = { 18 { 19 .num = 0, 20 .name = "LOOPBACK", 21 .num_elements = 32, 22 .event_ring = 1, 23 .dir = DMA_TO_DEVICE, 24 .ee_mask = 0x4, 25 .pollcfg = 0, 26 .doorbell = MHI_DB_BRST_DISABLE, 27 .lpm_notify = false, 28 .offload_channel = false, 29 .doorbell_mode_switch = false, 30 .auto_queue = false, 31 }, 32 { 33 .num = 1, 34 .name = "LOOPBACK", 35 .num_elements = 32, 36 .event_ring = 1, 37 .dir = DMA_FROM_DEVICE, 38 .ee_mask = 0x4, 39 .pollcfg = 0, 40 .doorbell = MHI_DB_BRST_DISABLE, 41 .lpm_notify = false, 42 .offload_channel = false, 43 .doorbell_mode_switch = false, 44 .auto_queue = false, 45 }, 46 { 47 .num = 20, 48 .name = "IPCR", 49 .num_elements = 32, 50 .event_ring = 1, 51 .dir = DMA_TO_DEVICE, 52 .ee_mask = 0x4, 53 .pollcfg = 0, 54 .doorbell = MHI_DB_BRST_DISABLE, 55 .lpm_notify = false, 56 .offload_channel = false, 57 .doorbell_mode_switch = false, 58 .auto_queue = false, 59 }, 60 { 61 .num = 21, 62 .name = "IPCR", 63 .num_elements = 32, 64 .event_ring = 1, 65 .dir = DMA_FROM_DEVICE, 66 .ee_mask = 0x4, 67 .pollcfg = 0, 68 .doorbell = MHI_DB_BRST_DISABLE, 69 .lpm_notify = false, 70 .offload_channel = false, 71 .doorbell_mode_switch = false, 72 .auto_queue = true, 73 }, 74 }; 75 76 static struct mhi_event_config ath12k_mhi_events_qcn9274[] = { 77 { 78 .num_elements = 32, 79 .irq_moderation_ms = 0, 80 .irq = 1, 81 .data_type = MHI_ER_CTRL, 82 .mode = MHI_DB_BRST_DISABLE, 83 .hardware_event = false, 84 .client_managed = false, 85 .offload_channel = false, 86 }, 87 { 88 .num_elements = 256, 89 .irq_moderation_ms = 1, 90 .irq = 2, 91 .mode = MHI_DB_BRST_DISABLE, 92 .priority = 1, 93 .hardware_event = false, 94 .client_managed = false, 95 .offload_channel = false, 96 }, 97 }; 98 99 const struct mhi_controller_config ath12k_mhi_config_qcn9274 = { 100 .max_channels = 30, 101 .timeout_ms = 10000, 102 .use_bounce_buf = false, 103 .buf_len = 0, 104 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_qcn9274), 105 .ch_cfg = ath12k_mhi_channels_qcn9274, 106 .num_events = ARRAY_SIZE(ath12k_mhi_events_qcn9274), 107 .event_cfg = ath12k_mhi_events_qcn9274, 108 }; 109 110 static const struct mhi_channel_config ath12k_mhi_channels_wcn7850[] = { 111 { 112 .num = 0, 113 .name = "LOOPBACK", 114 .num_elements = 32, 115 .event_ring = 0, 116 .dir = DMA_TO_DEVICE, 117 .ee_mask = 0x4, 118 .pollcfg = 0, 119 .doorbell = MHI_DB_BRST_DISABLE, 120 .lpm_notify = false, 121 .offload_channel = false, 122 .doorbell_mode_switch = false, 123 .auto_queue = false, 124 }, 125 { 126 .num = 1, 127 .name = "LOOPBACK", 128 .num_elements = 32, 129 .event_ring = 0, 130 .dir = DMA_FROM_DEVICE, 131 .ee_mask = 0x4, 132 .pollcfg = 0, 133 .doorbell = MHI_DB_BRST_DISABLE, 134 .lpm_notify = false, 135 .offload_channel = false, 136 .doorbell_mode_switch = false, 137 .auto_queue = false, 138 }, 139 { 140 .num = 20, 141 .name = "IPCR", 142 .num_elements = 64, 143 .event_ring = 1, 144 .dir = DMA_TO_DEVICE, 145 .ee_mask = 0x4, 146 .pollcfg = 0, 147 .doorbell = MHI_DB_BRST_DISABLE, 148 .lpm_notify = false, 149 .offload_channel = false, 150 .doorbell_mode_switch = false, 151 .auto_queue = false, 152 }, 153 { 154 .num = 21, 155 .name = "IPCR", 156 .num_elements = 64, 157 .event_ring = 1, 158 .dir = DMA_FROM_DEVICE, 159 .ee_mask = 0x4, 160 .pollcfg = 0, 161 .doorbell = MHI_DB_BRST_DISABLE, 162 .lpm_notify = false, 163 .offload_channel = false, 164 .doorbell_mode_switch = false, 165 .auto_queue = true, 166 }, 167 }; 168 169 static struct mhi_event_config ath12k_mhi_events_wcn7850[] = { 170 { 171 .num_elements = 32, 172 .irq_moderation_ms = 0, 173 .irq = 1, 174 .mode = MHI_DB_BRST_DISABLE, 175 .data_type = MHI_ER_CTRL, 176 .hardware_event = false, 177 .client_managed = false, 178 .offload_channel = false, 179 }, 180 { 181 .num_elements = 256, 182 .irq_moderation_ms = 1, 183 .irq = 2, 184 .mode = MHI_DB_BRST_DISABLE, 185 .priority = 1, 186 .hardware_event = false, 187 .client_managed = false, 188 .offload_channel = false, 189 }, 190 }; 191 192 const struct mhi_controller_config ath12k_mhi_config_wcn7850 = { 193 .max_channels = 128, 194 .timeout_ms = 2000, 195 .use_bounce_buf = false, 196 .buf_len = 0, 197 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_wcn7850), 198 .ch_cfg = ath12k_mhi_channels_wcn7850, 199 .num_events = ARRAY_SIZE(ath12k_mhi_events_wcn7850), 200 .event_cfg = ath12k_mhi_events_wcn7850, 201 }; 202 203 void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab) 204 { 205 u32 val; 206 207 val = ath12k_pci_read32(ab, MHISTATUS); 208 209 ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val); 210 211 /* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS 212 * has SYSERR bit set and thus need to set MHICTRL_RESET 213 * to clear SYSERR. 214 */ 215 ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 216 217 mdelay(10); 218 } 219 220 static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab) 221 { 222 ath12k_pci_write32(ab, PCIE_TXVECDB, 0); 223 } 224 225 static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab) 226 { 227 ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 228 } 229 230 static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab) 231 { 232 ath12k_pci_write32(ab, PCIE_RXVECDB, 0); 233 } 234 235 static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab) 236 { 237 ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 238 } 239 240 void ath12k_mhi_clear_vector(struct ath12k_base *ab) 241 { 242 ath12k_mhi_reset_txvecdb(ab); 243 ath12k_mhi_reset_txvecstatus(ab); 244 ath12k_mhi_reset_rxvecdb(ab); 245 ath12k_mhi_reset_rxvecstatus(ab); 246 } 247 248 static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci) 249 { 250 struct ath12k_base *ab = ab_pci->ab; 251 u32 user_base_data, base_vector; 252 int ret, num_vectors, i; 253 int *irq; 254 unsigned int msi_data; 255 256 ret = ath12k_pci_get_user_msi_assignment(ab, 257 "MHI", &num_vectors, 258 &user_base_data, &base_vector); 259 if (ret) 260 return ret; 261 262 ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 263 num_vectors, base_vector); 264 265 irq = kcalloc(num_vectors, sizeof(*irq), GFP_KERNEL); 266 if (!irq) 267 return -ENOMEM; 268 269 msi_data = base_vector; 270 for (i = 0; i < num_vectors; i++) { 271 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 272 irq[i] = ath12k_pci_get_msi_irq(ab->dev, 273 msi_data++); 274 else 275 irq[i] = ath12k_pci_get_msi_irq(ab->dev, 276 msi_data); 277 } 278 279 ab_pci->mhi_ctrl->irq = irq; 280 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 281 282 return 0; 283 } 284 285 static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 286 { 287 return 0; 288 } 289 290 static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 291 { 292 } 293 294 static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason) 295 { 296 switch (reason) { 297 case MHI_CB_IDLE: 298 return "MHI_CB_IDLE"; 299 case MHI_CB_PENDING_DATA: 300 return "MHI_CB_PENDING_DATA"; 301 case MHI_CB_LPM_ENTER: 302 return "MHI_CB_LPM_ENTER"; 303 case MHI_CB_LPM_EXIT: 304 return "MHI_CB_LPM_EXIT"; 305 case MHI_CB_EE_RDDM: 306 return "MHI_CB_EE_RDDM"; 307 case MHI_CB_EE_MISSION_MODE: 308 return "MHI_CB_EE_MISSION_MODE"; 309 case MHI_CB_SYS_ERROR: 310 return "MHI_CB_SYS_ERROR"; 311 case MHI_CB_FATAL_ERROR: 312 return "MHI_CB_FATAL_ERROR"; 313 case MHI_CB_BW_REQ: 314 return "MHI_CB_BW_REQ"; 315 default: 316 return "UNKNOWN"; 317 } 318 } 319 320 static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 321 enum mhi_callback cb) 322 { 323 struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 324 325 ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n", 326 ath12k_mhi_op_callback_to_str(cb)); 327 328 switch (cb) { 329 case MHI_CB_SYS_ERROR: 330 ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 331 break; 332 case MHI_CB_EE_RDDM: 333 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) 334 queue_work(ab->workqueue_aux, &ab->reset_work); 335 break; 336 default: 337 break; 338 } 339 } 340 341 static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 342 void __iomem *addr, 343 u32 *out) 344 { 345 *out = readl(addr); 346 347 return 0; 348 } 349 350 static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 351 void __iomem *addr, 352 u32 val) 353 { 354 writel(val, addr); 355 } 356 357 int ath12k_mhi_register(struct ath12k_pci *ab_pci) 358 { 359 struct ath12k_base *ab = ab_pci->ab; 360 struct mhi_controller *mhi_ctrl; 361 int ret; 362 363 mhi_ctrl = mhi_alloc_controller(); 364 if (!mhi_ctrl) 365 return -ENOMEM; 366 367 ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE, 368 ab_pci->amss_path, 369 sizeof(ab_pci->amss_path)); 370 371 ab_pci->mhi_ctrl = mhi_ctrl; 372 mhi_ctrl->cntrl_dev = ab->dev; 373 mhi_ctrl->fw_image = ab_pci->amss_path; 374 mhi_ctrl->regs = ab->mem; 375 mhi_ctrl->reg_len = ab->mem_len; 376 mhi_ctrl->rddm_size = ab->hw_params->rddm_size; 377 378 ret = ath12k_mhi_get_msi(ab_pci); 379 if (ret) { 380 ath12k_err(ab, "failed to get msi for mhi\n"); 381 goto free_controller; 382 } 383 384 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 385 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 386 387 mhi_ctrl->iova_start = 0; 388 mhi_ctrl->iova_stop = 0xffffffff; 389 mhi_ctrl->sbl_size = SZ_512K; 390 mhi_ctrl->seg_len = SZ_512K; 391 mhi_ctrl->fbc_download = true; 392 mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get; 393 mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put; 394 mhi_ctrl->status_cb = ath12k_mhi_op_status_cb; 395 mhi_ctrl->read_reg = ath12k_mhi_op_read_reg; 396 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg; 397 398 ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config); 399 if (ret) { 400 ath12k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 401 goto free_controller; 402 } 403 404 return 0; 405 406 free_controller: 407 mhi_free_controller(mhi_ctrl); 408 ab_pci->mhi_ctrl = NULL; 409 return ret; 410 } 411 412 void ath12k_mhi_unregister(struct ath12k_pci *ab_pci) 413 { 414 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 415 416 mhi_unregister_controller(mhi_ctrl); 417 kfree(mhi_ctrl->irq); 418 mhi_free_controller(mhi_ctrl); 419 ab_pci->mhi_ctrl = NULL; 420 } 421 422 static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state) 423 { 424 switch (mhi_state) { 425 case ATH12K_MHI_INIT: 426 return "INIT"; 427 case ATH12K_MHI_DEINIT: 428 return "DEINIT"; 429 case ATH12K_MHI_POWER_ON: 430 return "POWER_ON"; 431 case ATH12K_MHI_POWER_OFF: 432 return "POWER_OFF"; 433 case ATH12K_MHI_FORCE_POWER_OFF: 434 return "FORCE_POWER_OFF"; 435 case ATH12K_MHI_SUSPEND: 436 return "SUSPEND"; 437 case ATH12K_MHI_RESUME: 438 return "RESUME"; 439 case ATH12K_MHI_TRIGGER_RDDM: 440 return "TRIGGER_RDDM"; 441 case ATH12K_MHI_RDDM_DONE: 442 return "RDDM_DONE"; 443 default: 444 return "UNKNOWN"; 445 } 446 }; 447 448 static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci, 449 enum ath12k_mhi_state mhi_state) 450 { 451 struct ath12k_base *ab = ab_pci->ab; 452 453 switch (mhi_state) { 454 case ATH12K_MHI_INIT: 455 set_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state); 456 break; 457 case ATH12K_MHI_DEINIT: 458 clear_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state); 459 break; 460 case ATH12K_MHI_POWER_ON: 461 set_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state); 462 break; 463 case ATH12K_MHI_POWER_OFF: 464 case ATH12K_MHI_FORCE_POWER_OFF: 465 clear_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state); 466 clear_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 467 clear_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state); 468 break; 469 case ATH12K_MHI_SUSPEND: 470 set_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state); 471 break; 472 case ATH12K_MHI_RESUME: 473 clear_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state); 474 break; 475 case ATH12K_MHI_TRIGGER_RDDM: 476 set_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 477 break; 478 case ATH12K_MHI_RDDM_DONE: 479 set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state); 480 break; 481 default: 482 ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 483 } 484 } 485 486 static int ath12k_mhi_check_state_bit(struct ath12k_pci *ab_pci, 487 enum ath12k_mhi_state mhi_state) 488 { 489 struct ath12k_base *ab = ab_pci->ab; 490 491 switch (mhi_state) { 492 case ATH12K_MHI_INIT: 493 if (!test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state)) 494 return 0; 495 break; 496 case ATH12K_MHI_DEINIT: 497 case ATH12K_MHI_POWER_ON: 498 if (test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state) && 499 !test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state)) 500 return 0; 501 break; 502 case ATH12K_MHI_FORCE_POWER_OFF: 503 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state)) 504 return 0; 505 break; 506 case ATH12K_MHI_POWER_OFF: 507 case ATH12K_MHI_SUSPEND: 508 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) && 509 !test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state)) 510 return 0; 511 break; 512 case ATH12K_MHI_RESUME: 513 if (test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state)) 514 return 0; 515 break; 516 case ATH12K_MHI_TRIGGER_RDDM: 517 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) && 518 !test_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 519 return 0; 520 break; 521 case ATH12K_MHI_RDDM_DONE: 522 return 0; 523 default: 524 ath12k_err(ab, "unhandled mhi state: %s(%d)\n", 525 ath12k_mhi_state_to_str(mhi_state), mhi_state); 526 } 527 528 ath12k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 529 ath12k_mhi_state_to_str(mhi_state), mhi_state, 530 ab_pci->mhi_state); 531 532 return -EINVAL; 533 } 534 535 static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci, 536 enum ath12k_mhi_state mhi_state) 537 { 538 struct ath12k_base *ab = ab_pci->ab; 539 int ret; 540 541 ret = ath12k_mhi_check_state_bit(ab_pci, mhi_state); 542 if (ret) 543 goto out; 544 545 ath12k_dbg(ab, ATH12K_DBG_PCI, "setting mhi state: %s(%d)\n", 546 ath12k_mhi_state_to_str(mhi_state), mhi_state); 547 548 switch (mhi_state) { 549 case ATH12K_MHI_INIT: 550 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 551 break; 552 case ATH12K_MHI_DEINIT: 553 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 554 ret = 0; 555 break; 556 case ATH12K_MHI_POWER_ON: 557 ret = mhi_async_power_up(ab_pci->mhi_ctrl); 558 break; 559 case ATH12K_MHI_POWER_OFF: 560 mhi_power_down(ab_pci->mhi_ctrl, true); 561 ret = 0; 562 break; 563 case ATH12K_MHI_FORCE_POWER_OFF: 564 mhi_power_down(ab_pci->mhi_ctrl, false); 565 ret = 0; 566 break; 567 case ATH12K_MHI_SUSPEND: 568 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 569 break; 570 case ATH12K_MHI_RESUME: 571 ret = mhi_pm_resume(ab_pci->mhi_ctrl); 572 break; 573 case ATH12K_MHI_TRIGGER_RDDM: 574 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 575 break; 576 case ATH12K_MHI_RDDM_DONE: 577 break; 578 default: 579 ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 580 ret = -EINVAL; 581 } 582 583 if (ret) 584 goto out; 585 586 ath12k_mhi_set_state_bit(ab_pci, mhi_state); 587 588 return 0; 589 590 out: 591 ath12k_err(ab, "failed to set mhi state: %s(%d)\n", 592 ath12k_mhi_state_to_str(mhi_state), mhi_state); 593 return ret; 594 } 595 596 int ath12k_mhi_start(struct ath12k_pci *ab_pci) 597 { 598 int ret; 599 600 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 601 602 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_INIT); 603 if (ret) 604 goto out; 605 606 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_ON); 607 if (ret) 608 goto out; 609 610 return 0; 611 612 out: 613 return ret; 614 } 615 616 void ath12k_mhi_stop(struct ath12k_pci *ab_pci) 617 { 618 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF); 619 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_DEINIT); 620 } 621 622 void ath12k_mhi_suspend(struct ath12k_pci *ab_pci) 623 { 624 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SUSPEND); 625 } 626 627 void ath12k_mhi_resume(struct ath12k_pci *ab_pci) 628 { 629 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME); 630 } 631