1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_HW_H 8 #define ATH12K_HW_H 9 10 #include <linux/mhi.h> 11 #include <linux/uuid.h> 12 13 #include "wmi.h" 14 #include "hal.h" 15 16 /* Target configuration defines */ 17 18 /* Num VDEVS per radio */ 19 #define TARGET_NUM_VDEVS(ab) ((ab)->profile_param->num_vdevs) 20 21 /* Max num of stations for Single Radio mode */ 22 #define TARGET_NUM_STATIONS_SINGLE(ab) ((ab)->profile_param->max_client_single) 23 24 /* Max num of stations for DBS */ 25 #define TARGET_NUM_STATIONS_DBS(ab) ((ab)->profile_param->max_client_dbs) 26 27 /* Max num of stations for DBS_SBS */ 28 #define TARGET_NUM_STATIONS_DBS_SBS(ab) \ 29 ((ab)->profile_param->max_client_dbs_sbs) 30 31 #define TARGET_NUM_STATIONS(ab, x) TARGET_NUM_STATIONS_##x(ab) 32 33 #define TARGET_NUM_PEER_KEYS 2 34 35 #define TARGET_AST_SKID_LIMIT 16 36 #define TARGET_NUM_OFFLD_PEERS 4 37 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 38 39 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 40 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 41 #define TARGET_RX_TIMEOUT_LO_PRI 100 42 #define TARGET_RX_TIMEOUT_HI_PRI 40 43 44 #define TARGET_DECAP_MODE_RAW 0 45 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 46 #define TARGET_DECAP_MODE_ETH 2 47 48 #define TARGET_SCAN_MAX_PENDING_REQS 4 49 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 50 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 51 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 52 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 53 #define TARGET_NUM_MCAST_GROUPS 12 54 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 55 #define TARGET_MCAST2UCAST_MODE 2 56 #define TARGET_TX_DBG_LOG_SIZE 1024 57 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 58 #define TARGET_VOW_CONFIG 0 59 #define TARGET_NUM_MSDU_DESC (2500) 60 #define TARGET_MAX_FRAG_ENTRIES 6 61 #define TARGET_MAX_BCN_OFFLD 16 62 #define TARGET_NUM_WDS_ENTRIES 32 63 #define TARGET_DMA_BURST_SIZE 1 64 #define TARGET_RX_BATCHMODE 1 65 #define TARGET_EMA_MAX_PROFILE_PERIOD 8 66 67 #define ATH12K_HW_DEFAULT_QUEUE 0 68 #define ATH12K_HW_MAX_QUEUES 4 69 #define ATH12K_QUEUE_LEN 4096 70 71 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 72 73 #define ATH12K_FW_DIR "ath12k" 74 75 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD" 76 #define ATH12K_BOARD_API2_FILE "board-2.bin" 77 #define ATH12K_DEFAULT_BOARD_FILE "board.bin" 78 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin" 79 #define ATH12K_AMSS_FILE "amss.bin" 80 #define ATH12K_M3_FILE "m3.bin" 81 #define ATH12K_REGDB_FILE_NAME "regdb.bin" 82 83 #define ATH12K_PCIE_MAX_PAYLOAD_SIZE 128 84 #define ATH12K_IPQ5332_USERPD_ID 1 85 86 enum ath12k_hw_rate_cck { 87 ATH12K_HW_RATE_CCK_LP_11M = 0, 88 ATH12K_HW_RATE_CCK_LP_5_5M, 89 ATH12K_HW_RATE_CCK_LP_2M, 90 ATH12K_HW_RATE_CCK_LP_1M, 91 ATH12K_HW_RATE_CCK_SP_11M, 92 ATH12K_HW_RATE_CCK_SP_5_5M, 93 ATH12K_HW_RATE_CCK_SP_2M, 94 }; 95 96 enum ath12k_hw_rate_ofdm { 97 ATH12K_HW_RATE_OFDM_48M = 0, 98 ATH12K_HW_RATE_OFDM_24M, 99 ATH12K_HW_RATE_OFDM_12M, 100 ATH12K_HW_RATE_OFDM_6M, 101 ATH12K_HW_RATE_OFDM_54M, 102 ATH12K_HW_RATE_OFDM_36M, 103 ATH12K_HW_RATE_OFDM_18M, 104 ATH12K_HW_RATE_OFDM_9M, 105 }; 106 107 enum ath12k_bus { 108 ATH12K_BUS_PCI, 109 ATH12K_BUS_AHB, 110 }; 111 112 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 113 114 struct hal_rx_desc; 115 struct hal_tcl_data_cmd; 116 struct htt_rx_ring_tlv_filter; 117 enum hal_encrypt_type; 118 119 struct ath12k_hw_ring_mask { 120 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 121 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 122 u8 rx_mon_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 123 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 124 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 125 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 126 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 127 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 128 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 129 }; 130 131 struct ath12k_hw_hal_params { 132 enum hal_rx_buf_return_buf_manager rx_buf_rbm; 133 u32 wbm2sw_cc_enable; 134 }; 135 136 enum ath12k_m3_fw_loaders { 137 ath12k_m3_fw_loader_driver, 138 ath12k_m3_fw_loader_remoteproc, 139 }; 140 141 struct ath12k_hw_params { 142 const char *name; 143 u16 hw_rev; 144 145 struct { 146 const char *dir; 147 size_t board_size; 148 size_t cal_offset; 149 enum ath12k_m3_fw_loaders m3_loader; 150 } fw; 151 152 u8 max_radios; 153 bool single_pdev_only:1; 154 u32 qmi_service_ins_id; 155 bool internal_sleep_clock:1; 156 157 const struct ath12k_hw_ops *hw_ops; 158 const struct ath12k_hw_ring_mask *ring_mask; 159 const struct ath12k_hw_regs *regs; 160 161 const struct ce_attr *host_ce_config; 162 u32 ce_count; 163 const struct ce_pipe_config *target_ce_config; 164 u32 target_ce_count; 165 const struct service_to_pipe *svc_to_ce_map; 166 u32 svc_to_ce_map_len; 167 168 const struct ath12k_hw_hal_params *hal_params; 169 170 bool rxdma1_enable:1; 171 int num_rxdma_per_pdev; 172 int num_rxdma_dst_ring; 173 bool rx_mac_buf_ring:1; 174 bool vdev_start_delay:1; 175 176 u16 interface_modes; 177 bool supports_monitor:1; 178 179 bool idle_ps:1; 180 bool download_calib:1; 181 bool supports_suspend:1; 182 bool tcl_ring_retry:1; 183 bool reoq_lut_support:1; 184 bool supports_shadow_regs:1; 185 bool supports_aspm:1; 186 bool current_cc_support:1; 187 188 u32 num_tcl_banks; 189 u32 max_tx_ring; 190 191 const struct mhi_controller_config *mhi_config; 192 193 void (*wmi_init)(struct ath12k_base *ab, 194 struct ath12k_wmi_resource_config_arg *config); 195 196 const struct hal_ops *hal_ops; 197 198 u64 qmi_cnss_feature_bitmap; 199 200 u32 rfkill_pin; 201 u32 rfkill_cfg; 202 u32 rfkill_on_level; 203 204 u32 rddm_size; 205 206 u8 def_num_link; 207 u16 max_mlo_peer; 208 209 u32 otp_board_id_register; 210 211 bool supports_sta_ps; 212 213 const guid_t *acpi_guid; 214 bool supports_dynamic_smps_6ghz; 215 216 u32 iova_mask; 217 218 const struct ce_ie_addr *ce_ie_addr; 219 const struct ce_remap *ce_remap; 220 u32 bdf_addr_offset; 221 222 /* setup REO queue, frag etc only for primary link peer */ 223 bool dp_primary_link_only:1; 224 }; 225 226 struct ath12k_hw_ops { 227 u8 (*get_hw_mac_from_pdev_id)(int pdev_id); 228 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id); 229 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id); 230 int (*rxdma_ring_sel_config)(struct ath12k_base *ab); 231 u8 (*get_ring_selector)(struct sk_buff *skb); 232 bool (*dp_srng_is_tx_comp_ring)(int ring_num); 233 bool (*is_frame_link_agnostic)(struct ath12k_link_vif *arvif, 234 struct ieee80211_mgmt *mgmt); 235 }; 236 237 static inline 238 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw, 239 int pdev_idx) 240 { 241 if (hw->hw_ops->get_hw_mac_from_pdev_id) 242 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx); 243 244 return 0; 245 } 246 247 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw, 248 int mac_id) 249 { 250 if (hw->hw_ops->mac_id_to_pdev_id) 251 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id); 252 253 return 0; 254 } 255 256 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw, 257 int mac_id) 258 { 259 if (hw->hw_ops->mac_id_to_srng_id) 260 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id); 261 262 return 0; 263 } 264 265 struct ath12k_fw_ie { 266 __le32 id; 267 __le32 len; 268 u8 data[]; 269 }; 270 271 enum ath12k_bd_ie_board_type { 272 ATH12K_BD_IE_BOARD_NAME = 0, 273 ATH12K_BD_IE_BOARD_DATA = 1, 274 }; 275 276 enum ath12k_bd_ie_regdb_type { 277 ATH12K_BD_IE_REGDB_NAME = 0, 278 ATH12K_BD_IE_REGDB_DATA = 1, 279 }; 280 281 enum ath12k_bd_ie_type { 282 /* contains sub IEs of enum ath12k_bd_ie_board_type */ 283 ATH12K_BD_IE_BOARD = 0, 284 /* contains sub IEs of enum ath12k_bd_ie_regdb_type */ 285 ATH12K_BD_IE_REGDB = 1, 286 }; 287 288 struct ath12k_hw_regs { 289 u32 hal_tcl1_ring_id; 290 u32 hal_tcl1_ring_misc; 291 u32 hal_tcl1_ring_tp_addr_lsb; 292 u32 hal_tcl1_ring_tp_addr_msb; 293 u32 hal_tcl1_ring_consumer_int_setup_ix0; 294 u32 hal_tcl1_ring_consumer_int_setup_ix1; 295 u32 hal_tcl1_ring_msi1_base_lsb; 296 u32 hal_tcl1_ring_msi1_base_msb; 297 u32 hal_tcl1_ring_msi1_data; 298 u32 hal_tcl_ring_base_lsb; 299 u32 hal_tcl1_ring_base_lsb; 300 u32 hal_tcl1_ring_base_msb; 301 u32 hal_tcl2_ring_base_lsb; 302 303 u32 hal_tcl_status_ring_base_lsb; 304 305 u32 hal_reo1_qdesc_addr; 306 u32 hal_reo1_qdesc_max_peerid; 307 308 u32 hal_wbm_idle_ring_base_lsb; 309 u32 hal_wbm_idle_ring_misc_addr; 310 u32 hal_wbm_r0_idle_list_cntl_addr; 311 u32 hal_wbm_r0_idle_list_size_addr; 312 u32 hal_wbm_scattered_ring_base_lsb; 313 u32 hal_wbm_scattered_ring_base_msb; 314 u32 hal_wbm_scattered_desc_head_info_ix0; 315 u32 hal_wbm_scattered_desc_head_info_ix1; 316 u32 hal_wbm_scattered_desc_tail_info_ix0; 317 u32 hal_wbm_scattered_desc_tail_info_ix1; 318 u32 hal_wbm_scattered_desc_ptr_hp_addr; 319 320 u32 hal_wbm_sw_release_ring_base_lsb; 321 u32 hal_wbm_sw1_release_ring_base_lsb; 322 u32 hal_wbm0_release_ring_base_lsb; 323 u32 hal_wbm1_release_ring_base_lsb; 324 325 u32 pcie_qserdes_sysclk_en_sel; 326 u32 pcie_pcs_osc_dtct_config_base; 327 328 u32 hal_umac_ce0_src_reg_base; 329 u32 hal_umac_ce0_dest_reg_base; 330 u32 hal_umac_ce1_src_reg_base; 331 u32 hal_umac_ce1_dest_reg_base; 332 333 u32 hal_ppe_rel_ring_base; 334 335 u32 hal_reo2_ring_base; 336 u32 hal_reo1_misc_ctrl_addr; 337 u32 hal_reo1_sw_cookie_cfg0; 338 u32 hal_reo1_sw_cookie_cfg1; 339 u32 hal_reo1_qdesc_lut_base0; 340 u32 hal_reo1_qdesc_lut_base1; 341 u32 hal_reo1_ring_base_lsb; 342 u32 hal_reo1_ring_base_msb; 343 u32 hal_reo1_ring_id; 344 u32 hal_reo1_ring_misc; 345 u32 hal_reo1_ring_hp_addr_lsb; 346 u32 hal_reo1_ring_hp_addr_msb; 347 u32 hal_reo1_ring_producer_int_setup; 348 u32 hal_reo1_ring_msi1_base_lsb; 349 u32 hal_reo1_ring_msi1_base_msb; 350 u32 hal_reo1_ring_msi1_data; 351 u32 hal_reo1_aging_thres_ix0; 352 u32 hal_reo1_aging_thres_ix1; 353 u32 hal_reo1_aging_thres_ix2; 354 u32 hal_reo1_aging_thres_ix3; 355 356 u32 hal_reo2_sw0_ring_base; 357 358 u32 hal_sw2reo_ring_base; 359 u32 hal_sw2reo1_ring_base; 360 361 u32 hal_reo_cmd_ring_base; 362 363 u32 hal_reo_status_ring_base; 364 365 u32 gcc_gcc_pcie_hot_rst; 366 }; 367 368 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type) 369 { 370 switch (type) { 371 case ATH12K_BD_IE_BOARD: 372 return "board data"; 373 case ATH12K_BD_IE_REGDB: 374 return "regdb data"; 375 } 376 377 return "unknown"; 378 } 379 380 int ath12k_hw_init(struct ath12k_base *ab); 381 382 #endif 383