1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_HW_H 8 #define ATH12K_HW_H 9 10 #include <linux/mhi.h> 11 #include <linux/uuid.h> 12 13 #include "wmi.h" 14 #include "hal.h" 15 16 struct ath12k_dp_peer; 17 struct ath12k_skb_rxcb; 18 struct ieee80211_rx_status; 19 20 /* Target configuration defines */ 21 22 /* Num VDEVS per radio */ 23 #define TARGET_NUM_VDEVS(ab) ((ab)->profile_param->num_vdevs) 24 25 /* Max num of stations for Single Radio mode */ 26 #define TARGET_NUM_STATIONS_SINGLE(ab) \ 27 ({ \ 28 typeof(ab) _ab = (ab); \ 29 min_not_zero(_ab->hw_params->client.max_client_single, \ 30 _ab->profile_param->max_client_single); \ 31 }) 32 33 /* Max num of stations for DBS */ 34 #define TARGET_NUM_STATIONS_DBS(ab) \ 35 ({ \ 36 typeof(ab) _ab = (ab); \ 37 min_not_zero(_ab->hw_params->client.max_client_dbs, \ 38 _ab->profile_param->max_client_dbs); \ 39 }) 40 41 /* Max num of stations for DBS_SBS */ 42 #define TARGET_NUM_STATIONS_DBS_SBS(ab) \ 43 ({ \ 44 typeof(ab) _ab = (ab); \ 45 min_not_zero(_ab->hw_params->client.max_client_dbs_sbs, \ 46 _ab->profile_param->max_client_dbs_sbs); \ 47 }) 48 49 #define TARGET_NUM_STATIONS(ab, x) TARGET_NUM_STATIONS_##x(ab) 50 51 #define TARGET_NUM_PEER_KEYS 2 52 53 #define TARGET_AST_SKID_LIMIT 16 54 #define TARGET_NUM_OFFLD_PEERS 4 55 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 56 57 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 58 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 59 #define TARGET_RX_TIMEOUT_LO_PRI 100 60 #define TARGET_RX_TIMEOUT_HI_PRI 40 61 62 #define TARGET_DECAP_MODE_RAW 0 63 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 64 #define TARGET_DECAP_MODE_ETH 2 65 66 #define TARGET_SCAN_MAX_PENDING_REQS 4 67 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 68 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 69 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 70 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 71 #define TARGET_NUM_MCAST_GROUPS 12 72 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 73 #define TARGET_MCAST2UCAST_MODE 2 74 #define TARGET_TX_DBG_LOG_SIZE 1024 75 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 76 #define TARGET_VOW_CONFIG 0 77 #define TARGET_NUM_MSDU_DESC (2500) 78 #define TARGET_MAX_FRAG_ENTRIES 6 79 #define TARGET_MAX_BCN_OFFLD 16 80 #define TARGET_NUM_WDS_ENTRIES 32 81 #define TARGET_DMA_BURST_SIZE 1 82 #define TARGET_RX_BATCHMODE 1 83 #define TARGET_EMA_MAX_PROFILE_PERIOD 8 84 85 #define ATH12K_HW_DEFAULT_QUEUE 0 86 #define ATH12K_HW_MAX_QUEUES 4 87 #define ATH12K_QUEUE_LEN 4096 88 89 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 90 91 #define ATH12K_FW_DIR "ath12k" 92 93 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD" 94 #define ATH12K_BOARD_API2_FILE "board-2.bin" 95 #define ATH12K_DEFAULT_BOARD_FILE "board.bin" 96 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin" 97 #define ATH12K_AMSS_FILE "amss.bin" 98 #define ATH12K_M3_FILE "m3.bin" 99 #define ATH12K_AUX_UC_FILE "aux_ucode.bin" 100 #define ATH12K_REGDB_FILE_NAME "regdb.bin" 101 102 #define ATH12K_PCIE_MAX_PAYLOAD_SIZE 128 103 104 enum ath12k_hw_rate_cck { 105 ATH12K_HW_RATE_CCK_LP_11M = 0, 106 ATH12K_HW_RATE_CCK_LP_5_5M, 107 ATH12K_HW_RATE_CCK_LP_2M, 108 ATH12K_HW_RATE_CCK_LP_1M, 109 ATH12K_HW_RATE_CCK_SP_11M, 110 ATH12K_HW_RATE_CCK_SP_5_5M, 111 ATH12K_HW_RATE_CCK_SP_2M, 112 }; 113 114 enum ath12k_hw_rate_ofdm { 115 ATH12K_HW_RATE_OFDM_48M = 0, 116 ATH12K_HW_RATE_OFDM_24M, 117 ATH12K_HW_RATE_OFDM_12M, 118 ATH12K_HW_RATE_OFDM_6M, 119 ATH12K_HW_RATE_OFDM_54M, 120 ATH12K_HW_RATE_OFDM_36M, 121 ATH12K_HW_RATE_OFDM_18M, 122 ATH12K_HW_RATE_OFDM_9M, 123 }; 124 125 enum ath12k_bus { 126 ATH12K_BUS_PCI, 127 ATH12K_BUS_AHB, 128 }; 129 130 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 131 132 struct hal_rx_desc; 133 struct hal_tcl_data_cmd; 134 struct htt_rx_ring_tlv_filter; 135 enum hal_encrypt_type; 136 137 struct ath12k_hw_ring_mask { 138 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 139 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 140 u8 rx_mon_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 141 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 142 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 143 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 144 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 145 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 146 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 147 }; 148 149 enum ath12k_m3_fw_loaders { 150 ath12k_m3_fw_loader_driver, 151 ath12k_m3_fw_loader_remoteproc, 152 }; 153 154 struct ath12k_hw_params { 155 const char *name; 156 u16 hw_rev; 157 158 struct { 159 const char *dir; 160 size_t board_size; 161 size_t cal_offset; 162 enum ath12k_m3_fw_loaders m3_loader; 163 bool download_aux_ucode:1; 164 } fw; 165 166 u8 max_radios; 167 bool single_pdev_only:1; 168 u32 qmi_service_ins_id; 169 bool internal_sleep_clock:1; 170 171 const struct ath12k_hw_ops *hw_ops; 172 const struct ath12k_hw_ring_mask *ring_mask; 173 174 const struct ce_attr *host_ce_config; 175 u32 ce_count; 176 const struct ce_pipe_config *target_ce_config; 177 u32 target_ce_count; 178 const struct service_to_pipe *svc_to_ce_map; 179 u32 svc_to_ce_map_len; 180 181 bool rxdma1_enable:1; 182 int num_rxdma_per_pdev; 183 int num_rxdma_dst_ring; 184 bool rx_mac_buf_ring:1; 185 bool vdev_start_delay:1; 186 187 u16 interface_modes; 188 bool supports_monitor:1; 189 190 bool idle_ps:1; 191 bool download_calib:1; 192 bool supports_suspend:1; 193 bool tcl_ring_retry:1; 194 bool reoq_lut_support:1; 195 bool supports_shadow_regs:1; 196 bool supports_aspm:1; 197 bool current_cc_support:1; 198 bool supports_cong_ctrl_max_msdus:1; 199 200 u32 num_tcl_banks; 201 u32 max_tx_ring; 202 203 const struct mhi_controller_config *mhi_config; 204 205 void (*wmi_init)(struct ath12k_base *ab, 206 struct ath12k_wmi_resource_config_arg *config); 207 208 u64 qmi_cnss_feature_bitmap; 209 210 u32 rfkill_pin; 211 u32 rfkill_cfg; 212 u32 rfkill_on_level; 213 214 u32 rddm_size; 215 216 u8 def_num_link; 217 u16 max_mlo_peer; 218 219 u32 otp_board_id_register; 220 221 bool supports_sta_ps; 222 223 const guid_t *acpi_guid; 224 bool supports_dynamic_smps_6ghz; 225 226 u32 iova_mask; 227 228 const struct ce_ie_addr *ce_ie_addr; 229 const struct ce_remap *ce_remap; 230 u32 bdf_addr_offset; 231 232 /* setup REO queue, frag etc only for primary link peer */ 233 bool dp_primary_link_only:1; 234 struct { 235 u32 max_client_single; 236 u32 max_client_dbs; 237 u32 max_client_dbs_sbs; 238 } client; 239 240 bool host_alloc_ml_id; 241 }; 242 243 struct ath12k_hw_ops { 244 u8 (*get_hw_mac_from_pdev_id)(int pdev_id); 245 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id); 246 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id); 247 int (*rxdma_ring_sel_config)(struct ath12k_base *ab); 248 u8 (*get_ring_selector)(struct sk_buff *skb); 249 bool (*dp_srng_is_tx_comp_ring)(int ring_num); 250 bool (*is_frame_link_agnostic)(struct ath12k_link_vif *arvif, 251 struct ieee80211_mgmt *mgmt); 252 void (*set_rx_link_id)(struct ath12k_dp_peer *dp_peer, 253 struct ath12k_skb_rxcb *rxcb, 254 struct ieee80211_rx_status *status); 255 }; 256 257 static inline 258 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw, 259 int pdev_idx) 260 { 261 if (hw->hw_ops->get_hw_mac_from_pdev_id) 262 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx); 263 264 return 0; 265 } 266 267 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw, 268 int mac_id) 269 { 270 if (hw->hw_ops->mac_id_to_pdev_id) 271 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id); 272 273 return 0; 274 } 275 276 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw, 277 int mac_id) 278 { 279 if (hw->hw_ops->mac_id_to_srng_id) 280 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id); 281 282 return 0; 283 } 284 285 static inline void ath12k_hw_set_rx_link_id(const struct ath12k_hw_params *hw, 286 struct ath12k_dp_peer *dp_peer, 287 struct ath12k_skb_rxcb *rxcb, 288 struct ieee80211_rx_status *status) 289 { 290 if (hw->hw_ops->set_rx_link_id) 291 hw->hw_ops->set_rx_link_id(dp_peer, rxcb, status); 292 } 293 294 struct ath12k_fw_ie { 295 __le32 id; 296 __le32 len; 297 u8 data[]; 298 }; 299 300 enum ath12k_bd_ie_board_type { 301 ATH12K_BD_IE_BOARD_NAME = 0, 302 ATH12K_BD_IE_BOARD_DATA = 1, 303 }; 304 305 enum ath12k_bd_ie_regdb_type { 306 ATH12K_BD_IE_REGDB_NAME = 0, 307 ATH12K_BD_IE_REGDB_DATA = 1, 308 }; 309 310 enum ath12k_bd_ie_type { 311 /* contains sub IEs of enum ath12k_bd_ie_board_type */ 312 ATH12K_BD_IE_BOARD = 0, 313 /* contains sub IEs of enum ath12k_bd_ie_regdb_type */ 314 ATH12K_BD_IE_REGDB = 1, 315 }; 316 317 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type) 318 { 319 switch (type) { 320 case ATH12K_BD_IE_BOARD: 321 return "board data"; 322 case ATH12K_BD_IE_REGDB: 323 return "regdb data"; 324 } 325 326 return "unknown"; 327 } 328 329 #endif 330