1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_HW_H 8 #define ATH12K_HW_H 9 10 #include <linux/mhi.h> 11 #include <linux/uuid.h> 12 13 #include "wmi.h" 14 #include "hal.h" 15 16 /* Target configuration defines */ 17 18 /* Num VDEVS per radio */ 19 #define TARGET_NUM_VDEVS (16 + 1) 20 21 #define TARGET_NUM_PEERS_PDEV_SINGLE (TARGET_NUM_STATIONS_SINGLE + \ 22 TARGET_NUM_VDEVS) 23 #define TARGET_NUM_PEERS_PDEV_DBS (TARGET_NUM_STATIONS_DBS + \ 24 TARGET_NUM_VDEVS) 25 #define TARGET_NUM_PEERS_PDEV_DBS_SBS (TARGET_NUM_STATIONS_DBS_SBS + \ 26 TARGET_NUM_VDEVS) 27 28 /* Num of peers for Single Radio mode */ 29 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV_SINGLE) 30 31 /* Num of peers for DBS */ 32 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV_DBS) 33 34 /* Num of peers for DBS_SBS */ 35 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV_DBS_SBS) 36 37 /* Max num of stations for Single Radio mode */ 38 #define TARGET_NUM_STATIONS_SINGLE 512 39 40 /* Max num of stations for DBS */ 41 #define TARGET_NUM_STATIONS_DBS 128 42 43 /* Max num of stations for DBS_SBS */ 44 #define TARGET_NUM_STATIONS_DBS_SBS 128 45 46 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x 47 #define TARGET_NUM_PEER_KEYS 2 48 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \ 49 4 * TARGET_NUM_VDEVS + 8) 50 51 #define TARGET_AST_SKID_LIMIT 16 52 #define TARGET_NUM_OFFLD_PEERS 4 53 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 54 55 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 56 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 57 #define TARGET_RX_TIMEOUT_LO_PRI 100 58 #define TARGET_RX_TIMEOUT_HI_PRI 40 59 60 #define TARGET_DECAP_MODE_RAW 0 61 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 62 #define TARGET_DECAP_MODE_ETH 2 63 64 #define TARGET_SCAN_MAX_PENDING_REQS 4 65 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 66 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 67 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 68 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 69 #define TARGET_NUM_MCAST_GROUPS 12 70 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 71 #define TARGET_MCAST2UCAST_MODE 2 72 #define TARGET_TX_DBG_LOG_SIZE 1024 73 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 74 #define TARGET_VOW_CONFIG 0 75 #define TARGET_NUM_MSDU_DESC (2500) 76 #define TARGET_MAX_FRAG_ENTRIES 6 77 #define TARGET_MAX_BCN_OFFLD 16 78 #define TARGET_NUM_WDS_ENTRIES 32 79 #define TARGET_DMA_BURST_SIZE 1 80 #define TARGET_RX_BATCHMODE 1 81 #define TARGET_RX_PEER_METADATA_VER_V1A 2 82 #define TARGET_RX_PEER_METADATA_VER_V1B 3 83 84 #define ATH12K_HW_DEFAULT_QUEUE 0 85 #define ATH12K_HW_MAX_QUEUES 4 86 #define ATH12K_QUEUE_LEN 4096 87 88 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 89 90 #define ATH12K_FW_DIR "ath12k" 91 92 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD" 93 #define ATH12K_BOARD_API2_FILE "board-2.bin" 94 #define ATH12K_DEFAULT_BOARD_FILE "board.bin" 95 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin" 96 #define ATH12K_AMSS_FILE "amss.bin" 97 #define ATH12K_M3_FILE "m3.bin" 98 #define ATH12K_REGDB_FILE_NAME "regdb.bin" 99 100 enum ath12k_hw_rate_cck { 101 ATH12K_HW_RATE_CCK_LP_11M = 0, 102 ATH12K_HW_RATE_CCK_LP_5_5M, 103 ATH12K_HW_RATE_CCK_LP_2M, 104 ATH12K_HW_RATE_CCK_LP_1M, 105 ATH12K_HW_RATE_CCK_SP_11M, 106 ATH12K_HW_RATE_CCK_SP_5_5M, 107 ATH12K_HW_RATE_CCK_SP_2M, 108 }; 109 110 enum ath12k_hw_rate_ofdm { 111 ATH12K_HW_RATE_OFDM_48M = 0, 112 ATH12K_HW_RATE_OFDM_24M, 113 ATH12K_HW_RATE_OFDM_12M, 114 ATH12K_HW_RATE_OFDM_6M, 115 ATH12K_HW_RATE_OFDM_54M, 116 ATH12K_HW_RATE_OFDM_36M, 117 ATH12K_HW_RATE_OFDM_18M, 118 ATH12K_HW_RATE_OFDM_9M, 119 }; 120 121 enum ath12k_bus { 122 ATH12K_BUS_PCI, 123 }; 124 125 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 126 127 struct hal_rx_desc; 128 struct hal_tcl_data_cmd; 129 struct htt_rx_ring_tlv_filter; 130 enum hal_encrypt_type; 131 132 struct ath12k_hw_ring_mask { 133 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 134 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 135 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 136 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 137 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 138 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 139 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 140 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 141 }; 142 143 struct ath12k_hw_hal_params { 144 enum hal_rx_buf_return_buf_manager rx_buf_rbm; 145 u32 wbm2sw_cc_enable; 146 }; 147 148 struct ath12k_hw_params { 149 const char *name; 150 u16 hw_rev; 151 152 struct { 153 const char *dir; 154 size_t board_size; 155 size_t cal_offset; 156 } fw; 157 158 u8 max_radios; 159 bool single_pdev_only:1; 160 u32 qmi_service_ins_id; 161 bool internal_sleep_clock:1; 162 163 const struct ath12k_hw_ops *hw_ops; 164 const struct ath12k_hw_ring_mask *ring_mask; 165 const struct ath12k_hw_regs *regs; 166 167 const struct ce_attr *host_ce_config; 168 u32 ce_count; 169 const struct ce_pipe_config *target_ce_config; 170 u32 target_ce_count; 171 const struct service_to_pipe *svc_to_ce_map; 172 u32 svc_to_ce_map_len; 173 174 const struct ath12k_hw_hal_params *hal_params; 175 176 bool rxdma1_enable:1; 177 int num_rxmda_per_pdev; 178 int num_rxdma_dst_ring; 179 bool rx_mac_buf_ring:1; 180 bool vdev_start_delay:1; 181 182 u16 interface_modes; 183 bool supports_monitor:1; 184 185 bool idle_ps:1; 186 bool download_calib:1; 187 bool supports_suspend:1; 188 bool tcl_ring_retry:1; 189 bool reoq_lut_support:1; 190 bool supports_shadow_regs:1; 191 192 u32 num_tcl_banks; 193 u32 max_tx_ring; 194 195 const struct mhi_controller_config *mhi_config; 196 197 void (*wmi_init)(struct ath12k_base *ab, 198 struct ath12k_wmi_resource_config_arg *config); 199 200 const struct hal_ops *hal_ops; 201 202 u64 qmi_cnss_feature_bitmap; 203 204 u32 rfkill_pin; 205 u32 rfkill_cfg; 206 u32 rfkill_on_level; 207 208 u32 rddm_size; 209 210 u8 def_num_link; 211 u16 max_mlo_peer; 212 213 u32 otp_board_id_register; 214 215 bool supports_sta_ps; 216 217 const guid_t *acpi_guid; 218 }; 219 220 struct ath12k_hw_ops { 221 u8 (*get_hw_mac_from_pdev_id)(int pdev_id); 222 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id); 223 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id); 224 int (*rxdma_ring_sel_config)(struct ath12k_base *ab); 225 u8 (*get_ring_selector)(struct sk_buff *skb); 226 bool (*dp_srng_is_tx_comp_ring)(int ring_num); 227 }; 228 229 static inline 230 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw, 231 int pdev_idx) 232 { 233 if (hw->hw_ops->get_hw_mac_from_pdev_id) 234 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx); 235 236 return 0; 237 } 238 239 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw, 240 int mac_id) 241 { 242 if (hw->hw_ops->mac_id_to_pdev_id) 243 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id); 244 245 return 0; 246 } 247 248 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw, 249 int mac_id) 250 { 251 if (hw->hw_ops->mac_id_to_srng_id) 252 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id); 253 254 return 0; 255 } 256 257 struct ath12k_fw_ie { 258 __le32 id; 259 __le32 len; 260 u8 data[]; 261 }; 262 263 enum ath12k_bd_ie_board_type { 264 ATH12K_BD_IE_BOARD_NAME = 0, 265 ATH12K_BD_IE_BOARD_DATA = 1, 266 }; 267 268 enum ath12k_bd_ie_regdb_type { 269 ATH12K_BD_IE_REGDB_NAME = 0, 270 ATH12K_BD_IE_REGDB_DATA = 1, 271 }; 272 273 enum ath12k_bd_ie_type { 274 /* contains sub IEs of enum ath12k_bd_ie_board_type */ 275 ATH12K_BD_IE_BOARD = 0, 276 /* contains sub IEs of enum ath12k_bd_ie_regdb_type */ 277 ATH12K_BD_IE_REGDB = 1, 278 }; 279 280 struct ath12k_hw_regs { 281 u32 hal_tcl1_ring_id; 282 u32 hal_tcl1_ring_misc; 283 u32 hal_tcl1_ring_tp_addr_lsb; 284 u32 hal_tcl1_ring_tp_addr_msb; 285 u32 hal_tcl1_ring_consumer_int_setup_ix0; 286 u32 hal_tcl1_ring_consumer_int_setup_ix1; 287 u32 hal_tcl1_ring_msi1_base_lsb; 288 u32 hal_tcl1_ring_msi1_base_msb; 289 u32 hal_tcl1_ring_msi1_data; 290 u32 hal_tcl_ring_base_lsb; 291 292 u32 hal_tcl_status_ring_base_lsb; 293 294 u32 hal_wbm_idle_ring_base_lsb; 295 u32 hal_wbm_idle_ring_misc_addr; 296 u32 hal_wbm_r0_idle_list_cntl_addr; 297 u32 hal_wbm_r0_idle_list_size_addr; 298 u32 hal_wbm_scattered_ring_base_lsb; 299 u32 hal_wbm_scattered_ring_base_msb; 300 u32 hal_wbm_scattered_desc_head_info_ix0; 301 u32 hal_wbm_scattered_desc_head_info_ix1; 302 u32 hal_wbm_scattered_desc_tail_info_ix0; 303 u32 hal_wbm_scattered_desc_tail_info_ix1; 304 u32 hal_wbm_scattered_desc_ptr_hp_addr; 305 306 u32 hal_wbm_sw_release_ring_base_lsb; 307 u32 hal_wbm_sw1_release_ring_base_lsb; 308 u32 hal_wbm0_release_ring_base_lsb; 309 u32 hal_wbm1_release_ring_base_lsb; 310 311 u32 pcie_qserdes_sysclk_en_sel; 312 u32 pcie_pcs_osc_dtct_config_base; 313 314 u32 hal_ppe_rel_ring_base; 315 316 u32 hal_reo2_ring_base; 317 u32 hal_reo1_misc_ctrl_addr; 318 u32 hal_reo1_sw_cookie_cfg0; 319 u32 hal_reo1_sw_cookie_cfg1; 320 u32 hal_reo1_qdesc_lut_base0; 321 u32 hal_reo1_qdesc_lut_base1; 322 u32 hal_reo1_ring_base_lsb; 323 u32 hal_reo1_ring_base_msb; 324 u32 hal_reo1_ring_id; 325 u32 hal_reo1_ring_misc; 326 u32 hal_reo1_ring_hp_addr_lsb; 327 u32 hal_reo1_ring_hp_addr_msb; 328 u32 hal_reo1_ring_producer_int_setup; 329 u32 hal_reo1_ring_msi1_base_lsb; 330 u32 hal_reo1_ring_msi1_base_msb; 331 u32 hal_reo1_ring_msi1_data; 332 u32 hal_reo1_aging_thres_ix0; 333 u32 hal_reo1_aging_thres_ix1; 334 u32 hal_reo1_aging_thres_ix2; 335 u32 hal_reo1_aging_thres_ix3; 336 337 u32 hal_reo2_sw0_ring_base; 338 339 u32 hal_sw2reo_ring_base; 340 u32 hal_sw2reo1_ring_base; 341 342 u32 hal_reo_cmd_ring_base; 343 344 u32 hal_reo_status_ring_base; 345 }; 346 347 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type) 348 { 349 switch (type) { 350 case ATH12K_BD_IE_BOARD: 351 return "board data"; 352 case ATH12K_BD_IE_REGDB: 353 return "regdb data"; 354 } 355 356 return "unknown"; 357 } 358 359 int ath12k_hw_init(struct ath12k_base *ab); 360 361 #endif 362