1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 11 #include "debug.h" 12 #include "core.h" 13 #include "ce.h" 14 #include "hw.h" 15 #include "mhi.h" 16 #include "dp_rx.h" 17 18 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec, 19 0x90, 0xd6, 0x02, 0x42, 20 0xac, 0x12, 0x00, 0x03); 21 22 static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx) 23 { 24 return pdev_idx; 25 } 26 27 static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw, 28 int mac_id) 29 { 30 return mac_id; 31 } 32 33 static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw, 34 int mac_id) 35 { 36 return 0; 37 } 38 39 static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb) 40 { 41 return smp_processor_id(); 42 } 43 44 static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num) 45 { 46 if (ring_num < 3 || ring_num == 4) 47 return true; 48 49 return false; 50 } 51 52 static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw, 53 int mac_id) 54 { 55 return 0; 56 } 57 58 static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw, 59 int mac_id) 60 { 61 return mac_id; 62 } 63 64 static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb) 65 { 66 return skb_get_queue_mapping(skb); 67 } 68 69 static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num) 70 { 71 if (ring_num == 0 || ring_num == 2 || ring_num == 4) 72 return true; 73 74 return false; 75 } 76 77 static const struct ath12k_hw_ops qcn9274_ops = { 78 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 79 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274, 80 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274, 81 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274, 82 .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274, 83 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274, 84 }; 85 86 static const struct ath12k_hw_ops wcn7850_ops = { 87 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 88 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850, 89 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850, 90 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850, 91 .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850, 92 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850, 93 }; 94 95 #define ATH12K_TX_RING_MASK_0 0x1 96 #define ATH12K_TX_RING_MASK_1 0x2 97 #define ATH12K_TX_RING_MASK_2 0x4 98 #define ATH12K_TX_RING_MASK_3 0x8 99 #define ATH12K_TX_RING_MASK_4 0x10 100 101 #define ATH12K_RX_RING_MASK_0 0x1 102 #define ATH12K_RX_RING_MASK_1 0x2 103 #define ATH12K_RX_RING_MASK_2 0x4 104 #define ATH12K_RX_RING_MASK_3 0x8 105 106 #define ATH12K_RX_ERR_RING_MASK_0 0x1 107 108 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1 109 110 #define ATH12K_REO_STATUS_RING_MASK_0 0x1 111 112 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1 113 114 #define ATH12K_RX_MON_RING_MASK_0 0x1 115 #define ATH12K_RX_MON_RING_MASK_1 0x2 116 #define ATH12K_RX_MON_RING_MASK_2 0x4 117 118 #define ATH12K_TX_MON_RING_MASK_0 0x1 119 #define ATH12K_TX_MON_RING_MASK_1 0x2 120 121 /* Target firmware's Copy Engine configuration. */ 122 static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = { 123 /* CE0: host->target HTC control and raw streams */ 124 { 125 .pipenum = __cpu_to_le32(0), 126 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 127 .nentries = __cpu_to_le32(32), 128 .nbytes_max = __cpu_to_le32(2048), 129 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 130 .reserved = __cpu_to_le32(0), 131 }, 132 133 /* CE1: target->host HTT + HTC control */ 134 { 135 .pipenum = __cpu_to_le32(1), 136 .pipedir = __cpu_to_le32(PIPEDIR_IN), 137 .nentries = __cpu_to_le32(32), 138 .nbytes_max = __cpu_to_le32(2048), 139 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 140 .reserved = __cpu_to_le32(0), 141 }, 142 143 /* CE2: target->host WMI */ 144 { 145 .pipenum = __cpu_to_le32(2), 146 .pipedir = __cpu_to_le32(PIPEDIR_IN), 147 .nentries = __cpu_to_le32(32), 148 .nbytes_max = __cpu_to_le32(2048), 149 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 150 .reserved = __cpu_to_le32(0), 151 }, 152 153 /* CE3: host->target WMI (mac0) */ 154 { 155 .pipenum = __cpu_to_le32(3), 156 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 157 .nentries = __cpu_to_le32(32), 158 .nbytes_max = __cpu_to_le32(2048), 159 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 160 .reserved = __cpu_to_le32(0), 161 }, 162 163 /* CE4: host->target HTT */ 164 { 165 .pipenum = __cpu_to_le32(4), 166 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 167 .nentries = __cpu_to_le32(256), 168 .nbytes_max = __cpu_to_le32(256), 169 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 170 .reserved = __cpu_to_le32(0), 171 }, 172 173 /* CE5: target->host Pktlog */ 174 { 175 .pipenum = __cpu_to_le32(5), 176 .pipedir = __cpu_to_le32(PIPEDIR_IN), 177 .nentries = __cpu_to_le32(32), 178 .nbytes_max = __cpu_to_le32(2048), 179 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 180 .reserved = __cpu_to_le32(0), 181 }, 182 183 /* CE6: Reserved for target autonomous hif_memcpy */ 184 { 185 .pipenum = __cpu_to_le32(6), 186 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 187 .nentries = __cpu_to_le32(32), 188 .nbytes_max = __cpu_to_le32(16384), 189 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 190 .reserved = __cpu_to_le32(0), 191 }, 192 193 /* CE7: host->target WMI (mac1) */ 194 { 195 .pipenum = __cpu_to_le32(7), 196 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 197 .nentries = __cpu_to_le32(32), 198 .nbytes_max = __cpu_to_le32(2048), 199 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 200 .reserved = __cpu_to_le32(0), 201 }, 202 203 /* CE8: Reserved for target autonomous hif_memcpy */ 204 { 205 .pipenum = __cpu_to_le32(8), 206 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 207 .nentries = __cpu_to_le32(32), 208 .nbytes_max = __cpu_to_le32(16384), 209 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 210 .reserved = __cpu_to_le32(0), 211 }, 212 213 /* CE9, 10 and 11: Reserved for MHI */ 214 215 /* CE12: Target CV prefetch */ 216 { 217 .pipenum = __cpu_to_le32(12), 218 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 219 .nentries = __cpu_to_le32(32), 220 .nbytes_max = __cpu_to_le32(2048), 221 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 222 .reserved = __cpu_to_le32(0), 223 }, 224 225 /* CE13: Target CV prefetch */ 226 { 227 .pipenum = __cpu_to_le32(13), 228 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 229 .nentries = __cpu_to_le32(32), 230 .nbytes_max = __cpu_to_le32(2048), 231 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 232 .reserved = __cpu_to_le32(0), 233 }, 234 235 /* CE14: WMI logging/CFR/Spectral/Radar */ 236 { 237 .pipenum = __cpu_to_le32(14), 238 .pipedir = __cpu_to_le32(PIPEDIR_IN), 239 .nentries = __cpu_to_le32(32), 240 .nbytes_max = __cpu_to_le32(2048), 241 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 242 .reserved = __cpu_to_le32(0), 243 }, 244 245 /* CE15: Reserved */ 246 }; 247 248 /* Target firmware's Copy Engine configuration. */ 249 static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = { 250 /* CE0: host->target HTC control and raw streams */ 251 { 252 .pipenum = __cpu_to_le32(0), 253 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 254 .nentries = __cpu_to_le32(32), 255 .nbytes_max = __cpu_to_le32(2048), 256 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 257 .reserved = __cpu_to_le32(0), 258 }, 259 260 /* CE1: target->host HTT + HTC control */ 261 { 262 .pipenum = __cpu_to_le32(1), 263 .pipedir = __cpu_to_le32(PIPEDIR_IN), 264 .nentries = __cpu_to_le32(32), 265 .nbytes_max = __cpu_to_le32(2048), 266 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 267 .reserved = __cpu_to_le32(0), 268 }, 269 270 /* CE2: target->host WMI */ 271 { 272 .pipenum = __cpu_to_le32(2), 273 .pipedir = __cpu_to_le32(PIPEDIR_IN), 274 .nentries = __cpu_to_le32(32), 275 .nbytes_max = __cpu_to_le32(2048), 276 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 277 .reserved = __cpu_to_le32(0), 278 }, 279 280 /* CE3: host->target WMI */ 281 { 282 .pipenum = __cpu_to_le32(3), 283 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 284 .nentries = __cpu_to_le32(32), 285 .nbytes_max = __cpu_to_le32(2048), 286 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 287 .reserved = __cpu_to_le32(0), 288 }, 289 290 /* CE4: host->target HTT */ 291 { 292 .pipenum = __cpu_to_le32(4), 293 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 294 .nentries = __cpu_to_le32(256), 295 .nbytes_max = __cpu_to_le32(256), 296 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 297 .reserved = __cpu_to_le32(0), 298 }, 299 300 /* CE5: target->host Pktlog */ 301 { 302 .pipenum = __cpu_to_le32(5), 303 .pipedir = __cpu_to_le32(PIPEDIR_IN), 304 .nentries = __cpu_to_le32(32), 305 .nbytes_max = __cpu_to_le32(2048), 306 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 307 .reserved = __cpu_to_le32(0), 308 }, 309 310 /* CE6: Reserved for target autonomous hif_memcpy */ 311 { 312 .pipenum = __cpu_to_le32(6), 313 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 314 .nentries = __cpu_to_le32(32), 315 .nbytes_max = __cpu_to_le32(16384), 316 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 317 .reserved = __cpu_to_le32(0), 318 }, 319 320 /* CE7 used only by Host */ 321 { 322 .pipenum = __cpu_to_le32(7), 323 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 324 .nentries = __cpu_to_le32(0), 325 .nbytes_max = __cpu_to_le32(0), 326 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 327 .reserved = __cpu_to_le32(0), 328 }, 329 330 /* CE8 target->host used only by IPA */ 331 { 332 .pipenum = __cpu_to_le32(8), 333 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 334 .nentries = __cpu_to_le32(32), 335 .nbytes_max = __cpu_to_le32(16384), 336 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 337 .reserved = __cpu_to_le32(0), 338 }, 339 /* CE 9, 10, 11 are used by MHI driver */ 340 }; 341 342 /* Map from service/endpoint to Copy Engine. 343 * This table is derived from the CE_PCI TABLE, above. 344 * It is passed to the Target at startup for use by firmware. 345 */ 346 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = { 347 { 348 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 349 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 350 __cpu_to_le32(3), 351 }, 352 { 353 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 354 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 355 __cpu_to_le32(2), 356 }, 357 { 358 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 359 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 360 __cpu_to_le32(3), 361 }, 362 { 363 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 364 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 365 __cpu_to_le32(2), 366 }, 367 { 368 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 369 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 370 __cpu_to_le32(3), 371 }, 372 { 373 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 374 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 375 __cpu_to_le32(2), 376 }, 377 { 378 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 379 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 380 __cpu_to_le32(3), 381 }, 382 { 383 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 384 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 385 __cpu_to_le32(2), 386 }, 387 { 388 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 389 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 390 __cpu_to_le32(3), 391 }, 392 { 393 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 394 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 395 __cpu_to_le32(2), 396 }, 397 { 398 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 399 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 400 __cpu_to_le32(0), 401 }, 402 { 403 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 404 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 405 __cpu_to_le32(1), 406 }, 407 { 408 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 409 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 410 __cpu_to_le32(0), 411 }, 412 { 413 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 414 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 415 __cpu_to_le32(1), 416 }, 417 { 418 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 419 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 420 __cpu_to_le32(4), 421 }, 422 { 423 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 424 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 425 __cpu_to_le32(1), 426 }, 427 { 428 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 429 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 430 __cpu_to_le32(7), 431 }, 432 { 433 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 434 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 435 __cpu_to_le32(2), 436 }, 437 { 438 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG), 439 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 440 __cpu_to_le32(5), 441 }, 442 { 443 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG), 444 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 445 __cpu_to_le32(14), 446 }, 447 448 /* (Additions here) */ 449 450 { /* must be last */ 451 __cpu_to_le32(0), 452 __cpu_to_le32(0), 453 __cpu_to_le32(0), 454 }, 455 }; 456 457 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = { 458 { 459 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 460 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 461 __cpu_to_le32(3), 462 }, 463 { 464 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 465 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 466 __cpu_to_le32(2), 467 }, 468 { 469 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 470 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 471 __cpu_to_le32(3), 472 }, 473 { 474 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 475 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 476 __cpu_to_le32(2), 477 }, 478 { 479 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 480 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 481 __cpu_to_le32(3), 482 }, 483 { 484 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 485 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 486 __cpu_to_le32(2), 487 }, 488 { 489 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 490 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 491 __cpu_to_le32(3), 492 }, 493 { 494 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 495 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 496 __cpu_to_le32(2), 497 }, 498 { 499 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 500 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 501 __cpu_to_le32(3), 502 }, 503 { 504 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 505 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 506 __cpu_to_le32(2), 507 }, 508 { 509 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 510 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 511 __cpu_to_le32(0), 512 }, 513 { 514 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 515 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 516 __cpu_to_le32(2), 517 }, 518 { 519 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 520 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 521 __cpu_to_le32(4), 522 }, 523 { 524 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 525 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 526 __cpu_to_le32(1), 527 }, 528 529 /* (Additions here) */ 530 531 { /* must be last */ 532 __cpu_to_le32(0), 533 __cpu_to_le32(0), 534 __cpu_to_le32(0), 535 }, 536 }; 537 538 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = { 539 .tx = { 540 ATH12K_TX_RING_MASK_0, 541 ATH12K_TX_RING_MASK_1, 542 ATH12K_TX_RING_MASK_2, 543 ATH12K_TX_RING_MASK_3, 544 }, 545 .rx_mon_dest = { 546 0, 0, 0, 547 }, 548 .rx = { 549 0, 0, 0, 0, 550 ATH12K_RX_RING_MASK_0, 551 ATH12K_RX_RING_MASK_1, 552 ATH12K_RX_RING_MASK_2, 553 ATH12K_RX_RING_MASK_3, 554 }, 555 .rx_err = { 556 0, 0, 0, 557 ATH12K_RX_ERR_RING_MASK_0, 558 }, 559 .rx_wbm_rel = { 560 0, 0, 0, 561 ATH12K_RX_WBM_REL_RING_MASK_0, 562 }, 563 .reo_status = { 564 0, 0, 0, 565 ATH12K_REO_STATUS_RING_MASK_0, 566 }, 567 .host2rxdma = { 568 0, 0, 0, 569 ATH12K_HOST2RXDMA_RING_MASK_0, 570 }, 571 .tx_mon_dest = { 572 0, 0, 0, 573 }, 574 }; 575 576 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = { 577 .tx = { 578 ATH12K_TX_RING_MASK_0, 579 ATH12K_TX_RING_MASK_1, 580 ATH12K_TX_RING_MASK_2, 581 }, 582 .rx_mon_dest = { 583 }, 584 .rx = { 585 0, 0, 0, 586 ATH12K_RX_RING_MASK_0, 587 ATH12K_RX_RING_MASK_1, 588 ATH12K_RX_RING_MASK_2, 589 ATH12K_RX_RING_MASK_3, 590 }, 591 .rx_err = { 592 ATH12K_RX_ERR_RING_MASK_0, 593 }, 594 .rx_wbm_rel = { 595 ATH12K_RX_WBM_REL_RING_MASK_0, 596 }, 597 .reo_status = { 598 ATH12K_REO_STATUS_RING_MASK_0, 599 }, 600 .host2rxdma = { 601 }, 602 .tx_mon_dest = { 603 }, 604 }; 605 606 static const struct ath12k_hw_regs qcn9274_v1_regs = { 607 /* SW2TCL(x) R0 ring configuration address */ 608 .hal_tcl1_ring_id = 0x00000908, 609 .hal_tcl1_ring_misc = 0x00000910, 610 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 611 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 612 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 613 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 614 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 615 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 616 .hal_tcl1_ring_msi1_data = 0x00000950, 617 .hal_tcl_ring_base_lsb = 0x00000b58, 618 619 /* TCL STATUS ring address */ 620 .hal_tcl_status_ring_base_lsb = 0x00000d38, 621 622 .hal_wbm_idle_ring_base_lsb = 0x00000d0c, 623 .hal_wbm_idle_ring_misc_addr = 0x00000d1c, 624 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210, 625 .hal_wbm_r0_idle_list_size_addr = 0x00000214, 626 .hal_wbm_scattered_ring_base_lsb = 0x00000220, 627 .hal_wbm_scattered_ring_base_msb = 0x00000224, 628 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230, 629 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234, 630 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240, 631 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244, 632 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c, 633 634 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c, 635 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4, 636 .hal_wbm0_release_ring_base_lsb = 0x00000dd8, 637 .hal_wbm1_release_ring_base_lsb = 0x00000e50, 638 639 /* PCIe base address */ 640 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 641 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 642 643 /* PPE release ring address */ 644 .hal_ppe_rel_ring_base = 0x0000043c, 645 646 /* REO DEST ring address */ 647 .hal_reo2_ring_base = 0x0000055c, 648 .hal_reo1_misc_ctrl_addr = 0x00000b7c, 649 .hal_reo1_sw_cookie_cfg0 = 0x00000050, 650 .hal_reo1_sw_cookie_cfg1 = 0x00000054, 651 .hal_reo1_qdesc_lut_base0 = 0x00000058, 652 .hal_reo1_qdesc_lut_base1 = 0x0000005c, 653 .hal_reo1_ring_base_lsb = 0x000004e4, 654 .hal_reo1_ring_base_msb = 0x000004e8, 655 .hal_reo1_ring_id = 0x000004ec, 656 .hal_reo1_ring_misc = 0x000004f4, 657 .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 658 .hal_reo1_ring_hp_addr_msb = 0x000004fc, 659 .hal_reo1_ring_producer_int_setup = 0x00000508, 660 .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 661 .hal_reo1_ring_msi1_base_msb = 0x00000530, 662 .hal_reo1_ring_msi1_data = 0x00000534, 663 .hal_reo1_aging_thres_ix0 = 0x00000b08, 664 .hal_reo1_aging_thres_ix1 = 0x00000b0c, 665 .hal_reo1_aging_thres_ix2 = 0x00000b10, 666 .hal_reo1_aging_thres_ix3 = 0x00000b14, 667 668 /* REO Exception ring address */ 669 .hal_reo2_sw0_ring_base = 0x000008a4, 670 671 /* REO Reinject ring address */ 672 .hal_sw2reo_ring_base = 0x00000304, 673 .hal_sw2reo1_ring_base = 0x0000037c, 674 675 /* REO cmd ring address */ 676 .hal_reo_cmd_ring_base = 0x0000028c, 677 678 /* REO status ring address */ 679 .hal_reo_status_ring_base = 0x00000a84, 680 }; 681 682 static const struct ath12k_hw_regs qcn9274_v2_regs = { 683 /* SW2TCL(x) R0 ring configuration address */ 684 .hal_tcl1_ring_id = 0x00000908, 685 .hal_tcl1_ring_misc = 0x00000910, 686 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 687 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 688 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 689 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 690 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 691 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 692 .hal_tcl1_ring_msi1_data = 0x00000950, 693 .hal_tcl_ring_base_lsb = 0x00000b58, 694 695 /* TCL STATUS ring address */ 696 .hal_tcl_status_ring_base_lsb = 0x00000d38, 697 698 /* WBM idle link ring address */ 699 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 700 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 701 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 702 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 703 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 704 .hal_wbm_scattered_ring_base_msb = 0x00000254, 705 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 706 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 707 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 708 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 709 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 710 711 /* SW2WBM release ring address */ 712 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 713 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4, 714 715 /* WBM2SW release ring address */ 716 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 717 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 718 719 /* PCIe base address */ 720 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 721 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 722 723 /* PPE release ring address */ 724 .hal_ppe_rel_ring_base = 0x0000046c, 725 726 /* REO DEST ring address */ 727 .hal_reo2_ring_base = 0x00000578, 728 .hal_reo1_misc_ctrl_addr = 0x00000b9c, 729 .hal_reo1_sw_cookie_cfg0 = 0x0000006c, 730 .hal_reo1_sw_cookie_cfg1 = 0x00000070, 731 .hal_reo1_qdesc_lut_base0 = 0x00000074, 732 .hal_reo1_qdesc_lut_base1 = 0x00000078, 733 .hal_reo1_ring_base_lsb = 0x00000500, 734 .hal_reo1_ring_base_msb = 0x00000504, 735 .hal_reo1_ring_id = 0x00000508, 736 .hal_reo1_ring_misc = 0x00000510, 737 .hal_reo1_ring_hp_addr_lsb = 0x00000514, 738 .hal_reo1_ring_hp_addr_msb = 0x00000518, 739 .hal_reo1_ring_producer_int_setup = 0x00000524, 740 .hal_reo1_ring_msi1_base_lsb = 0x00000548, 741 .hal_reo1_ring_msi1_base_msb = 0x0000054C, 742 .hal_reo1_ring_msi1_data = 0x00000550, 743 .hal_reo1_aging_thres_ix0 = 0x00000B28, 744 .hal_reo1_aging_thres_ix1 = 0x00000B2C, 745 .hal_reo1_aging_thres_ix2 = 0x00000B30, 746 .hal_reo1_aging_thres_ix3 = 0x00000B34, 747 748 /* REO Exception ring address */ 749 .hal_reo2_sw0_ring_base = 0x000008c0, 750 751 /* REO Reinject ring address */ 752 .hal_sw2reo_ring_base = 0x00000320, 753 .hal_sw2reo1_ring_base = 0x00000398, 754 755 /* REO cmd ring address */ 756 .hal_reo_cmd_ring_base = 0x000002A8, 757 758 /* REO status ring address */ 759 .hal_reo_status_ring_base = 0x00000aa0, 760 }; 761 762 static const struct ath12k_hw_regs wcn7850_regs = { 763 /* SW2TCL(x) R0 ring configuration address */ 764 .hal_tcl1_ring_id = 0x00000908, 765 .hal_tcl1_ring_misc = 0x00000910, 766 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 767 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 768 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 769 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 770 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 771 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 772 .hal_tcl1_ring_msi1_data = 0x00000950, 773 .hal_tcl_ring_base_lsb = 0x00000b58, 774 775 /* TCL STATUS ring address */ 776 .hal_tcl_status_ring_base_lsb = 0x00000d38, 777 778 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 779 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 780 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 781 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 782 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 783 .hal_wbm_scattered_ring_base_msb = 0x00000254, 784 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 785 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 786 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 787 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 788 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c, 789 790 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 791 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284, 792 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 793 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 794 795 /* PCIe base address */ 796 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 797 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 798 799 /* PPE release ring address */ 800 .hal_ppe_rel_ring_base = 0x0000043c, 801 802 /* REO DEST ring address */ 803 .hal_reo2_ring_base = 0x0000055c, 804 .hal_reo1_misc_ctrl_addr = 0x00000b7c, 805 .hal_reo1_sw_cookie_cfg0 = 0x00000050, 806 .hal_reo1_sw_cookie_cfg1 = 0x00000054, 807 .hal_reo1_qdesc_lut_base0 = 0x00000058, 808 .hal_reo1_qdesc_lut_base1 = 0x0000005c, 809 .hal_reo1_ring_base_lsb = 0x000004e4, 810 .hal_reo1_ring_base_msb = 0x000004e8, 811 .hal_reo1_ring_id = 0x000004ec, 812 .hal_reo1_ring_misc = 0x000004f4, 813 .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 814 .hal_reo1_ring_hp_addr_msb = 0x000004fc, 815 .hal_reo1_ring_producer_int_setup = 0x00000508, 816 .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 817 .hal_reo1_ring_msi1_base_msb = 0x00000530, 818 .hal_reo1_ring_msi1_data = 0x00000534, 819 .hal_reo1_aging_thres_ix0 = 0x00000b08, 820 .hal_reo1_aging_thres_ix1 = 0x00000b0c, 821 .hal_reo1_aging_thres_ix2 = 0x00000b10, 822 .hal_reo1_aging_thres_ix3 = 0x00000b14, 823 824 /* REO Exception ring address */ 825 .hal_reo2_sw0_ring_base = 0x000008a4, 826 827 /* REO Reinject ring address */ 828 .hal_sw2reo_ring_base = 0x00000304, 829 .hal_sw2reo1_ring_base = 0x0000037c, 830 831 /* REO cmd ring address */ 832 .hal_reo_cmd_ring_base = 0x0000028c, 833 834 /* REO status ring address */ 835 .hal_reo_status_ring_base = 0x00000a84, 836 }; 837 838 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { 839 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 840 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 841 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 842 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 843 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 844 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 845 }; 846 847 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = { 848 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 849 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 850 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 851 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 852 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 853 }; 854 855 static const struct ath12k_hw_params ath12k_hw_params[] = { 856 { 857 .name = "qcn9274 hw1.0", 858 .hw_rev = ATH12K_HW_QCN9274_HW10, 859 .fw = { 860 .dir = "QCN9274/hw1.0", 861 .board_size = 256 * 1024, 862 .cal_offset = 128 * 1024, 863 }, 864 .max_radios = 1, 865 .single_pdev_only = false, 866 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 867 .internal_sleep_clock = false, 868 869 .hw_ops = &qcn9274_ops, 870 .ring_mask = &ath12k_hw_ring_mask_qcn9274, 871 .regs = &qcn9274_v1_regs, 872 873 .host_ce_config = ath12k_host_ce_config_qcn9274, 874 .ce_count = 16, 875 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 876 .target_ce_count = 12, 877 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 878 .svc_to_ce_map_len = 18, 879 880 .hal_params = &ath12k_hw_hal_params_qcn9274, 881 882 .rxdma1_enable = false, 883 .num_rxdma_per_pdev = 1, 884 .num_rxdma_dst_ring = 0, 885 .rx_mac_buf_ring = false, 886 .vdev_start_delay = false, 887 888 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 889 BIT(NL80211_IFTYPE_AP) | 890 BIT(NL80211_IFTYPE_MESH_POINT) | 891 BIT(NL80211_IFTYPE_AP_VLAN), 892 .supports_monitor = false, 893 894 .idle_ps = false, 895 .download_calib = true, 896 .supports_suspend = false, 897 .tcl_ring_retry = true, 898 .reoq_lut_support = false, 899 .supports_shadow_regs = false, 900 901 .num_tcl_banks = 48, 902 .max_tx_ring = 4, 903 904 .mhi_config = &ath12k_mhi_config_qcn9274, 905 906 .wmi_init = ath12k_wmi_init_qcn9274, 907 908 .hal_ops = &hal_qcn9274_ops, 909 910 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 911 912 .rfkill_pin = 0, 913 .rfkill_cfg = 0, 914 .rfkill_on_level = 0, 915 916 .rddm_size = 0, 917 918 .def_num_link = 0, 919 .max_mlo_peer = 256, 920 921 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB, 922 923 .supports_sta_ps = false, 924 925 .acpi_guid = NULL, 926 .supports_dynamic_smps_6ghz = true, 927 }, 928 { 929 .name = "wcn7850 hw2.0", 930 .hw_rev = ATH12K_HW_WCN7850_HW20, 931 932 .fw = { 933 .dir = "WCN7850/hw2.0", 934 .board_size = 256 * 1024, 935 .cal_offset = 256 * 1024, 936 }, 937 938 .max_radios = 1, 939 .single_pdev_only = true, 940 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850, 941 .internal_sleep_clock = true, 942 943 .hw_ops = &wcn7850_ops, 944 .ring_mask = &ath12k_hw_ring_mask_wcn7850, 945 .regs = &wcn7850_regs, 946 947 .host_ce_config = ath12k_host_ce_config_wcn7850, 948 .ce_count = 9, 949 .target_ce_config = ath12k_target_ce_config_wlan_wcn7850, 950 .target_ce_count = 9, 951 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850, 952 .svc_to_ce_map_len = 14, 953 954 .hal_params = &ath12k_hw_hal_params_wcn7850, 955 956 .rxdma1_enable = false, 957 .num_rxdma_per_pdev = 2, 958 .num_rxdma_dst_ring = 1, 959 .rx_mac_buf_ring = true, 960 .vdev_start_delay = true, 961 962 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 963 BIT(NL80211_IFTYPE_AP) | 964 BIT(NL80211_IFTYPE_P2P_DEVICE) | 965 BIT(NL80211_IFTYPE_P2P_CLIENT) | 966 BIT(NL80211_IFTYPE_P2P_GO), 967 .supports_monitor = false, 968 969 .idle_ps = true, 970 .download_calib = false, 971 .supports_suspend = true, 972 .tcl_ring_retry = false, 973 .reoq_lut_support = false, 974 .supports_shadow_regs = true, 975 976 .num_tcl_banks = 7, 977 .max_tx_ring = 3, 978 979 .mhi_config = &ath12k_mhi_config_wcn7850, 980 981 .wmi_init = ath12k_wmi_init_wcn7850, 982 983 .hal_ops = &hal_wcn7850_ops, 984 985 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) | 986 BIT(CNSS_PCIE_PERST_NO_PULL_V01), 987 988 .rfkill_pin = 48, 989 .rfkill_cfg = 0, 990 .rfkill_on_level = 1, 991 992 .rddm_size = 0x780000, 993 994 .def_num_link = 2, 995 .max_mlo_peer = 32, 996 997 .otp_board_id_register = 0, 998 999 .supports_sta_ps = true, 1000 1001 .acpi_guid = &wcn7850_uuid, 1002 .supports_dynamic_smps_6ghz = false, 1003 }, 1004 { 1005 .name = "qcn9274 hw2.0", 1006 .hw_rev = ATH12K_HW_QCN9274_HW20, 1007 .fw = { 1008 .dir = "QCN9274/hw2.0", 1009 .board_size = 256 * 1024, 1010 .cal_offset = 128 * 1024, 1011 }, 1012 .max_radios = 2, 1013 .single_pdev_only = false, 1014 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 1015 .internal_sleep_clock = false, 1016 1017 .hw_ops = &qcn9274_ops, 1018 .ring_mask = &ath12k_hw_ring_mask_qcn9274, 1019 .regs = &qcn9274_v2_regs, 1020 1021 .host_ce_config = ath12k_host_ce_config_qcn9274, 1022 .ce_count = 16, 1023 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 1024 .target_ce_count = 12, 1025 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 1026 .svc_to_ce_map_len = 18, 1027 1028 .hal_params = &ath12k_hw_hal_params_qcn9274, 1029 1030 .rxdma1_enable = false, 1031 .num_rxdma_per_pdev = 1, 1032 .num_rxdma_dst_ring = 0, 1033 .rx_mac_buf_ring = false, 1034 .vdev_start_delay = false, 1035 1036 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 1037 BIT(NL80211_IFTYPE_AP) | 1038 BIT(NL80211_IFTYPE_MESH_POINT) | 1039 BIT(NL80211_IFTYPE_AP_VLAN), 1040 .supports_monitor = false, 1041 1042 .idle_ps = false, 1043 .download_calib = true, 1044 .supports_suspend = false, 1045 .tcl_ring_retry = true, 1046 .reoq_lut_support = false, 1047 .supports_shadow_regs = false, 1048 1049 .num_tcl_banks = 48, 1050 .max_tx_ring = 4, 1051 1052 .mhi_config = &ath12k_mhi_config_qcn9274, 1053 1054 .wmi_init = ath12k_wmi_init_qcn9274, 1055 1056 .hal_ops = &hal_qcn9274_ops, 1057 1058 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 1059 1060 .rfkill_pin = 0, 1061 .rfkill_cfg = 0, 1062 .rfkill_on_level = 0, 1063 1064 .rddm_size = 0, 1065 1066 .def_num_link = 0, 1067 .max_mlo_peer = 256, 1068 1069 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB, 1070 1071 .supports_sta_ps = false, 1072 1073 .acpi_guid = NULL, 1074 .supports_dynamic_smps_6ghz = true, 1075 }, 1076 }; 1077 1078 int ath12k_hw_init(struct ath12k_base *ab) 1079 { 1080 const struct ath12k_hw_params *hw_params = NULL; 1081 int i; 1082 1083 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) { 1084 hw_params = &ath12k_hw_params[i]; 1085 1086 if (hw_params->hw_rev == ab->hw_rev) 1087 break; 1088 } 1089 1090 if (i == ARRAY_SIZE(ath12k_hw_params)) { 1091 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1092 return -EINVAL; 1093 } 1094 1095 ab->hw_params = hw_params; 1096 1097 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name); 1098 1099 return 0; 1100 } 1101