1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 11 #include "debug.h" 12 #include "core.h" 13 #include "ce.h" 14 #include "hw.h" 15 #include "mhi.h" 16 #include "dp_rx.h" 17 18 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec, 19 0x90, 0xd6, 0x02, 0x42, 20 0xac, 0x12, 0x00, 0x03); 21 22 static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx) 23 { 24 return pdev_idx; 25 } 26 27 static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw, 28 int mac_id) 29 { 30 return mac_id; 31 } 32 33 static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw, 34 int mac_id) 35 { 36 return 0; 37 } 38 39 static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb) 40 { 41 return smp_processor_id(); 42 } 43 44 static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num) 45 { 46 if (ring_num < 3 || ring_num == 4) 47 return true; 48 49 return false; 50 } 51 52 static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw, 53 int mac_id) 54 { 55 return 0; 56 } 57 58 static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw, 59 int mac_id) 60 { 61 return mac_id; 62 } 63 64 static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb) 65 { 66 return skb_get_queue_mapping(skb); 67 } 68 69 static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num) 70 { 71 if (ring_num == 0 || ring_num == 2 || ring_num == 4) 72 return true; 73 74 return false; 75 } 76 77 static const struct ath12k_hw_ops qcn9274_ops = { 78 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 79 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274, 80 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274, 81 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274, 82 .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274, 83 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274, 84 }; 85 86 static const struct ath12k_hw_ops wcn7850_ops = { 87 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 88 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850, 89 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850, 90 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850, 91 .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850, 92 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850, 93 }; 94 95 #define ATH12K_TX_RING_MASK_0 0x1 96 #define ATH12K_TX_RING_MASK_1 0x2 97 #define ATH12K_TX_RING_MASK_2 0x4 98 #define ATH12K_TX_RING_MASK_3 0x8 99 #define ATH12K_TX_RING_MASK_4 0x10 100 101 #define ATH12K_RX_RING_MASK_0 0x1 102 #define ATH12K_RX_RING_MASK_1 0x2 103 #define ATH12K_RX_RING_MASK_2 0x4 104 #define ATH12K_RX_RING_MASK_3 0x8 105 106 #define ATH12K_RX_ERR_RING_MASK_0 0x1 107 108 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1 109 110 #define ATH12K_REO_STATUS_RING_MASK_0 0x1 111 112 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1 113 114 #define ATH12K_RX_MON_RING_MASK_0 0x1 115 #define ATH12K_RX_MON_RING_MASK_1 0x2 116 #define ATH12K_RX_MON_RING_MASK_2 0x4 117 118 #define ATH12K_TX_MON_RING_MASK_0 0x1 119 #define ATH12K_TX_MON_RING_MASK_1 0x2 120 121 /* Target firmware's Copy Engine configuration. */ 122 static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = { 123 /* CE0: host->target HTC control and raw streams */ 124 { 125 .pipenum = __cpu_to_le32(0), 126 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 127 .nentries = __cpu_to_le32(32), 128 .nbytes_max = __cpu_to_le32(2048), 129 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 130 .reserved = __cpu_to_le32(0), 131 }, 132 133 /* CE1: target->host HTT + HTC control */ 134 { 135 .pipenum = __cpu_to_le32(1), 136 .pipedir = __cpu_to_le32(PIPEDIR_IN), 137 .nentries = __cpu_to_le32(32), 138 .nbytes_max = __cpu_to_le32(2048), 139 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 140 .reserved = __cpu_to_le32(0), 141 }, 142 143 /* CE2: target->host WMI */ 144 { 145 .pipenum = __cpu_to_le32(2), 146 .pipedir = __cpu_to_le32(PIPEDIR_IN), 147 .nentries = __cpu_to_le32(32), 148 .nbytes_max = __cpu_to_le32(2048), 149 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 150 .reserved = __cpu_to_le32(0), 151 }, 152 153 /* CE3: host->target WMI (mac0) */ 154 { 155 .pipenum = __cpu_to_le32(3), 156 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 157 .nentries = __cpu_to_le32(32), 158 .nbytes_max = __cpu_to_le32(2048), 159 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 160 .reserved = __cpu_to_le32(0), 161 }, 162 163 /* CE4: host->target HTT */ 164 { 165 .pipenum = __cpu_to_le32(4), 166 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 167 .nentries = __cpu_to_le32(256), 168 .nbytes_max = __cpu_to_le32(256), 169 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 170 .reserved = __cpu_to_le32(0), 171 }, 172 173 /* CE5: target->host Pktlog */ 174 { 175 .pipenum = __cpu_to_le32(5), 176 .pipedir = __cpu_to_le32(PIPEDIR_IN), 177 .nentries = __cpu_to_le32(32), 178 .nbytes_max = __cpu_to_le32(2048), 179 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 180 .reserved = __cpu_to_le32(0), 181 }, 182 183 /* CE6: Reserved for target autonomous hif_memcpy */ 184 { 185 .pipenum = __cpu_to_le32(6), 186 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 187 .nentries = __cpu_to_le32(32), 188 .nbytes_max = __cpu_to_le32(16384), 189 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 190 .reserved = __cpu_to_le32(0), 191 }, 192 193 /* CE7: host->target WMI (mac1) */ 194 { 195 .pipenum = __cpu_to_le32(7), 196 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 197 .nentries = __cpu_to_le32(32), 198 .nbytes_max = __cpu_to_le32(2048), 199 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 200 .reserved = __cpu_to_le32(0), 201 }, 202 203 /* CE8: Reserved for target autonomous hif_memcpy */ 204 { 205 .pipenum = __cpu_to_le32(8), 206 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 207 .nentries = __cpu_to_le32(32), 208 .nbytes_max = __cpu_to_le32(16384), 209 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 210 .reserved = __cpu_to_le32(0), 211 }, 212 213 /* CE9, 10 and 11: Reserved for MHI */ 214 215 /* CE12: Target CV prefetch */ 216 { 217 .pipenum = __cpu_to_le32(12), 218 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 219 .nentries = __cpu_to_le32(32), 220 .nbytes_max = __cpu_to_le32(2048), 221 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 222 .reserved = __cpu_to_le32(0), 223 }, 224 225 /* CE13: Target CV prefetch */ 226 { 227 .pipenum = __cpu_to_le32(13), 228 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 229 .nentries = __cpu_to_le32(32), 230 .nbytes_max = __cpu_to_le32(2048), 231 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 232 .reserved = __cpu_to_le32(0), 233 }, 234 235 /* CE14: WMI logging/CFR/Spectral/Radar */ 236 { 237 .pipenum = __cpu_to_le32(14), 238 .pipedir = __cpu_to_le32(PIPEDIR_IN), 239 .nentries = __cpu_to_le32(32), 240 .nbytes_max = __cpu_to_le32(2048), 241 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 242 .reserved = __cpu_to_le32(0), 243 }, 244 245 /* CE15: Reserved */ 246 }; 247 248 /* Target firmware's Copy Engine configuration. */ 249 static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = { 250 /* CE0: host->target HTC control and raw streams */ 251 { 252 .pipenum = __cpu_to_le32(0), 253 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 254 .nentries = __cpu_to_le32(32), 255 .nbytes_max = __cpu_to_le32(2048), 256 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 257 .reserved = __cpu_to_le32(0), 258 }, 259 260 /* CE1: target->host HTT + HTC control */ 261 { 262 .pipenum = __cpu_to_le32(1), 263 .pipedir = __cpu_to_le32(PIPEDIR_IN), 264 .nentries = __cpu_to_le32(32), 265 .nbytes_max = __cpu_to_le32(2048), 266 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 267 .reserved = __cpu_to_le32(0), 268 }, 269 270 /* CE2: target->host WMI */ 271 { 272 .pipenum = __cpu_to_le32(2), 273 .pipedir = __cpu_to_le32(PIPEDIR_IN), 274 .nentries = __cpu_to_le32(32), 275 .nbytes_max = __cpu_to_le32(2048), 276 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 277 .reserved = __cpu_to_le32(0), 278 }, 279 280 /* CE3: host->target WMI */ 281 { 282 .pipenum = __cpu_to_le32(3), 283 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 284 .nentries = __cpu_to_le32(32), 285 .nbytes_max = __cpu_to_le32(2048), 286 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 287 .reserved = __cpu_to_le32(0), 288 }, 289 290 /* CE4: host->target HTT */ 291 { 292 .pipenum = __cpu_to_le32(4), 293 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 294 .nentries = __cpu_to_le32(256), 295 .nbytes_max = __cpu_to_le32(256), 296 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 297 .reserved = __cpu_to_le32(0), 298 }, 299 300 /* CE5: target->host Pktlog */ 301 { 302 .pipenum = __cpu_to_le32(5), 303 .pipedir = __cpu_to_le32(PIPEDIR_IN), 304 .nentries = __cpu_to_le32(32), 305 .nbytes_max = __cpu_to_le32(2048), 306 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 307 .reserved = __cpu_to_le32(0), 308 }, 309 310 /* CE6: Reserved for target autonomous hif_memcpy */ 311 { 312 .pipenum = __cpu_to_le32(6), 313 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 314 .nentries = __cpu_to_le32(32), 315 .nbytes_max = __cpu_to_le32(16384), 316 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 317 .reserved = __cpu_to_le32(0), 318 }, 319 320 /* CE7 used only by Host */ 321 { 322 .pipenum = __cpu_to_le32(7), 323 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 324 .nentries = __cpu_to_le32(0), 325 .nbytes_max = __cpu_to_le32(0), 326 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 327 .reserved = __cpu_to_le32(0), 328 }, 329 330 /* CE8 target->host used only by IPA */ 331 { 332 .pipenum = __cpu_to_le32(8), 333 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 334 .nentries = __cpu_to_le32(32), 335 .nbytes_max = __cpu_to_le32(16384), 336 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 337 .reserved = __cpu_to_le32(0), 338 }, 339 /* CE 9, 10, 11 are used by MHI driver */ 340 }; 341 342 /* Map from service/endpoint to Copy Engine. 343 * This table is derived from the CE_PCI TABLE, above. 344 * It is passed to the Target at startup for use by firmware. 345 */ 346 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = { 347 { 348 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 349 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 350 __cpu_to_le32(3), 351 }, 352 { 353 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 354 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 355 __cpu_to_le32(2), 356 }, 357 { 358 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 359 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 360 __cpu_to_le32(3), 361 }, 362 { 363 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 364 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 365 __cpu_to_le32(2), 366 }, 367 { 368 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 369 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 370 __cpu_to_le32(3), 371 }, 372 { 373 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 374 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 375 __cpu_to_le32(2), 376 }, 377 { 378 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 379 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 380 __cpu_to_le32(3), 381 }, 382 { 383 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 384 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 385 __cpu_to_le32(2), 386 }, 387 { 388 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 389 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 390 __cpu_to_le32(3), 391 }, 392 { 393 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 394 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 395 __cpu_to_le32(2), 396 }, 397 { 398 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 399 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 400 __cpu_to_le32(0), 401 }, 402 { 403 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 404 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 405 __cpu_to_le32(1), 406 }, 407 { 408 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 409 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 410 __cpu_to_le32(0), 411 }, 412 { 413 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 414 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 415 __cpu_to_le32(1), 416 }, 417 { 418 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 419 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 420 __cpu_to_le32(4), 421 }, 422 { 423 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 424 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 425 __cpu_to_le32(1), 426 }, 427 { 428 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 429 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 430 __cpu_to_le32(7), 431 }, 432 { 433 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 434 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 435 __cpu_to_le32(2), 436 }, 437 { 438 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG), 439 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 440 __cpu_to_le32(5), 441 }, 442 { 443 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG), 444 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 445 __cpu_to_le32(14), 446 }, 447 448 /* (Additions here) */ 449 450 { /* must be last */ 451 __cpu_to_le32(0), 452 __cpu_to_le32(0), 453 __cpu_to_le32(0), 454 }, 455 }; 456 457 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = { 458 { 459 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 460 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 461 __cpu_to_le32(3), 462 }, 463 { 464 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 465 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 466 __cpu_to_le32(2), 467 }, 468 { 469 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 470 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 471 __cpu_to_le32(3), 472 }, 473 { 474 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 475 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 476 __cpu_to_le32(2), 477 }, 478 { 479 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 480 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 481 __cpu_to_le32(3), 482 }, 483 { 484 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 485 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 486 __cpu_to_le32(2), 487 }, 488 { 489 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 490 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 491 __cpu_to_le32(3), 492 }, 493 { 494 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 495 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 496 __cpu_to_le32(2), 497 }, 498 { 499 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 500 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 501 __cpu_to_le32(3), 502 }, 503 { 504 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 505 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 506 __cpu_to_le32(2), 507 }, 508 { 509 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 510 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 511 __cpu_to_le32(0), 512 }, 513 { 514 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 515 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 516 __cpu_to_le32(2), 517 }, 518 { 519 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 520 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 521 __cpu_to_le32(4), 522 }, 523 { 524 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 525 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 526 __cpu_to_le32(1), 527 }, 528 529 /* (Additions here) */ 530 531 { /* must be last */ 532 __cpu_to_le32(0), 533 __cpu_to_le32(0), 534 __cpu_to_le32(0), 535 }, 536 }; 537 538 static const struct ce_pipe_config ath12k_target_ce_config_wlan_ipq5332[] = { 539 /* host->target HTC control and raw streams */ 540 { 541 .pipenum = __cpu_to_le32(0), 542 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 543 .nentries = __cpu_to_le32(32), 544 .nbytes_max = __cpu_to_le32(2048), 545 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 546 .reserved = __cpu_to_le32(0), 547 }, 548 /* target->host HTT */ 549 { 550 .pipenum = __cpu_to_le32(1), 551 .pipedir = __cpu_to_le32(PIPEDIR_IN), 552 .nentries = __cpu_to_le32(32), 553 .nbytes_max = __cpu_to_le32(2048), 554 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 555 .reserved = __cpu_to_le32(0), 556 }, 557 /* target->host WMI + HTC control */ 558 { 559 .pipenum = __cpu_to_le32(2), 560 .pipedir = __cpu_to_le32(PIPEDIR_IN), 561 .nentries = __cpu_to_le32(32), 562 .nbytes_max = __cpu_to_le32(2048), 563 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 564 .reserved = __cpu_to_le32(0), 565 }, 566 /* host->target WMI */ 567 { 568 .pipenum = __cpu_to_le32(3), 569 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 570 .nentries = __cpu_to_le32(32), 571 .nbytes_max = __cpu_to_le32(2048), 572 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 573 .reserved = __cpu_to_le32(0), 574 }, 575 /* host->target HTT */ 576 { 577 .pipenum = __cpu_to_le32(4), 578 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 579 .nentries = __cpu_to_le32(256), 580 .nbytes_max = __cpu_to_le32(256), 581 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 582 .reserved = __cpu_to_le32(0), 583 }, 584 /* Target -> host PKTLOG */ 585 { 586 .pipenum = __cpu_to_le32(5), 587 .pipedir = __cpu_to_le32(PIPEDIR_IN), 588 .nentries = __cpu_to_le32(32), 589 .nbytes_max = __cpu_to_le32(2048), 590 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 591 .reserved = __cpu_to_le32(0), 592 }, 593 /* Reserved for target autonomous HIF_memcpy */ 594 { 595 .pipenum = __cpu_to_le32(6), 596 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 597 .nentries = __cpu_to_le32(32), 598 .nbytes_max = __cpu_to_le32(16384), 599 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 600 .reserved = __cpu_to_le32(0), 601 }, 602 /* CE7 Reserved for CV Prefetch */ 603 { 604 .pipenum = __cpu_to_le32(7), 605 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 606 .nentries = __cpu_to_le32(32), 607 .nbytes_max = __cpu_to_le32(2048), 608 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 609 .reserved = __cpu_to_le32(0), 610 }, 611 /* CE8 Reserved for target generic HIF memcpy */ 612 { 613 .pipenum = __cpu_to_le32(8), 614 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 615 .nentries = __cpu_to_le32(32), 616 .nbytes_max = __cpu_to_le32(16384), 617 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 618 .reserved = __cpu_to_le32(0), 619 }, 620 /* CE9 WMI logging/CFR/Spectral/Radar/ */ 621 { 622 .pipenum = __cpu_to_le32(9), 623 .pipedir = __cpu_to_le32(PIPEDIR_IN), 624 .nentries = __cpu_to_le32(32), 625 .nbytes_max = __cpu_to_le32(2048), 626 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 627 .reserved = __cpu_to_le32(0), 628 }, 629 /* Unused TBD */ 630 { 631 .pipenum = __cpu_to_le32(10), 632 .pipedir = __cpu_to_le32(PIPEDIR_NONE), 633 .nentries = __cpu_to_le32(0), 634 .nbytes_max = __cpu_to_le32(0), 635 .flags = __cpu_to_le32(0), 636 .reserved = __cpu_to_le32(0), 637 }, 638 /* Unused TBD */ 639 { 640 .pipenum = __cpu_to_le32(11), 641 .pipedir = __cpu_to_le32(PIPEDIR_NONE), 642 .nentries = __cpu_to_le32(0), 643 .nbytes_max = __cpu_to_le32(0), 644 .flags = __cpu_to_le32(0), 645 .reserved = __cpu_to_le32(0), 646 }, 647 }; 648 649 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_ipq5332[] = { 650 { 651 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 652 __cpu_to_le32(PIPEDIR_OUT), 653 __cpu_to_le32(3), 654 }, 655 { 656 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 657 __cpu_to_le32(PIPEDIR_IN), 658 __cpu_to_le32(2), 659 }, 660 { 661 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 662 __cpu_to_le32(PIPEDIR_OUT), 663 __cpu_to_le32(3), 664 }, 665 { 666 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 667 __cpu_to_le32(PIPEDIR_IN), 668 __cpu_to_le32(2), 669 }, 670 { 671 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 672 __cpu_to_le32(PIPEDIR_OUT), 673 __cpu_to_le32(3), 674 }, 675 { 676 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 677 __cpu_to_le32(PIPEDIR_IN), 678 __cpu_to_le32(2), 679 }, 680 { 681 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 682 __cpu_to_le32(PIPEDIR_OUT), 683 __cpu_to_le32(3), 684 }, 685 { 686 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 687 __cpu_to_le32(PIPEDIR_IN), 688 __cpu_to_le32(2), 689 }, 690 { 691 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 692 __cpu_to_le32(PIPEDIR_OUT), 693 __cpu_to_le32(3), 694 }, 695 { 696 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 697 __cpu_to_le32(PIPEDIR_IN), 698 __cpu_to_le32(2), 699 }, 700 { 701 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 702 __cpu_to_le32(PIPEDIR_OUT), 703 __cpu_to_le32(0), 704 }, 705 { 706 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 707 __cpu_to_le32(PIPEDIR_IN), 708 __cpu_to_le32(1), 709 }, 710 { 711 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 712 __cpu_to_le32(PIPEDIR_OUT), 713 __cpu_to_le32(0), 714 }, 715 { 716 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 717 __cpu_to_le32(PIPEDIR_IN), 718 __cpu_to_le32(1), 719 }, 720 { 721 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 722 __cpu_to_le32(PIPEDIR_OUT), 723 __cpu_to_le32(4), 724 }, 725 { 726 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 727 __cpu_to_le32(PIPEDIR_IN), 728 __cpu_to_le32(1), 729 }, 730 { 731 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG), 732 __cpu_to_le32(PIPEDIR_IN), 733 __cpu_to_le32(5), 734 }, 735 { 736 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG), 737 __cpu_to_le32(PIPEDIR_IN), 738 __cpu_to_le32(9), 739 }, 740 /* (Additions here) */ 741 742 { /* must be last */ 743 __cpu_to_le32(0), 744 __cpu_to_le32(0), 745 __cpu_to_le32(0), 746 }, 747 }; 748 749 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = { 750 .tx = { 751 ATH12K_TX_RING_MASK_0, 752 ATH12K_TX_RING_MASK_1, 753 ATH12K_TX_RING_MASK_2, 754 ATH12K_TX_RING_MASK_3, 755 }, 756 .rx_mon_dest = { 757 0, 0, 0, 0, 758 0, 0, 0, 0, 759 ATH12K_RX_MON_RING_MASK_0, 760 ATH12K_RX_MON_RING_MASK_1, 761 ATH12K_RX_MON_RING_MASK_2, 762 }, 763 .rx = { 764 0, 0, 0, 0, 765 ATH12K_RX_RING_MASK_0, 766 ATH12K_RX_RING_MASK_1, 767 ATH12K_RX_RING_MASK_2, 768 ATH12K_RX_RING_MASK_3, 769 }, 770 .rx_err = { 771 0, 0, 0, 772 ATH12K_RX_ERR_RING_MASK_0, 773 }, 774 .rx_wbm_rel = { 775 0, 0, 0, 776 ATH12K_RX_WBM_REL_RING_MASK_0, 777 }, 778 .reo_status = { 779 0, 0, 0, 780 ATH12K_REO_STATUS_RING_MASK_0, 781 }, 782 .host2rxdma = { 783 0, 0, 0, 784 ATH12K_HOST2RXDMA_RING_MASK_0, 785 }, 786 .tx_mon_dest = { 787 0, 0, 0, 788 }, 789 }; 790 791 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_ipq5332 = { 792 .tx = { 793 ATH12K_TX_RING_MASK_0, 794 ATH12K_TX_RING_MASK_1, 795 ATH12K_TX_RING_MASK_2, 796 ATH12K_TX_RING_MASK_3, 797 }, 798 .rx_mon_dest = { 799 0, 0, 0, 0, 0, 0, 0, 0, 800 ATH12K_RX_MON_RING_MASK_0, 801 }, 802 .rx = { 803 0, 0, 0, 0, 804 ATH12K_RX_RING_MASK_0, 805 ATH12K_RX_RING_MASK_1, 806 ATH12K_RX_RING_MASK_2, 807 ATH12K_RX_RING_MASK_3, 808 }, 809 .rx_err = { 810 0, 0, 0, 811 ATH12K_RX_ERR_RING_MASK_0, 812 }, 813 .rx_wbm_rel = { 814 0, 0, 0, 815 ATH12K_RX_WBM_REL_RING_MASK_0, 816 }, 817 .reo_status = { 818 0, 0, 0, 819 ATH12K_REO_STATUS_RING_MASK_0, 820 }, 821 .host2rxdma = { 822 0, 0, 0, 823 ATH12K_HOST2RXDMA_RING_MASK_0, 824 }, 825 .tx_mon_dest = { 826 ATH12K_TX_MON_RING_MASK_0, 827 ATH12K_TX_MON_RING_MASK_1, 828 }, 829 }; 830 831 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = { 832 .tx = { 833 ATH12K_TX_RING_MASK_0, 834 ATH12K_TX_RING_MASK_1, 835 ATH12K_TX_RING_MASK_2, 836 }, 837 .rx_mon_dest = { 838 }, 839 .rx = { 840 0, 0, 0, 841 ATH12K_RX_RING_MASK_0, 842 ATH12K_RX_RING_MASK_1, 843 ATH12K_RX_RING_MASK_2, 844 ATH12K_RX_RING_MASK_3, 845 }, 846 .rx_err = { 847 ATH12K_RX_ERR_RING_MASK_0, 848 }, 849 .rx_wbm_rel = { 850 ATH12K_RX_WBM_REL_RING_MASK_0, 851 }, 852 .reo_status = { 853 ATH12K_REO_STATUS_RING_MASK_0, 854 }, 855 .host2rxdma = { 856 }, 857 .tx_mon_dest = { 858 }, 859 }; 860 861 static const struct ath12k_hw_regs qcn9274_v1_regs = { 862 /* SW2TCL(x) R0 ring configuration address */ 863 .hal_tcl1_ring_id = 0x00000908, 864 .hal_tcl1_ring_misc = 0x00000910, 865 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 866 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 867 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 868 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 869 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 870 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 871 .hal_tcl1_ring_msi1_data = 0x00000950, 872 .hal_tcl_ring_base_lsb = 0x00000b58, 873 .hal_tcl1_ring_base_lsb = 0x00000900, 874 .hal_tcl1_ring_base_msb = 0x00000904, 875 .hal_tcl2_ring_base_lsb = 0x00000978, 876 877 /* TCL STATUS ring address */ 878 .hal_tcl_status_ring_base_lsb = 0x00000d38, 879 880 .hal_wbm_idle_ring_base_lsb = 0x00000d0c, 881 .hal_wbm_idle_ring_misc_addr = 0x00000d1c, 882 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210, 883 .hal_wbm_r0_idle_list_size_addr = 0x00000214, 884 .hal_wbm_scattered_ring_base_lsb = 0x00000220, 885 .hal_wbm_scattered_ring_base_msb = 0x00000224, 886 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230, 887 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234, 888 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240, 889 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244, 890 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c, 891 892 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c, 893 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4, 894 .hal_wbm0_release_ring_base_lsb = 0x00000dd8, 895 .hal_wbm1_release_ring_base_lsb = 0x00000e50, 896 897 /* PCIe base address */ 898 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 899 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 900 901 /* PPE release ring address */ 902 .hal_ppe_rel_ring_base = 0x0000043c, 903 904 /* REO DEST ring address */ 905 .hal_reo2_ring_base = 0x0000055c, 906 .hal_reo1_misc_ctrl_addr = 0x00000b7c, 907 .hal_reo1_sw_cookie_cfg0 = 0x00000050, 908 .hal_reo1_sw_cookie_cfg1 = 0x00000054, 909 .hal_reo1_qdesc_lut_base0 = 0x00000058, 910 .hal_reo1_qdesc_lut_base1 = 0x0000005c, 911 .hal_reo1_ring_base_lsb = 0x000004e4, 912 .hal_reo1_ring_base_msb = 0x000004e8, 913 .hal_reo1_ring_id = 0x000004ec, 914 .hal_reo1_ring_misc = 0x000004f4, 915 .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 916 .hal_reo1_ring_hp_addr_msb = 0x000004fc, 917 .hal_reo1_ring_producer_int_setup = 0x00000508, 918 .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 919 .hal_reo1_ring_msi1_base_msb = 0x00000530, 920 .hal_reo1_ring_msi1_data = 0x00000534, 921 .hal_reo1_aging_thres_ix0 = 0x00000b08, 922 .hal_reo1_aging_thres_ix1 = 0x00000b0c, 923 .hal_reo1_aging_thres_ix2 = 0x00000b10, 924 .hal_reo1_aging_thres_ix3 = 0x00000b14, 925 926 /* REO Exception ring address */ 927 .hal_reo2_sw0_ring_base = 0x000008a4, 928 929 /* REO Reinject ring address */ 930 .hal_sw2reo_ring_base = 0x00000304, 931 .hal_sw2reo1_ring_base = 0x0000037c, 932 933 /* REO cmd ring address */ 934 .hal_reo_cmd_ring_base = 0x0000028c, 935 936 /* REO status ring address */ 937 .hal_reo_status_ring_base = 0x00000a84, 938 939 /* CE base address */ 940 .hal_umac_ce0_src_reg_base = 0x01b80000, 941 .hal_umac_ce0_dest_reg_base = 0x01b81000, 942 .hal_umac_ce1_src_reg_base = 0x01b82000, 943 .hal_umac_ce1_dest_reg_base = 0x01b83000, 944 }; 945 946 static const struct ath12k_hw_regs qcn9274_v2_regs = { 947 /* SW2TCL(x) R0 ring configuration address */ 948 .hal_tcl1_ring_id = 0x00000908, 949 .hal_tcl1_ring_misc = 0x00000910, 950 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 951 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 952 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 953 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 954 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 955 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 956 .hal_tcl1_ring_msi1_data = 0x00000950, 957 .hal_tcl_ring_base_lsb = 0x00000b58, 958 .hal_tcl1_ring_base_lsb = 0x00000900, 959 .hal_tcl1_ring_base_msb = 0x00000904, 960 .hal_tcl2_ring_base_lsb = 0x00000978, 961 962 /* TCL STATUS ring address */ 963 .hal_tcl_status_ring_base_lsb = 0x00000d38, 964 965 /* WBM idle link ring address */ 966 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 967 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 968 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 969 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 970 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 971 .hal_wbm_scattered_ring_base_msb = 0x00000254, 972 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 973 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 974 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 975 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 976 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 977 978 /* SW2WBM release ring address */ 979 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 980 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4, 981 982 /* WBM2SW release ring address */ 983 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 984 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 985 986 /* PCIe base address */ 987 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 988 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 989 990 /* PPE release ring address */ 991 .hal_ppe_rel_ring_base = 0x0000046c, 992 993 /* REO DEST ring address */ 994 .hal_reo2_ring_base = 0x00000578, 995 .hal_reo1_misc_ctrl_addr = 0x00000b9c, 996 .hal_reo1_sw_cookie_cfg0 = 0x0000006c, 997 .hal_reo1_sw_cookie_cfg1 = 0x00000070, 998 .hal_reo1_qdesc_lut_base0 = 0x00000074, 999 .hal_reo1_qdesc_lut_base1 = 0x00000078, 1000 .hal_reo1_qdesc_addr = 0x0000007c, 1001 .hal_reo1_qdesc_max_peerid = 0x00000088, 1002 .hal_reo1_ring_base_lsb = 0x00000500, 1003 .hal_reo1_ring_base_msb = 0x00000504, 1004 .hal_reo1_ring_id = 0x00000508, 1005 .hal_reo1_ring_misc = 0x00000510, 1006 .hal_reo1_ring_hp_addr_lsb = 0x00000514, 1007 .hal_reo1_ring_hp_addr_msb = 0x00000518, 1008 .hal_reo1_ring_producer_int_setup = 0x00000524, 1009 .hal_reo1_ring_msi1_base_lsb = 0x00000548, 1010 .hal_reo1_ring_msi1_base_msb = 0x0000054C, 1011 .hal_reo1_ring_msi1_data = 0x00000550, 1012 .hal_reo1_aging_thres_ix0 = 0x00000B28, 1013 .hal_reo1_aging_thres_ix1 = 0x00000B2C, 1014 .hal_reo1_aging_thres_ix2 = 0x00000B30, 1015 .hal_reo1_aging_thres_ix3 = 0x00000B34, 1016 1017 /* REO Exception ring address */ 1018 .hal_reo2_sw0_ring_base = 0x000008c0, 1019 1020 /* REO Reinject ring address */ 1021 .hal_sw2reo_ring_base = 0x00000320, 1022 .hal_sw2reo1_ring_base = 0x00000398, 1023 1024 /* REO cmd ring address */ 1025 .hal_reo_cmd_ring_base = 0x000002A8, 1026 1027 /* REO status ring address */ 1028 .hal_reo_status_ring_base = 0x00000aa0, 1029 1030 /* CE base address */ 1031 .hal_umac_ce0_src_reg_base = 0x01b80000, 1032 .hal_umac_ce0_dest_reg_base = 0x01b81000, 1033 .hal_umac_ce1_src_reg_base = 0x01b82000, 1034 .hal_umac_ce1_dest_reg_base = 0x01b83000, 1035 }; 1036 1037 static const struct ath12k_hw_regs ipq5332_regs = { 1038 /* SW2TCL(x) R0 ring configuration address */ 1039 .hal_tcl1_ring_id = 0x00000918, 1040 .hal_tcl1_ring_misc = 0x00000920, 1041 .hal_tcl1_ring_tp_addr_lsb = 0x0000092c, 1042 .hal_tcl1_ring_tp_addr_msb = 0x00000930, 1043 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000940, 1044 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000944, 1045 .hal_tcl1_ring_msi1_base_lsb = 0x00000958, 1046 .hal_tcl1_ring_msi1_base_msb = 0x0000095c, 1047 .hal_tcl1_ring_base_lsb = 0x00000910, 1048 .hal_tcl1_ring_base_msb = 0x00000914, 1049 .hal_tcl1_ring_msi1_data = 0x00000960, 1050 .hal_tcl2_ring_base_lsb = 0x00000988, 1051 .hal_tcl_ring_base_lsb = 0x00000b68, 1052 1053 /* TCL STATUS ring address */ 1054 .hal_tcl_status_ring_base_lsb = 0x00000d48, 1055 1056 /* REO DEST ring address */ 1057 .hal_reo2_ring_base = 0x00000578, 1058 .hal_reo1_misc_ctrl_addr = 0x00000b9c, 1059 .hal_reo1_sw_cookie_cfg0 = 0x0000006c, 1060 .hal_reo1_sw_cookie_cfg1 = 0x00000070, 1061 .hal_reo1_qdesc_lut_base0 = 0x00000074, 1062 .hal_reo1_qdesc_lut_base1 = 0x00000078, 1063 .hal_reo1_ring_base_lsb = 0x00000500, 1064 .hal_reo1_ring_base_msb = 0x00000504, 1065 .hal_reo1_ring_id = 0x00000508, 1066 .hal_reo1_ring_misc = 0x00000510, 1067 .hal_reo1_ring_hp_addr_lsb = 0x00000514, 1068 .hal_reo1_ring_hp_addr_msb = 0x00000518, 1069 .hal_reo1_ring_producer_int_setup = 0x00000524, 1070 .hal_reo1_ring_msi1_base_lsb = 0x00000548, 1071 .hal_reo1_ring_msi1_base_msb = 0x0000054C, 1072 .hal_reo1_ring_msi1_data = 0x00000550, 1073 .hal_reo1_aging_thres_ix0 = 0x00000B28, 1074 .hal_reo1_aging_thres_ix1 = 0x00000B2C, 1075 .hal_reo1_aging_thres_ix2 = 0x00000B30, 1076 .hal_reo1_aging_thres_ix3 = 0x00000B34, 1077 1078 /* REO Exception ring address */ 1079 .hal_reo2_sw0_ring_base = 0x000008c0, 1080 1081 /* REO Reinject ring address */ 1082 .hal_sw2reo_ring_base = 0x00000320, 1083 .hal_sw2reo1_ring_base = 0x00000398, 1084 1085 /* REO cmd ring address */ 1086 .hal_reo_cmd_ring_base = 0x000002A8, 1087 1088 /* REO status ring address */ 1089 .hal_reo_status_ring_base = 0x00000aa0, 1090 1091 /* WBM idle link ring address */ 1092 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 1093 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 1094 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 1095 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 1096 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 1097 .hal_wbm_scattered_ring_base_msb = 0x00000254, 1098 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 1099 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 1100 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 1101 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 1102 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 1103 1104 /* SW2WBM release ring address */ 1105 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 1106 1107 /* WBM2SW release ring address */ 1108 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 1109 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 1110 1111 /* PPE release ring address */ 1112 .hal_ppe_rel_ring_base = 0x0000046c, 1113 1114 /* CE address */ 1115 .hal_umac_ce0_src_reg_base = 0x00740000 - 1116 HAL_IPQ5332_CE_WFSS_REG_BASE, 1117 .hal_umac_ce0_dest_reg_base = 0x00741000 - 1118 HAL_IPQ5332_CE_WFSS_REG_BASE, 1119 .hal_umac_ce1_src_reg_base = 0x00742000 - 1120 HAL_IPQ5332_CE_WFSS_REG_BASE, 1121 .hal_umac_ce1_dest_reg_base = 0x00743000 - 1122 HAL_IPQ5332_CE_WFSS_REG_BASE, 1123 }; 1124 1125 static const struct ath12k_hw_regs wcn7850_regs = { 1126 /* SW2TCL(x) R0 ring configuration address */ 1127 .hal_tcl1_ring_id = 0x00000908, 1128 .hal_tcl1_ring_misc = 0x00000910, 1129 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 1130 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 1131 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 1132 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 1133 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 1134 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 1135 .hal_tcl1_ring_msi1_data = 0x00000950, 1136 .hal_tcl_ring_base_lsb = 0x00000b58, 1137 .hal_tcl1_ring_base_lsb = 0x00000900, 1138 .hal_tcl1_ring_base_msb = 0x00000904, 1139 .hal_tcl2_ring_base_lsb = 0x00000978, 1140 1141 /* TCL STATUS ring address */ 1142 .hal_tcl_status_ring_base_lsb = 0x00000d38, 1143 1144 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 1145 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 1146 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 1147 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 1148 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 1149 .hal_wbm_scattered_ring_base_msb = 0x00000254, 1150 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 1151 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 1152 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 1153 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 1154 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c, 1155 1156 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 1157 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284, 1158 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 1159 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 1160 1161 /* PCIe base address */ 1162 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 1163 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 1164 1165 /* PPE release ring address */ 1166 .hal_ppe_rel_ring_base = 0x0000043c, 1167 1168 /* REO DEST ring address */ 1169 .hal_reo2_ring_base = 0x0000055c, 1170 .hal_reo1_misc_ctrl_addr = 0x00000b7c, 1171 .hal_reo1_sw_cookie_cfg0 = 0x00000050, 1172 .hal_reo1_sw_cookie_cfg1 = 0x00000054, 1173 .hal_reo1_qdesc_lut_base0 = 0x00000058, 1174 .hal_reo1_qdesc_lut_base1 = 0x0000005c, 1175 .hal_reo1_ring_base_lsb = 0x000004e4, 1176 .hal_reo1_ring_base_msb = 0x000004e8, 1177 .hal_reo1_ring_id = 0x000004ec, 1178 .hal_reo1_ring_misc = 0x000004f4, 1179 .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 1180 .hal_reo1_ring_hp_addr_msb = 0x000004fc, 1181 .hal_reo1_ring_producer_int_setup = 0x00000508, 1182 .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 1183 .hal_reo1_ring_msi1_base_msb = 0x00000530, 1184 .hal_reo1_ring_msi1_data = 0x00000534, 1185 .hal_reo1_aging_thres_ix0 = 0x00000b08, 1186 .hal_reo1_aging_thres_ix1 = 0x00000b0c, 1187 .hal_reo1_aging_thres_ix2 = 0x00000b10, 1188 .hal_reo1_aging_thres_ix3 = 0x00000b14, 1189 1190 /* REO Exception ring address */ 1191 .hal_reo2_sw0_ring_base = 0x000008a4, 1192 1193 /* REO Reinject ring address */ 1194 .hal_sw2reo_ring_base = 0x00000304, 1195 .hal_sw2reo1_ring_base = 0x0000037c, 1196 1197 /* REO cmd ring address */ 1198 .hal_reo_cmd_ring_base = 0x0000028c, 1199 1200 /* REO status ring address */ 1201 .hal_reo_status_ring_base = 0x00000a84, 1202 1203 /* CE base address */ 1204 .hal_umac_ce0_src_reg_base = 0x01b80000, 1205 .hal_umac_ce0_dest_reg_base = 0x01b81000, 1206 .hal_umac_ce1_src_reg_base = 0x01b82000, 1207 .hal_umac_ce1_dest_reg_base = 0x01b83000, 1208 }; 1209 1210 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { 1211 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 1212 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 1213 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 1214 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 1215 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 1216 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 1217 }; 1218 1219 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = { 1220 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 1221 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 1222 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 1223 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 1224 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 1225 }; 1226 1227 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_ipq5332 = { 1228 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 1229 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 1230 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 1231 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 1232 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 1233 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 1234 }; 1235 1236 static const struct ce_ie_addr ath12k_ce_ie_addr_ipq5332 = { 1237 .ie1_reg_addr = CE_HOST_IE_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE, 1238 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE, 1239 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE, 1240 }; 1241 1242 static const struct ce_remap ath12k_ce_remap_ipq5332 = { 1243 .base = HAL_IPQ5332_CE_WFSS_REG_BASE, 1244 .size = HAL_IPQ5332_CE_SIZE, 1245 }; 1246 1247 static const struct ath12k_hw_params ath12k_hw_params[] = { 1248 { 1249 .name = "qcn9274 hw1.0", 1250 .hw_rev = ATH12K_HW_QCN9274_HW10, 1251 .fw = { 1252 .dir = "QCN9274/hw1.0", 1253 .board_size = 256 * 1024, 1254 .cal_offset = 128 * 1024, 1255 .m3_loader = ath12k_m3_fw_loader_driver, 1256 }, 1257 .max_radios = 1, 1258 .single_pdev_only = false, 1259 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 1260 .internal_sleep_clock = false, 1261 1262 .hw_ops = &qcn9274_ops, 1263 .ring_mask = &ath12k_hw_ring_mask_qcn9274, 1264 .regs = &qcn9274_v1_regs, 1265 1266 .host_ce_config = ath12k_host_ce_config_qcn9274, 1267 .ce_count = 16, 1268 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 1269 .target_ce_count = 12, 1270 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 1271 .svc_to_ce_map_len = 18, 1272 1273 .hal_params = &ath12k_hw_hal_params_qcn9274, 1274 1275 .rxdma1_enable = false, 1276 .num_rxdma_per_pdev = 1, 1277 .num_rxdma_dst_ring = 0, 1278 .rx_mac_buf_ring = false, 1279 .vdev_start_delay = false, 1280 1281 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 1282 BIT(NL80211_IFTYPE_AP) | 1283 BIT(NL80211_IFTYPE_MESH_POINT) | 1284 BIT(NL80211_IFTYPE_AP_VLAN), 1285 .supports_monitor = false, 1286 1287 .idle_ps = false, 1288 .download_calib = true, 1289 .supports_suspend = false, 1290 .tcl_ring_retry = true, 1291 .reoq_lut_support = true, 1292 .supports_shadow_regs = false, 1293 1294 .num_tcl_banks = 48, 1295 .max_tx_ring = 4, 1296 1297 .mhi_config = &ath12k_mhi_config_qcn9274, 1298 1299 .wmi_init = ath12k_wmi_init_qcn9274, 1300 1301 .hal_ops = &hal_qcn9274_ops, 1302 1303 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 1304 1305 .rfkill_pin = 0, 1306 .rfkill_cfg = 0, 1307 .rfkill_on_level = 0, 1308 1309 .rddm_size = 0x600000, 1310 1311 .def_num_link = 0, 1312 .max_mlo_peer = 256, 1313 1314 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB, 1315 1316 .supports_sta_ps = false, 1317 1318 .acpi_guid = NULL, 1319 .supports_dynamic_smps_6ghz = true, 1320 1321 .iova_mask = 0, 1322 1323 .supports_aspm = false, 1324 1325 .ce_ie_addr = NULL, 1326 .ce_remap = NULL, 1327 .bdf_addr_offset = 0, 1328 1329 .current_cc_support = false, 1330 1331 .dp_primary_link_only = true, 1332 }, 1333 { 1334 .name = "wcn7850 hw2.0", 1335 .hw_rev = ATH12K_HW_WCN7850_HW20, 1336 1337 .fw = { 1338 .dir = "WCN7850/hw2.0", 1339 .board_size = 256 * 1024, 1340 .cal_offset = 256 * 1024, 1341 .m3_loader = ath12k_m3_fw_loader_driver, 1342 }, 1343 1344 .max_radios = 1, 1345 .single_pdev_only = true, 1346 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850, 1347 .internal_sleep_clock = true, 1348 1349 .hw_ops = &wcn7850_ops, 1350 .ring_mask = &ath12k_hw_ring_mask_wcn7850, 1351 .regs = &wcn7850_regs, 1352 1353 .host_ce_config = ath12k_host_ce_config_wcn7850, 1354 .ce_count = 9, 1355 .target_ce_config = ath12k_target_ce_config_wlan_wcn7850, 1356 .target_ce_count = 9, 1357 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850, 1358 .svc_to_ce_map_len = 14, 1359 1360 .hal_params = &ath12k_hw_hal_params_wcn7850, 1361 1362 .rxdma1_enable = false, 1363 .num_rxdma_per_pdev = 2, 1364 .num_rxdma_dst_ring = 1, 1365 .rx_mac_buf_ring = true, 1366 .vdev_start_delay = true, 1367 1368 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 1369 BIT(NL80211_IFTYPE_AP) | 1370 BIT(NL80211_IFTYPE_P2P_DEVICE) | 1371 BIT(NL80211_IFTYPE_P2P_CLIENT) | 1372 BIT(NL80211_IFTYPE_P2P_GO), 1373 .supports_monitor = false, 1374 1375 .idle_ps = true, 1376 .download_calib = false, 1377 .supports_suspend = true, 1378 .tcl_ring_retry = false, 1379 .reoq_lut_support = false, 1380 .supports_shadow_regs = true, 1381 1382 .num_tcl_banks = 7, 1383 .max_tx_ring = 3, 1384 1385 .mhi_config = &ath12k_mhi_config_wcn7850, 1386 1387 .wmi_init = ath12k_wmi_init_wcn7850, 1388 1389 .hal_ops = &hal_wcn7850_ops, 1390 1391 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) | 1392 BIT(CNSS_PCIE_PERST_NO_PULL_V01), 1393 1394 .rfkill_pin = 48, 1395 .rfkill_cfg = 0, 1396 .rfkill_on_level = 1, 1397 1398 .rddm_size = 0x780000, 1399 1400 .def_num_link = 2, 1401 .max_mlo_peer = 32, 1402 1403 .otp_board_id_register = 0, 1404 1405 .supports_sta_ps = true, 1406 1407 .acpi_guid = &wcn7850_uuid, 1408 .supports_dynamic_smps_6ghz = false, 1409 1410 .iova_mask = ATH12K_PCIE_MAX_PAYLOAD_SIZE - 1, 1411 1412 .supports_aspm = true, 1413 1414 .ce_ie_addr = NULL, 1415 .ce_remap = NULL, 1416 .bdf_addr_offset = 0, 1417 1418 .current_cc_support = true, 1419 1420 .dp_primary_link_only = false, 1421 }, 1422 { 1423 .name = "qcn9274 hw2.0", 1424 .hw_rev = ATH12K_HW_QCN9274_HW20, 1425 .fw = { 1426 .dir = "QCN9274/hw2.0", 1427 .board_size = 256 * 1024, 1428 .cal_offset = 128 * 1024, 1429 .m3_loader = ath12k_m3_fw_loader_driver, 1430 }, 1431 .max_radios = 2, 1432 .single_pdev_only = false, 1433 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 1434 .internal_sleep_clock = false, 1435 1436 .hw_ops = &qcn9274_ops, 1437 .ring_mask = &ath12k_hw_ring_mask_qcn9274, 1438 .regs = &qcn9274_v2_regs, 1439 1440 .host_ce_config = ath12k_host_ce_config_qcn9274, 1441 .ce_count = 16, 1442 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 1443 .target_ce_count = 12, 1444 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 1445 .svc_to_ce_map_len = 18, 1446 1447 .hal_params = &ath12k_hw_hal_params_qcn9274, 1448 1449 .rxdma1_enable = true, 1450 .num_rxdma_per_pdev = 1, 1451 .num_rxdma_dst_ring = 0, 1452 .rx_mac_buf_ring = false, 1453 .vdev_start_delay = false, 1454 1455 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 1456 BIT(NL80211_IFTYPE_AP) | 1457 BIT(NL80211_IFTYPE_MESH_POINT) | 1458 BIT(NL80211_IFTYPE_AP_VLAN), 1459 .supports_monitor = true, 1460 1461 .idle_ps = false, 1462 .download_calib = true, 1463 .supports_suspend = false, 1464 .tcl_ring_retry = true, 1465 .reoq_lut_support = false, 1466 .supports_shadow_regs = false, 1467 1468 .num_tcl_banks = 48, 1469 .max_tx_ring = 4, 1470 1471 .mhi_config = &ath12k_mhi_config_qcn9274, 1472 1473 .wmi_init = ath12k_wmi_init_qcn9274, 1474 1475 .hal_ops = &hal_qcn9274_ops, 1476 1477 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 1478 1479 .rfkill_pin = 0, 1480 .rfkill_cfg = 0, 1481 .rfkill_on_level = 0, 1482 1483 .rddm_size = 0x600000, 1484 1485 .def_num_link = 0, 1486 .max_mlo_peer = 256, 1487 1488 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB, 1489 1490 .supports_sta_ps = false, 1491 1492 .acpi_guid = NULL, 1493 .supports_dynamic_smps_6ghz = true, 1494 1495 .iova_mask = 0, 1496 1497 .supports_aspm = false, 1498 1499 .ce_ie_addr = NULL, 1500 .ce_remap = NULL, 1501 .bdf_addr_offset = 0, 1502 1503 .current_cc_support = false, 1504 1505 .dp_primary_link_only = true, 1506 }, 1507 { 1508 .name = "ipq5332 hw1.0", 1509 .hw_rev = ATH12K_HW_IPQ5332_HW10, 1510 .fw = { 1511 .dir = "IPQ5332/hw1.0", 1512 .board_size = 256 * 1024, 1513 .cal_offset = 128 * 1024, 1514 .m3_loader = ath12k_m3_fw_loader_remoteproc, 1515 }, 1516 .max_radios = 1, 1517 .single_pdev_only = false, 1518 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332, 1519 .internal_sleep_clock = false, 1520 1521 .hw_ops = &qcn9274_ops, 1522 .regs = &ipq5332_regs, 1523 .ring_mask = &ath12k_hw_ring_mask_ipq5332, 1524 1525 .host_ce_config = ath12k_host_ce_config_ipq5332, 1526 .ce_count = 12, 1527 .target_ce_config = ath12k_target_ce_config_wlan_ipq5332, 1528 .target_ce_count = 12, 1529 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_ipq5332, 1530 .svc_to_ce_map_len = 18, 1531 1532 .hal_params = &ath12k_hw_hal_params_ipq5332, 1533 1534 .rxdma1_enable = false, 1535 .num_rxdma_per_pdev = 1, 1536 .num_rxdma_dst_ring = 0, 1537 .rx_mac_buf_ring = false, 1538 .vdev_start_delay = false, 1539 1540 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 1541 BIT(NL80211_IFTYPE_AP) | 1542 BIT(NL80211_IFTYPE_MESH_POINT), 1543 .supports_monitor = false, 1544 1545 .idle_ps = false, 1546 .download_calib = true, 1547 .supports_suspend = false, 1548 .tcl_ring_retry = true, 1549 .reoq_lut_support = false, 1550 .supports_shadow_regs = false, 1551 1552 .num_tcl_banks = 48, 1553 .max_tx_ring = 4, 1554 1555 .wmi_init = &ath12k_wmi_init_qcn9274, 1556 1557 .hal_ops = &hal_qcn9274_ops, 1558 1559 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 1560 1561 .rfkill_pin = 0, 1562 .rfkill_cfg = 0, 1563 .rfkill_on_level = 0, 1564 1565 .rddm_size = 0, 1566 1567 .def_num_link = 0, 1568 .max_mlo_peer = 256, 1569 1570 .otp_board_id_register = 0, 1571 1572 .supports_sta_ps = false, 1573 1574 .acpi_guid = NULL, 1575 .supports_dynamic_smps_6ghz = false, 1576 .iova_mask = 0, 1577 .supports_aspm = false, 1578 1579 .ce_ie_addr = &ath12k_ce_ie_addr_ipq5332, 1580 .ce_remap = &ath12k_ce_remap_ipq5332, 1581 .bdf_addr_offset = 0xC00000, 1582 1583 .dp_primary_link_only = true, 1584 }, 1585 }; 1586 1587 int ath12k_hw_init(struct ath12k_base *ab) 1588 { 1589 const struct ath12k_hw_params *hw_params = NULL; 1590 int i; 1591 1592 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) { 1593 hw_params = &ath12k_hw_params[i]; 1594 1595 if (hw_params->hw_rev == ab->hw_rev) 1596 break; 1597 } 1598 1599 if (i == ARRAY_SIZE(ath12k_hw_params)) { 1600 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1601 return -EINVAL; 1602 } 1603 1604 ab->hw_params = hw_params; 1605 1606 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name); 1607 1608 return 0; 1609 } 1610