1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_HAL_RX_H 8 #define ATH12K_HAL_RX_H 9 10 struct hal_rx_wbm_rel_info { 11 u32 cookie; 12 enum hal_wbm_rel_src_module err_rel_src; 13 enum hal_reo_dest_ring_push_reason push_reason; 14 u32 err_code; 15 bool first_msdu; 16 bool last_msdu; 17 bool continuation; 18 void *rx_desc; 19 bool hw_cc_done; 20 }; 21 22 #define HAL_INVALID_PEERID 0x3fff 23 #define VHT_SIG_SU_NSS_MASK 0x7 24 25 #define HAL_RX_MAX_MCS 12 26 #define HAL_RX_MAX_NSS 8 27 28 #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \ 29 le32_get_bits((__val), GENMASK(7, 0)) 30 31 #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \ 32 le32_get_bits((__val), GENMASK(15, 8)) 33 34 #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \ 35 le32_get_bits((__val), GENMASK(23, 16)) 36 37 #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \ 38 le32_get_bits((__val), GENMASK(31, 24)) 39 40 struct hal_rx_mon_status_tlv_hdr { 41 u32 hdr; 42 u8 value[]; 43 }; 44 45 enum hal_rx_su_mu_coding { 46 HAL_RX_SU_MU_CODING_BCC, 47 HAL_RX_SU_MU_CODING_LDPC, 48 HAL_RX_SU_MU_CODING_MAX, 49 }; 50 51 enum hal_rx_gi { 52 HAL_RX_GI_0_8_US, 53 HAL_RX_GI_0_4_US, 54 HAL_RX_GI_1_6_US, 55 HAL_RX_GI_3_2_US, 56 HAL_RX_GI_MAX, 57 }; 58 59 enum hal_rx_bw { 60 HAL_RX_BW_20MHZ, 61 HAL_RX_BW_40MHZ, 62 HAL_RX_BW_80MHZ, 63 HAL_RX_BW_160MHZ, 64 HAL_RX_BW_320MHZ, 65 HAL_RX_BW_MAX, 66 }; 67 68 enum hal_rx_preamble { 69 HAL_RX_PREAMBLE_11A, 70 HAL_RX_PREAMBLE_11B, 71 HAL_RX_PREAMBLE_11N, 72 HAL_RX_PREAMBLE_11AC, 73 HAL_RX_PREAMBLE_11AX, 74 HAL_RX_PREAMBLE_MAX, 75 }; 76 77 enum hal_rx_reception_type { 78 HAL_RX_RECEPTION_TYPE_SU, 79 HAL_RX_RECEPTION_TYPE_MU_MIMO, 80 HAL_RX_RECEPTION_TYPE_MU_OFDMA, 81 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO, 82 HAL_RX_RECEPTION_TYPE_MAX, 83 }; 84 85 enum hal_rx_legacy_rate { 86 HAL_RX_LEGACY_RATE_1_MBPS, 87 HAL_RX_LEGACY_RATE_2_MBPS, 88 HAL_RX_LEGACY_RATE_5_5_MBPS, 89 HAL_RX_LEGACY_RATE_6_MBPS, 90 HAL_RX_LEGACY_RATE_9_MBPS, 91 HAL_RX_LEGACY_RATE_11_MBPS, 92 HAL_RX_LEGACY_RATE_12_MBPS, 93 HAL_RX_LEGACY_RATE_18_MBPS, 94 HAL_RX_LEGACY_RATE_24_MBPS, 95 HAL_RX_LEGACY_RATE_36_MBPS, 96 HAL_RX_LEGACY_RATE_48_MBPS, 97 HAL_RX_LEGACY_RATE_54_MBPS, 98 HAL_RX_LEGACY_RATE_INVALID, 99 }; 100 101 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 102 #define HAL_TLV_STATUS_PPDU_DONE 1 103 #define HAL_TLV_STATUS_BUF_DONE 2 104 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 105 #define HAL_RX_FCS_LEN 4 106 107 enum hal_rx_mon_status { 108 HAL_RX_MON_STATUS_PPDU_NOT_DONE, 109 HAL_RX_MON_STATUS_PPDU_DONE, 110 HAL_RX_MON_STATUS_BUF_DONE, 111 }; 112 113 #define HAL_RX_MAX_MPDU 256 114 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 115 116 struct hal_rx_user_status { 117 u32 mcs:4, 118 nss:3, 119 ofdma_info_valid:1, 120 ul_ofdma_ru_start_index:7, 121 ul_ofdma_ru_width:7, 122 ul_ofdma_ru_size:8; 123 u32 ul_ofdma_user_v0_word0; 124 u32 ul_ofdma_user_v0_word1; 125 u32 ast_index; 126 u32 tid; 127 u16 tcp_msdu_count; 128 u16 tcp_ack_msdu_count; 129 u16 udp_msdu_count; 130 u16 other_msdu_count; 131 u16 frame_control; 132 u8 frame_control_info_valid; 133 u8 data_sequence_control_info_valid; 134 u16 first_data_seq_ctrl; 135 u32 preamble_type; 136 u16 ht_flags; 137 u16 vht_flags; 138 u16 he_flags; 139 u8 rs_flags; 140 u8 ldpc; 141 u32 mpdu_cnt_fcs_ok; 142 u32 mpdu_cnt_fcs_err; 143 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 144 u32 mpdu_ok_byte_count; 145 u32 mpdu_err_byte_count; 146 }; 147 148 #define HAL_MAX_UL_MU_USERS 37 149 150 struct hal_rx_mon_ppdu_info { 151 u32 ppdu_id; 152 u32 last_ppdu_id; 153 u64 ppdu_ts; 154 u32 num_mpdu_fcs_ok; 155 u32 num_mpdu_fcs_err; 156 u32 preamble_type; 157 u32 mpdu_len; 158 u16 chan_num; 159 u16 freq; 160 u16 tcp_msdu_count; 161 u16 tcp_ack_msdu_count; 162 u16 udp_msdu_count; 163 u16 other_msdu_count; 164 u16 peer_id; 165 u8 rate; 166 u8 mcs; 167 u8 nss; 168 u8 bw; 169 u8 vht_flag_values1; 170 u8 vht_flag_values2; 171 u8 vht_flag_values3[4]; 172 u8 vht_flag_values4; 173 u8 vht_flag_values5; 174 u16 vht_flag_values6; 175 u8 is_stbc; 176 u8 gi; 177 u8 sgi; 178 u8 ldpc; 179 u8 beamformed; 180 u8 rssi_comb; 181 u16 tid; 182 u8 fc_valid; 183 u16 ht_flags; 184 u16 vht_flags; 185 u16 he_flags; 186 u16 he_mu_flags; 187 u8 dcm; 188 u8 ru_alloc; 189 u8 reception_type; 190 u64 tsft; 191 u64 rx_duration; 192 u16 frame_control; 193 u32 ast_index; 194 u8 rs_fcs_err; 195 u8 rs_flags; 196 u8 cck_flag; 197 u8 ofdm_flag; 198 u8 ulofdma_flag; 199 u8 frame_control_info_valid; 200 u16 he_per_user_1; 201 u16 he_per_user_2; 202 u8 he_per_user_position; 203 u8 he_per_user_known; 204 u16 he_flags1; 205 u16 he_flags2; 206 u8 he_RU[4]; 207 u16 he_data1; 208 u16 he_data2; 209 u16 he_data3; 210 u16 he_data4; 211 u16 he_data5; 212 u16 he_data6; 213 u32 ppdu_len; 214 u32 prev_ppdu_id; 215 u32 device_id; 216 u16 first_data_seq_ctrl; 217 u8 monitor_direct_used; 218 u8 data_sequence_control_info_valid; 219 u8 ltf_size; 220 u8 rxpcu_filter_pass; 221 s8 rssi_chain[8][8]; 222 u32 num_users; 223 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 224 u8 addr1[ETH_ALEN]; 225 u8 addr2[ETH_ALEN]; 226 u8 addr3[ETH_ALEN]; 227 u8 addr4[ETH_ALEN]; 228 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS]; 229 u8 userid; 230 u16 ampdu_id[HAL_MAX_UL_MU_USERS]; 231 bool first_msdu_in_mpdu; 232 bool is_ampdu; 233 u8 medium_prot_type; 234 }; 235 236 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0) 237 #define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0) 238 #define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16) 239 240 struct hal_rx_ppdu_start { 241 __le32 info0; 242 __le32 info1; 243 __le32 ppdu_start_ts_31_0; 244 __le32 ppdu_start_ts_63_32; 245 __le32 rsvd[2]; 246 } __packed; 247 248 #define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0) 249 #define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID GENMASK(15, 14) 250 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16) 251 252 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0) 253 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(11) 254 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(12) 255 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(13) 256 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21) 257 258 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0) 259 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16) 260 261 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16) 262 263 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0) 264 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16) 265 266 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0) 267 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16) 268 269 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0) 270 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16) 271 272 #define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0) 273 #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0) 274 275 struct hal_rx_ppdu_end_user_stats { 276 __le32 rsvd0[2]; 277 __le32 info0; 278 __le32 info1; 279 __le32 info2; 280 __le32 info3; 281 __le32 ht_ctrl; 282 __le32 rsvd1[2]; 283 __le32 info4; 284 __le32 info5; 285 __le32 usr_resp_ref; 286 __le32 info6; 287 __le32 rsvd3[4]; 288 __le32 info7; 289 __le32 rsvd4; 290 __le32 info8; 291 __le32 rsvd5[2]; 292 __le32 usr_resp_ref_ext; 293 __le32 rsvd6; 294 } __packed; 295 296 struct hal_rx_ppdu_end_user_stats_ext { 297 __le32 info0; 298 __le32 info1; 299 __le32 info2; 300 __le32 info3; 301 __le32 info4; 302 __le32 info5; 303 __le32 info6; 304 __le32 rsvd; 305 } __packed; 306 307 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0) 308 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7) 309 310 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4) 311 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6) 312 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7) 313 314 struct hal_rx_ht_sig_info { 315 __le32 info0; 316 __le32 info1; 317 } __packed; 318 319 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0) 320 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4) 321 322 struct hal_rx_lsig_b_info { 323 __le32 info0; 324 } __packed; 325 326 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0) 327 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5) 328 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24) 329 330 struct hal_rx_lsig_a_info { 331 __le32 info0; 332 } __packed; 333 334 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0) 335 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3) 336 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4) 337 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10) 338 339 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0) 340 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2) 341 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4) 342 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8) 343 344 struct hal_rx_vht_sig_a_info { 345 __le32 info0; 346 __le32 info1; 347 } __packed; 348 349 enum hal_rx_vht_sig_a_gi_setting { 350 HAL_RX_VHT_SIG_A_NORMAL_GI = 0, 351 HAL_RX_VHT_SIG_A_SHORT_GI = 1, 352 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3, 353 }; 354 355 #define HE_GI_0_8 0 356 #define HE_GI_0_4 1 357 #define HE_GI_1_6 2 358 #define HE_GI_3_2 3 359 360 #define HE_LTF_1_X 0 361 #define HE_LTF_2_X 1 362 #define HE_LTF_4_X 2 363 364 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3) 365 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7) 366 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19) 367 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21) 368 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23) 369 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8) 370 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15) 371 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0) 372 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1) 373 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2) 374 375 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0) 376 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7) 377 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8) 378 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9) 379 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10) 380 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11) 381 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13) 382 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15) 383 384 struct hal_rx_he_sig_a_su_info { 385 __le32 info0; 386 __le32 info1; 387 } __packed; 388 389 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1) 390 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1) 391 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4) 392 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5) 393 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11) 394 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15) 395 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18) 396 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22) 397 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23) 398 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25) 399 400 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0) 401 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8) 402 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11) 403 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12) 404 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13) 405 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15) 406 407 struct hal_rx_he_sig_a_mu_dl_info { 408 __le32 info0; 409 __le32 info1; 410 } __packed; 411 412 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0) 413 414 struct hal_rx_he_sig_b1_mu_info { 415 __le32 info0; 416 } __packed; 417 418 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0) 419 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15) 420 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20) 421 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29) 422 423 struct hal_rx_he_sig_b2_mu_info { 424 __le32 info0; 425 } __packed; 426 427 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0) 428 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11) 429 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(14) 430 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15) 431 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19) 432 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20) 433 434 struct hal_rx_he_sig_b2_ofdma_info { 435 __le32 info0; 436 } __packed; 437 438 enum hal_rx_ul_reception_type { 439 HAL_RECEPTION_TYPE_ULOFMDA, 440 HAL_RECEPTION_TYPE_ULMIMO, 441 HAL_RECEPTION_TYPE_OTHER, 442 HAL_RECEPTION_TYPE_FRAMELESS 443 }; 444 445 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0) 446 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5) 447 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8) 448 449 struct hal_rx_phyrx_rssi_legacy_info { 450 __le32 info0; 451 __le32 rsvd0[39]; 452 __le32 info1; 453 __le32 rsvd1; 454 } __packed; 455 456 #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) 457 #define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16) 458 #define HAL_RX_MPDU_START_INFO1_DEVICE_ID GENMASK(31, 30) 459 #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0) 460 struct hal_rx_mpdu_start { 461 __le32 rsvd0[9]; 462 __le32 info0; 463 __le32 info1; 464 __le32 rsvd1[2]; 465 __le32 info2; 466 __le32 rsvd2[16]; 467 } __packed; 468 469 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0) 470 struct hal_rx_ppdu_end_duration { 471 __le32 rsvd0[9]; 472 __le32 info0; 473 __le32 rsvd1[18]; 474 } __packed; 475 476 struct hal_rx_rxpcu_classification_overview { 477 u32 rsvd0; 478 } __packed; 479 480 struct hal_rx_msdu_desc_info { 481 u32 msdu_flags; 482 u16 msdu_len; /* 14 bits for length */ 483 }; 484 485 #define HAL_RX_NUM_MSDU_DESC 6 486 struct hal_rx_msdu_list { 487 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 488 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC]; 489 u8 rbm[HAL_RX_NUM_MSDU_DESC]; 490 }; 491 492 #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0) 493 #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0) 494 #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16) 495 #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0) 496 497 struct hal_rx_frame_bitmap_ack { 498 __le32 reserved; 499 __le32 info0; 500 __le32 info1; 501 __le32 info2; 502 __le32 reserved1[10]; 503 } __packed; 504 505 #define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0) 506 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16) 507 #define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0) 508 #define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21) 509 #define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25) 510 #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27) 511 #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28) 512 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29) 513 #define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0) 514 #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0) 515 #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0) 516 #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16) 517 #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0) 518 519 struct hal_rx_resp_req_info { 520 __le32 info0; 521 __le32 reserved[1]; 522 __le32 info1; 523 __le32 info2; 524 __le32 reserved1[2]; 525 __le32 info3; 526 __le32 info4; 527 __le32 info5; 528 __le32 reserved2[5]; 529 } __packed; 530 531 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF 532 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF 533 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF 534 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF 535 536 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30) 537 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31) 538 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0) 539 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3) 540 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7) 541 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8) 542 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9) 543 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16) 544 545 /* HE Radiotap data1 Mask */ 546 #define HE_SU_FORMAT_TYPE 0x0000 547 #define HE_EXT_SU_FORMAT_TYPE 0x0001 548 #define HE_MU_FORMAT_TYPE 0x0002 549 #define HE_TRIG_FORMAT_TYPE 0x0003 550 #define HE_BEAM_CHANGE_KNOWN 0x0008 551 #define HE_DL_UL_KNOWN 0x0010 552 #define HE_MCS_KNOWN 0x0020 553 #define HE_DCM_KNOWN 0x0040 554 #define HE_CODING_KNOWN 0x0080 555 #define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100 556 #define HE_STBC_KNOWN 0x0200 557 #define HE_DATA_BW_RU_KNOWN 0x4000 558 #define HE_DOPPLER_KNOWN 0x8000 559 #define HE_BSS_COLOR_KNOWN 0x0004 560 561 /* HE Radiotap data2 Mask */ 562 #define HE_GI_KNOWN 0x0002 563 #define HE_TXBF_KNOWN 0x0010 564 #define HE_PE_DISAMBIGUITY_KNOWN 0x0020 565 #define HE_TXOP_KNOWN 0x0040 566 #define HE_LTF_SYMBOLS_KNOWN 0x0004 567 #define HE_PRE_FEC_PADDING_KNOWN 0x0008 568 #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080 569 570 /* HE radiotap data3 shift values */ 571 #define HE_BEAM_CHANGE_SHIFT 6 572 #define HE_DL_UL_SHIFT 7 573 #define HE_TRANSMIT_MCS_SHIFT 8 574 #define HE_DCM_SHIFT 12 575 #define HE_CODING_SHIFT 13 576 #define HE_LDPC_EXTRA_SYMBOL_SHIFT 14 577 #define HE_STBC_SHIFT 15 578 579 /* HE radiotap data4 shift values */ 580 #define HE_STA_ID_SHIFT 4 581 582 /* HE radiotap data5 */ 583 #define HE_GI_SHIFT 4 584 #define HE_LTF_SIZE_SHIFT 6 585 #define HE_LTF_SYM_SHIFT 8 586 #define HE_TXBF_SHIFT 14 587 #define HE_PE_DISAMBIGUITY_SHIFT 15 588 #define HE_PRE_FEC_PAD_SHIFT 12 589 590 /* HE radiotap data6 */ 591 #define HE_DOPPLER_SHIFT 4 592 #define HE_TXOP_SHIFT 8 593 594 /* HE radiotap HE-MU flags1 */ 595 #define HE_SIG_B_MCS_KNOWN 0x0010 596 #define HE_SIG_B_DCM_KNOWN 0x0040 597 #define HE_SIG_B_SYM_NUM_KNOWN 0x8000 598 #define HE_RU_0_KNOWN 0x0100 599 #define HE_RU_1_KNOWN 0x0200 600 #define HE_RU_2_KNOWN 0x0400 601 #define HE_RU_3_KNOWN 0x0800 602 #define HE_DCM_FLAG_1_SHIFT 5 603 #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100 604 #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000 605 606 /* HE radiotap HE-MU flags2 */ 607 #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3 608 #define HE_BW_KNOWN 0x0004 609 #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4 610 #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100 611 #define HE_NUM_SIG_B_FLAG_2_SHIFT 9 612 #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12 613 #define HE_LTF_KNOWN 0x8000 614 615 /* HE radiotap per_user_1 */ 616 #define HE_STA_SPATIAL_SHIFT 11 617 #define HE_TXBF_SHIFT 14 618 #define HE_RESERVED_SET_TO_1_SHIFT 19 619 #define HE_STA_CODING_SHIFT 20 620 621 /* HE radiotap per_user_2 */ 622 #define HE_STA_MCS_SHIFT 4 623 #define HE_STA_DCM_SHIFT 5 624 625 /* HE radiotap per user known */ 626 #define HE_USER_FIELD_POSITION_KNOWN 0x01 627 #define HE_STA_ID_PER_USER_KNOWN 0x02 628 #define HE_STA_NSTS_KNOWN 0x04 629 #define HE_STA_TX_BF_KNOWN 0x08 630 #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10 631 #define HE_STA_MCS_KNOWN 0x20 632 #define HE_STA_DCM_KNOWN 0x40 633 #define HE_STA_CODING_KNOWN 0x80 634 635 #define HAL_RX_MPDU_ERR_FCS BIT(0) 636 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1) 637 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2) 638 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3) 639 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4) 640 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5) 641 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6) 642 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) 643 644 static inline 645 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) 646 { 647 enum nl80211_he_ru_alloc ret; 648 649 switch (ru_tones) { 650 case RU_52: 651 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; 652 break; 653 case RU_106: 654 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; 655 break; 656 case RU_242: 657 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; 658 break; 659 case RU_484: 660 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; 661 break; 662 case RU_996: 663 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; 664 break; 665 case RU_26: 666 fallthrough; 667 default: 668 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; 669 break; 670 } 671 return ret; 672 } 673 674 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, 675 struct hal_tlv_64_hdr *tlv, 676 struct hal_reo_status *status); 677 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, 678 struct hal_tlv_64_hdr *tlv, 679 struct hal_reo_status *status); 680 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, 681 struct hal_tlv_64_hdr *tlv, 682 struct hal_reo_status *status); 683 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, 684 struct hal_tlv_64_hdr *tlv, 685 struct hal_reo_status *status); 686 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, 687 struct hal_tlv_64_hdr *tlv, 688 struct hal_reo_status *status); 689 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, 690 struct hal_tlv_64_hdr *tlv, 691 struct hal_reo_status *status); 692 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, 693 struct hal_tlv_64_hdr *tlv, 694 struct hal_reo_status *status); 695 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus, 696 u32 *msdu_cookies, 697 enum hal_rx_buf_return_buf_manager *rbm); 698 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, 699 struct hal_wbm_release_ring *dst_desc, 700 struct hal_wbm_release_ring *src_desc, 701 enum hal_wbm_rel_bm_act action); 702 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, 703 dma_addr_t paddr, u32 cookie, u8 manager); 704 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, 705 dma_addr_t *paddr, 706 u32 *cookie, u8 *rbm); 707 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab, 708 struct hal_reo_dest_ring *desc, 709 dma_addr_t *paddr, u32 *desc_bank); 710 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc, 711 struct hal_rx_wbm_rel_info *rel_info); 712 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab, 713 struct ath12k_buffer_addr *buff_addr, 714 dma_addr_t *paddr, u32 *cookie); 715 716 #endif 717