1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "debug.h" 8 #include "hal.h" 9 #include "hal_tx.h" 10 #include "hal_rx.h" 11 #include "hal_desc.h" 12 #include "hif.h" 13 14 static void ath12k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, 15 u8 owner, u8 buffer_type, u32 magic) 16 { 17 hdr->info0 = le32_encode_bits(owner, HAL_DESC_HDR_INFO0_OWNER) | 18 le32_encode_bits(buffer_type, HAL_DESC_HDR_INFO0_BUF_TYPE); 19 20 /* Magic pattern in reserved bits for debugging */ 21 hdr->info0 |= le32_encode_bits(magic, HAL_DESC_HDR_INFO0_DBG_RESERVED); 22 } 23 24 static int ath12k_hal_reo_cmd_queue_stats(struct hal_tlv_64_hdr *tlv, 25 struct ath12k_hal_reo_cmd *cmd) 26 { 27 struct hal_reo_get_queue_stats *desc; 28 29 tlv->tl = le64_encode_bits(HAL_REO_GET_QUEUE_STATS, HAL_TLV_HDR_TAG) | 30 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN); 31 32 desc = (struct hal_reo_get_queue_stats *)tlv->value; 33 memset_startat(desc, 0, queue_addr_lo); 34 35 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 37 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 38 39 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo); 40 desc->info0 = le32_encode_bits(cmd->addr_hi, 41 HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI); 42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR) 43 desc->info0 |= cpu_to_le32(HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS); 44 45 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 46 } 47 48 static int ath12k_hal_reo_cmd_flush_cache(struct ath12k_hal *hal, 49 struct hal_tlv_64_hdr *tlv, 50 struct ath12k_hal_reo_cmd *cmd) 51 { 52 struct hal_reo_flush_cache *desc; 53 u8 avail_slot = ffz(hal->avail_blk_resource); 54 55 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 56 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES) 57 return -ENOSPC; 58 59 hal->current_blk_index = avail_slot; 60 } 61 62 tlv->tl = le64_encode_bits(HAL_REO_FLUSH_CACHE, HAL_TLV_HDR_TAG) | 63 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN); 64 65 desc = (struct hal_reo_flush_cache *)tlv->value; 66 memset_startat(desc, 0, cache_addr_lo); 67 68 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 69 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 70 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 71 72 desc->cache_addr_lo = cpu_to_le32(cmd->addr_lo); 73 desc->info0 = le32_encode_bits(cmd->addr_hi, 74 HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI); 75 76 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS) 77 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS); 78 79 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 80 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE); 81 desc->info0 |= 82 le32_encode_bits(avail_slot, 83 HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX); 84 } 85 86 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL) 87 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE); 88 89 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 90 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL); 91 92 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC) 93 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC); 94 95 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 96 } 97 98 static int ath12k_hal_reo_cmd_update_rx_queue(struct hal_tlv_64_hdr *tlv, 99 struct ath12k_hal_reo_cmd *cmd) 100 { 101 struct hal_reo_update_rx_queue *desc; 102 103 tlv->tl = le64_encode_bits(HAL_REO_UPDATE_RX_REO_QUEUE, HAL_TLV_HDR_TAG) | 104 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN); 105 106 desc = (struct hal_reo_update_rx_queue *)tlv->value; 107 memset_startat(desc, 0, queue_addr_lo); 108 109 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 110 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 111 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 112 113 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo); 114 desc->info0 = 115 le32_encode_bits(cmd->addr_hi, 116 HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI) | 117 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM), 118 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM) | 119 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD), 120 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD) | 121 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC), 122 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT) | 123 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION), 124 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION) | 125 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN), 126 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN) | 127 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_AC), 128 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC) | 129 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR), 130 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR) | 131 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY), 132 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY) | 133 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE), 134 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE) | 135 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE), 136 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE) | 137 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE), 138 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE) | 139 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK), 140 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK) | 141 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN), 142 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN) | 143 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN), 144 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN) | 145 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE), 146 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE) | 147 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE), 148 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE) | 149 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG), 150 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG) | 151 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD), 152 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD) | 153 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN), 154 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN) | 155 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR), 156 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR) | 157 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID), 158 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID) | 159 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN), 160 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN); 161 162 desc->info1 = 163 le32_encode_bits(cmd->rx_queue_num, 164 HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER) | 165 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD), 166 HAL_REO_UPD_RX_QUEUE_INFO1_VLD) | 167 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_ALDC), 168 HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER) | 169 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION), 170 HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION) | 171 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN), 172 HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN) | 173 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_AC), 174 HAL_REO_UPD_RX_QUEUE_INFO1_AC) | 175 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR), 176 HAL_REO_UPD_RX_QUEUE_INFO1_BAR) | 177 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE), 178 HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE) | 179 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY), 180 HAL_REO_UPD_RX_QUEUE_INFO1_RETRY) | 181 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE), 182 HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE) | 183 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK), 184 HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK) | 185 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN), 186 HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN) | 187 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN), 188 HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN) | 189 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE), 190 HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE) | 191 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG), 192 HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG); 193 194 if (cmd->pn_size == 24) 195 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24; 196 else if (cmd->pn_size == 48) 197 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48; 198 else if (cmd->pn_size == 128) 199 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128; 200 201 if (cmd->ba_window_size < 1) 202 cmd->ba_window_size = 1; 203 204 if (cmd->ba_window_size == 1) 205 cmd->ba_window_size++; 206 207 desc->info2 = 208 le32_encode_bits(cmd->ba_window_size - 1, 209 HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE) | 210 le32_encode_bits(cmd->pn_size, HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE) | 211 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD), 212 HAL_REO_UPD_RX_QUEUE_INFO2_SVLD) | 213 le32_encode_bits(u32_get_bits(cmd->upd2, HAL_REO_CMD_UPD2_SSN), 214 HAL_REO_UPD_RX_QUEUE_INFO2_SSN) | 215 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR), 216 HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR) | 217 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR), 218 HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR); 219 220 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 221 } 222 223 int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, 224 enum hal_reo_cmd_type type, 225 struct ath12k_hal_reo_cmd *cmd) 226 { 227 struct hal_tlv_64_hdr *reo_desc; 228 int ret; 229 230 spin_lock_bh(&srng->lock); 231 232 ath12k_hal_srng_access_begin(ab, srng); 233 reo_desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 234 if (!reo_desc) { 235 ret = -ENOBUFS; 236 goto out; 237 } 238 239 switch (type) { 240 case HAL_REO_CMD_GET_QUEUE_STATS: 241 ret = ath12k_hal_reo_cmd_queue_stats(reo_desc, cmd); 242 break; 243 case HAL_REO_CMD_FLUSH_CACHE: 244 ret = ath12k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd); 245 break; 246 case HAL_REO_CMD_UPDATE_RX_QUEUE: 247 ret = ath12k_hal_reo_cmd_update_rx_queue(reo_desc, cmd); 248 break; 249 case HAL_REO_CMD_FLUSH_QUEUE: 250 case HAL_REO_CMD_UNBLOCK_CACHE: 251 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST: 252 ath12k_warn(ab, "Unsupported reo command %d\n", type); 253 ret = -EOPNOTSUPP; 254 break; 255 default: 256 ath12k_warn(ab, "Unknown reo command %d\n", type); 257 ret = -EINVAL; 258 break; 259 } 260 261 out: 262 ath12k_hal_srng_access_end(ab, srng); 263 spin_unlock_bh(&srng->lock); 264 265 return ret; 266 } 267 268 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, 269 dma_addr_t paddr, u32 cookie, u8 manager) 270 { 271 u32 paddr_lo, paddr_hi; 272 273 paddr_lo = lower_32_bits(paddr); 274 paddr_hi = upper_32_bits(paddr); 275 binfo->info0 = le32_encode_bits(paddr_lo, BUFFER_ADDR_INFO0_ADDR); 276 binfo->info1 = le32_encode_bits(paddr_hi, BUFFER_ADDR_INFO1_ADDR) | 277 le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE) | 278 le32_encode_bits(manager, BUFFER_ADDR_INFO1_RET_BUF_MGR); 279 } 280 281 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, 282 dma_addr_t *paddr, 283 u32 *cookie, u8 *rbm) 284 { 285 *paddr = (((u64)le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_ADDR)) << 32) | 286 le32_get_bits(binfo->info0, BUFFER_ADDR_INFO0_ADDR); 287 *cookie = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_SW_COOKIE); 288 *rbm = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_RET_BUF_MGR); 289 } 290 291 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus, 292 u32 *msdu_cookies, 293 enum hal_rx_buf_return_buf_manager *rbm) 294 { 295 struct hal_rx_msdu_details *msdu; 296 u32 val; 297 int i; 298 299 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC; 300 301 msdu = &link->msdu_link[0]; 302 *rbm = le32_get_bits(msdu->buf_addr_info.info1, 303 BUFFER_ADDR_INFO1_RET_BUF_MGR); 304 305 for (i = 0; i < *num_msdus; i++) { 306 msdu = &link->msdu_link[i]; 307 308 val = le32_get_bits(msdu->buf_addr_info.info0, 309 BUFFER_ADDR_INFO0_ADDR); 310 if (val == 0) { 311 *num_msdus = i; 312 break; 313 } 314 *msdu_cookies = le32_get_bits(msdu->buf_addr_info.info1, 315 BUFFER_ADDR_INFO1_SW_COOKIE); 316 msdu_cookies++; 317 } 318 } 319 320 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab, 321 struct hal_reo_dest_ring *desc, 322 dma_addr_t *paddr, u32 *desc_bank) 323 { 324 enum hal_reo_dest_ring_push_reason push_reason; 325 enum hal_reo_dest_ring_error_code err_code; 326 u32 cookie, val; 327 328 push_reason = le32_get_bits(desc->info0, 329 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 330 err_code = le32_get_bits(desc->info0, 331 HAL_REO_DEST_RING_INFO0_ERROR_CODE); 332 ab->device_stats.reo_error[err_code]++; 333 334 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED && 335 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 336 ath12k_warn(ab, "expected error push reason code, received %d\n", 337 push_reason); 338 return -EINVAL; 339 } 340 341 val = le32_get_bits(desc->info0, HAL_REO_DEST_RING_INFO0_BUFFER_TYPE); 342 if (val != HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) { 343 ath12k_warn(ab, "expected buffer type link_desc"); 344 return -EINVAL; 345 } 346 347 ath12k_hal_rx_reo_ent_paddr_get(ab, &desc->buf_addr_info, paddr, &cookie); 348 *desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 349 350 return 0; 351 } 352 353 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc, 354 struct hal_rx_wbm_rel_info *rel_info) 355 { 356 struct hal_wbm_release_ring *wbm_desc = desc; 357 struct hal_wbm_release_ring_cc_rx *wbm_cc_desc = desc; 358 enum hal_wbm_rel_desc_type type; 359 enum hal_wbm_rel_src_module rel_src; 360 bool hw_cc_done; 361 u64 desc_va; 362 u32 val; 363 364 type = le32_get_bits(wbm_desc->info0, HAL_WBM_RELEASE_INFO0_DESC_TYPE); 365 /* We expect only WBM_REL buffer type */ 366 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) { 367 WARN_ON(1); 368 return -EINVAL; 369 } 370 371 rel_src = le32_get_bits(wbm_desc->info0, 372 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE); 373 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA && 374 rel_src != HAL_WBM_REL_SRC_MODULE_REO) 375 return -EINVAL; 376 377 /* The format of wbm rel ring desc changes based on the 378 * hw cookie conversion status 379 */ 380 hw_cc_done = le32_get_bits(wbm_desc->info0, 381 HAL_WBM_RELEASE_RX_INFO0_CC_STATUS); 382 383 if (!hw_cc_done) { 384 val = le32_get_bits(wbm_desc->buf_addr_info.info1, 385 BUFFER_ADDR_INFO1_RET_BUF_MGR); 386 if (val != HAL_RX_BUF_RBM_SW3_BM) { 387 ab->device_stats.invalid_rbm++; 388 return -EINVAL; 389 } 390 391 rel_info->cookie = le32_get_bits(wbm_desc->buf_addr_info.info1, 392 BUFFER_ADDR_INFO1_SW_COOKIE); 393 394 rel_info->rx_desc = NULL; 395 } else { 396 val = le32_get_bits(wbm_cc_desc->info0, 397 HAL_WBM_RELEASE_RX_CC_INFO0_RBM); 398 if (val != HAL_RX_BUF_RBM_SW3_BM) { 399 ab->device_stats.invalid_rbm++; 400 return -EINVAL; 401 } 402 403 rel_info->cookie = le32_get_bits(wbm_cc_desc->info1, 404 HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE); 405 406 desc_va = ((u64)le32_to_cpu(wbm_cc_desc->buf_va_hi) << 32 | 407 le32_to_cpu(wbm_cc_desc->buf_va_lo)); 408 rel_info->rx_desc = 409 (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 410 } 411 412 rel_info->err_rel_src = rel_src; 413 rel_info->hw_cc_done = hw_cc_done; 414 415 rel_info->first_msdu = le32_get_bits(wbm_desc->info3, 416 HAL_WBM_RELEASE_INFO3_FIRST_MSDU); 417 rel_info->last_msdu = le32_get_bits(wbm_desc->info3, 418 HAL_WBM_RELEASE_INFO3_LAST_MSDU); 419 rel_info->continuation = le32_get_bits(wbm_desc->info3, 420 HAL_WBM_RELEASE_INFO3_CONTINUATION); 421 422 if (rel_info->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO) { 423 rel_info->push_reason = 424 le32_get_bits(wbm_desc->info0, 425 HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON); 426 rel_info->err_code = 427 le32_get_bits(wbm_desc->info0, 428 HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE); 429 } else { 430 rel_info->push_reason = 431 le32_get_bits(wbm_desc->info0, 432 HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON); 433 rel_info->err_code = 434 le32_get_bits(wbm_desc->info0, 435 HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE); 436 } 437 438 return 0; 439 } 440 441 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab, 442 struct ath12k_buffer_addr *buff_addr, 443 dma_addr_t *paddr, u32 *cookie) 444 { 445 *paddr = ((u64)(le32_get_bits(buff_addr->info1, 446 BUFFER_ADDR_INFO1_ADDR)) << 32) | 447 le32_get_bits(buff_addr->info0, BUFFER_ADDR_INFO0_ADDR); 448 449 *cookie = le32_get_bits(buff_addr->info1, BUFFER_ADDR_INFO1_SW_COOKIE); 450 } 451 452 void ath12k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, 453 u32 *sw_cookie, 454 struct ath12k_buffer_addr **pp_buf_addr, 455 u8 *rbm, u32 *msdu_cnt) 456 { 457 struct hal_reo_entrance_ring *reo_ent_ring = 458 (struct hal_reo_entrance_ring *)rx_desc; 459 struct ath12k_buffer_addr *buf_addr_info; 460 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 461 462 rx_mpdu_desc_info_details = 463 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info; 464 465 *msdu_cnt = le32_get_bits(rx_mpdu_desc_info_details->info0, 466 RX_MPDU_DESC_INFO0_MSDU_COUNT); 467 468 buf_addr_info = (struct ath12k_buffer_addr *)&reo_ent_ring->buf_addr_info; 469 470 *paddr = (((u64)le32_get_bits(buf_addr_info->info1, 471 BUFFER_ADDR_INFO1_ADDR)) << 32) | 472 le32_get_bits(buf_addr_info->info0, 473 BUFFER_ADDR_INFO0_ADDR); 474 475 *sw_cookie = le32_get_bits(buf_addr_info->info1, 476 BUFFER_ADDR_INFO1_SW_COOKIE); 477 *rbm = le32_get_bits(buf_addr_info->info1, 478 BUFFER_ADDR_INFO1_RET_BUF_MGR); 479 480 *pp_buf_addr = (void *)buf_addr_info; 481 } 482 483 void ath12k_hal_rx_msdu_list_get(struct ath12k *ar, 484 struct hal_rx_msdu_link *link_desc, 485 struct hal_rx_msdu_list *msdu_list, 486 u16 *num_msdus) 487 { 488 struct hal_rx_msdu_details *msdu_details = NULL; 489 struct rx_msdu_desc *msdu_desc_info = NULL; 490 u32 last = 0, first = 0; 491 u8 tmp = 0; 492 int i; 493 494 last = u32_encode_bits(last, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 495 first = u32_encode_bits(first, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 496 msdu_details = &link_desc->msdu_link[0]; 497 498 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 499 if (!i && le32_get_bits(msdu_details[i].buf_addr_info.info0, 500 BUFFER_ADDR_INFO0_ADDR) == 0) 501 break; 502 if (le32_get_bits(msdu_details[i].buf_addr_info.info0, 503 BUFFER_ADDR_INFO0_ADDR) == 0) { 504 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 505 msdu_desc_info->info0 |= cpu_to_le32(last); 506 break; 507 } 508 msdu_desc_info = &msdu_details[i].rx_msdu_info; 509 510 if (!i) 511 msdu_desc_info->info0 |= cpu_to_le32(first); 512 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 513 msdu_desc_info->info0 |= cpu_to_le32(last); 514 msdu_list->msdu_info[i].msdu_flags = le32_to_cpu(msdu_desc_info->info0); 515 msdu_list->msdu_info[i].msdu_len = 516 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 517 msdu_list->sw_cookie[i] = 518 le32_get_bits(msdu_details[i].buf_addr_info.info1, 519 BUFFER_ADDR_INFO1_SW_COOKIE); 520 tmp = le32_get_bits(msdu_details[i].buf_addr_info.info1, 521 BUFFER_ADDR_INFO1_RET_BUF_MGR); 522 msdu_list->paddr[i] = 523 ((u64)(le32_get_bits(msdu_details[i].buf_addr_info.info1, 524 BUFFER_ADDR_INFO1_ADDR)) << 32) | 525 le32_get_bits(msdu_details[i].buf_addr_info.info0, 526 BUFFER_ADDR_INFO0_ADDR); 527 msdu_list->rbm[i] = tmp; 528 } 529 *num_msdus = i; 530 } 531 532 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, 533 struct hal_wbm_release_ring *desc, 534 struct ath12k_buffer_addr *buf_addr_info, 535 enum hal_wbm_rel_bm_act action) 536 { 537 desc->buf_addr_info = *buf_addr_info; 538 desc->info0 |= le32_encode_bits(HAL_WBM_REL_SRC_MODULE_SW, 539 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE) | 540 le32_encode_bits(action, HAL_WBM_RELEASE_INFO0_BM_ACTION) | 541 le32_encode_bits(HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 542 HAL_WBM_RELEASE_INFO0_DESC_TYPE); 543 } 544 545 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 546 struct hal_reo_status *status) 547 { 548 struct hal_reo_get_queue_stats_status *desc = 549 (struct hal_reo_get_queue_stats_status *)tlv->value; 550 551 status->uniform_hdr.cmd_num = 552 le32_get_bits(desc->hdr.info0, 553 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 554 status->uniform_hdr.cmd_status = 555 le32_get_bits(desc->hdr.info0, 556 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 557 558 ath12k_dbg(ab, ATH12K_DBG_HAL, "Queue stats status:\n"); 559 ath12k_dbg(ab, ATH12K_DBG_HAL, "header: cmd_num %d status %d\n", 560 status->uniform_hdr.cmd_num, 561 status->uniform_hdr.cmd_status); 562 ath12k_dbg(ab, ATH12K_DBG_HAL, "ssn %u cur_idx %u\n", 563 le32_get_bits(desc->info0, 564 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN), 565 le32_get_bits(desc->info0, 566 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX)); 567 ath12k_dbg(ab, ATH12K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n", 568 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]); 569 ath12k_dbg(ab, ATH12K_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n", 570 desc->last_rx_enqueue_timestamp, 571 desc->last_rx_dequeue_timestamp); 572 ath12k_dbg(ab, ATH12K_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n", 573 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2], 574 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5], 575 desc->rx_bitmap[6], desc->rx_bitmap[7]); 576 ath12k_dbg(ab, ATH12K_DBG_HAL, "count: cur_mpdu %u cur_msdu %u\n", 577 le32_get_bits(desc->info1, 578 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT), 579 le32_get_bits(desc->info1, 580 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT)); 581 ath12k_dbg(ab, ATH12K_DBG_HAL, "fwd_timeout %u fwd_bar %u dup_count %u\n", 582 le32_get_bits(desc->info2, 583 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT), 584 le32_get_bits(desc->info2, 585 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT), 586 le32_get_bits(desc->info2, 587 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT)); 588 ath12k_dbg(ab, ATH12K_DBG_HAL, "frames_in_order %u bar_rcvd %u\n", 589 le32_get_bits(desc->info3, 590 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT), 591 le32_get_bits(desc->info3, 592 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT)); 593 ath12k_dbg(ab, ATH12K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n", 594 desc->num_mpdu_frames, desc->num_msdu_frames, 595 desc->total_bytes); 596 ath12k_dbg(ab, ATH12K_DBG_HAL, "late_rcvd %u win_jump_2k %u hole_cnt %u\n", 597 le32_get_bits(desc->info4, 598 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU), 599 le32_get_bits(desc->info2, 600 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K), 601 le32_get_bits(desc->info4, 602 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT)); 603 ath12k_dbg(ab, ATH12K_DBG_HAL, "looping count %u\n", 604 le32_get_bits(desc->info5, 605 HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT)); 606 } 607 608 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 609 struct hal_reo_status *status) 610 { 611 struct hal_reo_flush_queue_status *desc = 612 (struct hal_reo_flush_queue_status *)tlv->value; 613 614 status->uniform_hdr.cmd_num = 615 le32_get_bits(desc->hdr.info0, 616 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 617 status->uniform_hdr.cmd_status = 618 le32_get_bits(desc->hdr.info0, 619 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 620 status->u.flush_queue.err_detected = 621 le32_get_bits(desc->info0, 622 HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED); 623 } 624 625 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 626 struct hal_reo_status *status) 627 { 628 struct ath12k_hal *hal = &ab->hal; 629 struct hal_reo_flush_cache_status *desc = 630 (struct hal_reo_flush_cache_status *)tlv->value; 631 632 status->uniform_hdr.cmd_num = 633 le32_get_bits(desc->hdr.info0, 634 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 635 status->uniform_hdr.cmd_status = 636 le32_get_bits(desc->hdr.info0, 637 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 638 639 status->u.flush_cache.err_detected = 640 le32_get_bits(desc->info0, 641 HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR); 642 status->u.flush_cache.err_code = 643 le32_get_bits(desc->info0, 644 HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE); 645 if (!status->u.flush_cache.err_code) 646 hal->avail_blk_resource |= BIT(hal->current_blk_index); 647 648 status->u.flush_cache.cache_controller_flush_status_hit = 649 le32_get_bits(desc->info0, 650 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT); 651 652 status->u.flush_cache.cache_controller_flush_status_desc_type = 653 le32_get_bits(desc->info0, 654 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE); 655 status->u.flush_cache.cache_controller_flush_status_client_id = 656 le32_get_bits(desc->info0, 657 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID); 658 status->u.flush_cache.cache_controller_flush_status_err = 659 le32_get_bits(desc->info0, 660 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR); 661 status->u.flush_cache.cache_controller_flush_status_cnt = 662 le32_get_bits(desc->info0, 663 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT); 664 } 665 666 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 667 struct hal_reo_status *status) 668 { 669 struct ath12k_hal *hal = &ab->hal; 670 struct hal_reo_unblock_cache_status *desc = 671 (struct hal_reo_unblock_cache_status *)tlv->value; 672 673 status->uniform_hdr.cmd_num = 674 le32_get_bits(desc->hdr.info0, 675 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 676 status->uniform_hdr.cmd_status = 677 le32_get_bits(desc->hdr.info0, 678 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 679 680 status->u.unblock_cache.err_detected = 681 le32_get_bits(desc->info0, 682 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR); 683 status->u.unblock_cache.unblock_type = 684 le32_get_bits(desc->info0, 685 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE); 686 687 if (!status->u.unblock_cache.err_detected && 688 status->u.unblock_cache.unblock_type == 689 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE) 690 hal->avail_blk_resource &= ~BIT(hal->current_blk_index); 691 } 692 693 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, 694 struct hal_tlv_64_hdr *tlv, 695 struct hal_reo_status *status) 696 { 697 struct hal_reo_flush_timeout_list_status *desc = 698 (struct hal_reo_flush_timeout_list_status *)tlv->value; 699 700 status->uniform_hdr.cmd_num = 701 le32_get_bits(desc->hdr.info0, 702 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 703 status->uniform_hdr.cmd_status = 704 le32_get_bits(desc->hdr.info0, 705 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 706 707 status->u.timeout_list.err_detected = 708 le32_get_bits(desc->info0, 709 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR); 710 status->u.timeout_list.list_empty = 711 le32_get_bits(desc->info0, 712 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY); 713 714 status->u.timeout_list.release_desc_cnt = 715 le32_get_bits(desc->info1, 716 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT); 717 status->u.timeout_list.fwd_buf_cnt = 718 le32_get_bits(desc->info0, 719 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT); 720 } 721 722 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, 723 struct hal_tlv_64_hdr *tlv, 724 struct hal_reo_status *status) 725 { 726 struct hal_reo_desc_thresh_reached_status *desc = 727 (struct hal_reo_desc_thresh_reached_status *)tlv->value; 728 729 status->uniform_hdr.cmd_num = 730 le32_get_bits(desc->hdr.info0, 731 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 732 status->uniform_hdr.cmd_status = 733 le32_get_bits(desc->hdr.info0, 734 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 735 736 status->u.desc_thresh_reached.threshold_idx = 737 le32_get_bits(desc->info0, 738 HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX); 739 740 status->u.desc_thresh_reached.link_desc_counter0 = 741 le32_get_bits(desc->info1, 742 HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0); 743 744 status->u.desc_thresh_reached.link_desc_counter1 = 745 le32_get_bits(desc->info2, 746 HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1); 747 748 status->u.desc_thresh_reached.link_desc_counter2 = 749 le32_get_bits(desc->info3, 750 HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2); 751 752 status->u.desc_thresh_reached.link_desc_counter_sum = 753 le32_get_bits(desc->info4, 754 HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM); 755 } 756 757 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, 758 struct hal_tlv_64_hdr *tlv, 759 struct hal_reo_status *status) 760 { 761 struct hal_reo_status_hdr *desc = 762 (struct hal_reo_status_hdr *)tlv->value; 763 764 status->uniform_hdr.cmd_num = 765 le32_get_bits(desc->info0, 766 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 767 status->uniform_hdr.cmd_status = 768 le32_get_bits(desc->info0, 769 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 770 } 771 772 u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) 773 { 774 u32 num_ext_desc, num_1k_desc = 0; 775 776 if (ba_window_size <= 1) { 777 if (tid != HAL_DESC_REO_NON_QOS_TID) 778 num_ext_desc = 1; 779 else 780 num_ext_desc = 0; 781 782 } else if (ba_window_size <= 105) { 783 num_ext_desc = 1; 784 } else if (ba_window_size <= 210) { 785 num_ext_desc = 2; 786 } else if (ba_window_size <= 256) { 787 num_ext_desc = 3; 788 } else { 789 num_ext_desc = 10; 790 num_1k_desc = 1; 791 } 792 793 return sizeof(struct hal_rx_reo_queue) + 794 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)) + 795 (num_1k_desc * sizeof(struct hal_rx_reo_queue_1k)); 796 } 797 798 void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, 799 int tid, u32 ba_window_size, 800 u32 start_seq, enum hal_pn_type type) 801 { 802 struct hal_rx_reo_queue_ext *ext_desc; 803 804 ath12k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, 805 HAL_DESC_REO_QUEUE_DESC, 806 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); 807 808 qdesc->rx_queue_num = le32_encode_bits(tid, HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER); 809 810 qdesc->info0 = 811 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_VLD) | 812 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER) | 813 le32_encode_bits(ath12k_tid_to_ac(tid), HAL_RX_REO_QUEUE_INFO0_AC); 814 815 if (ba_window_size < 1) 816 ba_window_size = 1; 817 818 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID) 819 ba_window_size++; 820 821 if (ba_window_size == 1) 822 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_RETRY); 823 824 qdesc->info0 |= le32_encode_bits(ba_window_size - 1, 825 HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE); 826 switch (type) { 827 case HAL_PN_TYPE_NONE: 828 case HAL_PN_TYPE_WAPI_EVEN: 829 case HAL_PN_TYPE_WAPI_UNEVEN: 830 break; 831 case HAL_PN_TYPE_WPA: 832 qdesc->info0 |= 833 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_PN_CHECK) | 834 le32_encode_bits(HAL_RX_REO_QUEUE_PN_SIZE_48, 835 HAL_RX_REO_QUEUE_INFO0_PN_SIZE); 836 break; 837 } 838 839 /* TODO: Set Ignore ampdu flags based on BA window size and/or 840 * AMPDU capabilities 841 */ 842 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG); 843 844 qdesc->info1 |= le32_encode_bits(0, HAL_RX_REO_QUEUE_INFO1_SVLD); 845 846 if (start_seq <= 0xfff) 847 qdesc->info1 = le32_encode_bits(start_seq, 848 HAL_RX_REO_QUEUE_INFO1_SSN); 849 850 if (tid == HAL_DESC_REO_NON_QOS_TID) 851 return; 852 853 ext_desc = qdesc->ext_desc; 854 855 /* TODO: HW queue descriptors are currently allocated for max BA 856 * window size for all QOS TIDs so that same descriptor can be used 857 * later when ADDBA request is received. This should be changed to 858 * allocate HW queue descriptors based on BA window size being 859 * negotiated (0 for non BA cases), and reallocate when BA window 860 * size changes and also send WMI message to FW to change the REO 861 * queue descriptor in Rx peer entry as part of dp_rx_tid_update. 862 */ 863 memset(ext_desc, 0, 3 * sizeof(*ext_desc)); 864 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 865 HAL_DESC_REO_QUEUE_EXT_DESC, 866 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); 867 ext_desc++; 868 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 869 HAL_DESC_REO_QUEUE_EXT_DESC, 870 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); 871 ext_desc++; 872 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 873 HAL_DESC_REO_QUEUE_EXT_DESC, 874 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); 875 } 876 877 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, 878 struct hal_srng *srng) 879 { 880 struct hal_srng_params params; 881 struct hal_tlv_64_hdr *tlv; 882 struct hal_reo_get_queue_stats *desc; 883 int i, cmd_num = 1; 884 int entry_size; 885 u8 *entry; 886 887 memset(¶ms, 0, sizeof(params)); 888 889 entry_size = ath12k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 890 ath12k_hal_srng_get_params(ab, srng, ¶ms); 891 entry = (u8 *)params.ring_base_vaddr; 892 893 for (i = 0; i < params.num_entries; i++) { 894 tlv = (struct hal_tlv_64_hdr *)entry; 895 desc = (struct hal_reo_get_queue_stats *)tlv->value; 896 desc->cmd.info0 = le32_encode_bits(cmd_num++, 897 HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 898 entry += entry_size; 899 } 900 } 901 902 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map) 903 { 904 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 905 u32 val; 906 907 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 908 909 val |= u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE) | 910 u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE); 911 ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 912 913 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab)); 914 915 val &= ~(HAL_REO1_MISC_CTL_FRAG_DST_RING | 916 HAL_REO1_MISC_CTL_BAR_DST_RING); 917 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0, 918 HAL_REO1_MISC_CTL_FRAG_DST_RING); 919 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0, 920 HAL_REO1_MISC_CTL_BAR_DST_RING); 921 ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab), val); 922 923 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 924 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 925 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 926 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 927 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 928 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 929 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 930 HAL_DEFAULT_VO_REO_TIMEOUT_USEC); 931 932 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 933 ring_hash_map); 934 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 935 ring_hash_map); 936 } 937 938 void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab) 939 { 940 u32 val; 941 942 lockdep_assert_held(&ab->base_lock); 943 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 944 HAL_REO1_QDESC_ADDR(ab)); 945 946 val |= u32_encode_bits(1, HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY); 947 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 948 HAL_REO1_QDESC_ADDR(ab), val); 949 950 val &= ~HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY; 951 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 952 HAL_REO1_QDESC_ADDR(ab), val); 953 } 954