1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_HAL_H 8 #define ATH12K_HAL_H 9 10 #include "hw.h" 11 12 struct ath12k_base; 13 14 #define HAL_DESC_REO_NON_QOS_TID 16 15 16 #define HAL_INVALID_PEERID 0x3fff 17 #define VHT_SIG_SU_NSS_MASK 0x7 18 19 #define HAL_TX_ADDRX_EN 1 20 #define HAL_TX_ADDRY_EN 2 21 22 #define HAL_TX_ADDR_SEARCH_DEFAULT 0 23 #define HAL_TX_ADDR_SEARCH_INDEX 1 24 25 #define HAL_RX_MAX_MPDU 256 26 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 27 28 /* TODO: 16 entries per radio times MAX_VAPS_SUPPORTED */ 29 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 32 30 #define HAL_DSCP_TID_TBL_SIZE 24 31 32 #define EHT_MAX_USER_INFO 4 33 #define HAL_RX_MON_MAX_AGGR_SIZE 128 34 #define HAL_MAX_UL_MU_USERS 37 35 36 #define MAX_USER_POS 8 37 #define MAX_MU_GROUP_ID 64 38 #define MAX_MU_GROUP_SHOW 16 39 #define MAX_MU_GROUP_LENGTH (6 * MAX_MU_GROUP_SHOW) 40 41 #define HAL_CE_REMAP_REG_BASE (ab->ce_remap_base_addr) 42 43 #define HAL_LINK_DESC_SIZE (32 << 2) 44 #define HAL_LINK_DESC_ALIGN 128 45 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 46 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 47 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 48 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 49 #define HAL_MAX_AVAIL_BLK_RES 3 50 51 #define HAL_RING_BASE_ALIGN 8 52 #define HAL_REO_QLUT_ADDR_ALIGN 256 53 54 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 55 #define HAL_ADDR_MSB_REG_SHIFT 32 56 57 #define HAL_WBM2SW_REL_ERR_RING_NUM 3 58 59 #define HAL_SHADOW_NUM_REGS_MAX 40 60 61 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 62 /* TODO: Check with hw team on the supported scatter buf size */ 63 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 64 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 65 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 66 67 #define HAL_AST_IDX_INVALID 0xFFFF 68 #define HAL_RX_MAX_MCS 12 69 #define HAL_RX_MAX_MCS_HT 31 70 #define HAL_RX_MAX_MCS_VHT 9 71 #define HAL_RX_MAX_MCS_HE 11 72 #define HAL_RX_MAX_MCS_BE 15 73 #define HAL_RX_MAX_NSS 8 74 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 75 76 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30) 77 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31) 78 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0) 79 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3) 80 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7) 81 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8) 82 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9) 83 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16) 84 #define HAL_RX_FCS_LEN 4 85 86 enum hal_srng_ring_id { 87 HAL_SRNG_RING_ID_REO2SW0 = 0, 88 HAL_SRNG_RING_ID_REO2SW1, 89 HAL_SRNG_RING_ID_REO2SW2, 90 HAL_SRNG_RING_ID_REO2SW3, 91 HAL_SRNG_RING_ID_REO2SW4, 92 HAL_SRNG_RING_ID_REO2SW5, 93 HAL_SRNG_RING_ID_REO2SW6, 94 HAL_SRNG_RING_ID_REO2SW7, 95 HAL_SRNG_RING_ID_REO2SW8, 96 HAL_SRNG_RING_ID_REO2TCL, 97 HAL_SRNG_RING_ID_REO2PPE, 98 99 HAL_SRNG_RING_ID_SW2REO = 16, 100 HAL_SRNG_RING_ID_SW2REO1, 101 HAL_SRNG_RING_ID_SW2REO2, 102 HAL_SRNG_RING_ID_SW2REO3, 103 104 HAL_SRNG_RING_ID_REO_CMD, 105 HAL_SRNG_RING_ID_REO_STATUS, 106 107 HAL_SRNG_RING_ID_SW2TCL1 = 24, 108 HAL_SRNG_RING_ID_SW2TCL2, 109 HAL_SRNG_RING_ID_SW2TCL3, 110 HAL_SRNG_RING_ID_SW2TCL4, 111 HAL_SRNG_RING_ID_SW2TCL5, 112 HAL_SRNG_RING_ID_SW2TCL6, 113 HAL_SRNG_RING_ID_PPE2TCL1 = 30, 114 115 HAL_SRNG_RING_ID_SW2TCL_CMD = 40, 116 HAL_SRNG_RING_ID_SW2TCL1_CMD, 117 HAL_SRNG_RING_ID_TCL_STATUS, 118 119 HAL_SRNG_RING_ID_CE0_SRC = 64, 120 HAL_SRNG_RING_ID_CE1_SRC, 121 HAL_SRNG_RING_ID_CE2_SRC, 122 HAL_SRNG_RING_ID_CE3_SRC, 123 HAL_SRNG_RING_ID_CE4_SRC, 124 HAL_SRNG_RING_ID_CE5_SRC, 125 HAL_SRNG_RING_ID_CE6_SRC, 126 HAL_SRNG_RING_ID_CE7_SRC, 127 HAL_SRNG_RING_ID_CE8_SRC, 128 HAL_SRNG_RING_ID_CE9_SRC, 129 HAL_SRNG_RING_ID_CE10_SRC, 130 HAL_SRNG_RING_ID_CE11_SRC, 131 HAL_SRNG_RING_ID_CE12_SRC, 132 HAL_SRNG_RING_ID_CE13_SRC, 133 HAL_SRNG_RING_ID_CE14_SRC, 134 HAL_SRNG_RING_ID_CE15_SRC, 135 136 HAL_SRNG_RING_ID_CE0_DST = 81, 137 HAL_SRNG_RING_ID_CE1_DST, 138 HAL_SRNG_RING_ID_CE2_DST, 139 HAL_SRNG_RING_ID_CE3_DST, 140 HAL_SRNG_RING_ID_CE4_DST, 141 HAL_SRNG_RING_ID_CE5_DST, 142 HAL_SRNG_RING_ID_CE6_DST, 143 HAL_SRNG_RING_ID_CE7_DST, 144 HAL_SRNG_RING_ID_CE8_DST, 145 HAL_SRNG_RING_ID_CE9_DST, 146 HAL_SRNG_RING_ID_CE10_DST, 147 HAL_SRNG_RING_ID_CE11_DST, 148 HAL_SRNG_RING_ID_CE12_DST, 149 HAL_SRNG_RING_ID_CE13_DST, 150 HAL_SRNG_RING_ID_CE14_DST, 151 HAL_SRNG_RING_ID_CE15_DST, 152 153 HAL_SRNG_RING_ID_CE0_DST_STATUS = 100, 154 HAL_SRNG_RING_ID_CE1_DST_STATUS, 155 HAL_SRNG_RING_ID_CE2_DST_STATUS, 156 HAL_SRNG_RING_ID_CE3_DST_STATUS, 157 HAL_SRNG_RING_ID_CE4_DST_STATUS, 158 HAL_SRNG_RING_ID_CE5_DST_STATUS, 159 HAL_SRNG_RING_ID_CE6_DST_STATUS, 160 HAL_SRNG_RING_ID_CE7_DST_STATUS, 161 HAL_SRNG_RING_ID_CE8_DST_STATUS, 162 HAL_SRNG_RING_ID_CE9_DST_STATUS, 163 HAL_SRNG_RING_ID_CE10_DST_STATUS, 164 HAL_SRNG_RING_ID_CE11_DST_STATUS, 165 HAL_SRNG_RING_ID_CE12_DST_STATUS, 166 HAL_SRNG_RING_ID_CE13_DST_STATUS, 167 HAL_SRNG_RING_ID_CE14_DST_STATUS, 168 HAL_SRNG_RING_ID_CE15_DST_STATUS, 169 170 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120, 171 HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 172 HAL_SRNG_RING_ID_WBM_SW1_RELEASE, 173 HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123, 174 175 HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128, 176 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 177 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 178 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */ 179 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 180 HAL_SRNG_RING_ID_WBM2SW5_RELEASE, 181 HAL_SRNG_RING_ID_WBM2SW6_RELEASE, 182 HAL_SRNG_RING_ID_WBM2SW7_RELEASE, 183 184 HAL_SRNG_RING_ID_UMAC_ID_END = 159, 185 186 /* Common DMAC rings shared by all LMACs */ 187 HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160, 188 HAL_SRNG_SW2RXDMA_BUF0 = HAL_SRNG_RING_ID_DMAC_CMN_ID_START, 189 HAL_SRNG_SW2RXDMA_BUF1 = 161, 190 HAL_SRNG_SW2RXDMA_BUF2 = 162, 191 192 HAL_SRNG_SW2RXMON_BUF0 = 168, 193 194 HAL_SRNG_SW2TXMON_BUF0 = 176, 195 196 HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183, 197 HAL_SRNG_RING_ID_PMAC1_ID_START = 184, 198 199 HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 = HAL_SRNG_RING_ID_PMAC1_ID_START, 200 201 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 202 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 203 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 204 HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 205 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 206 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 207 HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, 208 HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, 209 210 HAL_SRNG_RING_ID_PMAC1_ID_END, 211 }; 212 213 /* SRNG registers are split into two groups R0 and R2 */ 214 #define HAL_SRNG_REG_GRP_R0 0 215 #define HAL_SRNG_REG_GRP_R2 1 216 #define HAL_SRNG_NUM_REG_GRP 2 217 218 /* TODO: number of PMACs */ 219 #define HAL_SRNG_NUM_PMACS 3 220 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \ 221 HAL_SRNG_RING_ID_DMAC_CMN_ID_START) 222 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \ 223 HAL_SRNG_RING_ID_PMAC1_ID_START) 224 #define HAL_SRNG_NUM_PMAC_RINGS (HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC) 225 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_DMAC_CMN_ID_END + \ 226 HAL_SRNG_NUM_PMAC_RINGS) 227 228 enum hal_rx_su_mu_coding { 229 HAL_RX_SU_MU_CODING_BCC, 230 HAL_RX_SU_MU_CODING_LDPC, 231 HAL_RX_SU_MU_CODING_MAX, 232 }; 233 234 enum hal_rx_gi { 235 HAL_RX_GI_0_8_US, 236 HAL_RX_GI_0_4_US, 237 HAL_RX_GI_1_6_US, 238 HAL_RX_GI_3_2_US, 239 HAL_RX_GI_MAX, 240 }; 241 242 enum hal_rx_bw { 243 HAL_RX_BW_20MHZ, 244 HAL_RX_BW_40MHZ, 245 HAL_RX_BW_80MHZ, 246 HAL_RX_BW_160MHZ, 247 HAL_RX_BW_320MHZ, 248 HAL_RX_BW_MAX, 249 }; 250 251 enum hal_rx_preamble { 252 HAL_RX_PREAMBLE_11A, 253 HAL_RX_PREAMBLE_11B, 254 HAL_RX_PREAMBLE_11N, 255 HAL_RX_PREAMBLE_11AC, 256 HAL_RX_PREAMBLE_11AX, 257 HAL_RX_PREAMBLE_11BA, 258 HAL_RX_PREAMBLE_11BE, 259 HAL_RX_PREAMBLE_MAX, 260 }; 261 262 enum hal_rx_reception_type { 263 HAL_RX_RECEPTION_TYPE_SU, 264 HAL_RX_RECEPTION_TYPE_MU_MIMO, 265 HAL_RX_RECEPTION_TYPE_MU_OFDMA, 266 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO, 267 HAL_RX_RECEPTION_TYPE_MAX, 268 }; 269 270 enum hal_rx_legacy_rate { 271 HAL_RX_LEGACY_RATE_LP_1_MBPS, 272 HAL_RX_LEGACY_RATE_LP_2_MBPS, 273 HAL_RX_LEGACY_RATE_LP_5_5_MBPS, 274 HAL_RX_LEGACY_RATE_LP_11_MBPS, 275 HAL_RX_LEGACY_RATE_SP_2_MBPS, 276 HAL_RX_LEGACY_RATE_SP_5_5_MBPS, 277 HAL_RX_LEGACY_RATE_SP_11_MBPS, 278 HAL_RX_LEGACY_RATE_INVALID, 279 }; 280 281 enum hal_rx_legacy_rates_ofdm { 282 HAL_RX_LEGACY_RATE_OFDM_48_MBPS, 283 HAL_RX_LEGACY_RATE_OFDM_24_MBPS, 284 HAL_RX_LEGACY_RATE_OFDM_12_MBPS, 285 HAL_RX_LEGACY_RATE_OFDM_6_MBPS, 286 HAL_RX_LEGACY_RATE_OFDM_54_MBPS, 287 HAL_RX_LEGACY_RATE_OFDM_36_MBPS, 288 HAL_RX_LEGACY_RATE_OFDM_18_MBPS, 289 HAL_RX_LEGACY_RATE_OFDM_9_MBPS, 290 HAL_RX_LEGACY_RATE_OFDM_INVALID, 291 }; 292 293 enum hal_ring_type { 294 HAL_REO_DST, 295 HAL_REO_EXCEPTION, 296 HAL_REO_REINJECT, 297 HAL_REO_CMD, 298 HAL_REO_STATUS, 299 HAL_TCL_DATA, 300 HAL_TCL_CMD, 301 HAL_TCL_STATUS, 302 HAL_CE_SRC, 303 HAL_CE_DST, 304 HAL_CE_DST_STATUS, 305 HAL_WBM_IDLE_LINK, 306 HAL_SW2WBM_RELEASE, 307 HAL_WBM2SW_RELEASE, 308 HAL_RXDMA_BUF, 309 HAL_RXDMA_DST, 310 HAL_RXDMA_MONITOR_BUF, 311 HAL_RXDMA_MONITOR_STATUS, 312 HAL_RXDMA_MONITOR_DST, 313 HAL_RXDMA_MONITOR_DESC, 314 HAL_RXDMA_DIR_BUF, 315 HAL_PPE2TCL, 316 HAL_PPE_RELEASE, 317 HAL_TX_MONITOR_BUF, 318 HAL_TX_MONITOR_DST, 319 HAL_MAX_RING_TYPES, 320 }; 321 322 /** 323 * enum hal_reo_cmd_type: Enum for REO command type 324 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 325 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 326 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 327 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 328 * earlier with a 'REO_FLUSH_CACHE' command 329 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 330 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 331 */ 332 enum hal_reo_cmd_type { 333 HAL_REO_CMD_GET_QUEUE_STATS = 0, 334 HAL_REO_CMD_FLUSH_QUEUE = 1, 335 HAL_REO_CMD_FLUSH_CACHE = 2, 336 HAL_REO_CMD_UNBLOCK_CACHE = 3, 337 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 338 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 339 }; 340 341 /** 342 * enum hal_reo_cmd_status: Enum for execution status of REO command 343 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 344 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 345 * or cache was blocked 346 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 347 * invalid queue desc 348 * @HAL_REO_CMD_RESOURCE_BLOCKED: Command could not be executed because 349 * one or more descriptors were blocked 350 * @HAL_REO_CMD_DRAIN: 351 */ 352 enum hal_reo_cmd_status { 353 HAL_REO_CMD_SUCCESS = 0, 354 HAL_REO_CMD_BLOCKED = 1, 355 HAL_REO_CMD_FAILED = 2, 356 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 357 HAL_REO_CMD_DRAIN = 0xff, 358 }; 359 360 enum hal_tcl_encap_type { 361 HAL_TCL_ENCAP_TYPE_RAW, 362 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 363 HAL_TCL_ENCAP_TYPE_ETHERNET, 364 HAL_TCL_ENCAP_TYPE_802_3 = 3, 365 HAL_TCL_ENCAP_TYPE_MAX 366 }; 367 368 enum hal_tcl_desc_type { 369 HAL_TCL_DESC_TYPE_BUFFER, 370 HAL_TCL_DESC_TYPE_EXT_DESC, 371 HAL_TCL_DESC_TYPE_MAX, 372 }; 373 374 enum hal_reo_dest_ring_buffer_type { 375 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 376 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 377 }; 378 379 enum hal_reo_dest_ring_push_reason { 380 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 381 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 382 }; 383 384 enum hal_reo_entr_rxdma_push_reason { 385 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ERR_DETECTED, 386 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ROUTING_INSTRUCTION, 387 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_RX_FLUSH, 388 }; 389 390 enum hal_reo_dest_ring_error_code { 391 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 392 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 393 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 394 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 395 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 396 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 397 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 398 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 399 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 400 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 401 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 402 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 403 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 404 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 405 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 406 HAL_REO_DEST_RING_ERROR_CODE_MAX, 407 }; 408 409 enum hal_reo_entr_rxdma_ecode { 410 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 411 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 412 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 413 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 414 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 415 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 416 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 417 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 418 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 419 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 420 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 421 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 422 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 423 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 424 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_FRAG_ERR, 425 HAL_REO_ENTR_RING_RXDMA_ECODE_MULTICAST_ECHO_ERR, 426 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_MISMATCH_ERR, 427 HAL_REO_ENTR_RING_RXDMA_ECODE_UNAUTH_WDS_ERR, 428 HAL_REO_ENTR_RING_RXDMA_ECODE_GRPCAST_AMSDU_WDS_ERR, 429 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 430 }; 431 432 enum hal_wbm_htt_tx_comp_status { 433 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 434 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 435 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 436 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 437 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 438 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 439 HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH, 440 HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX, 441 }; 442 443 enum hal_encrypt_type { 444 HAL_ENCRYPT_TYPE_WEP_40, 445 HAL_ENCRYPT_TYPE_WEP_104, 446 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 447 HAL_ENCRYPT_TYPE_WEP_128, 448 HAL_ENCRYPT_TYPE_TKIP_MIC, 449 HAL_ENCRYPT_TYPE_WAPI, 450 HAL_ENCRYPT_TYPE_CCMP_128, 451 HAL_ENCRYPT_TYPE_OPEN, 452 HAL_ENCRYPT_TYPE_CCMP_256, 453 HAL_ENCRYPT_TYPE_GCMP_128, 454 HAL_ENCRYPT_TYPE_AES_GCMP_256, 455 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 456 }; 457 458 enum hal_tx_rate_stats_bw { 459 HAL_TX_RATE_STATS_BW_20, 460 HAL_TX_RATE_STATS_BW_40, 461 HAL_TX_RATE_STATS_BW_80, 462 HAL_TX_RATE_STATS_BW_160, 463 }; 464 465 enum hal_tx_rate_stats_pkt_type { 466 HAL_TX_RATE_STATS_PKT_TYPE_11A, 467 HAL_TX_RATE_STATS_PKT_TYPE_11B, 468 HAL_TX_RATE_STATS_PKT_TYPE_11N, 469 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 470 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 471 HAL_TX_RATE_STATS_PKT_TYPE_11BA, 472 HAL_TX_RATE_STATS_PKT_TYPE_11BE, 473 }; 474 475 enum hal_tx_rate_stats_sgi { 476 HAL_TX_RATE_STATS_SGI_08US, 477 HAL_TX_RATE_STATS_SGI_04US, 478 HAL_TX_RATE_STATS_SGI_16US, 479 HAL_TX_RATE_STATS_SGI_32US, 480 }; 481 482 struct hal_wbm_idle_scatter_list { 483 dma_addr_t paddr; 484 struct hal_wbm_link_desc *vaddr; 485 }; 486 487 struct hal_srng_params { 488 dma_addr_t ring_base_paddr; 489 u32 *ring_base_vaddr; 490 int num_entries; 491 u32 intr_batch_cntr_thres_entries; 492 u32 intr_timer_thres_us; 493 u32 flags; 494 u32 max_buffer_len; 495 u32 low_threshold; 496 u32 high_threshold; 497 dma_addr_t msi_addr; 498 dma_addr_t msi2_addr; 499 u32 msi_data; 500 u32 msi2_data; 501 502 /* Add more params as needed */ 503 }; 504 505 enum hal_srng_dir { 506 HAL_SRNG_DIR_SRC, 507 HAL_SRNG_DIR_DST 508 }; 509 510 enum rx_msdu_start_pkt_type { 511 RX_MSDU_START_PKT_TYPE_11A, 512 RX_MSDU_START_PKT_TYPE_11B, 513 RX_MSDU_START_PKT_TYPE_11N, 514 RX_MSDU_START_PKT_TYPE_11AC, 515 RX_MSDU_START_PKT_TYPE_11AX, 516 RX_MSDU_START_PKT_TYPE_11BA, 517 RX_MSDU_START_PKT_TYPE_11BE, 518 }; 519 520 enum rx_msdu_start_sgi { 521 RX_MSDU_START_SGI_0_8_US, 522 RX_MSDU_START_SGI_0_4_US, 523 RX_MSDU_START_SGI_1_6_US, 524 RX_MSDU_START_SGI_3_2_US, 525 }; 526 527 enum rx_msdu_start_recv_bw { 528 RX_MSDU_START_RECV_BW_20MHZ, 529 RX_MSDU_START_RECV_BW_40MHZ, 530 RX_MSDU_START_RECV_BW_80MHZ, 531 RX_MSDU_START_RECV_BW_160MHZ, 532 }; 533 534 enum rx_msdu_start_reception_type { 535 RX_MSDU_START_RECEPTION_TYPE_SU, 536 RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO, 537 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA, 538 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 539 RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO, 540 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA, 541 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, 542 }; 543 544 enum rx_desc_decap_type { 545 RX_DESC_DECAP_TYPE_RAW, 546 RX_DESC_DECAP_TYPE_NATIVE_WIFI, 547 RX_DESC_DECAP_TYPE_ETHERNET2_DIX, 548 RX_DESC_DECAP_TYPE_8023, 549 }; 550 551 struct hal_rx_user_status { 552 u32 mcs:4, 553 nss:3, 554 ofdma_info_valid:1, 555 ul_ofdma_ru_start_index:7, 556 ul_ofdma_ru_width:7, 557 ul_ofdma_ru_size:8; 558 u32 ul_ofdma_user_v0_word0; 559 u32 ul_ofdma_user_v0_word1; 560 u32 ast_index; 561 u32 tid; 562 u16 tcp_msdu_count; 563 u16 tcp_ack_msdu_count; 564 u16 udp_msdu_count; 565 u16 other_msdu_count; 566 u16 frame_control; 567 u8 frame_control_info_valid; 568 u8 data_sequence_control_info_valid; 569 u16 first_data_seq_ctrl; 570 u32 preamble_type; 571 u16 ht_flags; 572 u16 vht_flags; 573 u16 he_flags; 574 u8 rs_flags; 575 u8 ldpc; 576 u32 mpdu_cnt_fcs_ok; 577 u32 mpdu_cnt_fcs_err; 578 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 579 u32 mpdu_ok_byte_count; 580 u32 mpdu_err_byte_count; 581 bool ampdu_present; 582 u16 ampdu_id; 583 }; 584 585 struct hal_rx_u_sig_info { 586 bool ul_dl; 587 u8 bw; 588 u8 ppdu_type_comp_mode; 589 u8 eht_sig_mcs; 590 u8 num_eht_sig_sym; 591 struct ieee80211_radiotap_eht_usig usig; 592 }; 593 594 struct hal_rx_tlv_aggr_info { 595 bool in_progress; 596 u16 cur_len; 597 u16 tlv_tag; 598 u8 buf[HAL_RX_MON_MAX_AGGR_SIZE]; 599 }; 600 601 struct hal_rx_radiotap_eht { 602 __le32 known; 603 __le32 data[9]; 604 }; 605 606 struct hal_rx_eht_info { 607 u8 num_user_info; 608 struct hal_rx_radiotap_eht eht; 609 u32 user_info[EHT_MAX_USER_INFO]; 610 }; 611 612 struct hal_rx_msdu_desc_info { 613 u32 msdu_flags; 614 u16 msdu_len; /* 14 bits for length */ 615 }; 616 617 /* hal_mon_buf_ring 618 * Producer : SW 619 * Consumer : Monitor 620 * 621 * paddr_lo 622 * Lower 32-bit physical address of the buffer pointer from the source ring. 623 * paddr_hi 624 * bit range 7-0 : upper 8 bit of the physical address. 625 * bit range 31-8 : reserved. 626 * cookie 627 * Consumer: RxMon/TxMon 64 bit cookie of the buffers. 628 */ 629 struct hal_mon_buf_ring { 630 __le32 paddr_lo; 631 __le32 paddr_hi; 632 __le64 cookie; 633 }; 634 635 struct hal_rx_mon_ppdu_info { 636 u32 ppdu_id; 637 u32 last_ppdu_id; 638 u64 ppdu_ts; 639 u32 num_mpdu_fcs_ok; 640 u32 num_mpdu_fcs_err; 641 u32 preamble_type; 642 u32 mpdu_len; 643 u16 chan_num; 644 u16 freq; 645 u16 tcp_msdu_count; 646 u16 tcp_ack_msdu_count; 647 u16 udp_msdu_count; 648 u16 other_msdu_count; 649 u16 peer_id; 650 u8 rate; 651 u8 mcs; 652 u8 nss; 653 u8 bw; 654 u8 vht_flag_values1; 655 u8 vht_flag_values2; 656 u8 vht_flag_values3[4]; 657 u8 vht_flag_values4; 658 u8 vht_flag_values5; 659 u16 vht_flag_values6; 660 u8 is_stbc; 661 u8 gi; 662 u8 sgi; 663 u8 ldpc; 664 u8 beamformed; 665 u8 rssi_comb; 666 u16 tid; 667 u8 fc_valid; 668 u16 ht_flags; 669 u16 vht_flags; 670 u16 he_flags; 671 u16 he_mu_flags; 672 u8 dcm; 673 u8 ru_alloc; 674 u8 reception_type; 675 u64 tsft; 676 u64 rx_duration; 677 u16 frame_control; 678 u32 ast_index; 679 u8 rs_fcs_err; 680 u8 rs_flags; 681 u8 cck_flag; 682 u8 ofdm_flag; 683 u8 ulofdma_flag; 684 u8 frame_control_info_valid; 685 u16 he_per_user_1; 686 u16 he_per_user_2; 687 u8 he_per_user_position; 688 u8 he_per_user_known; 689 u16 he_flags1; 690 u16 he_flags2; 691 u8 he_RU[4]; 692 u16 he_data1; 693 u16 he_data2; 694 u16 he_data3; 695 u16 he_data4; 696 u16 he_data5; 697 u16 he_data6; 698 u32 ppdu_len; 699 u32 prev_ppdu_id; 700 u32 device_id; 701 u16 first_data_seq_ctrl; 702 u8 monitor_direct_used; 703 u8 data_sequence_control_info_valid; 704 u8 ltf_size; 705 u8 rxpcu_filter_pass; 706 s8 rssi_chain[8][8]; 707 u32 num_users; 708 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 709 u8 addr1[ETH_ALEN]; 710 u8 addr2[ETH_ALEN]; 711 u8 addr3[ETH_ALEN]; 712 u8 addr4[ETH_ALEN]; 713 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS]; 714 u8 userid; 715 bool first_msdu_in_mpdu; 716 bool is_ampdu; 717 u8 medium_prot_type; 718 bool ppdu_continuation; 719 bool eht_usig; 720 struct hal_rx_u_sig_info u_sig_info; 721 bool is_eht; 722 struct hal_rx_eht_info eht_info; 723 struct hal_rx_tlv_aggr_info tlv_aggr; 724 }; 725 726 struct hal_rx_desc_data { 727 struct ieee80211_rx_status *rx_status; 728 u32 phy_meta_data; 729 u32 err_bitmap; 730 u32 enctype; 731 u32 msdu_done:1, 732 is_decrypted:1, 733 ip_csum_fail:1, 734 l4_csum_fail:1, 735 is_first_msdu:1, 736 is_last_msdu:1, 737 mesh_ctrl_present:1, 738 addr2_present:1, 739 is_mcbc:1, 740 seq_ctl_valid:1, 741 fc_valid:1; 742 u16 msdu_len; 743 u16 peer_id; 744 u16 seq_no; 745 u8 *addr2; 746 u8 pkt_type; 747 u8 l3_pad_bytes; 748 u8 decap_type; 749 u8 bw; 750 u8 rate_mcs; 751 u8 nss; 752 u8 sgi; 753 u8 tid; 754 }; 755 756 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 757 758 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 759 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8) 760 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12) 761 762 struct ath12k_buffer_addr { 763 __le32 info0; 764 __le32 info1; 765 } __packed; 766 767 /* ath12k_buffer_addr 768 * 769 * buffer_addr_31_0 770 * Address (lower 32 bits) of the MSDU buffer or MSDU_EXTENSION 771 * descriptor or Link descriptor 772 * 773 * buffer_addr_39_32 774 * Address (upper 8 bits) of the MSDU buffer or MSDU_EXTENSION 775 * descriptor or Link descriptor 776 * 777 * return_buffer_manager (RBM) 778 * Consumer: WBM 779 * Producer: SW/FW 780 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 781 * descriptor or link descriptor that is being pointed to shall be 782 * returned after the frame has been processed. It is used by WBM 783 * for routing purposes. 784 * 785 * Values are defined in enum %HAL_RX_BUF_RBM_ 786 * 787 * sw_buffer_cookie 788 * Cookie field exclusively used by SW. HW ignores the contents, 789 * accept that it passes the programmed value on to other 790 * descriptors together with the physical address. 791 * 792 * Field can be used by SW to for example associate the buffers 793 * physical address with the virtual address. 794 * 795 * NOTE1: 796 * The three most significant bits can have a special meaning 797 * in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 798 * and field transmit_bw_restriction is set 799 * 800 * In case of NON punctured transmission: 801 * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 802 * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 803 * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 804 * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 805 * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 806 * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 807 * Sw_buffer_cookie[19:18] = 2'b11: reserved 808 * 809 * In case of punctured transmission: 810 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 811 * Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 812 * Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 813 * Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 814 * Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 815 * Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 816 * Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 817 * Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 818 * Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 819 * Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 820 * Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 821 * Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 822 * Sw_buffer_cookie[19:18] = 2'b11: reserved 823 * 824 * Note: a punctured transmission is indicated by the presence 825 * of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 826 * 827 * Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS control 828 * field 829 * 830 * Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 831 * indicates MPDUs with a QoS control field. 832 * 833 */ 834 835 struct hal_ce_srng_dest_desc; 836 struct hal_ce_srng_dst_status_desc; 837 struct hal_ce_srng_src_desc; 838 839 struct hal_wbm_link_desc { 840 struct ath12k_buffer_addr buf_addr_info; 841 } __packed; 842 843 /* srng flags */ 844 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 845 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 846 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 847 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 848 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 849 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000 850 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 851 852 /* Common SRNG ring structure for source and destination rings */ 853 struct hal_srng { 854 /* Unique SRNG ring ID */ 855 u8 ring_id; 856 857 /* Ring initialization done */ 858 u8 initialized; 859 860 /* Interrupt/MSI value assigned to this ring */ 861 int irq; 862 863 /* Physical base address of the ring */ 864 dma_addr_t ring_base_paddr; 865 866 /* Virtual base address of the ring */ 867 u32 *ring_base_vaddr; 868 869 /* Number of entries in ring */ 870 u32 num_entries; 871 872 /* Ring size */ 873 u32 ring_size; 874 875 /* Ring size mask */ 876 u32 ring_size_mask; 877 878 /* Size of ring entry */ 879 u32 entry_size; 880 881 /* Interrupt timer threshold - in micro seconds */ 882 u32 intr_timer_thres_us; 883 884 /* Interrupt batch counter threshold - in number of ring entries */ 885 u32 intr_batch_cntr_thres_entries; 886 887 /* MSI Address */ 888 dma_addr_t msi_addr; 889 890 /* MSI data */ 891 u32 msi_data; 892 893 /* MSI2 Address */ 894 dma_addr_t msi2_addr; 895 896 /* MSI2 data */ 897 u32 msi2_data; 898 899 /* Misc flags */ 900 u32 flags; 901 902 /* Lock for serializing ring index updates */ 903 spinlock_t lock; 904 905 struct lock_class_key lock_key; 906 907 /* Start offset of SRNG register groups for this ring 908 * TBD: See if this is required - register address can be derived 909 * from ring ID 910 */ 911 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 912 913 u64 timestamp; 914 915 /* Source or Destination ring */ 916 enum hal_srng_dir ring_dir; 917 918 union { 919 struct { 920 /* SW tail pointer */ 921 u32 tp; 922 923 /* Shadow head pointer location to be updated by HW */ 924 volatile u32 *hp_addr; 925 926 /* Cached head pointer */ 927 u32 cached_hp; 928 929 /* Tail pointer location to be updated by SW - This 930 * will be a register address and need not be 931 * accessed through SW structure 932 */ 933 u32 *tp_addr; 934 935 /* Current SW loop cnt */ 936 u32 loop_cnt; 937 938 /* max transfer size */ 939 u16 max_buffer_length; 940 941 /* head pointer at access end */ 942 u32 last_hp; 943 } dst_ring; 944 945 struct { 946 /* SW head pointer */ 947 u32 hp; 948 949 /* SW reap head pointer */ 950 u32 reap_hp; 951 952 /* Shadow tail pointer location to be updated by HW */ 953 u32 *tp_addr; 954 955 /* Cached tail pointer */ 956 u32 cached_tp; 957 958 /* Head pointer location to be updated by SW - This 959 * will be a register address and need not be accessed 960 * through SW structure 961 */ 962 u32 *hp_addr; 963 964 /* Low threshold - in number of ring entries */ 965 u32 low_threshold; 966 967 /* tail pointer at access end */ 968 u32 last_tp; 969 } src_ring; 970 } u; 971 }; 972 973 /* hal_wbm_link_desc 974 * 975 * Producer: WBM 976 * Consumer: WBM 977 * 978 * buf_addr_info 979 * Details of the physical address of a buffer or MSDU 980 * link descriptor. 981 */ 982 983 enum hal_wbm_rel_src_module { 984 HAL_WBM_REL_SRC_MODULE_TQM, 985 HAL_WBM_REL_SRC_MODULE_RXDMA, 986 HAL_WBM_REL_SRC_MODULE_REO, 987 HAL_WBM_REL_SRC_MODULE_FW, 988 HAL_WBM_REL_SRC_MODULE_SW, 989 HAL_WBM_REL_SRC_MODULE_MAX, 990 }; 991 992 /* hal_wbm_rel_desc_type 993 * 994 * msdu_buffer 995 * The address points to an MSDU buffer 996 * 997 * msdu_link_descriptor 998 * The address points to an Tx MSDU link descriptor 999 * 1000 * mpdu_link_descriptor 1001 * The address points to an MPDU link descriptor 1002 * 1003 * msdu_ext_descriptor 1004 * The address points to an MSDU extension descriptor 1005 * 1006 * queue_ext_descriptor 1007 * The address points to an TQM queue extension descriptor. WBM should 1008 * treat this is the same way as a link descriptor. 1009 */ 1010 enum hal_wbm_rel_desc_type { 1011 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1012 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1013 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1014 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1015 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1016 }; 1017 1018 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 1019 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 1020 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 1021 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 1022 1023 /* Interrupt mitigation - timer threshold in us */ 1024 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 1025 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 1026 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 1027 1028 enum hal_srng_mac_type { 1029 ATH12K_HAL_SRNG_UMAC, 1030 ATH12K_HAL_SRNG_DMAC, 1031 ATH12K_HAL_SRNG_PMAC 1032 }; 1033 1034 /* HW SRNG configuration table */ 1035 struct hal_srng_config { 1036 int start_ring_id; 1037 u16 max_rings; 1038 u16 entry_size; 1039 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 1040 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 1041 enum hal_srng_mac_type mac_type; 1042 enum hal_srng_dir ring_dir; 1043 u32 max_size; 1044 }; 1045 1046 /** 1047 * enum hal_rx_buf_return_buf_manager - manager for returned rx buffers 1048 * 1049 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 1050 * @HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST: Descriptor returned to WBM idle 1051 * descriptor list, where the device 0 WBM is chosen in case of a multi-device config 1052 * @HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST: Descriptor returned to WBM idle 1053 * descriptor list, where the device 1 WBM is chosen in case of a multi-device config 1054 * @HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST: Descriptor returned to WBM idle 1055 * descriptor list, where the device 2 WBM is chosen in case of a multi-device config 1056 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 1057 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host 1058 * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host 1059 * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host 1060 * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host 1061 * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host 1062 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host 1063 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host 1064 */ 1065 1066 enum hal_rx_buf_return_buf_manager { 1067 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 1068 HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST, 1069 HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST, 1070 HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST, 1071 HAL_RX_BUF_RBM_FW_BM, 1072 HAL_RX_BUF_RBM_SW0_BM, 1073 HAL_RX_BUF_RBM_SW1_BM, 1074 HAL_RX_BUF_RBM_SW2_BM, 1075 HAL_RX_BUF_RBM_SW3_BM, 1076 HAL_RX_BUF_RBM_SW4_BM, 1077 HAL_RX_BUF_RBM_SW5_BM, 1078 HAL_RX_BUF_RBM_SW6_BM, 1079 }; 1080 1081 struct ath12k_hal_reo_cmd { 1082 u32 addr_lo; 1083 u32 flag; 1084 u32 upd0; 1085 u32 upd1; 1086 u32 upd2; 1087 u32 pn[4]; 1088 u16 rx_queue_num; 1089 u16 min_rel; 1090 u16 min_fwd; 1091 u8 addr_hi; 1092 u8 ac_list; 1093 u8 blocking_idx; 1094 u16 ba_window_size; 1095 u8 pn_size; 1096 }; 1097 1098 enum hal_pn_type { 1099 HAL_PN_TYPE_NONE, 1100 HAL_PN_TYPE_WPA, 1101 HAL_PN_TYPE_WAPI_EVEN, 1102 HAL_PN_TYPE_WAPI_UNEVEN, 1103 }; 1104 1105 enum hal_ce_desc { 1106 HAL_CE_DESC_SRC, 1107 HAL_CE_DESC_DST, 1108 HAL_CE_DESC_DST_STATUS, 1109 }; 1110 1111 #define HAL_HASH_ROUTING_RING_TCL 0 1112 #define HAL_HASH_ROUTING_RING_SW1 1 1113 #define HAL_HASH_ROUTING_RING_SW2 2 1114 #define HAL_HASH_ROUTING_RING_SW3 3 1115 #define HAL_HASH_ROUTING_RING_SW4 4 1116 #define HAL_HASH_ROUTING_RING_REL 5 1117 #define HAL_HASH_ROUTING_RING_FW 6 1118 1119 struct hal_reo_status_header { 1120 u16 cmd_num; 1121 enum hal_reo_cmd_status cmd_status; 1122 u16 cmd_exe_time; 1123 u32 timestamp; 1124 }; 1125 1126 struct ath12k_hw_hal_params { 1127 enum hal_rx_buf_return_buf_manager rx_buf_rbm; 1128 u32 wbm2sw_cc_enable; 1129 }; 1130 1131 #define ATH12K_HW_REG_UNDEFINED 0xdeadbeaf 1132 1133 struct ath12k_hw_regs { 1134 u32 tcl1_ring_id; 1135 u32 tcl1_ring_misc; 1136 u32 tcl1_ring_tp_addr_lsb; 1137 u32 tcl1_ring_tp_addr_msb; 1138 u32 tcl1_ring_consumer_int_setup_ix0; 1139 u32 tcl1_ring_consumer_int_setup_ix1; 1140 u32 tcl1_ring_msi1_base_lsb; 1141 u32 tcl1_ring_msi1_base_msb; 1142 u32 tcl1_ring_msi1_data; 1143 u32 tcl_ring_base_lsb; 1144 u32 tcl1_ring_base_lsb; 1145 u32 tcl1_ring_base_msb; 1146 u32 tcl2_ring_base_lsb; 1147 1148 u32 tcl_status_ring_base_lsb; 1149 1150 u32 reo1_qdesc_addr; 1151 u32 reo1_qdesc_max_peerid; 1152 1153 u32 wbm_idle_ring_base_lsb; 1154 u32 wbm_idle_ring_misc_addr; 1155 u32 wbm_r0_idle_list_cntl_addr; 1156 u32 wbm_r0_idle_list_size_addr; 1157 u32 wbm_scattered_ring_base_lsb; 1158 u32 wbm_scattered_ring_base_msb; 1159 u32 wbm_scattered_desc_head_info_ix0; 1160 u32 wbm_scattered_desc_head_info_ix1; 1161 u32 wbm_scattered_desc_tail_info_ix0; 1162 u32 wbm_scattered_desc_tail_info_ix1; 1163 u32 wbm_scattered_desc_ptr_hp_addr; 1164 1165 u32 wbm_sw_release_ring_base_lsb; 1166 u32 wbm_sw1_release_ring_base_lsb; 1167 u32 wbm0_release_ring_base_lsb; 1168 u32 wbm1_release_ring_base_lsb; 1169 1170 u32 pcie_qserdes_sysclk_en_sel; 1171 u32 pcie_pcs_osc_dtct_config_base; 1172 1173 u32 umac_ce0_src_reg_base; 1174 u32 umac_ce0_dest_reg_base; 1175 u32 umac_ce1_src_reg_base; 1176 u32 umac_ce1_dest_reg_base; 1177 1178 u32 ppe_rel_ring_base; 1179 1180 u32 reo2_ring_base; 1181 u32 reo1_misc_ctrl_addr; 1182 u32 reo1_sw_cookie_cfg0; 1183 u32 reo1_sw_cookie_cfg1; 1184 u32 reo1_qdesc_lut_base0; 1185 u32 reo1_qdesc_lut_base1; 1186 u32 reo1_ring_base_lsb; 1187 u32 reo1_ring_base_msb; 1188 u32 reo1_ring_id; 1189 u32 reo1_ring_misc; 1190 u32 reo1_ring_hp_addr_lsb; 1191 u32 reo1_ring_hp_addr_msb; 1192 u32 reo1_ring_producer_int_setup; 1193 u32 reo1_ring_msi1_base_lsb; 1194 u32 reo1_ring_msi1_base_msb; 1195 u32 reo1_ring_msi1_data; 1196 u32 reo1_aging_thres_ix0; 1197 u32 reo1_aging_thres_ix1; 1198 u32 reo1_aging_thres_ix2; 1199 u32 reo1_aging_thres_ix3; 1200 1201 u32 reo2_sw0_ring_base; 1202 1203 u32 sw2reo_ring_base; 1204 u32 sw2reo1_ring_base; 1205 1206 u32 reo_cmd_ring_base; 1207 1208 u32 reo_status_ring_base; 1209 1210 u32 gcc_gcc_pcie_hot_rst; 1211 1212 u32 qrtr_node_id; 1213 }; 1214 1215 /* HAL context to be used to access SRNG APIs (currently used by data path 1216 * and transport (CE) modules) 1217 */ 1218 struct ath12k_hal { 1219 /* HAL internal state for all SRNG rings. 1220 */ 1221 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 1222 1223 /* SRNG configuration table */ 1224 struct hal_srng_config *srng_config; 1225 1226 /* Remote pointer memory for HW/FW updates */ 1227 struct { 1228 u32 *vaddr; 1229 dma_addr_t paddr; 1230 } rdp; 1231 1232 /* Shared memory for ring pointer updates from host to FW */ 1233 struct { 1234 u32 *vaddr; 1235 dma_addr_t paddr; 1236 } wrp; 1237 1238 struct device *dev; 1239 const struct hal_ops *ops; 1240 const struct ath12k_hw_regs *regs; 1241 const struct ath12k_hw_hal_params *hal_params; 1242 /* Available REO blocking resources bitmap */ 1243 u8 avail_blk_resource; 1244 1245 u8 current_blk_index; 1246 1247 /* shadow register configuration */ 1248 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS_MAX]; 1249 int num_shadow_reg_configured; 1250 1251 u32 hal_desc_sz; 1252 u32 hal_wbm_release_ring_tx_size; 1253 1254 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 1255 }; 1256 1257 /* Maps WBM ring number and Return Buffer Manager Id per TCL ring */ 1258 struct ath12k_hal_tcl_to_wbm_rbm_map { 1259 u8 wbm_ring_num; 1260 u8 rbm_id; 1261 }; 1262 1263 enum hal_wbm_rel_bm_act { 1264 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1265 HAL_WBM_REL_BM_ACT_REL_MSDU, 1266 }; 1267 1268 /* hal_wbm_rel_bm_act 1269 * 1270 * put_in_idle_list 1271 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1272 * MDPU link descriptor, BM does not need to check to release any 1273 * individual MSDU buffers. 1274 * 1275 * release_msdu_list 1276 * This BM action can only be used in combination with desc_type being 1277 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1278 * pointer in the MSDU link descriptor is the first of an MPDU that is 1279 * released. BM shall release all the MSDU buffers linked to this first 1280 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1281 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1282 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1283 * descriptor itself shall also be released. 1284 */ 1285 1286 #define RU_INVALID 0 1287 #define RU_26 1 1288 #define RU_52 2 1289 #define RU_106 4 1290 #define RU_242 9 1291 #define RU_484 18 1292 #define RU_996 37 1293 #define RU_2X996 74 1294 #define RU_3X996 111 1295 #define RU_4X996 148 1296 #define RU_52_26 (RU_52 + RU_26) 1297 #define RU_106_26 (RU_106 + RU_26) 1298 #define RU_484_242 (RU_484 + RU_242) 1299 #define RU_996_484 (RU_996 + RU_484) 1300 #define RU_996_484_242 (RU_996 + RU_484_242) 1301 #define RU_2X996_484 (RU_2X996 + RU_484) 1302 #define RU_3X996_484 (RU_3X996 + RU_484) 1303 1304 enum ath12k_eht_ru_size { 1305 ATH12K_EHT_RU_26, 1306 ATH12K_EHT_RU_52, 1307 ATH12K_EHT_RU_106, 1308 ATH12K_EHT_RU_242, 1309 ATH12K_EHT_RU_484, 1310 ATH12K_EHT_RU_996, 1311 ATH12K_EHT_RU_996x2, 1312 ATH12K_EHT_RU_996x4, 1313 ATH12K_EHT_RU_52_26, 1314 ATH12K_EHT_RU_106_26, 1315 ATH12K_EHT_RU_484_242, 1316 ATH12K_EHT_RU_996_484, 1317 ATH12K_EHT_RU_996_484_242, 1318 ATH12K_EHT_RU_996x2_484, 1319 ATH12K_EHT_RU_996x3, 1320 ATH12K_EHT_RU_996x3_484, 1321 1322 /* Keep last */ 1323 ATH12K_EHT_RU_INVALID, 1324 }; 1325 1326 #define HAL_RX_RU_ALLOC_TYPE_MAX ATH12K_EHT_RU_INVALID 1327 1328 static inline 1329 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) 1330 { 1331 enum nl80211_he_ru_alloc ret; 1332 1333 switch (ru_tones) { 1334 case RU_52: 1335 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; 1336 break; 1337 case RU_106: 1338 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; 1339 break; 1340 case RU_242: 1341 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; 1342 break; 1343 case RU_484: 1344 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; 1345 break; 1346 case RU_996: 1347 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; 1348 break; 1349 case RU_2X996: 1350 ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 1351 break; 1352 case RU_26: 1353 fallthrough; 1354 default: 1355 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; 1356 break; 1357 } 1358 return ret; 1359 } 1360 1361 struct ath12k_hw_version_map { 1362 const struct hal_ops *hal_ops; 1363 u32 hal_desc_sz; 1364 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 1365 const struct ath12k_hw_hal_params *hal_params; 1366 const struct ath12k_hw_regs *hw_regs; 1367 }; 1368 1369 struct hal_ops { 1370 int (*create_srng_config)(struct ath12k_hal *hal); 1371 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len); 1372 void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc, 1373 struct ieee80211_hdr *hdr); 1374 void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc, 1375 u8 *crypto_hdr, 1376 enum hal_encrypt_type enctype); 1377 void (*rx_desc_copy_end_tlv)(struct hal_rx_desc *fdesc, 1378 struct hal_rx_desc *ldesc); 1379 u8 (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc); 1380 void (*extract_rx_desc_data)(struct hal_rx_desc_data *rx_desc_data, 1381 struct hal_rx_desc *rx_desc, 1382 struct hal_rx_desc *ldesc); 1383 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 1384 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 1385 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 1386 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 1387 void (*ce_dst_setup)(struct ath12k_base *ab, 1388 struct hal_srng *srng, int ring_num); 1389 void (*set_umac_srng_ptr_addr)(struct ath12k_base *ab, 1390 struct hal_srng *srng); 1391 void (*srng_src_hw_init)(struct ath12k_base *ab, struct hal_srng *srng); 1392 void (*srng_dst_hw_init)(struct ath12k_base *ab, struct hal_srng *srng); 1393 int (*srng_update_shadow_config)(struct ath12k_base *ab, 1394 enum hal_ring_type ring_type, 1395 int ring_num); 1396 int (*srng_get_ring_id)(struct ath12k_hal *hal, enum hal_ring_type type, 1397 int ring_num, int mac_id); 1398 u32 (*ce_get_desc_size)(enum hal_ce_desc type); 1399 void (*ce_src_set_desc)(struct hal_ce_srng_src_desc *desc, 1400 dma_addr_t paddr, u32 len, u32 id, 1401 u8 byte_swap_data); 1402 void (*ce_dst_set_desc)(struct hal_ce_srng_dest_desc *desc, 1403 dma_addr_t paddr); 1404 u32 (*ce_dst_status_get_length)(struct hal_ce_srng_dst_status_desc *desc); 1405 void (*set_link_desc_addr)(struct hal_wbm_link_desc *desc, u32 cookie, 1406 dma_addr_t paddr, 1407 enum hal_rx_buf_return_buf_manager rbm); 1408 void (*tx_set_dscp_tid_map)(struct ath12k_base *ab, int id); 1409 void (*tx_configure_bank_register)(struct ath12k_base *ab, 1410 u32 bank_config, u8 bank_id); 1411 void (*reoq_lut_addr_read_enable)(struct ath12k_base *ab); 1412 void (*reoq_lut_set_max_peerid)(struct ath12k_base *ab); 1413 void (*write_ml_reoq_lut_addr)(struct ath12k_base *ab, 1414 dma_addr_t paddr); 1415 void (*write_reoq_lut_addr)(struct ath12k_base *ab, dma_addr_t paddr); 1416 void (*setup_link_idle_list)(struct ath12k_base *ab, 1417 struct hal_wbm_idle_scatter_list *sbuf, 1418 u32 nsbufs, u32 tot_link_desc, 1419 u32 end_offset); 1420 void (*reo_init_cmd_ring)(struct ath12k_base *ab, 1421 struct hal_srng *srng); 1422 void (*reo_shared_qaddr_cache_clear)(struct ath12k_base *ab); 1423 void (*reo_hw_setup)(struct ath12k_base *ab, u32 ring_hash_map); 1424 void (*rx_buf_addr_info_set)(struct ath12k_buffer_addr *binfo, 1425 dma_addr_t paddr, u32 cookie, u8 manager); 1426 void (*rx_buf_addr_info_get)(struct ath12k_buffer_addr *binfo, 1427 dma_addr_t *paddr, u32 *msdu_cookies, 1428 u8 *rbm); 1429 void (*cc_config)(struct ath12k_base *ab); 1430 enum hal_rx_buf_return_buf_manager 1431 (*get_idle_link_rbm)(struct ath12k_hal *hal, u8 device_id); 1432 void (*rx_msdu_list_get)(struct ath12k *ar, 1433 void *link_desc, 1434 void *msdu_list, 1435 u16 *num_msdus); 1436 void (*rx_reo_ent_buf_paddr_get)(void *rx_desc, dma_addr_t *paddr, 1437 u32 *sw_cookie, 1438 struct ath12k_buffer_addr **pp_buf_addr, 1439 u8 *rbm, u32 *msdu_cnt); 1440 void *(*reo_cmd_enc_tlv_hdr)(void *tlv, u64 tag, u64 len); 1441 u16 (*reo_status_dec_tlv_hdr)(void *tlv, void **desc); 1442 }; 1443 1444 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 1445 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 1446 #define HAL_TLV_USR_ID GENMASK(31, 26) 1447 1448 #define HAL_TLV_ALIGN 4 1449 1450 struct hal_tlv_hdr { 1451 __le32 tl; 1452 u8 value[]; 1453 } __packed; 1454 1455 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1) 1456 #define HAL_TLV_64_HDR_LEN GENMASK(21, 10) 1457 #define HAL_TLV_64_USR_ID GENMASK(31, 26) 1458 #define HAL_TLV_64_ALIGN 8 1459 1460 struct hal_tlv_64_hdr { 1461 __le64 tl; 1462 u8 value[]; 1463 } __packed; 1464 1465 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 1466 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 1467 1468 dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab, 1469 struct hal_srng *srng); 1470 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab, 1471 struct hal_srng *srng); 1472 u32 ath12k_hal_ce_get_desc_size(struct ath12k_hal *hal, enum hal_ce_desc type); 1473 void ath12k_hal_ce_dst_set_desc(struct ath12k_hal *hal, 1474 struct hal_ce_srng_dest_desc *desc, 1475 dma_addr_t paddr); 1476 void ath12k_hal_ce_src_set_desc(struct ath12k_hal *hal, 1477 struct hal_ce_srng_src_desc *desc, 1478 dma_addr_t paddr, u32 len, u32 id, 1479 u8 byte_swap_data); 1480 int ath12k_hal_srng_get_entrysize(struct ath12k_base *ab, u32 ring_type); 1481 int ath12k_hal_srng_get_max_entries(struct ath12k_base *ab, u32 ring_type); 1482 void ath12k_hal_srng_get_params(struct ath12k_base *ab, struct hal_srng *srng, 1483 struct hal_srng_params *params); 1484 void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab, 1485 struct hal_srng *srng); 1486 void *ath12k_hal_srng_src_peek(struct ath12k_base *ab, struct hal_srng *srng); 1487 void *ath12k_hal_srng_dst_peek(struct ath12k_base *ab, struct hal_srng *srng); 1488 int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1489 bool sync_hw_ptr); 1490 void *ath12k_hal_srng_src_get_next_reaped(struct ath12k_base *ab, 1491 struct hal_srng *srng); 1492 void *ath12k_hal_srng_src_reap_next(struct ath12k_base *ab, 1493 struct hal_srng *srng); 1494 void *ath12k_hal_srng_src_next_peek(struct ath12k_base *ab, 1495 struct hal_srng *srng); 1496 void *ath12k_hal_srng_src_get_next_entry(struct ath12k_base *ab, 1497 struct hal_srng *srng); 1498 int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1499 bool sync_hw_ptr); 1500 void ath12k_hal_srng_access_begin(struct ath12k_base *ab, 1501 struct hal_srng *srng); 1502 void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng); 1503 int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type, 1504 int ring_num, int mac_id, 1505 struct hal_srng_params *params); 1506 int ath12k_hal_srng_init(struct ath12k_base *ath12k); 1507 void ath12k_hal_srng_deinit(struct ath12k_base *ath12k); 1508 void ath12k_hal_dump_srng_stats(struct ath12k_base *ab); 1509 void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab, 1510 u32 **cfg, u32 *len); 1511 int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab, 1512 enum hal_ring_type ring_type, 1513 int ring_num); 1514 void ath12k_hal_srng_shadow_config(struct ath12k_base *ab); 1515 void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, 1516 struct hal_srng *srng); 1517 void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab); 1518 void ath12k_hal_set_link_desc_addr(struct ath12k_hal *hal, 1519 struct hal_wbm_link_desc *desc, u32 cookie, 1520 dma_addr_t paddr, int rbm); 1521 void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab, 1522 struct hal_wbm_idle_scatter_list *sbuf, 1523 u32 nsbufs, u32 tot_link_desc, 1524 u32 end_offset); 1525 u32 1526 ath12k_hal_ce_dst_status_get_length(struct ath12k_hal *hal, 1527 struct hal_ce_srng_dst_status_desc *desc); 1528 void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id); 1529 void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, 1530 u32 bank_config, u8 bank_id); 1531 void ath12k_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab); 1532 void ath12k_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab); 1533 void ath12k_hal_write_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr); 1534 void 1535 ath12k_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr); 1536 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, struct hal_srng *srng); 1537 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map); 1538 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_hal *hal, 1539 struct ath12k_buffer_addr *binfo, 1540 dma_addr_t paddr, u32 cookie, u8 manager); 1541 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_hal *hal, 1542 struct ath12k_buffer_addr *binfo, 1543 dma_addr_t *paddr, u32 *msdu_cookies, 1544 u8 *rbm); 1545 void ath12k_hal_cc_config(struct ath12k_base *ab); 1546 enum hal_rx_buf_return_buf_manager 1547 ath12k_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id); 1548 void ath12k_hal_rx_msdu_list_get(struct ath12k_hal *hal, struct ath12k *ar, 1549 void *link_desc, void *msdu_list, 1550 u16 *num_msdus); 1551 void ath12k_hal_rx_reo_ent_buf_paddr_get(struct ath12k_hal *hal, void *rx_desc, 1552 dma_addr_t *paddr, u32 *sw_cookie, 1553 struct ath12k_buffer_addr **pp_buf_addr, 1554 u8 *rbm, u32 *msdu_cnt); 1555 void *ath12k_hal_encode_tlv64_hdr(void *tlv, u64 tag, u64 len); 1556 void *ath12k_hal_encode_tlv32_hdr(void *tlv, u64 tag, u64 len); 1557 u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc); 1558 u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc); 1559 #endif 1560