1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_HAL_H 8 #define ATH12K_HAL_H 9 10 #include "hal_desc.h" 11 #include "rx_desc.h" 12 13 struct ath12k_base; 14 #define HAL_CE_REMAP_REG_BASE (ab->ce_remap_base_addr) 15 16 #define HAL_LINK_DESC_SIZE (32 << 2) 17 #define HAL_LINK_DESC_ALIGN 128 18 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 19 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 20 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 21 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 22 #define HAL_MAX_AVAIL_BLK_RES 3 23 24 #define HAL_RING_BASE_ALIGN 8 25 #define HAL_REO_QLUT_ADDR_ALIGN 256 26 27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 28 /* TODO: Check with hw team on the supported scatter buf size */ 29 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 30 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 31 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 32 33 /* TODO: 16 entries per radio times MAX_VAPS_SUPPORTED */ 34 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 32 35 #define HAL_DSCP_TID_TBL_SIZE 24 36 37 /* calculate the register address from bar0 of shadow register x */ 38 #define HAL_SHADOW_BASE_ADDR 0x000008fc 39 #define HAL_SHADOW_NUM_REGS 40 40 #define HAL_HP_OFFSET_IN_REG_START 1 41 #define HAL_OFFSET_FROM_HP_TO_TP 4 42 43 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) 44 #define HAL_REO_QDESC_MAX_PEERID 8191 45 46 /* WCSS Relative address */ 47 #define HAL_SEQ_WCSS_CMEM_OFFSET 0x00100000 48 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 49 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 50 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 51 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) \ 52 ((ab)->hw_params->regs->hal_umac_ce0_src_reg_base) 53 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) \ 54 ((ab)->hw_params->regs->hal_umac_ce0_dest_reg_base) 55 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) \ 56 ((ab)->hw_params->regs->hal_umac_ce1_src_reg_base) 57 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) \ 58 ((ab)->hw_params->regs->hal_umac_ce1_dest_reg_base) 59 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 60 61 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 62 63 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c 64 65 /* SW2TCL(x) R0 ring configuration address */ 66 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020 67 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240 68 #define HAL_TCL1_RING_BASE_LSB(ab) \ 69 ((ab)->hw_params->regs->hal_tcl1_ring_base_lsb) 70 #define HAL_TCL1_RING_BASE_MSB(ab) \ 71 ((ab)->hw_params->regs->hal_tcl1_ring_base_msb) 72 #define HAL_TCL1_RING_ID(ab) ((ab)->hw_params->regs->hal_tcl1_ring_id) 73 #define HAL_TCL1_RING_MISC(ab) \ 74 ((ab)->hw_params->regs->hal_tcl1_ring_misc) 75 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \ 76 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_lsb) 77 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \ 78 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_msb) 79 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \ 80 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix0) 81 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \ 82 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix1) 83 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \ 84 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_lsb) 85 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \ 86 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb) 87 #define HAL_TCL1_RING_MSI1_DATA(ab) \ 88 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_data) 89 #define HAL_TCL2_RING_BASE_LSB(ab) \ 90 ((ab)->hw_params->regs->hal_tcl2_ring_base_lsb) 91 #define HAL_TCL_RING_BASE_LSB(ab) \ 92 ((ab)->hw_params->regs->hal_tcl_ring_base_lsb) 93 94 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 95 (HAL_TCL1_RING_MSI1_BASE_LSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 96 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 97 (HAL_TCL1_RING_MSI1_BASE_MSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 98 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 99 (HAL_TCL1_RING_MSI1_DATA(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 100 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 101 (HAL_TCL1_RING_BASE_MSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 102 #define HAL_TCL1_RING_ID_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 103 (HAL_TCL1_RING_ID(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 104 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 105 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 106 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 107 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 108 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 109 (HAL_TCL1_RING_TP_ADDR_LSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 110 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 111 (HAL_TCL1_RING_TP_ADDR_MSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 112 #define HAL_TCL1_RING_MISC_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 113 (HAL_TCL1_RING_MISC(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 114 115 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 116 #define HAL_TCL1_RING_HP 0x00002000 117 #define HAL_TCL1_RING_TP 0x00002004 118 #define HAL_TCL2_RING_HP 0x00002008 119 #define HAL_TCL_RING_HP 0x00002028 120 121 #define HAL_TCL1_RING_TP_OFFSET \ 122 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 123 124 /* TCL STATUS ring address */ 125 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ 126 ((ab)->hw_params->regs->hal_tcl_status_ring_base_lsb) 127 #define HAL_TCL_STATUS_RING_HP 0x00002048 128 129 /* PPE2TCL1 Ring address */ 130 #define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48 131 #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038 132 133 /* WBM PPE Release Ring address */ 134 #define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab) \ 135 ((ab)->hw_params->regs->hal_ppe_rel_ring_base) 136 #define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020 137 138 /* REO2SW(x) R0 ring configuration address */ 139 #define HAL_REO1_GEN_ENABLE 0x00000000 140 #define HAL_REO1_MISC_CTRL_ADDR(ab) \ 141 ((ab)->hw_params->regs->hal_reo1_misc_ctrl_addr) 142 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 143 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 144 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 145 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 146 #define HAL_REO1_QDESC_ADDR(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_addr) 147 #define HAL_REO1_QDESC_MAX_PEERID(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_max_peerid) 148 #define HAL_REO1_SW_COOKIE_CFG0(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg0) 149 #define HAL_REO1_SW_COOKIE_CFG1(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg1) 150 #define HAL_REO1_QDESC_LUT_BASE0(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base0) 151 #define HAL_REO1_QDESC_LUT_BASE1(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base1) 152 #define HAL_REO1_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_lsb) 153 #define HAL_REO1_RING_BASE_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_msb) 154 #define HAL_REO1_RING_ID(ab) ((ab)->hw_params->regs->hal_reo1_ring_id) 155 #define HAL_REO1_RING_MISC(ab) ((ab)->hw_params->regs->hal_reo1_ring_misc) 156 #define HAL_REO1_RING_HP_ADDR_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_lsb) 157 #define HAL_REO1_RING_HP_ADDR_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_msb) 158 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \ 159 ((ab)->hw_params->regs->hal_reo1_ring_producer_int_setup) 160 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \ 161 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_lsb) 162 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \ 163 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_msb) 164 #define HAL_REO1_RING_MSI1_DATA(ab) ((ab)->hw_params->regs->hal_reo1_ring_msi1_data) 165 #define HAL_REO2_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo2_ring_base) 166 #define HAL_REO1_AGING_THRESH_IX_0(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix0) 167 #define HAL_REO1_AGING_THRESH_IX_1(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix1) 168 #define HAL_REO1_AGING_THRESH_IX_2(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix2) 169 #define HAL_REO1_AGING_THRESH_IX_3(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix3) 170 171 /* REO2SW(x) R2 ring pointers (head/tail) address */ 172 #define HAL_REO1_RING_HP 0x00003048 173 #define HAL_REO1_RING_TP 0x0000304c 174 #define HAL_REO2_RING_HP 0x00003050 175 176 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) 177 178 /* REO2SW0 ring configuration address */ 179 #define HAL_REO_SW0_RING_BASE_LSB(ab) \ 180 ((ab)->hw_params->regs->hal_reo2_sw0_ring_base) 181 182 /* REO2SW0 R2 ring pointer (head/tail) address */ 183 #define HAL_REO_SW0_RING_HP 0x00003088 184 185 /* REO CMD R0 address */ 186 #define HAL_REO_CMD_RING_BASE_LSB(ab) \ 187 ((ab)->hw_params->regs->hal_reo_cmd_ring_base) 188 189 /* REO CMD R2 address */ 190 #define HAL_REO_CMD_HP 0x00003020 191 192 /* SW2REO R0 address */ 193 #define HAL_SW2REO_RING_BASE_LSB(ab) \ 194 ((ab)->hw_params->regs->hal_sw2reo_ring_base) 195 #define HAL_SW2REO1_RING_BASE_LSB(ab) \ 196 ((ab)->hw_params->regs->hal_sw2reo1_ring_base) 197 198 /* SW2REO R2 address */ 199 #define HAL_SW2REO_RING_HP 0x00003028 200 #define HAL_SW2REO1_RING_HP 0x00003030 201 202 /* CE ring R0 address */ 203 #define HAL_CE_SRC_RING_BASE_LSB 0x00000000 204 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 205 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 206 #define HAL_CE_DST_RING_CTRL 0x000000b0 207 208 /* CE ring R2 address */ 209 #define HAL_CE_DST_RING_HP 0x00000400 210 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 211 212 /* REO status address */ 213 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \ 214 ((ab)->hw_params->regs->hal_reo_status_ring_base) 215 #define HAL_REO_STATUS_HP 0x000030a8 216 217 /* WBM Idle R0 address */ 218 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab) \ 219 ((ab)->hw_params->regs->hal_wbm_idle_ring_base_lsb) 220 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab) \ 221 ((ab)->hw_params->regs->hal_wbm_idle_ring_misc_addr) 222 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(ab) \ 223 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_cntl_addr) 224 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(ab) \ 225 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_size_addr) 226 #define HAL_WBM_SCATTERED_RING_BASE_LSB(ab) \ 227 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_lsb) 228 #define HAL_WBM_SCATTERED_RING_BASE_MSB(ab) \ 229 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_msb) 230 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(ab) \ 231 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix0) 232 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(ab) \ 233 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix1) 234 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(ab) \ 235 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix0) 236 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(ab) \ 237 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix1) 238 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(ab) \ 239 ((ab)->hw_params->regs->hal_wbm_scattered_desc_ptr_hp_addr) 240 241 /* WBM Idle R2 address */ 242 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b8 243 244 /* SW2WBM R0 release address */ 245 #define HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab) \ 246 ((ab)->hw_params->regs->hal_wbm_sw_release_ring_base_lsb) 247 #define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) \ 248 ((ab)->hw_params->regs->hal_wbm_sw1_release_ring_base_lsb) 249 250 /* SW2WBM R2 release address */ 251 #define HAL_WBM_SW_RELEASE_RING_HP 0x00003010 252 #define HAL_WBM_SW1_RELEASE_RING_HP 0x00003018 253 254 /* WBM2SW R0 release address */ 255 #define HAL_WBM0_RELEASE_RING_BASE_LSB(ab) \ 256 ((ab)->hw_params->regs->hal_wbm0_release_ring_base_lsb) 257 258 #define HAL_WBM1_RELEASE_RING_BASE_LSB(ab) \ 259 ((ab)->hw_params->regs->hal_wbm1_release_ring_base_lsb) 260 261 /* WBM2SW R2 release address */ 262 #define HAL_WBM0_RELEASE_RING_HP 0x000030c8 263 #define HAL_WBM1_RELEASE_RING_HP 0x000030d0 264 265 /* WBM cookie config address and mask */ 266 #define HAL_WBM_SW_COOKIE_CFG0 0x00000040 267 #define HAL_WBM_SW_COOKIE_CFG1 0x00000044 268 #define HAL_WBM_SW_COOKIE_CFG2 0x00000090 269 #define HAL_WBM_SW_COOKIE_CONVERT_CFG 0x00000094 270 271 #define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 272 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 273 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 274 #define HAL_WBM_SW_COOKIE_CFG_ALIGN BIT(18) 275 #define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0) 276 #define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN BIT(1) 277 #define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3) 278 279 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1) 280 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2) 281 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3) 282 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4) 283 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5) 284 #define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8) 285 286 /* TCL ring field mask and offset */ 287 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 288 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 289 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 290 #define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0) 291 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 292 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 293 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 294 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 295 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 296 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 297 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 298 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 299 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 300 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 301 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(23) 302 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 303 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 304 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 305 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 306 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 307 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 308 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 309 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 310 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 311 312 /* REO ring field mask and offset */ 313 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 314 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 315 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 316 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 317 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 318 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 319 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 320 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 321 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 322 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 323 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 324 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 325 #define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17) 326 #define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21) 327 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 328 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 329 #define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 330 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 331 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 332 #define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18) 333 #define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19) 334 #define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20) 335 #define HAL_REO_QDESC_ADDR_READ_LUT_ENABLE BIT(7) 336 #define HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY BIT(6) 337 338 /* CE ring bit field mask and shift */ 339 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 340 341 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 342 343 #define HAL_ADDR_MSB_REG_SHIFT 32 344 345 /* WBM ring bit field mask and shift */ 346 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 347 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 348 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 349 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 350 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 351 352 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 353 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 354 355 #define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE BIT(6) 356 #define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0) 357 358 #define BASE_ADDR_MATCH_TAG_VAL 0x5 359 360 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 361 #define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE 0x000fffff 362 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 363 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 364 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 365 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 366 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 367 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 368 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 369 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 370 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 371 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x000fffff 372 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 373 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 374 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 375 #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff 376 #define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 377 378 #define HAL_WBM2SW_REL_ERR_RING_NUM 3 379 /* Add any other errors here and return them in 380 * ath12k_hal_rx_desc_get_err(). 381 */ 382 383 #define HAL_IPQ5332_CE_WFSS_REG_BASE 0x740000 384 #define HAL_IPQ5332_CE_SIZE 0x100000 385 386 enum hal_srng_ring_id { 387 HAL_SRNG_RING_ID_REO2SW0 = 0, 388 HAL_SRNG_RING_ID_REO2SW1, 389 HAL_SRNG_RING_ID_REO2SW2, 390 HAL_SRNG_RING_ID_REO2SW3, 391 HAL_SRNG_RING_ID_REO2SW4, 392 HAL_SRNG_RING_ID_REO2SW5, 393 HAL_SRNG_RING_ID_REO2SW6, 394 HAL_SRNG_RING_ID_REO2SW7, 395 HAL_SRNG_RING_ID_REO2SW8, 396 HAL_SRNG_RING_ID_REO2TCL, 397 HAL_SRNG_RING_ID_REO2PPE, 398 399 HAL_SRNG_RING_ID_SW2REO = 16, 400 HAL_SRNG_RING_ID_SW2REO1, 401 HAL_SRNG_RING_ID_SW2REO2, 402 HAL_SRNG_RING_ID_SW2REO3, 403 404 HAL_SRNG_RING_ID_REO_CMD, 405 HAL_SRNG_RING_ID_REO_STATUS, 406 407 HAL_SRNG_RING_ID_SW2TCL1 = 24, 408 HAL_SRNG_RING_ID_SW2TCL2, 409 HAL_SRNG_RING_ID_SW2TCL3, 410 HAL_SRNG_RING_ID_SW2TCL4, 411 HAL_SRNG_RING_ID_SW2TCL5, 412 HAL_SRNG_RING_ID_SW2TCL6, 413 HAL_SRNG_RING_ID_PPE2TCL1 = 30, 414 415 HAL_SRNG_RING_ID_SW2TCL_CMD = 40, 416 HAL_SRNG_RING_ID_SW2TCL1_CMD, 417 HAL_SRNG_RING_ID_TCL_STATUS, 418 419 HAL_SRNG_RING_ID_CE0_SRC = 64, 420 HAL_SRNG_RING_ID_CE1_SRC, 421 HAL_SRNG_RING_ID_CE2_SRC, 422 HAL_SRNG_RING_ID_CE3_SRC, 423 HAL_SRNG_RING_ID_CE4_SRC, 424 HAL_SRNG_RING_ID_CE5_SRC, 425 HAL_SRNG_RING_ID_CE6_SRC, 426 HAL_SRNG_RING_ID_CE7_SRC, 427 HAL_SRNG_RING_ID_CE8_SRC, 428 HAL_SRNG_RING_ID_CE9_SRC, 429 HAL_SRNG_RING_ID_CE10_SRC, 430 HAL_SRNG_RING_ID_CE11_SRC, 431 HAL_SRNG_RING_ID_CE12_SRC, 432 HAL_SRNG_RING_ID_CE13_SRC, 433 HAL_SRNG_RING_ID_CE14_SRC, 434 HAL_SRNG_RING_ID_CE15_SRC, 435 436 HAL_SRNG_RING_ID_CE0_DST = 81, 437 HAL_SRNG_RING_ID_CE1_DST, 438 HAL_SRNG_RING_ID_CE2_DST, 439 HAL_SRNG_RING_ID_CE3_DST, 440 HAL_SRNG_RING_ID_CE4_DST, 441 HAL_SRNG_RING_ID_CE5_DST, 442 HAL_SRNG_RING_ID_CE6_DST, 443 HAL_SRNG_RING_ID_CE7_DST, 444 HAL_SRNG_RING_ID_CE8_DST, 445 HAL_SRNG_RING_ID_CE9_DST, 446 HAL_SRNG_RING_ID_CE10_DST, 447 HAL_SRNG_RING_ID_CE11_DST, 448 HAL_SRNG_RING_ID_CE12_DST, 449 HAL_SRNG_RING_ID_CE13_DST, 450 HAL_SRNG_RING_ID_CE14_DST, 451 HAL_SRNG_RING_ID_CE15_DST, 452 453 HAL_SRNG_RING_ID_CE0_DST_STATUS = 100, 454 HAL_SRNG_RING_ID_CE1_DST_STATUS, 455 HAL_SRNG_RING_ID_CE2_DST_STATUS, 456 HAL_SRNG_RING_ID_CE3_DST_STATUS, 457 HAL_SRNG_RING_ID_CE4_DST_STATUS, 458 HAL_SRNG_RING_ID_CE5_DST_STATUS, 459 HAL_SRNG_RING_ID_CE6_DST_STATUS, 460 HAL_SRNG_RING_ID_CE7_DST_STATUS, 461 HAL_SRNG_RING_ID_CE8_DST_STATUS, 462 HAL_SRNG_RING_ID_CE9_DST_STATUS, 463 HAL_SRNG_RING_ID_CE10_DST_STATUS, 464 HAL_SRNG_RING_ID_CE11_DST_STATUS, 465 HAL_SRNG_RING_ID_CE12_DST_STATUS, 466 HAL_SRNG_RING_ID_CE13_DST_STATUS, 467 HAL_SRNG_RING_ID_CE14_DST_STATUS, 468 HAL_SRNG_RING_ID_CE15_DST_STATUS, 469 470 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120, 471 HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 472 HAL_SRNG_RING_ID_WBM_SW1_RELEASE, 473 HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123, 474 475 HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128, 476 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 477 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 478 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */ 479 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 480 HAL_SRNG_RING_ID_WBM2SW5_RELEASE, 481 HAL_SRNG_RING_ID_WBM2SW6_RELEASE, 482 HAL_SRNG_RING_ID_WBM2SW7_RELEASE, 483 484 HAL_SRNG_RING_ID_UMAC_ID_END = 159, 485 486 /* Common DMAC rings shared by all LMACs */ 487 HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160, 488 HAL_SRNG_SW2RXDMA_BUF0 = HAL_SRNG_RING_ID_DMAC_CMN_ID_START, 489 HAL_SRNG_SW2RXDMA_BUF1 = 161, 490 HAL_SRNG_SW2RXDMA_BUF2 = 162, 491 492 HAL_SRNG_SW2RXMON_BUF0 = 168, 493 494 HAL_SRNG_SW2TXMON_BUF0 = 176, 495 496 HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183, 497 HAL_SRNG_RING_ID_PMAC1_ID_START = 184, 498 499 HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 = HAL_SRNG_RING_ID_PMAC1_ID_START, 500 501 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 502 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 503 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 504 HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 505 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 506 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 507 HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, 508 HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, 509 510 HAL_SRNG_RING_ID_PMAC1_ID_END, 511 }; 512 513 /* SRNG registers are split into two groups R0 and R2 */ 514 #define HAL_SRNG_REG_GRP_R0 0 515 #define HAL_SRNG_REG_GRP_R2 1 516 #define HAL_SRNG_NUM_REG_GRP 2 517 518 /* TODO: number of PMACs */ 519 #define HAL_SRNG_NUM_PMACS 3 520 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \ 521 HAL_SRNG_RING_ID_DMAC_CMN_ID_START) 522 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \ 523 HAL_SRNG_RING_ID_PMAC1_ID_START) 524 #define HAL_SRNG_NUM_PMAC_RINGS (HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC) 525 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_DMAC_CMN_ID_END + \ 526 HAL_SRNG_NUM_PMAC_RINGS) 527 528 enum hal_ring_type { 529 HAL_REO_DST, 530 HAL_REO_EXCEPTION, 531 HAL_REO_REINJECT, 532 HAL_REO_CMD, 533 HAL_REO_STATUS, 534 HAL_TCL_DATA, 535 HAL_TCL_CMD, 536 HAL_TCL_STATUS, 537 HAL_CE_SRC, 538 HAL_CE_DST, 539 HAL_CE_DST_STATUS, 540 HAL_WBM_IDLE_LINK, 541 HAL_SW2WBM_RELEASE, 542 HAL_WBM2SW_RELEASE, 543 HAL_RXDMA_BUF, 544 HAL_RXDMA_DST, 545 HAL_RXDMA_MONITOR_BUF, 546 HAL_RXDMA_MONITOR_STATUS, 547 HAL_RXDMA_MONITOR_DST, 548 HAL_RXDMA_MONITOR_DESC, 549 HAL_RXDMA_DIR_BUF, 550 HAL_PPE2TCL, 551 HAL_PPE_RELEASE, 552 HAL_TX_MONITOR_BUF, 553 HAL_TX_MONITOR_DST, 554 HAL_MAX_RING_TYPES, 555 }; 556 557 #define HAL_RX_MAX_BA_WINDOW 256 558 559 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000) 560 #define HAL_DEFAULT_VO_REO_TIMEOUT_USEC (40 * 1000) 561 562 /** 563 * enum hal_reo_cmd_type: Enum for REO command type 564 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 565 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 566 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 567 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 568 * earlier with a 'REO_FLUSH_CACHE' command 569 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 570 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 571 */ 572 enum hal_reo_cmd_type { 573 HAL_REO_CMD_GET_QUEUE_STATS = 0, 574 HAL_REO_CMD_FLUSH_QUEUE = 1, 575 HAL_REO_CMD_FLUSH_CACHE = 2, 576 HAL_REO_CMD_UNBLOCK_CACHE = 3, 577 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 578 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 579 }; 580 581 /** 582 * enum hal_reo_cmd_status: Enum for execution status of REO command 583 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 584 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 585 * or cache was blocked 586 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 587 * invalid queue desc 588 * @HAL_REO_CMD_RESOURCE_BLOCKED: 589 * @HAL_REO_CMD_DRAIN: 590 */ 591 enum hal_reo_cmd_status { 592 HAL_REO_CMD_SUCCESS = 0, 593 HAL_REO_CMD_BLOCKED = 1, 594 HAL_REO_CMD_FAILED = 2, 595 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 596 HAL_REO_CMD_DRAIN = 0xff, 597 }; 598 599 struct hal_wbm_idle_scatter_list { 600 dma_addr_t paddr; 601 struct hal_wbm_link_desc *vaddr; 602 }; 603 604 struct hal_srng_params { 605 dma_addr_t ring_base_paddr; 606 u32 *ring_base_vaddr; 607 int num_entries; 608 u32 intr_batch_cntr_thres_entries; 609 u32 intr_timer_thres_us; 610 u32 flags; 611 u32 max_buffer_len; 612 u32 low_threshold; 613 u32 high_threshold; 614 dma_addr_t msi_addr; 615 dma_addr_t msi2_addr; 616 u32 msi_data; 617 u32 msi2_data; 618 619 /* Add more params as needed */ 620 }; 621 622 enum hal_srng_dir { 623 HAL_SRNG_DIR_SRC, 624 HAL_SRNG_DIR_DST 625 }; 626 627 /* srng flags */ 628 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 629 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 630 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 631 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 632 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 633 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000 634 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 635 636 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 637 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 638 639 /* Common SRNG ring structure for source and destination rings */ 640 struct hal_srng { 641 /* Unique SRNG ring ID */ 642 u8 ring_id; 643 644 /* Ring initialization done */ 645 u8 initialized; 646 647 /* Interrupt/MSI value assigned to this ring */ 648 int irq; 649 650 /* Physical base address of the ring */ 651 dma_addr_t ring_base_paddr; 652 653 /* Virtual base address of the ring */ 654 u32 *ring_base_vaddr; 655 656 /* Number of entries in ring */ 657 u32 num_entries; 658 659 /* Ring size */ 660 u32 ring_size; 661 662 /* Ring size mask */ 663 u32 ring_size_mask; 664 665 /* Size of ring entry */ 666 u32 entry_size; 667 668 /* Interrupt timer threshold - in micro seconds */ 669 u32 intr_timer_thres_us; 670 671 /* Interrupt batch counter threshold - in number of ring entries */ 672 u32 intr_batch_cntr_thres_entries; 673 674 /* MSI Address */ 675 dma_addr_t msi_addr; 676 677 /* MSI data */ 678 u32 msi_data; 679 680 /* MSI2 Address */ 681 dma_addr_t msi2_addr; 682 683 /* MSI2 data */ 684 u32 msi2_data; 685 686 /* Misc flags */ 687 u32 flags; 688 689 /* Lock for serializing ring index updates */ 690 spinlock_t lock; 691 692 struct lock_class_key lock_key; 693 694 /* Start offset of SRNG register groups for this ring 695 * TBD: See if this is required - register address can be derived 696 * from ring ID 697 */ 698 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 699 700 u64 timestamp; 701 702 /* Source or Destination ring */ 703 enum hal_srng_dir ring_dir; 704 705 union { 706 struct { 707 /* SW tail pointer */ 708 u32 tp; 709 710 /* Shadow head pointer location to be updated by HW */ 711 volatile u32 *hp_addr; 712 713 /* Cached head pointer */ 714 u32 cached_hp; 715 716 /* Tail pointer location to be updated by SW - This 717 * will be a register address and need not be 718 * accessed through SW structure 719 */ 720 u32 *tp_addr; 721 722 /* Current SW loop cnt */ 723 u32 loop_cnt; 724 725 /* max transfer size */ 726 u16 max_buffer_length; 727 728 /* head pointer at access end */ 729 u32 last_hp; 730 } dst_ring; 731 732 struct { 733 /* SW head pointer */ 734 u32 hp; 735 736 /* SW reap head pointer */ 737 u32 reap_hp; 738 739 /* Shadow tail pointer location to be updated by HW */ 740 u32 *tp_addr; 741 742 /* Cached tail pointer */ 743 u32 cached_tp; 744 745 /* Head pointer location to be updated by SW - This 746 * will be a register address and need not be accessed 747 * through SW structure 748 */ 749 u32 *hp_addr; 750 751 /* Low threshold - in number of ring entries */ 752 u32 low_threshold; 753 754 /* tail pointer at access end */ 755 u32 last_tp; 756 } src_ring; 757 } u; 758 }; 759 760 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 761 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 762 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 763 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 764 765 /* Interrupt mitigation - timer threshold in us */ 766 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 767 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 768 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 769 770 enum hal_srng_mac_type { 771 ATH12K_HAL_SRNG_UMAC, 772 ATH12K_HAL_SRNG_DMAC, 773 ATH12K_HAL_SRNG_PMAC 774 }; 775 776 /* HW SRNG configuration table */ 777 struct hal_srng_config { 778 int start_ring_id; 779 u16 max_rings; 780 u16 entry_size; 781 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 782 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 783 enum hal_srng_mac_type mac_type; 784 enum hal_srng_dir ring_dir; 785 u32 max_size; 786 }; 787 788 /** 789 * enum hal_rx_buf_return_buf_manager - manager for returned rx buffers 790 * 791 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 792 * @HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST: Descriptor returned to WBM idle 793 * descriptor list, where the device 0 WBM is chosen in case of a multi-device config 794 * @HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST: Descriptor returned to WBM idle 795 * descriptor list, where the device 1 WBM is chosen in case of a multi-device config 796 * @HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST: Descriptor returned to WBM idle 797 * descriptor list, where the device 2 WBM is chosen in case of a multi-device config 798 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 799 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host 800 * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host 801 * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host 802 * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host 803 * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host 804 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host 805 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host 806 */ 807 808 enum hal_rx_buf_return_buf_manager { 809 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 810 HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST, 811 HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST, 812 HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST, 813 HAL_RX_BUF_RBM_FW_BM, 814 HAL_RX_BUF_RBM_SW0_BM, 815 HAL_RX_BUF_RBM_SW1_BM, 816 HAL_RX_BUF_RBM_SW2_BM, 817 HAL_RX_BUF_RBM_SW3_BM, 818 HAL_RX_BUF_RBM_SW4_BM, 819 HAL_RX_BUF_RBM_SW5_BM, 820 HAL_RX_BUF_RBM_SW6_BM, 821 }; 822 823 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 824 825 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 826 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 827 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 828 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 829 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 830 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 831 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 832 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 833 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 834 835 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */ 836 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 837 #define HAL_REO_CMD_UPD0_VLD BIT(9) 838 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 839 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 840 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 841 #define HAL_REO_CMD_UPD0_AC BIT(13) 842 #define HAL_REO_CMD_UPD0_BAR BIT(14) 843 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 844 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 845 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 846 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 847 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 848 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 849 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 850 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 851 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 852 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 853 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 854 #define HAL_REO_CMD_UPD0_SSN BIT(26) 855 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 856 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 857 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 858 #define HAL_REO_CMD_UPD0_PN BIT(30) 859 860 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */ 861 #define HAL_REO_CMD_UPD1_VLD BIT(16) 862 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 863 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 864 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 865 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 866 #define HAL_REO_CMD_UPD1_BAR BIT(23) 867 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 868 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 869 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 870 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 871 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 872 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 873 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 874 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 875 876 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */ 877 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 878 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 879 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 880 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 881 882 struct ath12k_hal_reo_cmd { 883 u32 addr_lo; 884 u32 flag; 885 u32 upd0; 886 u32 upd1; 887 u32 upd2; 888 u32 pn[4]; 889 u16 rx_queue_num; 890 u16 min_rel; 891 u16 min_fwd; 892 u8 addr_hi; 893 u8 ac_list; 894 u8 blocking_idx; 895 u16 ba_window_size; 896 u8 pn_size; 897 }; 898 899 enum hal_pn_type { 900 HAL_PN_TYPE_NONE, 901 HAL_PN_TYPE_WPA, 902 HAL_PN_TYPE_WAPI_EVEN, 903 HAL_PN_TYPE_WAPI_UNEVEN, 904 }; 905 906 enum hal_ce_desc { 907 HAL_CE_DESC_SRC, 908 HAL_CE_DESC_DST, 909 HAL_CE_DESC_DST_STATUS, 910 }; 911 912 #define HAL_HASH_ROUTING_RING_TCL 0 913 #define HAL_HASH_ROUTING_RING_SW1 1 914 #define HAL_HASH_ROUTING_RING_SW2 2 915 #define HAL_HASH_ROUTING_RING_SW3 3 916 #define HAL_HASH_ROUTING_RING_SW4 4 917 #define HAL_HASH_ROUTING_RING_REL 5 918 #define HAL_HASH_ROUTING_RING_FW 6 919 920 struct hal_reo_status_header { 921 u16 cmd_num; 922 enum hal_reo_cmd_status cmd_status; 923 u16 cmd_exe_time; 924 u32 timestamp; 925 }; 926 927 struct hal_reo_status_queue_stats { 928 u16 ssn; 929 u16 curr_idx; 930 u32 pn[4]; 931 u32 last_rx_queue_ts; 932 u32 last_rx_dequeue_ts; 933 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 934 u32 curr_mpdu_cnt; 935 u32 curr_msdu_cnt; 936 u16 fwd_due_to_bar_cnt; 937 u16 dup_cnt; 938 u32 frames_in_order_cnt; 939 u32 num_mpdu_processed_cnt; 940 u32 num_msdu_processed_cnt; 941 u32 total_num_processed_byte_cnt; 942 u32 late_rx_mpdu_cnt; 943 u32 reorder_hole_cnt; 944 u8 timeout_cnt; 945 u8 bar_rx_cnt; 946 u8 num_window_2k_jump_cnt; 947 }; 948 949 struct hal_reo_status_flush_queue { 950 bool err_detected; 951 }; 952 953 enum hal_reo_status_flush_cache_err_code { 954 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 955 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 956 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 957 }; 958 959 struct hal_reo_status_flush_cache { 960 bool err_detected; 961 enum hal_reo_status_flush_cache_err_code err_code; 962 bool cache_controller_flush_status_hit; 963 u8 cache_controller_flush_status_desc_type; 964 u8 cache_controller_flush_status_client_id; 965 u8 cache_controller_flush_status_err; 966 u8 cache_controller_flush_status_cnt; 967 }; 968 969 enum hal_reo_status_unblock_cache_type { 970 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 971 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 972 }; 973 974 struct hal_reo_status_unblock_cache { 975 bool err_detected; 976 enum hal_reo_status_unblock_cache_type unblock_type; 977 }; 978 979 struct hal_reo_status_flush_timeout_list { 980 bool err_detected; 981 bool list_empty; 982 u16 release_desc_cnt; 983 u16 fwd_buf_cnt; 984 }; 985 986 enum hal_reo_threshold_idx { 987 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 988 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 989 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 990 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 991 }; 992 993 struct hal_reo_status_desc_thresh_reached { 994 enum hal_reo_threshold_idx threshold_idx; 995 u32 link_desc_counter0; 996 u32 link_desc_counter1; 997 u32 link_desc_counter2; 998 u32 link_desc_counter_sum; 999 }; 1000 1001 struct hal_reo_status { 1002 struct hal_reo_status_header uniform_hdr; 1003 u8 loop_cnt; 1004 union { 1005 struct hal_reo_status_queue_stats queue_stats; 1006 struct hal_reo_status_flush_queue flush_queue; 1007 struct hal_reo_status_flush_cache flush_cache; 1008 struct hal_reo_status_unblock_cache unblock_cache; 1009 struct hal_reo_status_flush_timeout_list timeout_list; 1010 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 1011 } u; 1012 }; 1013 1014 /* HAL context to be used to access SRNG APIs (currently used by data path 1015 * and transport (CE) modules) 1016 */ 1017 struct ath12k_hal { 1018 /* HAL internal state for all SRNG rings. 1019 */ 1020 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 1021 1022 /* SRNG configuration table */ 1023 struct hal_srng_config *srng_config; 1024 1025 /* Remote pointer memory for HW/FW updates */ 1026 struct { 1027 u32 *vaddr; 1028 dma_addr_t paddr; 1029 } rdp; 1030 1031 /* Shared memory for ring pointer updates from host to FW */ 1032 struct { 1033 u32 *vaddr; 1034 dma_addr_t paddr; 1035 } wrp; 1036 1037 /* Available REO blocking resources bitmap */ 1038 u8 avail_blk_resource; 1039 1040 u8 current_blk_index; 1041 1042 /* shadow register configuration */ 1043 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS]; 1044 int num_shadow_reg_configured; 1045 1046 u32 hal_desc_sz; 1047 }; 1048 1049 /* Maps WBM ring number and Return Buffer Manager Id per TCL ring */ 1050 struct ath12k_hal_tcl_to_wbm_rbm_map { 1051 u8 wbm_ring_num; 1052 u8 rbm_id; 1053 }; 1054 1055 struct hal_rx_ops { 1056 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc); 1057 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc); 1058 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 1059 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc); 1060 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc); 1061 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc); 1062 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc); 1063 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc); 1064 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc); 1065 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc); 1066 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc); 1067 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc); 1068 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc); 1069 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc); 1070 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc); 1071 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc); 1072 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc); 1073 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc); 1074 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc); 1075 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc); 1076 void (*rx_desc_copy_end_tlv)(struct hal_rx_desc *fdesc, 1077 struct hal_rx_desc *ldesc); 1078 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 1079 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 1080 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len); 1081 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc); 1082 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 1083 u32 (*rx_desc_get_mpdu_start_offset)(void); 1084 u32 (*rx_desc_get_msdu_end_offset)(void); 1085 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc); 1086 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc); 1087 bool (*rx_desc_is_da_mcbc)(struct hal_rx_desc *desc); 1088 void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc, 1089 struct ieee80211_hdr *hdr); 1090 void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc, 1091 u8 *crypto_hdr, 1092 enum hal_encrypt_type enctype); 1093 bool (*dp_rx_h_msdu_done)(struct hal_rx_desc *desc); 1094 bool (*dp_rx_h_l4_cksum_fail)(struct hal_rx_desc *desc); 1095 bool (*dp_rx_h_ip_cksum_fail)(struct hal_rx_desc *desc); 1096 bool (*dp_rx_h_is_decrypted)(struct hal_rx_desc *desc); 1097 u32 (*dp_rx_h_mpdu_err)(struct hal_rx_desc *desc); 1098 u32 (*rx_desc_get_desc_size)(void); 1099 u8 (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc); 1100 }; 1101 1102 struct hal_ops { 1103 int (*create_srng_config)(struct ath12k_base *ab); 1104 u16 (*rxdma_ring_wmask_rx_mpdu_start)(void); 1105 u32 (*rxdma_ring_wmask_rx_msdu_end)(void); 1106 const struct hal_rx_ops *(*get_hal_rx_compact_ops)(void); 1107 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 1108 }; 1109 1110 extern const struct hal_ops hal_qcn9274_ops; 1111 extern const struct hal_ops hal_wcn7850_ops; 1112 1113 extern const struct hal_rx_ops hal_rx_qcn9274_ops; 1114 extern const struct hal_rx_ops hal_rx_qcn9274_compact_ops; 1115 extern const struct hal_rx_ops hal_rx_wcn7850_ops; 1116 1117 u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 1118 void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, 1119 int tid, u32 ba_window_size, 1120 u32 start_seq, enum hal_pn_type type); 1121 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, 1122 struct hal_srng *srng); 1123 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map); 1124 void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab, 1125 struct hal_wbm_idle_scatter_list *sbuf, 1126 u32 nsbufs, u32 tot_link_desc, 1127 u32 end_offset); 1128 1129 dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab, 1130 struct hal_srng *srng); 1131 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab, 1132 struct hal_srng *srng); 1133 void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 1134 dma_addr_t paddr, 1135 enum hal_rx_buf_return_buf_manager rbm); 1136 u32 ath12k_hal_ce_get_desc_size(enum hal_ce_desc type); 1137 void ath12k_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, dma_addr_t paddr, 1138 u32 len, u32 id, u8 byte_swap_data); 1139 void ath12k_hal_ce_dst_set_desc(struct hal_ce_srng_dest_desc *desc, dma_addr_t paddr); 1140 u32 ath12k_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc); 1141 int ath12k_hal_srng_get_entrysize(struct ath12k_base *ab, u32 ring_type); 1142 int ath12k_hal_srng_get_max_entries(struct ath12k_base *ab, u32 ring_type); 1143 void ath12k_hal_srng_get_params(struct ath12k_base *ab, struct hal_srng *srng, 1144 struct hal_srng_params *params); 1145 void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab, 1146 struct hal_srng *srng); 1147 void *ath12k_hal_srng_src_peek(struct ath12k_base *ab, struct hal_srng *srng); 1148 void *ath12k_hal_srng_dst_peek(struct ath12k_base *ab, struct hal_srng *srng); 1149 int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1150 bool sync_hw_ptr); 1151 void *ath12k_hal_srng_src_get_next_reaped(struct ath12k_base *ab, 1152 struct hal_srng *srng); 1153 void *ath12k_hal_srng_src_reap_next(struct ath12k_base *ab, 1154 struct hal_srng *srng); 1155 void *ath12k_hal_srng_src_next_peek(struct ath12k_base *ab, 1156 struct hal_srng *srng); 1157 void *ath12k_hal_srng_src_get_next_entry(struct ath12k_base *ab, 1158 struct hal_srng *srng); 1159 int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1160 bool sync_hw_ptr); 1161 void ath12k_hal_srng_access_begin(struct ath12k_base *ab, 1162 struct hal_srng *srng); 1163 void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng); 1164 int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type, 1165 int ring_num, int mac_id, 1166 struct hal_srng_params *params); 1167 int ath12k_hal_srng_init(struct ath12k_base *ath12k); 1168 void ath12k_hal_srng_deinit(struct ath12k_base *ath12k); 1169 void ath12k_hal_dump_srng_stats(struct ath12k_base *ab); 1170 void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab, 1171 u32 **cfg, u32 *len); 1172 int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab, 1173 enum hal_ring_type ring_type, 1174 int ring_num); 1175 void ath12k_hal_srng_shadow_config(struct ath12k_base *ab); 1176 void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, 1177 struct hal_srng *srng); 1178 void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab); 1179 #endif 1180