1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_HAL_H 8 #define ATH12K_HAL_H 9 10 #include "hw.h" 11 12 struct ath12k_base; 13 14 #define HAL_DESC_REO_NON_QOS_TID 16 15 16 #define HAL_INVALID_PEERID 0x3fff 17 #define VHT_SIG_SU_NSS_MASK 0x7 18 19 #define HAL_TX_ADDRX_EN 1 20 #define HAL_TX_ADDRY_EN 2 21 22 #define HAL_TX_ADDR_SEARCH_DEFAULT 0 23 #define HAL_TX_ADDR_SEARCH_INDEX 1 24 25 #define HAL_RX_MAX_MPDU 256 26 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 27 28 /* TODO: 16 entries per radio times MAX_VAPS_SUPPORTED */ 29 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 32 30 #define HAL_DSCP_TID_TBL_SIZE 24 31 32 #define EHT_MAX_USER_INFO 4 33 #define HAL_RX_MON_MAX_AGGR_SIZE 128 34 #define HAL_MAX_UL_MU_USERS 37 35 36 #define MAX_USER_POS 8 37 #define MAX_MU_GROUP_ID 64 38 #define MAX_MU_GROUP_SHOW 16 39 #define MAX_MU_GROUP_LENGTH (6 * MAX_MU_GROUP_SHOW) 40 41 #define HAL_CE_REMAP_REG_BASE (ab->ce_remap_base_addr) 42 43 #define HAL_LINK_DESC_SIZE (32 << 2) 44 #define HAL_LINK_DESC_ALIGN 128 45 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 46 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 47 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 48 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 49 #define HAL_MAX_AVAIL_BLK_RES 3 50 51 #define HAL_RING_BASE_ALIGN 8 52 #define HAL_REO_QLUT_ADDR_ALIGN 256 53 54 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 55 #define HAL_ADDR_MSB_REG_SHIFT 32 56 57 #define HAL_WBM2SW_REL_ERR_RING_NUM 3 58 59 #define HAL_SHADOW_NUM_REGS_MAX 40 60 61 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 62 /* TODO: Check with hw team on the supported scatter buf size */ 63 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 64 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 65 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 66 67 #define HAL_AST_IDX_INVALID 0xFFFF 68 #define HAL_RX_MAX_MCS 12 69 #define HAL_RX_MAX_MCS_HT 31 70 #define HAL_RX_MAX_MCS_VHT 9 71 #define HAL_RX_MAX_MCS_HE 11 72 #define HAL_RX_MAX_MCS_BE 15 73 #define HAL_RX_MAX_NSS 8 74 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 75 76 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30) 77 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31) 78 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0) 79 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3) 80 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7) 81 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8) 82 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9) 83 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16) 84 #define HAL_RX_FCS_LEN 4 85 86 enum hal_srng_ring_id { 87 HAL_SRNG_RING_ID_REO2SW0 = 0, 88 HAL_SRNG_RING_ID_REO2SW1, 89 HAL_SRNG_RING_ID_REO2SW2, 90 HAL_SRNG_RING_ID_REO2SW3, 91 HAL_SRNG_RING_ID_REO2SW4, 92 HAL_SRNG_RING_ID_REO2SW5, 93 HAL_SRNG_RING_ID_REO2SW6, 94 HAL_SRNG_RING_ID_REO2SW7, 95 HAL_SRNG_RING_ID_REO2SW8, 96 HAL_SRNG_RING_ID_REO2TCL, 97 HAL_SRNG_RING_ID_REO2PPE, 98 99 HAL_SRNG_RING_ID_SW2REO = 16, 100 HAL_SRNG_RING_ID_SW2REO1, 101 HAL_SRNG_RING_ID_SW2REO2, 102 HAL_SRNG_RING_ID_SW2REO3, 103 104 HAL_SRNG_RING_ID_REO_CMD, 105 HAL_SRNG_RING_ID_REO_STATUS, 106 107 HAL_SRNG_RING_ID_SW2TCL1 = 24, 108 HAL_SRNG_RING_ID_SW2TCL2, 109 HAL_SRNG_RING_ID_SW2TCL3, 110 HAL_SRNG_RING_ID_SW2TCL4, 111 HAL_SRNG_RING_ID_SW2TCL5, 112 HAL_SRNG_RING_ID_SW2TCL6, 113 HAL_SRNG_RING_ID_PPE2TCL1 = 30, 114 115 HAL_SRNG_RING_ID_SW2TCL_CMD = 40, 116 HAL_SRNG_RING_ID_SW2TCL1_CMD, 117 HAL_SRNG_RING_ID_TCL_STATUS, 118 119 HAL_SRNG_RING_ID_CE0_SRC = 64, 120 HAL_SRNG_RING_ID_CE1_SRC, 121 HAL_SRNG_RING_ID_CE2_SRC, 122 HAL_SRNG_RING_ID_CE3_SRC, 123 HAL_SRNG_RING_ID_CE4_SRC, 124 HAL_SRNG_RING_ID_CE5_SRC, 125 HAL_SRNG_RING_ID_CE6_SRC, 126 HAL_SRNG_RING_ID_CE7_SRC, 127 HAL_SRNG_RING_ID_CE8_SRC, 128 HAL_SRNG_RING_ID_CE9_SRC, 129 HAL_SRNG_RING_ID_CE10_SRC, 130 HAL_SRNG_RING_ID_CE11_SRC, 131 HAL_SRNG_RING_ID_CE12_SRC, 132 HAL_SRNG_RING_ID_CE13_SRC, 133 HAL_SRNG_RING_ID_CE14_SRC, 134 HAL_SRNG_RING_ID_CE15_SRC, 135 136 HAL_SRNG_RING_ID_CE0_DST = 81, 137 HAL_SRNG_RING_ID_CE1_DST, 138 HAL_SRNG_RING_ID_CE2_DST, 139 HAL_SRNG_RING_ID_CE3_DST, 140 HAL_SRNG_RING_ID_CE4_DST, 141 HAL_SRNG_RING_ID_CE5_DST, 142 HAL_SRNG_RING_ID_CE6_DST, 143 HAL_SRNG_RING_ID_CE7_DST, 144 HAL_SRNG_RING_ID_CE8_DST, 145 HAL_SRNG_RING_ID_CE9_DST, 146 HAL_SRNG_RING_ID_CE10_DST, 147 HAL_SRNG_RING_ID_CE11_DST, 148 HAL_SRNG_RING_ID_CE12_DST, 149 HAL_SRNG_RING_ID_CE13_DST, 150 HAL_SRNG_RING_ID_CE14_DST, 151 HAL_SRNG_RING_ID_CE15_DST, 152 153 HAL_SRNG_RING_ID_CE0_DST_STATUS = 100, 154 HAL_SRNG_RING_ID_CE1_DST_STATUS, 155 HAL_SRNG_RING_ID_CE2_DST_STATUS, 156 HAL_SRNG_RING_ID_CE3_DST_STATUS, 157 HAL_SRNG_RING_ID_CE4_DST_STATUS, 158 HAL_SRNG_RING_ID_CE5_DST_STATUS, 159 HAL_SRNG_RING_ID_CE6_DST_STATUS, 160 HAL_SRNG_RING_ID_CE7_DST_STATUS, 161 HAL_SRNG_RING_ID_CE8_DST_STATUS, 162 HAL_SRNG_RING_ID_CE9_DST_STATUS, 163 HAL_SRNG_RING_ID_CE10_DST_STATUS, 164 HAL_SRNG_RING_ID_CE11_DST_STATUS, 165 HAL_SRNG_RING_ID_CE12_DST_STATUS, 166 HAL_SRNG_RING_ID_CE13_DST_STATUS, 167 HAL_SRNG_RING_ID_CE14_DST_STATUS, 168 HAL_SRNG_RING_ID_CE15_DST_STATUS, 169 170 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120, 171 HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 172 HAL_SRNG_RING_ID_WBM_SW1_RELEASE, 173 HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123, 174 175 HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128, 176 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 177 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 178 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */ 179 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 180 HAL_SRNG_RING_ID_WBM2SW5_RELEASE, 181 HAL_SRNG_RING_ID_WBM2SW6_RELEASE, 182 HAL_SRNG_RING_ID_WBM2SW7_RELEASE, 183 184 HAL_SRNG_RING_ID_UMAC_ID_END = 159, 185 186 /* Common DMAC rings shared by all LMACs */ 187 HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160, 188 HAL_SRNG_SW2RXDMA_BUF0 = HAL_SRNG_RING_ID_DMAC_CMN_ID_START, 189 HAL_SRNG_SW2RXDMA_BUF1 = 161, 190 HAL_SRNG_SW2RXDMA_BUF2 = 162, 191 192 HAL_SRNG_SW2RXMON_BUF0 = 168, 193 194 HAL_SRNG_SW2TXMON_BUF0 = 176, 195 196 HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183, 197 HAL_SRNG_RING_ID_PMAC1_ID_START = 184, 198 199 HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 = HAL_SRNG_RING_ID_PMAC1_ID_START, 200 201 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 202 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 203 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 204 HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 205 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 206 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 207 HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, 208 HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, 209 210 HAL_SRNG_RING_ID_PMAC1_ID_END, 211 }; 212 213 /* SRNG registers are split into two groups R0 and R2 */ 214 #define HAL_SRNG_REG_GRP_R0 0 215 #define HAL_SRNG_REG_GRP_R2 1 216 #define HAL_SRNG_NUM_REG_GRP 2 217 218 /* TODO: number of PMACs */ 219 #define HAL_SRNG_NUM_PMACS 3 220 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \ 221 HAL_SRNG_RING_ID_DMAC_CMN_ID_START) 222 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \ 223 HAL_SRNG_RING_ID_PMAC1_ID_START) 224 #define HAL_SRNG_NUM_PMAC_RINGS (HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC) 225 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_DMAC_CMN_ID_END + \ 226 HAL_SRNG_NUM_PMAC_RINGS) 227 228 enum hal_rx_su_mu_coding { 229 HAL_RX_SU_MU_CODING_BCC, 230 HAL_RX_SU_MU_CODING_LDPC, 231 HAL_RX_SU_MU_CODING_MAX, 232 }; 233 234 enum hal_rx_gi { 235 HAL_RX_GI_0_8_US, 236 HAL_RX_GI_0_4_US, 237 HAL_RX_GI_1_6_US, 238 HAL_RX_GI_3_2_US, 239 HAL_RX_GI_MAX, 240 }; 241 242 enum hal_rx_bw { 243 HAL_RX_BW_20MHZ, 244 HAL_RX_BW_40MHZ, 245 HAL_RX_BW_80MHZ, 246 HAL_RX_BW_160MHZ, 247 HAL_RX_BW_320MHZ, 248 HAL_RX_BW_MAX, 249 }; 250 251 enum hal_rx_preamble { 252 HAL_RX_PREAMBLE_11A, 253 HAL_RX_PREAMBLE_11B, 254 HAL_RX_PREAMBLE_11N, 255 HAL_RX_PREAMBLE_11AC, 256 HAL_RX_PREAMBLE_11AX, 257 HAL_RX_PREAMBLE_11BA, 258 HAL_RX_PREAMBLE_11BE, 259 HAL_RX_PREAMBLE_MAX, 260 }; 261 262 enum hal_rx_reception_type { 263 HAL_RX_RECEPTION_TYPE_SU, 264 HAL_RX_RECEPTION_TYPE_MU_MIMO, 265 HAL_RX_RECEPTION_TYPE_MU_OFDMA, 266 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO, 267 HAL_RX_RECEPTION_TYPE_MAX, 268 }; 269 270 enum hal_rx_legacy_rate { 271 HAL_RX_LEGACY_RATE_1_MBPS, 272 HAL_RX_LEGACY_RATE_2_MBPS, 273 HAL_RX_LEGACY_RATE_5_5_MBPS, 274 HAL_RX_LEGACY_RATE_6_MBPS, 275 HAL_RX_LEGACY_RATE_9_MBPS, 276 HAL_RX_LEGACY_RATE_11_MBPS, 277 HAL_RX_LEGACY_RATE_12_MBPS, 278 HAL_RX_LEGACY_RATE_18_MBPS, 279 HAL_RX_LEGACY_RATE_24_MBPS, 280 HAL_RX_LEGACY_RATE_36_MBPS, 281 HAL_RX_LEGACY_RATE_48_MBPS, 282 HAL_RX_LEGACY_RATE_54_MBPS, 283 HAL_RX_LEGACY_RATE_INVALID, 284 }; 285 286 enum hal_ring_type { 287 HAL_REO_DST, 288 HAL_REO_EXCEPTION, 289 HAL_REO_REINJECT, 290 HAL_REO_CMD, 291 HAL_REO_STATUS, 292 HAL_TCL_DATA, 293 HAL_TCL_CMD, 294 HAL_TCL_STATUS, 295 HAL_CE_SRC, 296 HAL_CE_DST, 297 HAL_CE_DST_STATUS, 298 HAL_WBM_IDLE_LINK, 299 HAL_SW2WBM_RELEASE, 300 HAL_WBM2SW_RELEASE, 301 HAL_RXDMA_BUF, 302 HAL_RXDMA_DST, 303 HAL_RXDMA_MONITOR_BUF, 304 HAL_RXDMA_MONITOR_STATUS, 305 HAL_RXDMA_MONITOR_DST, 306 HAL_RXDMA_MONITOR_DESC, 307 HAL_RXDMA_DIR_BUF, 308 HAL_PPE2TCL, 309 HAL_PPE_RELEASE, 310 HAL_TX_MONITOR_BUF, 311 HAL_TX_MONITOR_DST, 312 HAL_MAX_RING_TYPES, 313 }; 314 315 /** 316 * enum hal_reo_cmd_type: Enum for REO command type 317 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 318 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 319 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 320 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 321 * earlier with a 'REO_FLUSH_CACHE' command 322 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 323 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 324 */ 325 enum hal_reo_cmd_type { 326 HAL_REO_CMD_GET_QUEUE_STATS = 0, 327 HAL_REO_CMD_FLUSH_QUEUE = 1, 328 HAL_REO_CMD_FLUSH_CACHE = 2, 329 HAL_REO_CMD_UNBLOCK_CACHE = 3, 330 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 331 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 332 }; 333 334 /** 335 * enum hal_reo_cmd_status: Enum for execution status of REO command 336 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 337 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 338 * or cache was blocked 339 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 340 * invalid queue desc 341 * @HAL_REO_CMD_RESOURCE_BLOCKED: Command could not be executed because 342 * one or more descriptors were blocked 343 * @HAL_REO_CMD_DRAIN: 344 */ 345 enum hal_reo_cmd_status { 346 HAL_REO_CMD_SUCCESS = 0, 347 HAL_REO_CMD_BLOCKED = 1, 348 HAL_REO_CMD_FAILED = 2, 349 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 350 HAL_REO_CMD_DRAIN = 0xff, 351 }; 352 353 enum hal_tcl_encap_type { 354 HAL_TCL_ENCAP_TYPE_RAW, 355 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 356 HAL_TCL_ENCAP_TYPE_ETHERNET, 357 HAL_TCL_ENCAP_TYPE_802_3 = 3, 358 HAL_TCL_ENCAP_TYPE_MAX 359 }; 360 361 enum hal_tcl_desc_type { 362 HAL_TCL_DESC_TYPE_BUFFER, 363 HAL_TCL_DESC_TYPE_EXT_DESC, 364 HAL_TCL_DESC_TYPE_MAX, 365 }; 366 367 enum hal_reo_dest_ring_buffer_type { 368 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 369 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 370 }; 371 372 enum hal_reo_dest_ring_push_reason { 373 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 374 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 375 }; 376 377 enum hal_reo_entr_rxdma_push_reason { 378 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ERR_DETECTED, 379 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ROUTING_INSTRUCTION, 380 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_RX_FLUSH, 381 }; 382 383 enum hal_reo_dest_ring_error_code { 384 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 385 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 386 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 387 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 388 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 389 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 390 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 391 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 392 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 393 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 394 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 395 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 396 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 397 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 398 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 399 HAL_REO_DEST_RING_ERROR_CODE_MAX, 400 }; 401 402 enum hal_reo_entr_rxdma_ecode { 403 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 404 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 405 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 406 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 407 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 408 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 409 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 410 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 411 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 412 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 413 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 414 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 415 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 416 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 417 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_FRAG_ERR, 418 HAL_REO_ENTR_RING_RXDMA_ECODE_MULTICAST_ECHO_ERR, 419 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_MISMATCH_ERR, 420 HAL_REO_ENTR_RING_RXDMA_ECODE_UNAUTH_WDS_ERR, 421 HAL_REO_ENTR_RING_RXDMA_ECODE_GRPCAST_AMSDU_WDS_ERR, 422 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 423 }; 424 425 enum hal_wbm_htt_tx_comp_status { 426 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 427 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 428 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 429 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 430 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 431 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 432 HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH, 433 HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX, 434 }; 435 436 enum hal_encrypt_type { 437 HAL_ENCRYPT_TYPE_WEP_40, 438 HAL_ENCRYPT_TYPE_WEP_104, 439 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 440 HAL_ENCRYPT_TYPE_WEP_128, 441 HAL_ENCRYPT_TYPE_TKIP_MIC, 442 HAL_ENCRYPT_TYPE_WAPI, 443 HAL_ENCRYPT_TYPE_CCMP_128, 444 HAL_ENCRYPT_TYPE_OPEN, 445 HAL_ENCRYPT_TYPE_CCMP_256, 446 HAL_ENCRYPT_TYPE_GCMP_128, 447 HAL_ENCRYPT_TYPE_AES_GCMP_256, 448 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 449 }; 450 451 enum hal_tx_rate_stats_bw { 452 HAL_TX_RATE_STATS_BW_20, 453 HAL_TX_RATE_STATS_BW_40, 454 HAL_TX_RATE_STATS_BW_80, 455 HAL_TX_RATE_STATS_BW_160, 456 }; 457 458 enum hal_tx_rate_stats_pkt_type { 459 HAL_TX_RATE_STATS_PKT_TYPE_11A, 460 HAL_TX_RATE_STATS_PKT_TYPE_11B, 461 HAL_TX_RATE_STATS_PKT_TYPE_11N, 462 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 463 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 464 HAL_TX_RATE_STATS_PKT_TYPE_11BA, 465 HAL_TX_RATE_STATS_PKT_TYPE_11BE, 466 }; 467 468 enum hal_tx_rate_stats_sgi { 469 HAL_TX_RATE_STATS_SGI_08US, 470 HAL_TX_RATE_STATS_SGI_04US, 471 HAL_TX_RATE_STATS_SGI_16US, 472 HAL_TX_RATE_STATS_SGI_32US, 473 }; 474 475 struct hal_wbm_idle_scatter_list { 476 dma_addr_t paddr; 477 struct hal_wbm_link_desc *vaddr; 478 }; 479 480 struct hal_srng_params { 481 dma_addr_t ring_base_paddr; 482 u32 *ring_base_vaddr; 483 int num_entries; 484 u32 intr_batch_cntr_thres_entries; 485 u32 intr_timer_thres_us; 486 u32 flags; 487 u32 max_buffer_len; 488 u32 low_threshold; 489 u32 high_threshold; 490 dma_addr_t msi_addr; 491 dma_addr_t msi2_addr; 492 u32 msi_data; 493 u32 msi2_data; 494 495 /* Add more params as needed */ 496 }; 497 498 enum hal_srng_dir { 499 HAL_SRNG_DIR_SRC, 500 HAL_SRNG_DIR_DST 501 }; 502 503 enum rx_msdu_start_pkt_type { 504 RX_MSDU_START_PKT_TYPE_11A, 505 RX_MSDU_START_PKT_TYPE_11B, 506 RX_MSDU_START_PKT_TYPE_11N, 507 RX_MSDU_START_PKT_TYPE_11AC, 508 RX_MSDU_START_PKT_TYPE_11AX, 509 RX_MSDU_START_PKT_TYPE_11BA, 510 RX_MSDU_START_PKT_TYPE_11BE, 511 }; 512 513 enum rx_msdu_start_sgi { 514 RX_MSDU_START_SGI_0_8_US, 515 RX_MSDU_START_SGI_0_4_US, 516 RX_MSDU_START_SGI_1_6_US, 517 RX_MSDU_START_SGI_3_2_US, 518 }; 519 520 enum rx_msdu_start_recv_bw { 521 RX_MSDU_START_RECV_BW_20MHZ, 522 RX_MSDU_START_RECV_BW_40MHZ, 523 RX_MSDU_START_RECV_BW_80MHZ, 524 RX_MSDU_START_RECV_BW_160MHZ, 525 }; 526 527 enum rx_msdu_start_reception_type { 528 RX_MSDU_START_RECEPTION_TYPE_SU, 529 RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO, 530 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA, 531 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 532 RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO, 533 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA, 534 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, 535 }; 536 537 enum rx_desc_decap_type { 538 RX_DESC_DECAP_TYPE_RAW, 539 RX_DESC_DECAP_TYPE_NATIVE_WIFI, 540 RX_DESC_DECAP_TYPE_ETHERNET2_DIX, 541 RX_DESC_DECAP_TYPE_8023, 542 }; 543 544 struct hal_rx_user_status { 545 u32 mcs:4, 546 nss:3, 547 ofdma_info_valid:1, 548 ul_ofdma_ru_start_index:7, 549 ul_ofdma_ru_width:7, 550 ul_ofdma_ru_size:8; 551 u32 ul_ofdma_user_v0_word0; 552 u32 ul_ofdma_user_v0_word1; 553 u32 ast_index; 554 u32 tid; 555 u16 tcp_msdu_count; 556 u16 tcp_ack_msdu_count; 557 u16 udp_msdu_count; 558 u16 other_msdu_count; 559 u16 frame_control; 560 u8 frame_control_info_valid; 561 u8 data_sequence_control_info_valid; 562 u16 first_data_seq_ctrl; 563 u32 preamble_type; 564 u16 ht_flags; 565 u16 vht_flags; 566 u16 he_flags; 567 u8 rs_flags; 568 u8 ldpc; 569 u32 mpdu_cnt_fcs_ok; 570 u32 mpdu_cnt_fcs_err; 571 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 572 u32 mpdu_ok_byte_count; 573 u32 mpdu_err_byte_count; 574 bool ampdu_present; 575 u16 ampdu_id; 576 }; 577 578 struct hal_rx_u_sig_info { 579 bool ul_dl; 580 u8 bw; 581 u8 ppdu_type_comp_mode; 582 u8 eht_sig_mcs; 583 u8 num_eht_sig_sym; 584 struct ieee80211_radiotap_eht_usig usig; 585 }; 586 587 struct hal_rx_tlv_aggr_info { 588 bool in_progress; 589 u16 cur_len; 590 u16 tlv_tag; 591 u8 buf[HAL_RX_MON_MAX_AGGR_SIZE]; 592 }; 593 594 struct hal_rx_radiotap_eht { 595 __le32 known; 596 __le32 data[9]; 597 }; 598 599 struct hal_rx_eht_info { 600 u8 num_user_info; 601 struct hal_rx_radiotap_eht eht; 602 u32 user_info[EHT_MAX_USER_INFO]; 603 }; 604 605 struct hal_rx_msdu_desc_info { 606 u32 msdu_flags; 607 u16 msdu_len; /* 14 bits for length */ 608 }; 609 610 /* hal_mon_buf_ring 611 * Producer : SW 612 * Consumer : Monitor 613 * 614 * paddr_lo 615 * Lower 32-bit physical address of the buffer pointer from the source ring. 616 * paddr_hi 617 * bit range 7-0 : upper 8 bit of the physical address. 618 * bit range 31-8 : reserved. 619 * cookie 620 * Consumer: RxMon/TxMon 64 bit cookie of the buffers. 621 */ 622 struct hal_mon_buf_ring { 623 __le32 paddr_lo; 624 __le32 paddr_hi; 625 __le64 cookie; 626 }; 627 628 struct hal_rx_mon_ppdu_info { 629 u32 ppdu_id; 630 u32 last_ppdu_id; 631 u64 ppdu_ts; 632 u32 num_mpdu_fcs_ok; 633 u32 num_mpdu_fcs_err; 634 u32 preamble_type; 635 u32 mpdu_len; 636 u16 chan_num; 637 u16 freq; 638 u16 tcp_msdu_count; 639 u16 tcp_ack_msdu_count; 640 u16 udp_msdu_count; 641 u16 other_msdu_count; 642 u16 peer_id; 643 u8 rate; 644 u8 mcs; 645 u8 nss; 646 u8 bw; 647 u8 vht_flag_values1; 648 u8 vht_flag_values2; 649 u8 vht_flag_values3[4]; 650 u8 vht_flag_values4; 651 u8 vht_flag_values5; 652 u16 vht_flag_values6; 653 u8 is_stbc; 654 u8 gi; 655 u8 sgi; 656 u8 ldpc; 657 u8 beamformed; 658 u8 rssi_comb; 659 u16 tid; 660 u8 fc_valid; 661 u16 ht_flags; 662 u16 vht_flags; 663 u16 he_flags; 664 u16 he_mu_flags; 665 u8 dcm; 666 u8 ru_alloc; 667 u8 reception_type; 668 u64 tsft; 669 u64 rx_duration; 670 u16 frame_control; 671 u32 ast_index; 672 u8 rs_fcs_err; 673 u8 rs_flags; 674 u8 cck_flag; 675 u8 ofdm_flag; 676 u8 ulofdma_flag; 677 u8 frame_control_info_valid; 678 u16 he_per_user_1; 679 u16 he_per_user_2; 680 u8 he_per_user_position; 681 u8 he_per_user_known; 682 u16 he_flags1; 683 u16 he_flags2; 684 u8 he_RU[4]; 685 u16 he_data1; 686 u16 he_data2; 687 u16 he_data3; 688 u16 he_data4; 689 u16 he_data5; 690 u16 he_data6; 691 u32 ppdu_len; 692 u32 prev_ppdu_id; 693 u32 device_id; 694 u16 first_data_seq_ctrl; 695 u8 monitor_direct_used; 696 u8 data_sequence_control_info_valid; 697 u8 ltf_size; 698 u8 rxpcu_filter_pass; 699 s8 rssi_chain[8][8]; 700 u32 num_users; 701 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 702 u8 addr1[ETH_ALEN]; 703 u8 addr2[ETH_ALEN]; 704 u8 addr3[ETH_ALEN]; 705 u8 addr4[ETH_ALEN]; 706 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS]; 707 u8 userid; 708 bool first_msdu_in_mpdu; 709 bool is_ampdu; 710 u8 medium_prot_type; 711 bool ppdu_continuation; 712 bool eht_usig; 713 struct hal_rx_u_sig_info u_sig_info; 714 bool is_eht; 715 struct hal_rx_eht_info eht_info; 716 struct hal_rx_tlv_aggr_info tlv_aggr; 717 }; 718 719 struct hal_rx_desc_data { 720 struct ieee80211_rx_status *rx_status; 721 u32 phy_meta_data; 722 u32 err_bitmap; 723 u32 enctype; 724 u32 msdu_done:1, 725 is_decrypted:1, 726 ip_csum_fail:1, 727 l4_csum_fail:1, 728 is_first_msdu:1, 729 is_last_msdu:1, 730 mesh_ctrl_present:1, 731 addr2_present:1, 732 is_mcbc:1, 733 seq_ctl_valid:1, 734 fc_valid:1; 735 u16 msdu_len; 736 u16 peer_id; 737 u16 seq_no; 738 u8 *addr2; 739 u8 pkt_type; 740 u8 l3_pad_bytes; 741 u8 decap_type; 742 u8 bw; 743 u8 rate_mcs; 744 u8 nss; 745 u8 sgi; 746 u8 tid; 747 }; 748 749 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 750 751 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 752 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8) 753 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12) 754 755 struct ath12k_buffer_addr { 756 __le32 info0; 757 __le32 info1; 758 } __packed; 759 760 /* ath12k_buffer_addr 761 * 762 * buffer_addr_31_0 763 * Address (lower 32 bits) of the MSDU buffer or MSDU_EXTENSION 764 * descriptor or Link descriptor 765 * 766 * buffer_addr_39_32 767 * Address (upper 8 bits) of the MSDU buffer or MSDU_EXTENSION 768 * descriptor or Link descriptor 769 * 770 * return_buffer_manager (RBM) 771 * Consumer: WBM 772 * Producer: SW/FW 773 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 774 * descriptor or link descriptor that is being pointed to shall be 775 * returned after the frame has been processed. It is used by WBM 776 * for routing purposes. 777 * 778 * Values are defined in enum %HAL_RX_BUF_RBM_ 779 * 780 * sw_buffer_cookie 781 * Cookie field exclusively used by SW. HW ignores the contents, 782 * accept that it passes the programmed value on to other 783 * descriptors together with the physical address. 784 * 785 * Field can be used by SW to for example associate the buffers 786 * physical address with the virtual address. 787 * 788 * NOTE1: 789 * The three most significant bits can have a special meaning 790 * in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 791 * and field transmit_bw_restriction is set 792 * 793 * In case of NON punctured transmission: 794 * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 795 * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 796 * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 797 * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 798 * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 799 * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 800 * Sw_buffer_cookie[19:18] = 2'b11: reserved 801 * 802 * In case of punctured transmission: 803 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 804 * Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 805 * Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 806 * Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 807 * Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 808 * Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 809 * Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 810 * Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 811 * Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 812 * Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 813 * Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 814 * Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 815 * Sw_buffer_cookie[19:18] = 2'b11: reserved 816 * 817 * Note: a punctured transmission is indicated by the presence 818 * of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 819 * 820 * Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS control 821 * field 822 * 823 * Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 824 * indicates MPDUs with a QoS control field. 825 * 826 */ 827 828 struct hal_ce_srng_dest_desc; 829 struct hal_ce_srng_dst_status_desc; 830 struct hal_ce_srng_src_desc; 831 832 struct hal_wbm_link_desc { 833 struct ath12k_buffer_addr buf_addr_info; 834 } __packed; 835 836 /* srng flags */ 837 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 838 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 839 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 840 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 841 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 842 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000 843 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 844 845 /* Common SRNG ring structure for source and destination rings */ 846 struct hal_srng { 847 /* Unique SRNG ring ID */ 848 u8 ring_id; 849 850 /* Ring initialization done */ 851 u8 initialized; 852 853 /* Interrupt/MSI value assigned to this ring */ 854 int irq; 855 856 /* Physical base address of the ring */ 857 dma_addr_t ring_base_paddr; 858 859 /* Virtual base address of the ring */ 860 u32 *ring_base_vaddr; 861 862 /* Number of entries in ring */ 863 u32 num_entries; 864 865 /* Ring size */ 866 u32 ring_size; 867 868 /* Ring size mask */ 869 u32 ring_size_mask; 870 871 /* Size of ring entry */ 872 u32 entry_size; 873 874 /* Interrupt timer threshold - in micro seconds */ 875 u32 intr_timer_thres_us; 876 877 /* Interrupt batch counter threshold - in number of ring entries */ 878 u32 intr_batch_cntr_thres_entries; 879 880 /* MSI Address */ 881 dma_addr_t msi_addr; 882 883 /* MSI data */ 884 u32 msi_data; 885 886 /* MSI2 Address */ 887 dma_addr_t msi2_addr; 888 889 /* MSI2 data */ 890 u32 msi2_data; 891 892 /* Misc flags */ 893 u32 flags; 894 895 /* Lock for serializing ring index updates */ 896 spinlock_t lock; 897 898 struct lock_class_key lock_key; 899 900 /* Start offset of SRNG register groups for this ring 901 * TBD: See if this is required - register address can be derived 902 * from ring ID 903 */ 904 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 905 906 u64 timestamp; 907 908 /* Source or Destination ring */ 909 enum hal_srng_dir ring_dir; 910 911 union { 912 struct { 913 /* SW tail pointer */ 914 u32 tp; 915 916 /* Shadow head pointer location to be updated by HW */ 917 volatile u32 *hp_addr; 918 919 /* Cached head pointer */ 920 u32 cached_hp; 921 922 /* Tail pointer location to be updated by SW - This 923 * will be a register address and need not be 924 * accessed through SW structure 925 */ 926 u32 *tp_addr; 927 928 /* Current SW loop cnt */ 929 u32 loop_cnt; 930 931 /* max transfer size */ 932 u16 max_buffer_length; 933 934 /* head pointer at access end */ 935 u32 last_hp; 936 } dst_ring; 937 938 struct { 939 /* SW head pointer */ 940 u32 hp; 941 942 /* SW reap head pointer */ 943 u32 reap_hp; 944 945 /* Shadow tail pointer location to be updated by HW */ 946 u32 *tp_addr; 947 948 /* Cached tail pointer */ 949 u32 cached_tp; 950 951 /* Head pointer location to be updated by SW - This 952 * will be a register address and need not be accessed 953 * through SW structure 954 */ 955 u32 *hp_addr; 956 957 /* Low threshold - in number of ring entries */ 958 u32 low_threshold; 959 960 /* tail pointer at access end */ 961 u32 last_tp; 962 } src_ring; 963 } u; 964 }; 965 966 /* hal_wbm_link_desc 967 * 968 * Producer: WBM 969 * Consumer: WBM 970 * 971 * buf_addr_info 972 * Details of the physical address of a buffer or MSDU 973 * link descriptor. 974 */ 975 976 enum hal_wbm_rel_src_module { 977 HAL_WBM_REL_SRC_MODULE_TQM, 978 HAL_WBM_REL_SRC_MODULE_RXDMA, 979 HAL_WBM_REL_SRC_MODULE_REO, 980 HAL_WBM_REL_SRC_MODULE_FW, 981 HAL_WBM_REL_SRC_MODULE_SW, 982 HAL_WBM_REL_SRC_MODULE_MAX, 983 }; 984 985 /* hal_wbm_rel_desc_type 986 * 987 * msdu_buffer 988 * The address points to an MSDU buffer 989 * 990 * msdu_link_descriptor 991 * The address points to an Tx MSDU link descriptor 992 * 993 * mpdu_link_descriptor 994 * The address points to an MPDU link descriptor 995 * 996 * msdu_ext_descriptor 997 * The address points to an MSDU extension descriptor 998 * 999 * queue_ext_descriptor 1000 * The address points to an TQM queue extension descriptor. WBM should 1001 * treat this is the same way as a link descriptor. 1002 */ 1003 enum hal_wbm_rel_desc_type { 1004 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1005 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1006 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1007 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1008 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1009 }; 1010 1011 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 1012 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 1013 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 1014 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 1015 1016 /* Interrupt mitigation - timer threshold in us */ 1017 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 1018 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 1019 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 1020 1021 enum hal_srng_mac_type { 1022 ATH12K_HAL_SRNG_UMAC, 1023 ATH12K_HAL_SRNG_DMAC, 1024 ATH12K_HAL_SRNG_PMAC 1025 }; 1026 1027 /* HW SRNG configuration table */ 1028 struct hal_srng_config { 1029 int start_ring_id; 1030 u16 max_rings; 1031 u16 entry_size; 1032 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 1033 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 1034 enum hal_srng_mac_type mac_type; 1035 enum hal_srng_dir ring_dir; 1036 u32 max_size; 1037 }; 1038 1039 /** 1040 * enum hal_rx_buf_return_buf_manager - manager for returned rx buffers 1041 * 1042 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 1043 * @HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST: Descriptor returned to WBM idle 1044 * descriptor list, where the device 0 WBM is chosen in case of a multi-device config 1045 * @HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST: Descriptor returned to WBM idle 1046 * descriptor list, where the device 1 WBM is chosen in case of a multi-device config 1047 * @HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST: Descriptor returned to WBM idle 1048 * descriptor list, where the device 2 WBM is chosen in case of a multi-device config 1049 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 1050 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host 1051 * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host 1052 * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host 1053 * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host 1054 * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host 1055 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host 1056 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host 1057 */ 1058 1059 enum hal_rx_buf_return_buf_manager { 1060 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 1061 HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST, 1062 HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST, 1063 HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST, 1064 HAL_RX_BUF_RBM_FW_BM, 1065 HAL_RX_BUF_RBM_SW0_BM, 1066 HAL_RX_BUF_RBM_SW1_BM, 1067 HAL_RX_BUF_RBM_SW2_BM, 1068 HAL_RX_BUF_RBM_SW3_BM, 1069 HAL_RX_BUF_RBM_SW4_BM, 1070 HAL_RX_BUF_RBM_SW5_BM, 1071 HAL_RX_BUF_RBM_SW6_BM, 1072 }; 1073 1074 struct ath12k_hal_reo_cmd { 1075 u32 addr_lo; 1076 u32 flag; 1077 u32 upd0; 1078 u32 upd1; 1079 u32 upd2; 1080 u32 pn[4]; 1081 u16 rx_queue_num; 1082 u16 min_rel; 1083 u16 min_fwd; 1084 u8 addr_hi; 1085 u8 ac_list; 1086 u8 blocking_idx; 1087 u16 ba_window_size; 1088 u8 pn_size; 1089 }; 1090 1091 enum hal_pn_type { 1092 HAL_PN_TYPE_NONE, 1093 HAL_PN_TYPE_WPA, 1094 HAL_PN_TYPE_WAPI_EVEN, 1095 HAL_PN_TYPE_WAPI_UNEVEN, 1096 }; 1097 1098 enum hal_ce_desc { 1099 HAL_CE_DESC_SRC, 1100 HAL_CE_DESC_DST, 1101 HAL_CE_DESC_DST_STATUS, 1102 }; 1103 1104 #define HAL_HASH_ROUTING_RING_TCL 0 1105 #define HAL_HASH_ROUTING_RING_SW1 1 1106 #define HAL_HASH_ROUTING_RING_SW2 2 1107 #define HAL_HASH_ROUTING_RING_SW3 3 1108 #define HAL_HASH_ROUTING_RING_SW4 4 1109 #define HAL_HASH_ROUTING_RING_REL 5 1110 #define HAL_HASH_ROUTING_RING_FW 6 1111 1112 struct hal_reo_status_header { 1113 u16 cmd_num; 1114 enum hal_reo_cmd_status cmd_status; 1115 u16 cmd_exe_time; 1116 u32 timestamp; 1117 }; 1118 1119 struct ath12k_hw_hal_params { 1120 enum hal_rx_buf_return_buf_manager rx_buf_rbm; 1121 u32 wbm2sw_cc_enable; 1122 }; 1123 1124 #define ATH12K_HW_REG_UNDEFINED 0xdeadbeaf 1125 1126 struct ath12k_hw_regs { 1127 u32 tcl1_ring_id; 1128 u32 tcl1_ring_misc; 1129 u32 tcl1_ring_tp_addr_lsb; 1130 u32 tcl1_ring_tp_addr_msb; 1131 u32 tcl1_ring_consumer_int_setup_ix0; 1132 u32 tcl1_ring_consumer_int_setup_ix1; 1133 u32 tcl1_ring_msi1_base_lsb; 1134 u32 tcl1_ring_msi1_base_msb; 1135 u32 tcl1_ring_msi1_data; 1136 u32 tcl_ring_base_lsb; 1137 u32 tcl1_ring_base_lsb; 1138 u32 tcl1_ring_base_msb; 1139 u32 tcl2_ring_base_lsb; 1140 1141 u32 tcl_status_ring_base_lsb; 1142 1143 u32 reo1_qdesc_addr; 1144 u32 reo1_qdesc_max_peerid; 1145 1146 u32 wbm_idle_ring_base_lsb; 1147 u32 wbm_idle_ring_misc_addr; 1148 u32 wbm_r0_idle_list_cntl_addr; 1149 u32 wbm_r0_idle_list_size_addr; 1150 u32 wbm_scattered_ring_base_lsb; 1151 u32 wbm_scattered_ring_base_msb; 1152 u32 wbm_scattered_desc_head_info_ix0; 1153 u32 wbm_scattered_desc_head_info_ix1; 1154 u32 wbm_scattered_desc_tail_info_ix0; 1155 u32 wbm_scattered_desc_tail_info_ix1; 1156 u32 wbm_scattered_desc_ptr_hp_addr; 1157 1158 u32 wbm_sw_release_ring_base_lsb; 1159 u32 wbm_sw1_release_ring_base_lsb; 1160 u32 wbm0_release_ring_base_lsb; 1161 u32 wbm1_release_ring_base_lsb; 1162 1163 u32 pcie_qserdes_sysclk_en_sel; 1164 u32 pcie_pcs_osc_dtct_config_base; 1165 1166 u32 umac_ce0_src_reg_base; 1167 u32 umac_ce0_dest_reg_base; 1168 u32 umac_ce1_src_reg_base; 1169 u32 umac_ce1_dest_reg_base; 1170 1171 u32 ppe_rel_ring_base; 1172 1173 u32 reo2_ring_base; 1174 u32 reo1_misc_ctrl_addr; 1175 u32 reo1_sw_cookie_cfg0; 1176 u32 reo1_sw_cookie_cfg1; 1177 u32 reo1_qdesc_lut_base0; 1178 u32 reo1_qdesc_lut_base1; 1179 u32 reo1_ring_base_lsb; 1180 u32 reo1_ring_base_msb; 1181 u32 reo1_ring_id; 1182 u32 reo1_ring_misc; 1183 u32 reo1_ring_hp_addr_lsb; 1184 u32 reo1_ring_hp_addr_msb; 1185 u32 reo1_ring_producer_int_setup; 1186 u32 reo1_ring_msi1_base_lsb; 1187 u32 reo1_ring_msi1_base_msb; 1188 u32 reo1_ring_msi1_data; 1189 u32 reo1_aging_thres_ix0; 1190 u32 reo1_aging_thres_ix1; 1191 u32 reo1_aging_thres_ix2; 1192 u32 reo1_aging_thres_ix3; 1193 1194 u32 reo2_sw0_ring_base; 1195 1196 u32 sw2reo_ring_base; 1197 u32 sw2reo1_ring_base; 1198 1199 u32 reo_cmd_ring_base; 1200 1201 u32 reo_status_ring_base; 1202 1203 u32 gcc_gcc_pcie_hot_rst; 1204 1205 u32 qrtr_node_id; 1206 }; 1207 1208 /* HAL context to be used to access SRNG APIs (currently used by data path 1209 * and transport (CE) modules) 1210 */ 1211 struct ath12k_hal { 1212 /* HAL internal state for all SRNG rings. 1213 */ 1214 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 1215 1216 /* SRNG configuration table */ 1217 struct hal_srng_config *srng_config; 1218 1219 /* Remote pointer memory for HW/FW updates */ 1220 struct { 1221 u32 *vaddr; 1222 dma_addr_t paddr; 1223 } rdp; 1224 1225 /* Shared memory for ring pointer updates from host to FW */ 1226 struct { 1227 u32 *vaddr; 1228 dma_addr_t paddr; 1229 } wrp; 1230 1231 struct device *dev; 1232 const struct hal_ops *ops; 1233 const struct ath12k_hw_regs *regs; 1234 const struct ath12k_hw_hal_params *hal_params; 1235 /* Available REO blocking resources bitmap */ 1236 u8 avail_blk_resource; 1237 1238 u8 current_blk_index; 1239 1240 /* shadow register configuration */ 1241 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS_MAX]; 1242 int num_shadow_reg_configured; 1243 1244 u32 hal_desc_sz; 1245 u32 hal_wbm_release_ring_tx_size; 1246 1247 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 1248 }; 1249 1250 /* Maps WBM ring number and Return Buffer Manager Id per TCL ring */ 1251 struct ath12k_hal_tcl_to_wbm_rbm_map { 1252 u8 wbm_ring_num; 1253 u8 rbm_id; 1254 }; 1255 1256 enum hal_wbm_rel_bm_act { 1257 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1258 HAL_WBM_REL_BM_ACT_REL_MSDU, 1259 }; 1260 1261 /* hal_wbm_rel_bm_act 1262 * 1263 * put_in_idle_list 1264 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1265 * MDPU link descriptor, BM does not need to check to release any 1266 * individual MSDU buffers. 1267 * 1268 * release_msdu_list 1269 * This BM action can only be used in combination with desc_type being 1270 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1271 * pointer in the MSDU link descriptor is the first of an MPDU that is 1272 * released. BM shall release all the MSDU buffers linked to this first 1273 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1274 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1275 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1276 * descriptor itself shall also be released. 1277 */ 1278 1279 #define RU_INVALID 0 1280 #define RU_26 1 1281 #define RU_52 2 1282 #define RU_106 4 1283 #define RU_242 9 1284 #define RU_484 18 1285 #define RU_996 37 1286 #define RU_2X996 74 1287 #define RU_3X996 111 1288 #define RU_4X996 148 1289 #define RU_52_26 (RU_52 + RU_26) 1290 #define RU_106_26 (RU_106 + RU_26) 1291 #define RU_484_242 (RU_484 + RU_242) 1292 #define RU_996_484 (RU_996 + RU_484) 1293 #define RU_996_484_242 (RU_996 + RU_484_242) 1294 #define RU_2X996_484 (RU_2X996 + RU_484) 1295 #define RU_3X996_484 (RU_3X996 + RU_484) 1296 1297 enum ath12k_eht_ru_size { 1298 ATH12K_EHT_RU_26, 1299 ATH12K_EHT_RU_52, 1300 ATH12K_EHT_RU_106, 1301 ATH12K_EHT_RU_242, 1302 ATH12K_EHT_RU_484, 1303 ATH12K_EHT_RU_996, 1304 ATH12K_EHT_RU_996x2, 1305 ATH12K_EHT_RU_996x4, 1306 ATH12K_EHT_RU_52_26, 1307 ATH12K_EHT_RU_106_26, 1308 ATH12K_EHT_RU_484_242, 1309 ATH12K_EHT_RU_996_484, 1310 ATH12K_EHT_RU_996_484_242, 1311 ATH12K_EHT_RU_996x2_484, 1312 ATH12K_EHT_RU_996x3, 1313 ATH12K_EHT_RU_996x3_484, 1314 1315 /* Keep last */ 1316 ATH12K_EHT_RU_INVALID, 1317 }; 1318 1319 #define HAL_RX_RU_ALLOC_TYPE_MAX ATH12K_EHT_RU_INVALID 1320 1321 static inline 1322 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) 1323 { 1324 enum nl80211_he_ru_alloc ret; 1325 1326 switch (ru_tones) { 1327 case RU_52: 1328 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; 1329 break; 1330 case RU_106: 1331 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; 1332 break; 1333 case RU_242: 1334 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; 1335 break; 1336 case RU_484: 1337 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; 1338 break; 1339 case RU_996: 1340 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; 1341 break; 1342 case RU_2X996: 1343 ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 1344 break; 1345 case RU_26: 1346 fallthrough; 1347 default: 1348 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; 1349 break; 1350 } 1351 return ret; 1352 } 1353 1354 struct ath12k_hw_version_map { 1355 const struct hal_ops *hal_ops; 1356 u32 hal_desc_sz; 1357 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 1358 const struct ath12k_hw_hal_params *hal_params; 1359 const struct ath12k_hw_regs *hw_regs; 1360 }; 1361 1362 struct hal_ops { 1363 int (*create_srng_config)(struct ath12k_hal *hal); 1364 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len); 1365 void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc, 1366 struct ieee80211_hdr *hdr); 1367 void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc, 1368 u8 *crypto_hdr, 1369 enum hal_encrypt_type enctype); 1370 void (*rx_desc_copy_end_tlv)(struct hal_rx_desc *fdesc, 1371 struct hal_rx_desc *ldesc); 1372 u8 (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc); 1373 void (*extract_rx_desc_data)(struct hal_rx_desc_data *rx_desc_data, 1374 struct hal_rx_desc *rx_desc, 1375 struct hal_rx_desc *ldesc); 1376 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 1377 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 1378 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 1379 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 1380 void (*ce_dst_setup)(struct ath12k_base *ab, 1381 struct hal_srng *srng, int ring_num); 1382 void (*set_umac_srng_ptr_addr)(struct ath12k_base *ab, 1383 struct hal_srng *srng); 1384 void (*srng_src_hw_init)(struct ath12k_base *ab, struct hal_srng *srng); 1385 void (*srng_dst_hw_init)(struct ath12k_base *ab, struct hal_srng *srng); 1386 int (*srng_update_shadow_config)(struct ath12k_base *ab, 1387 enum hal_ring_type ring_type, 1388 int ring_num); 1389 int (*srng_get_ring_id)(struct ath12k_hal *hal, enum hal_ring_type type, 1390 int ring_num, int mac_id); 1391 u32 (*ce_get_desc_size)(enum hal_ce_desc type); 1392 void (*ce_src_set_desc)(struct hal_ce_srng_src_desc *desc, 1393 dma_addr_t paddr, u32 len, u32 id, 1394 u8 byte_swap_data); 1395 void (*ce_dst_set_desc)(struct hal_ce_srng_dest_desc *desc, 1396 dma_addr_t paddr); 1397 u32 (*ce_dst_status_get_length)(struct hal_ce_srng_dst_status_desc *desc); 1398 void (*set_link_desc_addr)(struct hal_wbm_link_desc *desc, u32 cookie, 1399 dma_addr_t paddr, 1400 enum hal_rx_buf_return_buf_manager rbm); 1401 void (*tx_set_dscp_tid_map)(struct ath12k_base *ab, int id); 1402 void (*tx_configure_bank_register)(struct ath12k_base *ab, 1403 u32 bank_config, u8 bank_id); 1404 void (*reoq_lut_addr_read_enable)(struct ath12k_base *ab); 1405 void (*reoq_lut_set_max_peerid)(struct ath12k_base *ab); 1406 void (*write_ml_reoq_lut_addr)(struct ath12k_base *ab, 1407 dma_addr_t paddr); 1408 void (*write_reoq_lut_addr)(struct ath12k_base *ab, dma_addr_t paddr); 1409 void (*setup_link_idle_list)(struct ath12k_base *ab, 1410 struct hal_wbm_idle_scatter_list *sbuf, 1411 u32 nsbufs, u32 tot_link_desc, 1412 u32 end_offset); 1413 void (*reo_init_cmd_ring)(struct ath12k_base *ab, 1414 struct hal_srng *srng); 1415 void (*reo_shared_qaddr_cache_clear)(struct ath12k_base *ab); 1416 void (*reo_hw_setup)(struct ath12k_base *ab, u32 ring_hash_map); 1417 void (*rx_buf_addr_info_set)(struct ath12k_buffer_addr *binfo, 1418 dma_addr_t paddr, u32 cookie, u8 manager); 1419 void (*rx_buf_addr_info_get)(struct ath12k_buffer_addr *binfo, 1420 dma_addr_t *paddr, u32 *msdu_cookies, 1421 u8 *rbm); 1422 void (*cc_config)(struct ath12k_base *ab); 1423 enum hal_rx_buf_return_buf_manager 1424 (*get_idle_link_rbm)(struct ath12k_hal *hal, u8 device_id); 1425 void (*rx_msdu_list_get)(struct ath12k *ar, 1426 void *link_desc, 1427 void *msdu_list, 1428 u16 *num_msdus); 1429 void (*rx_reo_ent_buf_paddr_get)(void *rx_desc, dma_addr_t *paddr, 1430 u32 *sw_cookie, 1431 struct ath12k_buffer_addr **pp_buf_addr, 1432 u8 *rbm, u32 *msdu_cnt); 1433 void *(*reo_cmd_enc_tlv_hdr)(void *tlv, u64 tag, u64 len); 1434 u16 (*reo_status_dec_tlv_hdr)(void *tlv, void **desc); 1435 }; 1436 1437 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 1438 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 1439 #define HAL_TLV_USR_ID GENMASK(31, 26) 1440 1441 #define HAL_TLV_ALIGN 4 1442 1443 struct hal_tlv_hdr { 1444 __le32 tl; 1445 u8 value[]; 1446 } __packed; 1447 1448 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1) 1449 #define HAL_TLV_64_HDR_LEN GENMASK(21, 10) 1450 #define HAL_TLV_64_USR_ID GENMASK(31, 26) 1451 #define HAL_TLV_64_ALIGN 8 1452 1453 struct hal_tlv_64_hdr { 1454 __le64 tl; 1455 u8 value[]; 1456 } __packed; 1457 1458 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 1459 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 1460 1461 dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab, 1462 struct hal_srng *srng); 1463 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab, 1464 struct hal_srng *srng); 1465 u32 ath12k_hal_ce_get_desc_size(struct ath12k_hal *hal, enum hal_ce_desc type); 1466 void ath12k_hal_ce_dst_set_desc(struct ath12k_hal *hal, 1467 struct hal_ce_srng_dest_desc *desc, 1468 dma_addr_t paddr); 1469 void ath12k_hal_ce_src_set_desc(struct ath12k_hal *hal, 1470 struct hal_ce_srng_src_desc *desc, 1471 dma_addr_t paddr, u32 len, u32 id, 1472 u8 byte_swap_data); 1473 int ath12k_hal_srng_get_entrysize(struct ath12k_base *ab, u32 ring_type); 1474 int ath12k_hal_srng_get_max_entries(struct ath12k_base *ab, u32 ring_type); 1475 void ath12k_hal_srng_get_params(struct ath12k_base *ab, struct hal_srng *srng, 1476 struct hal_srng_params *params); 1477 void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab, 1478 struct hal_srng *srng); 1479 void *ath12k_hal_srng_src_peek(struct ath12k_base *ab, struct hal_srng *srng); 1480 void *ath12k_hal_srng_dst_peek(struct ath12k_base *ab, struct hal_srng *srng); 1481 int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1482 bool sync_hw_ptr); 1483 void *ath12k_hal_srng_src_get_next_reaped(struct ath12k_base *ab, 1484 struct hal_srng *srng); 1485 void *ath12k_hal_srng_src_reap_next(struct ath12k_base *ab, 1486 struct hal_srng *srng); 1487 void *ath12k_hal_srng_src_next_peek(struct ath12k_base *ab, 1488 struct hal_srng *srng); 1489 void *ath12k_hal_srng_src_get_next_entry(struct ath12k_base *ab, 1490 struct hal_srng *srng); 1491 int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1492 bool sync_hw_ptr); 1493 void ath12k_hal_srng_access_begin(struct ath12k_base *ab, 1494 struct hal_srng *srng); 1495 void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng); 1496 int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type, 1497 int ring_num, int mac_id, 1498 struct hal_srng_params *params); 1499 int ath12k_hal_srng_init(struct ath12k_base *ath12k); 1500 void ath12k_hal_srng_deinit(struct ath12k_base *ath12k); 1501 void ath12k_hal_dump_srng_stats(struct ath12k_base *ab); 1502 void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab, 1503 u32 **cfg, u32 *len); 1504 int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab, 1505 enum hal_ring_type ring_type, 1506 int ring_num); 1507 void ath12k_hal_srng_shadow_config(struct ath12k_base *ab); 1508 void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, 1509 struct hal_srng *srng); 1510 void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab); 1511 void ath12k_hal_set_link_desc_addr(struct ath12k_hal *hal, 1512 struct hal_wbm_link_desc *desc, u32 cookie, 1513 dma_addr_t paddr, int rbm); 1514 void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab, 1515 struct hal_wbm_idle_scatter_list *sbuf, 1516 u32 nsbufs, u32 tot_link_desc, 1517 u32 end_offset); 1518 u32 1519 ath12k_hal_ce_dst_status_get_length(struct ath12k_hal *hal, 1520 struct hal_ce_srng_dst_status_desc *desc); 1521 void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id); 1522 void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, 1523 u32 bank_config, u8 bank_id); 1524 void ath12k_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab); 1525 void ath12k_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab); 1526 void ath12k_hal_write_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr); 1527 void 1528 ath12k_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr); 1529 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, struct hal_srng *srng); 1530 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map); 1531 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_hal *hal, 1532 struct ath12k_buffer_addr *binfo, 1533 dma_addr_t paddr, u32 cookie, u8 manager); 1534 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_hal *hal, 1535 struct ath12k_buffer_addr *binfo, 1536 dma_addr_t *paddr, u32 *msdu_cookies, 1537 u8 *rbm); 1538 void ath12k_hal_cc_config(struct ath12k_base *ab); 1539 enum hal_rx_buf_return_buf_manager 1540 ath12k_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id); 1541 void ath12k_hal_rx_msdu_list_get(struct ath12k_hal *hal, struct ath12k *ar, 1542 void *link_desc, void *msdu_list, 1543 u16 *num_msdus); 1544 void ath12k_hal_rx_reo_ent_buf_paddr_get(struct ath12k_hal *hal, void *rx_desc, 1545 dma_addr_t *paddr, u32 *sw_cookie, 1546 struct ath12k_buffer_addr **pp_buf_addr, 1547 u8 *rbm, u32 *msdu_cnt); 1548 void *ath12k_hal_encode_tlv64_hdr(void *tlv, u64 tag, u64 len); 1549 void *ath12k_hal_encode_tlv32_hdr(void *tlv, u64 tag, u64 len); 1550 u16 ath12k_hal_decode_tlv64_hdr(void *tlv, void **desc); 1551 u16 ath12k_hal_decode_tlv32_hdr(void *tlv, void **desc); 1552 #endif 1553