1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "hw.h" 11 12 static enum hal_tcl_encap_type 13 ath12k_dp_tx_get_encap_type(struct ath12k_link_vif *arvif, struct sk_buff *skb) 14 { 15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 16 struct ath12k_base *ab = arvif->ar->ab; 17 18 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) 19 return HAL_TCL_ENCAP_TYPE_RAW; 20 21 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 22 return HAL_TCL_ENCAP_TYPE_ETHERNET; 23 24 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 25 } 26 27 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 28 { 29 struct ieee80211_hdr *hdr = (void *)skb->data; 30 u8 *qos_ctl; 31 32 if (!ieee80211_is_data_qos(hdr->frame_control)) 33 return; 34 35 qos_ctl = ieee80211_get_qos_ctl(hdr); 36 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 37 skb->data, (void *)qos_ctl - (void *)skb->data); 38 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 39 40 hdr = (void *)skb->data; 41 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 42 } 43 44 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 45 { 46 struct ieee80211_hdr *hdr = (void *)skb->data; 47 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 48 49 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 51 else if (!ieee80211_is_data_qos(hdr->frame_control)) 52 return HAL_DESC_REO_NON_QOS_TID; 53 else 54 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 55 } 56 57 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 58 { 59 switch (cipher) { 60 case WLAN_CIPHER_SUITE_WEP40: 61 return HAL_ENCRYPT_TYPE_WEP_40; 62 case WLAN_CIPHER_SUITE_WEP104: 63 return HAL_ENCRYPT_TYPE_WEP_104; 64 case WLAN_CIPHER_SUITE_TKIP: 65 return HAL_ENCRYPT_TYPE_TKIP_MIC; 66 case WLAN_CIPHER_SUITE_CCMP: 67 return HAL_ENCRYPT_TYPE_CCMP_128; 68 case WLAN_CIPHER_SUITE_CCMP_256: 69 return HAL_ENCRYPT_TYPE_CCMP_256; 70 case WLAN_CIPHER_SUITE_GCMP: 71 return HAL_ENCRYPT_TYPE_GCMP_128; 72 case WLAN_CIPHER_SUITE_GCMP_256: 73 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 74 default: 75 return HAL_ENCRYPT_TYPE_OPEN; 76 } 77 } 78 79 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 80 struct ath12k_tx_desc_info *tx_desc, 81 u8 pool_id) 82 { 83 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 84 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 85 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 86 } 87 88 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 89 u8 pool_id) 90 { 91 struct ath12k_tx_desc_info *desc; 92 93 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 94 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 95 struct ath12k_tx_desc_info, 96 list); 97 if (!desc) { 98 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 99 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 100 return NULL; 101 } 102 103 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 104 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 105 106 return desc; 107 } 108 109 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, 110 struct hal_tx_msdu_ext_desc *tcl_ext_cmd, 111 struct hal_tx_info *ti) 112 { 113 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 114 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 115 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 116 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 117 le32_encode_bits(ti->data_len, 118 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 119 120 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 121 le32_encode_bits(ti->encap_type, 122 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 123 le32_encode_bits(ti->encrypt_type, 124 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 125 } 126 127 #define HTT_META_DATA_ALIGNMENT 0x8 128 129 static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len) 130 { 131 struct sk_buff *tail; 132 void *metadata; 133 134 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0)) 135 return NULL; 136 137 metadata = pskb_put(skb, tail, tail_len); 138 memset(metadata, 0, tail_len); 139 return metadata; 140 } 141 142 /* Preparing HTT Metadata when utilized with ext MSDU */ 143 static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb) 144 { 145 struct hal_tx_msdu_metadata *desc_ext; 146 u8 htt_desc_size; 147 /* Size rounded of multiple of 8 bytes */ 148 u8 htt_desc_size_aligned; 149 150 htt_desc_size = sizeof(struct hal_tx_msdu_metadata); 151 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); 152 153 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned); 154 if (!desc_ext) 155 return -ENOMEM; 156 157 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) | 158 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) | 159 le32_encode_bits(1, 160 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL); 161 162 return 0; 163 } 164 165 static void ath12k_dp_tx_move_payload(struct sk_buff *skb, 166 unsigned long delta, 167 bool head) 168 { 169 unsigned long len = skb->len; 170 171 if (head) { 172 skb_push(skb, delta); 173 memmove(skb->data, skb->data + delta, len); 174 skb_trim(skb, len); 175 } else { 176 skb_put(skb, delta); 177 memmove(skb->data + delta, skb->data, len); 178 skb_pull(skb, delta); 179 } 180 } 181 182 static int ath12k_dp_tx_align_payload(struct ath12k_base *ab, 183 struct sk_buff **pskb) 184 { 185 u32 iova_mask = ab->hw_params->iova_mask; 186 unsigned long offset, delta1, delta2; 187 struct sk_buff *skb2, *skb = *pskb; 188 unsigned int headroom = skb_headroom(skb); 189 int tailroom = skb_tailroom(skb); 190 int ret = 0; 191 192 offset = (unsigned long)skb->data & iova_mask; 193 delta1 = offset; 194 delta2 = iova_mask - offset + 1; 195 196 if (headroom >= delta1) { 197 ath12k_dp_tx_move_payload(skb, delta1, true); 198 } else if (tailroom >= delta2) { 199 ath12k_dp_tx_move_payload(skb, delta2, false); 200 } else { 201 skb2 = skb_realloc_headroom(skb, iova_mask); 202 if (!skb2) { 203 ret = -ENOMEM; 204 goto out; 205 } 206 207 dev_kfree_skb_any(skb); 208 209 offset = (unsigned long)skb2->data & iova_mask; 210 if (offset) 211 ath12k_dp_tx_move_payload(skb2, offset, true); 212 *pskb = skb2; 213 } 214 215 out: 216 return ret; 217 } 218 219 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif, 220 struct sk_buff *skb) 221 { 222 struct ath12k_base *ab = ar->ab; 223 struct ath12k_dp *dp = &ab->dp; 224 struct hal_tx_info ti = {0}; 225 struct ath12k_tx_desc_info *tx_desc; 226 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 227 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 228 struct hal_tcl_data_cmd *hal_tcl_desc; 229 struct hal_tx_msdu_ext_desc *msg; 230 struct sk_buff *skb_ext_desc; 231 struct hal_srng *tcl_ring; 232 struct ieee80211_hdr *hdr = (void *)skb->data; 233 struct ath12k_vif *ahvif = arvif->ahvif; 234 struct dp_tx_ring *tx_ring; 235 u8 pool_id; 236 u8 hal_ring_id; 237 int ret; 238 u8 ring_selector, ring_map = 0; 239 bool tcl_ring_retry; 240 bool msdu_ext_desc = false; 241 bool add_htt_metadata = false; 242 u32 iova_mask = ab->hw_params->iova_mask; 243 244 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 245 return -ESHUTDOWN; 246 247 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 248 !ieee80211_is_data(hdr->frame_control)) 249 return -EOPNOTSUPP; 250 251 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 252 253 /* Let the default ring selection be based on current processor 254 * number, where one of the 3 tcl rings are selected based on 255 * the smp_processor_id(). In case that ring 256 * is full/busy, we resort to other available rings. 257 * If all rings are full, we drop the packet. 258 * TODO: Add throttling logic when all rings are full 259 */ 260 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 261 262 tcl_ring_sel: 263 tcl_ring_retry = false; 264 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 265 266 ring_map |= BIT(ti.ring_id); 267 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 268 269 tx_ring = &dp->tx_ring[ti.ring_id]; 270 271 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 272 if (!tx_desc) 273 return -ENOMEM; 274 275 ti.bank_id = arvif->bank_id; 276 ti.meta_data_flags = arvif->tcl_metadata; 277 278 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 279 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 280 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 281 ti.encrypt_type = 282 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 283 284 if (ieee80211_has_protected(hdr->frame_control)) 285 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 286 } else { 287 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 288 } 289 290 msdu_ext_desc = true; 291 } 292 293 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); 294 ti.addr_search_flags = arvif->hal_addr_search_flags; 295 ti.search_type = arvif->search_type; 296 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 297 ti.pkt_offset = 0; 298 ti.lmac_id = ar->lmac_id; 299 ti.vdev_id = arvif->vdev_id; 300 ti.bss_ast_hash = arvif->ast_hash; 301 ti.bss_ast_idx = arvif->ast_idx; 302 ti.dscp_tid_tbl_idx = 0; 303 304 if (skb->ip_summed == CHECKSUM_PARTIAL && 305 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 306 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 307 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 308 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 309 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 310 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 311 } 312 313 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 314 315 ti.tid = ath12k_dp_tx_get_tid(skb); 316 317 switch (ti.encap_type) { 318 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 319 ath12k_dp_tx_encap_nwifi(skb); 320 break; 321 case HAL_TCL_ENCAP_TYPE_RAW: 322 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 323 ret = -EINVAL; 324 goto fail_remove_tx_buf; 325 } 326 break; 327 case HAL_TCL_ENCAP_TYPE_ETHERNET: 328 /* no need to encap */ 329 break; 330 case HAL_TCL_ENCAP_TYPE_802_3: 331 default: 332 /* TODO: Take care of other encap modes as well */ 333 ret = -EINVAL; 334 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 335 goto fail_remove_tx_buf; 336 } 337 338 if (iova_mask && 339 (unsigned long)skb->data & iova_mask) { 340 ret = ath12k_dp_tx_align_payload(ab, &skb); 341 if (ret) { 342 ath12k_warn(ab, "failed to align TX buffer %d\n", ret); 343 /* don't bail out, give original buffer 344 * a chance even unaligned. 345 */ 346 goto map; 347 } 348 349 /* hdr is pointing to a wrong place after alignment, 350 * so refresh it for later use. 351 */ 352 hdr = (void *)skb->data; 353 } 354 map: 355 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 356 if (dma_mapping_error(ab->dev, ti.paddr)) { 357 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 358 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 359 ret = -ENOMEM; 360 goto fail_remove_tx_buf; 361 } 362 363 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) && 364 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && 365 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) && 366 ieee80211_has_protected(hdr->frame_control)) { 367 /* Add metadata for sw encrypted vlan group traffic */ 368 add_htt_metadata = true; 369 msdu_ext_desc = true; 370 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW); 371 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; 372 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 373 } 374 375 tx_desc->skb = skb; 376 tx_desc->mac_id = ar->pdev_idx; 377 ti.desc_id = tx_desc->desc_id; 378 ti.data_len = skb->len; 379 skb_cb->paddr = ti.paddr; 380 skb_cb->vif = ahvif->vif; 381 skb_cb->ar = ar; 382 383 if (msdu_ext_desc) { 384 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 385 if (!skb_ext_desc) { 386 ret = -ENOMEM; 387 goto fail_unmap_dma; 388 } 389 390 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 391 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 392 393 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 394 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 395 396 if (add_htt_metadata) { 397 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc); 398 if (ret < 0) { 399 ath12k_dbg(ab, ATH12K_DBG_DP_TX, 400 "Failed to add HTT meta data, dropping packet\n"); 401 goto fail_unmap_dma; 402 } 403 } 404 405 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 406 skb_ext_desc->len, DMA_TO_DEVICE); 407 ret = dma_mapping_error(ab->dev, ti.paddr); 408 if (ret) { 409 kfree_skb(skb_ext_desc); 410 goto fail_unmap_dma; 411 } 412 413 ti.data_len = skb_ext_desc->len; 414 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 415 416 skb_cb->paddr_ext_desc = ti.paddr; 417 } 418 419 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 420 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 421 422 spin_lock_bh(&tcl_ring->lock); 423 424 ath12k_hal_srng_access_begin(ab, tcl_ring); 425 426 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 427 if (!hal_tcl_desc) { 428 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 429 * desc because the desc is directly enqueued onto hw queue. 430 */ 431 ath12k_hal_srng_access_end(ab, tcl_ring); 432 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 433 spin_unlock_bh(&tcl_ring->lock); 434 ret = -ENOMEM; 435 436 /* Checking for available tcl descriptors in another ring in 437 * case of failure due to full tcl ring now, is better than 438 * checking this ring earlier for each pkt tx. 439 * Restart ring selection if some rings are not checked yet. 440 */ 441 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 442 ab->hw_params->tcl_ring_retry) { 443 tcl_ring_retry = true; 444 ring_selector++; 445 } 446 447 goto fail_unmap_dma; 448 } 449 450 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 451 452 ath12k_hal_srng_access_end(ab, tcl_ring); 453 454 spin_unlock_bh(&tcl_ring->lock); 455 456 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 457 skb->data, skb->len); 458 459 atomic_inc(&ar->dp.num_tx_pending); 460 461 return 0; 462 463 fail_unmap_dma: 464 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 465 466 if (skb_cb->paddr_ext_desc) 467 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 468 sizeof(struct hal_tx_msdu_ext_desc), 469 DMA_TO_DEVICE); 470 471 fail_remove_tx_buf: 472 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 473 if (tcl_ring_retry) 474 goto tcl_ring_sel; 475 476 return ret; 477 } 478 479 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 480 struct sk_buff *msdu, u8 mac_id, 481 struct dp_tx_ring *tx_ring) 482 { 483 struct ath12k *ar; 484 struct ath12k_skb_cb *skb_cb; 485 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 486 487 skb_cb = ATH12K_SKB_CB(msdu); 488 ar = ab->pdevs[pdev_id].ar; 489 490 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 491 if (skb_cb->paddr_ext_desc) 492 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 493 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 494 495 ieee80211_free_txskb(ar->ah->hw, msdu); 496 497 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 498 wake_up(&ar->dp.tx_empty_waitq); 499 } 500 501 static void 502 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 503 struct sk_buff *msdu, 504 struct dp_tx_ring *tx_ring, 505 struct ath12k_dp_htt_wbm_tx_status *ts) 506 { 507 struct ieee80211_tx_info *info; 508 struct ath12k_skb_cb *skb_cb; 509 struct ath12k *ar; 510 511 skb_cb = ATH12K_SKB_CB(msdu); 512 info = IEEE80211_SKB_CB(msdu); 513 514 ar = skb_cb->ar; 515 516 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 517 wake_up(&ar->dp.tx_empty_waitq); 518 519 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 520 if (skb_cb->paddr_ext_desc) 521 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 522 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 523 524 memset(&info->status, 0, sizeof(info->status)); 525 526 if (ts->acked) { 527 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 528 info->flags |= IEEE80211_TX_STAT_ACK; 529 info->status.ack_signal = ts->ack_rssi; 530 531 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 532 ab->wmi_ab.svc_map)) 533 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 534 535 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 536 } else { 537 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 538 } 539 } 540 541 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 542 } 543 544 static void 545 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, 546 void *desc, u8 mac_id, 547 struct sk_buff *msdu, 548 struct dp_tx_ring *tx_ring) 549 { 550 struct htt_tx_wbm_completion *status_desc; 551 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 552 enum hal_wbm_htt_tx_comp_status wbm_status; 553 554 status_desc = desc; 555 556 wbm_status = le32_get_bits(status_desc->info0, 557 HTT_TX_WBM_COMP_INFO0_STATUS); 558 559 switch (wbm_status) { 560 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 561 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 562 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 563 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 564 ts.ack_rssi = le32_get_bits(status_desc->info2, 565 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 566 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts); 567 break; 568 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 569 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 570 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring); 571 break; 572 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 573 /* This event is to be handled only when the driver decides to 574 * use WDS offload functionality. 575 */ 576 break; 577 default: 578 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 579 break; 580 } 581 } 582 583 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 584 struct sk_buff *msdu, 585 struct hal_tx_status *ts) 586 { 587 struct ath12k_base *ab = ar->ab; 588 struct ath12k_hw *ah = ar->ah; 589 struct ieee80211_tx_info *info; 590 struct ath12k_skb_cb *skb_cb; 591 592 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 593 /* Must not happen */ 594 return; 595 } 596 597 skb_cb = ATH12K_SKB_CB(msdu); 598 599 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 600 if (skb_cb->paddr_ext_desc) 601 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 602 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 603 604 rcu_read_lock(); 605 606 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 607 ieee80211_free_txskb(ah->hw, msdu); 608 goto exit; 609 } 610 611 if (!skb_cb->vif) { 612 ieee80211_free_txskb(ah->hw, msdu); 613 goto exit; 614 } 615 616 info = IEEE80211_SKB_CB(msdu); 617 memset(&info->status, 0, sizeof(info->status)); 618 619 /* skip tx rate update from ieee80211_status*/ 620 info->status.rates[0].idx = -1; 621 622 switch (ts->status) { 623 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED: 624 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 625 info->flags |= IEEE80211_TX_STAT_ACK; 626 info->status.ack_signal = ts->ack_rssi; 627 628 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 629 ab->wmi_ab.svc_map)) 630 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 631 632 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 633 } 634 break; 635 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: 636 if (info->flags & IEEE80211_TX_CTL_NO_ACK) { 637 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 638 break; 639 } 640 fallthrough; 641 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: 642 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: 643 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: 644 /* The failure status is due to internal firmware tx failure 645 * hence drop the frame; do not update the status of frame to 646 * the upper layer 647 */ 648 ieee80211_free_txskb(ah->hw, msdu); 649 goto exit; 650 default: 651 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", 652 ts->status); 653 break; 654 } 655 656 /* NOTE: Tx rate status reporting. Tx completion status does not have 657 * necessary information (for example nss) to build the tx rate. 658 * Might end up reporting it out-of-band from HTT stats. 659 */ 660 661 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 662 663 exit: 664 rcu_read_unlock(); 665 } 666 667 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 668 struct hal_wbm_completion_ring_tx *desc, 669 struct hal_tx_status *ts) 670 { 671 ts->buf_rel_source = 672 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 673 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 674 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 675 return; 676 677 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 678 return; 679 680 ts->status = le32_get_bits(desc->info0, 681 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 682 683 ts->ppdu_id = le32_get_bits(desc->info1, 684 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 685 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID) 686 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0); 687 else 688 ts->rate_stats = 0; 689 } 690 691 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 692 { 693 struct ath12k *ar; 694 struct ath12k_dp *dp = &ab->dp; 695 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 696 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 697 struct ath12k_tx_desc_info *tx_desc = NULL; 698 struct sk_buff *msdu; 699 struct hal_tx_status ts = { 0 }; 700 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 701 struct hal_wbm_release_ring *desc; 702 u8 mac_id, pdev_id; 703 u64 desc_va; 704 705 spin_lock_bh(&status_ring->lock); 706 707 ath12k_hal_srng_access_begin(ab, status_ring); 708 709 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 710 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 711 if (!desc) 712 break; 713 714 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 715 desc, sizeof(*desc)); 716 tx_ring->tx_status_head = 717 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 718 } 719 720 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 721 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 722 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 723 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 724 } 725 726 ath12k_hal_srng_access_end(ab, status_ring); 727 728 spin_unlock_bh(&status_ring->lock); 729 730 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 731 struct hal_wbm_completion_ring_tx *tx_status; 732 u32 desc_id; 733 734 tx_ring->tx_status_tail = 735 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 736 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 737 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 738 739 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 740 /* HW done cookie conversion */ 741 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 742 le32_to_cpu(tx_status->buf_va_lo)); 743 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 744 } else { 745 /* SW does cookie conversion to VA */ 746 desc_id = le32_get_bits(tx_status->buf_va_hi, 747 BUFFER_ADDR_INFO1_SW_COOKIE); 748 749 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 750 } 751 if (!tx_desc) { 752 ath12k_warn(ab, "unable to retrieve tx_desc!"); 753 continue; 754 } 755 756 msdu = tx_desc->skb; 757 mac_id = tx_desc->mac_id; 758 759 /* Release descriptor as soon as extracting necessary info 760 * to reduce contention 761 */ 762 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 763 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 764 ath12k_dp_tx_process_htt_tx_complete(ab, 765 (void *)tx_status, 766 mac_id, msdu, 767 tx_ring); 768 continue; 769 } 770 771 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 772 ar = ab->pdevs[pdev_id].ar; 773 774 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 775 wake_up(&ar->dp.tx_empty_waitq); 776 777 ath12k_dp_tx_complete_msdu(ar, msdu, &ts); 778 } 779 } 780 781 static int 782 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 783 int mac_id, u32 ring_id, 784 enum hal_ring_type ring_type, 785 enum htt_srng_ring_type *htt_ring_type, 786 enum htt_srng_ring_id *htt_ring_id) 787 { 788 int ret = 0; 789 790 switch (ring_type) { 791 case HAL_RXDMA_BUF: 792 /* for some targets, host fills rx buffer to fw and fw fills to 793 * rxbuf ring for each rxdma 794 */ 795 if (!ab->hw_params->rx_mac_buf_ring) { 796 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 797 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 798 ret = -EINVAL; 799 } 800 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 801 *htt_ring_type = HTT_SW_TO_HW_RING; 802 } else { 803 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 804 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 805 *htt_ring_type = HTT_SW_TO_SW_RING; 806 } else { 807 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 808 *htt_ring_type = HTT_SW_TO_HW_RING; 809 } 810 } 811 break; 812 case HAL_RXDMA_DST: 813 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 814 *htt_ring_type = HTT_HW_TO_SW_RING; 815 break; 816 case HAL_RXDMA_MONITOR_BUF: 817 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 818 *htt_ring_type = HTT_SW_TO_HW_RING; 819 break; 820 case HAL_RXDMA_MONITOR_STATUS: 821 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 822 *htt_ring_type = HTT_SW_TO_HW_RING; 823 break; 824 case HAL_RXDMA_MONITOR_DST: 825 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 826 *htt_ring_type = HTT_HW_TO_SW_RING; 827 break; 828 case HAL_RXDMA_MONITOR_DESC: 829 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 830 *htt_ring_type = HTT_SW_TO_HW_RING; 831 break; 832 default: 833 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 834 ret = -EINVAL; 835 } 836 return ret; 837 } 838 839 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 840 int mac_id, enum hal_ring_type ring_type) 841 { 842 struct htt_srng_setup_cmd *cmd; 843 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 844 struct hal_srng_params params; 845 struct sk_buff *skb; 846 u32 ring_entry_sz; 847 int len = sizeof(*cmd); 848 dma_addr_t hp_addr, tp_addr; 849 enum htt_srng_ring_type htt_ring_type; 850 enum htt_srng_ring_id htt_ring_id; 851 int ret; 852 853 skb = ath12k_htc_alloc_skb(ab, len); 854 if (!skb) 855 return -ENOMEM; 856 857 memset(¶ms, 0, sizeof(params)); 858 ath12k_hal_srng_get_params(ab, srng, ¶ms); 859 860 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 861 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 862 863 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 864 ring_type, &htt_ring_type, 865 &htt_ring_id); 866 if (ret) 867 goto err_free; 868 869 skb_put(skb, len); 870 cmd = (struct htt_srng_setup_cmd *)skb->data; 871 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 872 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 873 if (htt_ring_type == HTT_SW_TO_HW_RING || 874 htt_ring_type == HTT_HW_TO_SW_RING) 875 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 876 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 877 else 878 cmd->info0 |= le32_encode_bits(mac_id, 879 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 880 cmd->info0 |= le32_encode_bits(htt_ring_type, 881 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 882 cmd->info0 |= le32_encode_bits(htt_ring_id, 883 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 884 885 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 886 HAL_ADDR_LSB_REG_MASK); 887 888 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 889 HAL_ADDR_MSB_REG_SHIFT); 890 891 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 892 if (ret < 0) 893 goto err_free; 894 895 ring_entry_sz = ret; 896 897 ring_entry_sz >>= 2; 898 cmd->info1 = le32_encode_bits(ring_entry_sz, 899 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 900 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 901 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 902 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 903 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 904 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 905 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 906 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 907 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 908 if (htt_ring_type == HTT_SW_TO_HW_RING) 909 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 910 911 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 912 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 913 914 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 915 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 916 917 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 918 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 919 cmd->msi_data = cpu_to_le32(params.msi_data); 920 921 cmd->intr_info = 922 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 923 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 924 cmd->intr_info |= 925 le32_encode_bits(params.intr_timer_thres_us >> 3, 926 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 927 928 cmd->info2 = 0; 929 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 930 cmd->info2 = le32_encode_bits(params.low_threshold, 931 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 932 } 933 934 ath12k_dbg(ab, ATH12K_DBG_HAL, 935 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 936 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 937 cmd->msi_data); 938 939 ath12k_dbg(ab, ATH12K_DBG_HAL, 940 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 941 ring_id, ring_type, cmd->intr_info, cmd->info2); 942 943 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 944 if (ret) 945 goto err_free; 946 947 return 0; 948 949 err_free: 950 dev_kfree_skb_any(skb); 951 952 return ret; 953 } 954 955 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 956 957 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 958 { 959 struct ath12k_dp *dp = &ab->dp; 960 struct sk_buff *skb; 961 struct htt_ver_req_cmd *cmd; 962 int len = sizeof(*cmd); 963 int ret; 964 965 init_completion(&dp->htt_tgt_version_received); 966 967 skb = ath12k_htc_alloc_skb(ab, len); 968 if (!skb) 969 return -ENOMEM; 970 971 skb_put(skb, len); 972 cmd = (struct htt_ver_req_cmd *)skb->data; 973 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 974 HTT_VER_REQ_INFO_MSG_ID); 975 976 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 977 if (ret) { 978 dev_kfree_skb_any(skb); 979 return ret; 980 } 981 982 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 983 HTT_TARGET_VERSION_TIMEOUT_HZ); 984 if (ret == 0) { 985 ath12k_warn(ab, "htt target version request timed out\n"); 986 return -ETIMEDOUT; 987 } 988 989 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 990 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 991 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 992 return -EOPNOTSUPP; 993 } 994 995 return 0; 996 } 997 998 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 999 { 1000 struct ath12k_base *ab = ar->ab; 1001 struct ath12k_dp *dp = &ab->dp; 1002 struct sk_buff *skb; 1003 struct htt_ppdu_stats_cfg_cmd *cmd; 1004 int len = sizeof(*cmd); 1005 u8 pdev_mask; 1006 int ret; 1007 int i; 1008 1009 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1010 skb = ath12k_htc_alloc_skb(ab, len); 1011 if (!skb) 1012 return -ENOMEM; 1013 1014 skb_put(skb, len); 1015 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 1016 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 1017 HTT_PPDU_STATS_CFG_MSG_TYPE); 1018 1019 pdev_mask = 1 << (i + 1); 1020 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 1021 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 1022 1023 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1024 if (ret) { 1025 dev_kfree_skb_any(skb); 1026 return ret; 1027 } 1028 } 1029 1030 return 0; 1031 } 1032 1033 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1034 int mac_id, enum hal_ring_type ring_type, 1035 int rx_buf_size, 1036 struct htt_rx_ring_tlv_filter *tlv_filter) 1037 { 1038 struct htt_rx_ring_selection_cfg_cmd *cmd; 1039 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1040 struct hal_srng_params params; 1041 struct sk_buff *skb; 1042 int len = sizeof(*cmd); 1043 enum htt_srng_ring_type htt_ring_type; 1044 enum htt_srng_ring_id htt_ring_id; 1045 int ret; 1046 1047 skb = ath12k_htc_alloc_skb(ab, len); 1048 if (!skb) 1049 return -ENOMEM; 1050 1051 memset(¶ms, 0, sizeof(params)); 1052 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1053 1054 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1055 ring_type, &htt_ring_type, 1056 &htt_ring_id); 1057 if (ret) 1058 goto err_free; 1059 1060 skb_put(skb, len); 1061 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 1062 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 1063 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1064 if (htt_ring_type == HTT_SW_TO_HW_RING || 1065 htt_ring_type == HTT_HW_TO_SW_RING) 1066 cmd->info0 |= 1067 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1068 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1069 else 1070 cmd->info0 |= 1071 le32_encode_bits(mac_id, 1072 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1073 cmd->info0 |= le32_encode_bits(htt_ring_id, 1074 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1075 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1076 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 1077 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1078 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 1079 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 1080 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID); 1081 cmd->info1 = le32_encode_bits(rx_buf_size, 1082 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 1083 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 1084 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 1085 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 1086 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 1087 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 1088 1089 if (tlv_filter->offset_valid) { 1090 cmd->rx_packet_offset = 1091 le32_encode_bits(tlv_filter->rx_packet_offset, 1092 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 1093 1094 cmd->rx_packet_offset |= 1095 le32_encode_bits(tlv_filter->rx_header_offset, 1096 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 1097 1098 cmd->rx_mpdu_offset = 1099 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 1100 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 1101 1102 cmd->rx_mpdu_offset |= 1103 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 1104 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 1105 1106 cmd->rx_msdu_offset = 1107 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 1108 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 1109 1110 cmd->rx_msdu_offset |= 1111 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 1112 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 1113 1114 cmd->rx_attn_offset = 1115 le32_encode_bits(tlv_filter->rx_attn_offset, 1116 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 1117 } 1118 1119 if (tlv_filter->rx_mpdu_start_wmask > 0 && 1120 tlv_filter->rx_msdu_end_wmask > 0) { 1121 cmd->info2 |= 1122 le32_encode_bits(true, 1123 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET); 1124 cmd->rx_mpdu_start_end_mask = 1125 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask, 1126 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK); 1127 /* mpdu_end is not used for any hardwares so far 1128 * please assign it in future if any chip is 1129 * using through hal ops 1130 */ 1131 cmd->rx_mpdu_start_end_mask |= 1132 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask, 1133 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK); 1134 cmd->rx_msdu_end_word_mask = 1135 le32_encode_bits(tlv_filter->rx_msdu_end_wmask, 1136 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK); 1137 } 1138 1139 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1140 if (ret) 1141 goto err_free; 1142 1143 return 0; 1144 1145 err_free: 1146 dev_kfree_skb_any(skb); 1147 1148 return ret; 1149 } 1150 1151 int 1152 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 1153 struct htt_ext_stats_cfg_params *cfg_params, 1154 u64 cookie) 1155 { 1156 struct ath12k_base *ab = ar->ab; 1157 struct ath12k_dp *dp = &ab->dp; 1158 struct sk_buff *skb; 1159 struct htt_ext_stats_cfg_cmd *cmd; 1160 int len = sizeof(*cmd); 1161 int ret; 1162 u32 pdev_id; 1163 1164 skb = ath12k_htc_alloc_skb(ab, len); 1165 if (!skb) 1166 return -ENOMEM; 1167 1168 skb_put(skb, len); 1169 1170 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1171 memset(cmd, 0, sizeof(*cmd)); 1172 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1173 1174 pdev_id = ath12k_mac_get_target_pdev_id(ar); 1175 cmd->hdr.pdev_mask = 1 << pdev_id; 1176 1177 cmd->hdr.stats_type = type; 1178 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 1179 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 1180 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 1181 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1182 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1183 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1184 1185 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1186 if (ret) { 1187 ath12k_warn(ab, "failed to send htt type stats request: %d", 1188 ret); 1189 dev_kfree_skb_any(skb); 1190 return ret; 1191 } 1192 1193 return 0; 1194 } 1195 1196 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1197 { 1198 struct ath12k_base *ab = ar->ab; 1199 int ret; 1200 1201 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset); 1202 if (ret) { 1203 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1204 return ret; 1205 } 1206 1207 return 0; 1208 } 1209 1210 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1211 { 1212 struct ath12k_base *ab = ar->ab; 1213 struct ath12k_dp *dp = &ab->dp; 1214 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1215 int ret, ring_id; 1216 1217 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1218 tlv_filter.offset_valid = false; 1219 1220 if (!reset) { 1221 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1222 tlv_filter.pkt_filter_flags0 = 1223 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1224 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1225 tlv_filter.pkt_filter_flags1 = 1226 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1227 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1228 tlv_filter.pkt_filter_flags2 = 1229 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1230 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1231 tlv_filter.pkt_filter_flags3 = 1232 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1233 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1234 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1235 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1236 } 1237 1238 if (ab->hw_params->rxdma1_enable) { 1239 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0, 1240 HAL_RXDMA_MONITOR_BUF, 1241 DP_RXDMA_REFILL_RING_SIZE, 1242 &tlv_filter); 1243 if (ret) { 1244 ath12k_err(ab, 1245 "failed to setup filter for monitor buf %d\n", ret); 1246 return ret; 1247 } 1248 } 1249 1250 return 0; 1251 } 1252 1253 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1254 int mac_id, enum hal_ring_type ring_type, 1255 int tx_buf_size, 1256 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1257 { 1258 struct htt_tx_ring_selection_cfg_cmd *cmd; 1259 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1260 struct hal_srng_params params; 1261 struct sk_buff *skb; 1262 int len = sizeof(*cmd); 1263 enum htt_srng_ring_type htt_ring_type; 1264 enum htt_srng_ring_id htt_ring_id; 1265 int ret; 1266 1267 skb = ath12k_htc_alloc_skb(ab, len); 1268 if (!skb) 1269 return -ENOMEM; 1270 1271 memset(¶ms, 0, sizeof(params)); 1272 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1273 1274 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1275 ring_type, &htt_ring_type, 1276 &htt_ring_id); 1277 1278 if (ret) 1279 goto err_free; 1280 1281 skb_put(skb, len); 1282 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1283 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1284 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1285 if (htt_ring_type == HTT_SW_TO_HW_RING || 1286 htt_ring_type == HTT_HW_TO_SW_RING) 1287 cmd->info0 |= 1288 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1289 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1290 else 1291 cmd->info0 |= 1292 le32_encode_bits(mac_id, 1293 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1294 cmd->info0 |= le32_encode_bits(htt_ring_id, 1295 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1296 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1297 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1298 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1299 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1300 1301 cmd->info1 |= 1302 le32_encode_bits(tx_buf_size, 1303 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1304 1305 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1306 cmd->info1 |= 1307 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1308 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1309 cmd->info1 |= 1310 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1311 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1312 cmd->info2 |= 1313 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1314 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1315 } 1316 1317 if (htt_tlv_filter->tx_mon_data_filter) { 1318 cmd->info1 |= 1319 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1320 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1321 cmd->info1 |= 1322 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1323 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1324 cmd->info2 |= 1325 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1326 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1327 } 1328 1329 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1330 cmd->info1 |= 1331 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1332 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1333 cmd->info1 |= 1334 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1335 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1336 cmd->info2 |= 1337 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1338 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1339 } 1340 1341 cmd->tlv_filter_mask_in0 = 1342 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1343 cmd->tlv_filter_mask_in1 = 1344 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1345 cmd->tlv_filter_mask_in2 = 1346 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1347 cmd->tlv_filter_mask_in3 = 1348 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1349 1350 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1351 if (ret) 1352 goto err_free; 1353 1354 return 0; 1355 1356 err_free: 1357 dev_kfree_skb_any(skb); 1358 return ret; 1359 } 1360