1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "debugfs.h" 11 #include "hw.h" 12 #include "peer.h" 13 #include "mac.h" 14 15 static enum hal_tcl_encap_type 16 ath12k_dp_tx_get_encap_type(struct ath12k_base *ab, struct sk_buff *skb) 17 { 18 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 19 20 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) 21 return HAL_TCL_ENCAP_TYPE_RAW; 22 23 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 24 return HAL_TCL_ENCAP_TYPE_ETHERNET; 25 26 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 27 } 28 29 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 30 { 31 struct ieee80211_hdr *hdr = (void *)skb->data; 32 u8 *qos_ctl; 33 34 if (!ieee80211_is_data_qos(hdr->frame_control)) 35 return; 36 37 qos_ctl = ieee80211_get_qos_ctl(hdr); 38 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 39 skb->data, (void *)qos_ctl - (void *)skb->data); 40 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 41 42 hdr = (void *)skb->data; 43 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 44 } 45 46 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 47 { 48 struct ieee80211_hdr *hdr = (void *)skb->data; 49 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 50 51 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 52 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 53 else if (!ieee80211_is_data_qos(hdr->frame_control)) 54 return HAL_DESC_REO_NON_QOS_TID; 55 else 56 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 57 } 58 59 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 60 { 61 switch (cipher) { 62 case WLAN_CIPHER_SUITE_WEP40: 63 return HAL_ENCRYPT_TYPE_WEP_40; 64 case WLAN_CIPHER_SUITE_WEP104: 65 return HAL_ENCRYPT_TYPE_WEP_104; 66 case WLAN_CIPHER_SUITE_TKIP: 67 return HAL_ENCRYPT_TYPE_TKIP_MIC; 68 case WLAN_CIPHER_SUITE_CCMP: 69 return HAL_ENCRYPT_TYPE_CCMP_128; 70 case WLAN_CIPHER_SUITE_CCMP_256: 71 return HAL_ENCRYPT_TYPE_CCMP_256; 72 case WLAN_CIPHER_SUITE_GCMP: 73 return HAL_ENCRYPT_TYPE_GCMP_128; 74 case WLAN_CIPHER_SUITE_GCMP_256: 75 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 76 default: 77 return HAL_ENCRYPT_TYPE_OPEN; 78 } 79 } 80 81 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 82 struct ath12k_tx_desc_info *tx_desc, 83 u8 pool_id) 84 { 85 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 86 tx_desc->skb_ext_desc = NULL; 87 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 88 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 89 } 90 91 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 92 u8 pool_id) 93 { 94 struct ath12k_tx_desc_info *desc; 95 96 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 97 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 98 struct ath12k_tx_desc_info, 99 list); 100 if (!desc) { 101 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 102 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 103 return NULL; 104 } 105 106 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 107 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 108 109 return desc; 110 } 111 112 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, 113 struct hal_tx_msdu_ext_desc *tcl_ext_cmd, 114 struct hal_tx_info *ti) 115 { 116 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 117 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 118 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 119 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 120 le32_encode_bits(ti->data_len, 121 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 122 123 tcl_ext_cmd->info1 |= le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 124 le32_encode_bits(ti->encap_type, 125 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 126 le32_encode_bits(ti->encrypt_type, 127 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 128 } 129 130 #define HTT_META_DATA_ALIGNMENT 0x8 131 132 static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len) 133 { 134 struct sk_buff *tail; 135 void *metadata; 136 137 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0)) 138 return NULL; 139 140 metadata = pskb_put(skb, tail, tail_len); 141 memset(metadata, 0, tail_len); 142 return metadata; 143 } 144 145 /* Preparing HTT Metadata when utilized with ext MSDU */ 146 static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb) 147 { 148 struct hal_tx_msdu_metadata *desc_ext; 149 u8 htt_desc_size; 150 /* Size rounded of multiple of 8 bytes */ 151 u8 htt_desc_size_aligned; 152 153 htt_desc_size = sizeof(struct hal_tx_msdu_metadata); 154 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); 155 156 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned); 157 if (!desc_ext) 158 return -ENOMEM; 159 160 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) | 161 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) | 162 le32_encode_bits(1, 163 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL); 164 165 return 0; 166 } 167 168 static void ath12k_dp_tx_move_payload(struct sk_buff *skb, 169 unsigned long delta, 170 bool head) 171 { 172 unsigned long len = skb->len; 173 174 if (head) { 175 skb_push(skb, delta); 176 memmove(skb->data, skb->data + delta, len); 177 skb_trim(skb, len); 178 } else { 179 skb_put(skb, delta); 180 memmove(skb->data + delta, skb->data, len); 181 skb_pull(skb, delta); 182 } 183 } 184 185 static int ath12k_dp_tx_align_payload(struct ath12k_base *ab, 186 struct sk_buff **pskb) 187 { 188 u32 iova_mask = ab->hw_params->iova_mask; 189 unsigned long offset, delta1, delta2; 190 struct sk_buff *skb2, *skb = *pskb; 191 unsigned int headroom = skb_headroom(skb); 192 int tailroom = skb_tailroom(skb); 193 int ret = 0; 194 195 offset = (unsigned long)skb->data & iova_mask; 196 delta1 = offset; 197 delta2 = iova_mask - offset + 1; 198 199 if (headroom >= delta1) { 200 ath12k_dp_tx_move_payload(skb, delta1, true); 201 } else if (tailroom >= delta2) { 202 ath12k_dp_tx_move_payload(skb, delta2, false); 203 } else { 204 skb2 = skb_realloc_headroom(skb, iova_mask); 205 if (!skb2) { 206 ret = -ENOMEM; 207 goto out; 208 } 209 210 dev_kfree_skb_any(skb); 211 212 offset = (unsigned long)skb2->data & iova_mask; 213 if (offset) 214 ath12k_dp_tx_move_payload(skb2, offset, true); 215 *pskb = skb2; 216 } 217 218 out: 219 return ret; 220 } 221 222 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif, 223 struct sk_buff *skb, bool gsn_valid, int mcbc_gsn, 224 bool is_mcast) 225 { 226 struct ath12k_base *ab = ar->ab; 227 struct ath12k_dp *dp = &ab->dp; 228 struct hal_tx_info ti = {0}; 229 struct ath12k_tx_desc_info *tx_desc; 230 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 231 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 232 struct hal_tcl_data_cmd *hal_tcl_desc; 233 struct hal_tx_msdu_ext_desc *msg; 234 struct sk_buff *skb_ext_desc = NULL; 235 struct hal_srng *tcl_ring; 236 struct ieee80211_hdr *hdr = (void *)skb->data; 237 struct ath12k_vif *ahvif = arvif->ahvif; 238 struct dp_tx_ring *tx_ring; 239 u8 pool_id; 240 u8 hal_ring_id; 241 int ret; 242 u8 ring_selector, ring_map = 0; 243 bool tcl_ring_retry; 244 bool msdu_ext_desc = false; 245 bool add_htt_metadata = false; 246 u32 iova_mask = ab->hw_params->iova_mask; 247 248 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 249 return -ESHUTDOWN; 250 251 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 252 !ieee80211_is_data(hdr->frame_control)) 253 return -EOPNOTSUPP; 254 255 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 256 257 /* Let the default ring selection be based on current processor 258 * number, where one of the 3 tcl rings are selected based on 259 * the smp_processor_id(). In case that ring 260 * is full/busy, we resort to other available rings. 261 * If all rings are full, we drop the packet. 262 * TODO: Add throttling logic when all rings are full 263 */ 264 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 265 266 tcl_ring_sel: 267 tcl_ring_retry = false; 268 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 269 270 ring_map |= BIT(ti.ring_id); 271 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 272 273 tx_ring = &dp->tx_ring[ti.ring_id]; 274 275 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 276 if (!tx_desc) 277 return -ENOMEM; 278 279 ti.bank_id = arvif->bank_id; 280 ti.meta_data_flags = arvif->tcl_metadata; 281 282 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 283 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 284 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 285 ti.encrypt_type = 286 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 287 288 if (ieee80211_has_protected(hdr->frame_control)) 289 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 290 } else { 291 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 292 } 293 294 msdu_ext_desc = true; 295 } 296 297 if (gsn_valid) { 298 /* Reset and Initialize meta_data_flags with Global Sequence 299 * Number (GSN) info. 300 */ 301 ti.meta_data_flags = 302 u32_encode_bits(HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM, 303 HTT_TCL_META_DATA_TYPE) | 304 u32_encode_bits(mcbc_gsn, HTT_TCL_META_DATA_GLOBAL_SEQ_NUM); 305 } 306 307 ti.encap_type = ath12k_dp_tx_get_encap_type(ab, skb); 308 ti.addr_search_flags = arvif->hal_addr_search_flags; 309 ti.search_type = arvif->search_type; 310 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 311 ti.pkt_offset = 0; 312 ti.lmac_id = ar->lmac_id; 313 314 ti.vdev_id = arvif->vdev_id; 315 if (gsn_valid) 316 ti.vdev_id += HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID; 317 318 ti.bss_ast_hash = arvif->ast_hash; 319 ti.bss_ast_idx = arvif->ast_idx; 320 ti.dscp_tid_tbl_idx = 0; 321 322 if (skb->ip_summed == CHECKSUM_PARTIAL && 323 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 324 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 325 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 326 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 327 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 328 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 329 } 330 331 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 332 333 ti.tid = ath12k_dp_tx_get_tid(skb); 334 335 switch (ti.encap_type) { 336 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 337 ath12k_dp_tx_encap_nwifi(skb); 338 break; 339 case HAL_TCL_ENCAP_TYPE_RAW: 340 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 341 ret = -EINVAL; 342 goto fail_remove_tx_buf; 343 } 344 break; 345 case HAL_TCL_ENCAP_TYPE_ETHERNET: 346 /* no need to encap */ 347 break; 348 case HAL_TCL_ENCAP_TYPE_802_3: 349 default: 350 /* TODO: Take care of other encap modes as well */ 351 ret = -EINVAL; 352 atomic_inc(&ab->device_stats.tx_err.misc_fail); 353 goto fail_remove_tx_buf; 354 } 355 356 if (iova_mask && 357 (unsigned long)skb->data & iova_mask) { 358 ret = ath12k_dp_tx_align_payload(ab, &skb); 359 if (ret) { 360 ath12k_warn(ab, "failed to align TX buffer %d\n", ret); 361 /* don't bail out, give original buffer 362 * a chance even unaligned. 363 */ 364 goto map; 365 } 366 367 /* hdr is pointing to a wrong place after alignment, 368 * so refresh it for later use. 369 */ 370 hdr = (void *)skb->data; 371 } 372 map: 373 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 374 if (dma_mapping_error(ab->dev, ti.paddr)) { 375 atomic_inc(&ab->device_stats.tx_err.misc_fail); 376 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 377 ret = -ENOMEM; 378 goto fail_remove_tx_buf; 379 } 380 381 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) && 382 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && 383 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) && 384 ieee80211_has_protected(hdr->frame_control)) { 385 /* Add metadata for sw encrypted vlan group traffic */ 386 add_htt_metadata = true; 387 msdu_ext_desc = true; 388 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW); 389 ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT; 390 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; 391 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 392 } 393 394 tx_desc->skb = skb; 395 tx_desc->mac_id = ar->pdev_idx; 396 ti.desc_id = tx_desc->desc_id; 397 ti.data_len = skb->len; 398 skb_cb->paddr = ti.paddr; 399 skb_cb->vif = ahvif->vif; 400 skb_cb->ar = ar; 401 402 if (msdu_ext_desc) { 403 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 404 if (!skb_ext_desc) { 405 ret = -ENOMEM; 406 goto fail_unmap_dma; 407 } 408 409 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 410 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 411 412 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 413 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 414 415 if (add_htt_metadata) { 416 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc); 417 if (ret < 0) { 418 ath12k_dbg(ab, ATH12K_DBG_DP_TX, 419 "Failed to add HTT meta data, dropping packet\n"); 420 goto fail_free_ext_skb; 421 } 422 } 423 424 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 425 skb_ext_desc->len, DMA_TO_DEVICE); 426 ret = dma_mapping_error(ab->dev, ti.paddr); 427 if (ret) 428 goto fail_free_ext_skb; 429 430 ti.data_len = skb_ext_desc->len; 431 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 432 433 skb_cb->paddr_ext_desc = ti.paddr; 434 tx_desc->skb_ext_desc = skb_ext_desc; 435 } 436 437 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 438 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 439 440 spin_lock_bh(&tcl_ring->lock); 441 442 ath12k_hal_srng_access_begin(ab, tcl_ring); 443 444 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 445 if (!hal_tcl_desc) { 446 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 447 * desc because the desc is directly enqueued onto hw queue. 448 */ 449 ath12k_hal_srng_access_end(ab, tcl_ring); 450 ab->device_stats.tx_err.desc_na[ti.ring_id]++; 451 spin_unlock_bh(&tcl_ring->lock); 452 ret = -ENOMEM; 453 454 /* Checking for available tcl descriptors in another ring in 455 * case of failure due to full tcl ring now, is better than 456 * checking this ring earlier for each pkt tx. 457 * Restart ring selection if some rings are not checked yet. 458 */ 459 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 460 ab->hw_params->tcl_ring_retry) { 461 tcl_ring_retry = true; 462 ring_selector++; 463 } 464 465 goto fail_unmap_dma_ext; 466 } 467 468 spin_lock_bh(&arvif->link_stats_lock); 469 arvif->link_stats.tx_encap_type[ti.encap_type]++; 470 arvif->link_stats.tx_encrypt_type[ti.encrypt_type]++; 471 arvif->link_stats.tx_desc_type[ti.type]++; 472 473 if (is_mcast) 474 arvif->link_stats.tx_bcast_mcast++; 475 else 476 arvif->link_stats.tx_enqueued++; 477 spin_unlock_bh(&arvif->link_stats_lock); 478 479 ab->device_stats.tx_enqueued[ti.ring_id]++; 480 481 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 482 483 ath12k_hal_srng_access_end(ab, tcl_ring); 484 485 spin_unlock_bh(&tcl_ring->lock); 486 487 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 488 skb->data, skb->len); 489 490 atomic_inc(&ar->dp.num_tx_pending); 491 492 return 0; 493 494 fail_unmap_dma_ext: 495 if (skb_cb->paddr_ext_desc) 496 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 497 skb_ext_desc->len, 498 DMA_TO_DEVICE); 499 fail_free_ext_skb: 500 kfree_skb(skb_ext_desc); 501 502 fail_unmap_dma: 503 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 504 505 fail_remove_tx_buf: 506 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 507 508 spin_lock_bh(&arvif->link_stats_lock); 509 arvif->link_stats.tx_dropped++; 510 spin_unlock_bh(&arvif->link_stats_lock); 511 512 if (tcl_ring_retry) 513 goto tcl_ring_sel; 514 515 return ret; 516 } 517 518 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 519 struct dp_tx_ring *tx_ring, 520 struct ath12k_tx_desc_params *desc_params) 521 { 522 struct ath12k *ar; 523 struct sk_buff *msdu = desc_params->skb; 524 struct ath12k_skb_cb *skb_cb; 525 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, desc_params->mac_id); 526 527 skb_cb = ATH12K_SKB_CB(msdu); 528 ar = ab->pdevs[pdev_id].ar; 529 530 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 531 if (skb_cb->paddr_ext_desc) { 532 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 533 desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 534 dev_kfree_skb_any(desc_params->skb_ext_desc); 535 } 536 537 ieee80211_free_txskb(ar->ah->hw, msdu); 538 539 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 540 wake_up(&ar->dp.tx_empty_waitq); 541 } 542 543 static void 544 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 545 struct ath12k_tx_desc_params *desc_params, 546 struct dp_tx_ring *tx_ring, 547 struct ath12k_dp_htt_wbm_tx_status *ts) 548 { 549 struct ieee80211_tx_info *info; 550 struct ath12k_link_vif *arvif; 551 struct ath12k_skb_cb *skb_cb; 552 struct ieee80211_vif *vif; 553 struct ath12k_vif *ahvif; 554 struct ath12k *ar; 555 struct sk_buff *msdu = desc_params->skb; 556 557 skb_cb = ATH12K_SKB_CB(msdu); 558 info = IEEE80211_SKB_CB(msdu); 559 560 ar = skb_cb->ar; 561 ab->device_stats.tx_completed[tx_ring->tcl_data_ring_id]++; 562 563 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 564 wake_up(&ar->dp.tx_empty_waitq); 565 566 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 567 if (skb_cb->paddr_ext_desc) { 568 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 569 desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 570 dev_kfree_skb_any(desc_params->skb_ext_desc); 571 } 572 573 vif = skb_cb->vif; 574 if (vif) { 575 ahvif = ath12k_vif_to_ahvif(vif); 576 rcu_read_lock(); 577 arvif = rcu_dereference(ahvif->link[skb_cb->link_id]); 578 if (arvif) { 579 spin_lock_bh(&arvif->link_stats_lock); 580 arvif->link_stats.tx_completed++; 581 spin_unlock_bh(&arvif->link_stats_lock); 582 } 583 rcu_read_unlock(); 584 } 585 586 memset(&info->status, 0, sizeof(info->status)); 587 588 if (ts->acked) { 589 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 590 info->flags |= IEEE80211_TX_STAT_ACK; 591 info->status.ack_signal = ts->ack_rssi; 592 593 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 594 ab->wmi_ab.svc_map)) 595 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 596 597 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 598 } else { 599 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 600 } 601 } 602 603 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 604 } 605 606 static void 607 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, void *desc, 608 struct dp_tx_ring *tx_ring, 609 struct ath12k_tx_desc_params *desc_params) 610 { 611 struct htt_tx_wbm_completion *status_desc; 612 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 613 enum hal_wbm_htt_tx_comp_status wbm_status; 614 615 status_desc = desc; 616 617 wbm_status = le32_get_bits(status_desc->info0, 618 HTT_TX_WBM_COMP_INFO0_STATUS); 619 ab->device_stats.fw_tx_status[wbm_status]++; 620 621 switch (wbm_status) { 622 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 623 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 624 ts.ack_rssi = le32_get_bits(status_desc->info2, 625 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 626 ath12k_dp_tx_htt_tx_complete_buf(ab, desc_params, tx_ring, &ts); 627 break; 628 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 629 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 630 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 631 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 632 case HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH: 633 ath12k_dp_tx_free_txbuf(ab, tx_ring, desc_params); 634 break; 635 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 636 /* This event is to be handled only when the driver decides to 637 * use WDS offload functionality. 638 */ 639 break; 640 default: 641 ath12k_warn(ab, "Unknown htt wbm tx status %d\n", wbm_status); 642 break; 643 } 644 } 645 646 static void ath12k_dp_tx_update_txcompl(struct ath12k *ar, struct hal_tx_status *ts) 647 { 648 struct ath12k_base *ab = ar->ab; 649 struct ath12k_peer *peer; 650 struct ieee80211_sta *sta; 651 struct ath12k_sta *ahsta; 652 struct ath12k_link_sta *arsta; 653 struct rate_info txrate = {0}; 654 u16 rate, ru_tones; 655 u8 rate_idx = 0; 656 int ret; 657 658 spin_lock_bh(&ab->base_lock); 659 peer = ath12k_peer_find_by_id(ab, ts->peer_id); 660 if (!peer || !peer->sta) { 661 ath12k_dbg(ab, ATH12K_DBG_DP_TX, 662 "failed to find the peer by id %u\n", ts->peer_id); 663 spin_unlock_bh(&ab->base_lock); 664 return; 665 } 666 sta = peer->sta; 667 ahsta = ath12k_sta_to_ahsta(sta); 668 arsta = &ahsta->deflink; 669 670 /* This is to prefer choose the real NSS value arsta->last_txrate.nss, 671 * if it is invalid, then choose the NSS value while assoc. 672 */ 673 if (arsta->last_txrate.nss) 674 txrate.nss = arsta->last_txrate.nss; 675 else 676 txrate.nss = arsta->peer_nss; 677 spin_unlock_bh(&ab->base_lock); 678 679 switch (ts->pkt_type) { 680 case HAL_TX_RATE_STATS_PKT_TYPE_11A: 681 case HAL_TX_RATE_STATS_PKT_TYPE_11B: 682 ret = ath12k_mac_hw_ratecode_to_legacy_rate(ts->mcs, 683 ts->pkt_type, 684 &rate_idx, 685 &rate); 686 if (ret < 0) { 687 ath12k_warn(ab, "Invalid tx legacy rate %d\n", ret); 688 return; 689 } 690 691 txrate.legacy = rate; 692 break; 693 case HAL_TX_RATE_STATS_PKT_TYPE_11N: 694 if (ts->mcs > ATH12K_HT_MCS_MAX) { 695 ath12k_warn(ab, "Invalid HT mcs index %d\n", ts->mcs); 696 return; 697 } 698 699 if (txrate.nss != 0) 700 txrate.mcs = ts->mcs + 8 * (txrate.nss - 1); 701 702 txrate.flags = RATE_INFO_FLAGS_MCS; 703 704 if (ts->sgi) 705 txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 706 break; 707 case HAL_TX_RATE_STATS_PKT_TYPE_11AC: 708 if (ts->mcs > ATH12K_VHT_MCS_MAX) { 709 ath12k_warn(ab, "Invalid VHT mcs index %d\n", ts->mcs); 710 return; 711 } 712 713 txrate.mcs = ts->mcs; 714 txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 715 716 if (ts->sgi) 717 txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 718 break; 719 case HAL_TX_RATE_STATS_PKT_TYPE_11AX: 720 if (ts->mcs > ATH12K_HE_MCS_MAX) { 721 ath12k_warn(ab, "Invalid HE mcs index %d\n", ts->mcs); 722 return; 723 } 724 725 txrate.mcs = ts->mcs; 726 txrate.flags = RATE_INFO_FLAGS_HE_MCS; 727 txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(ts->sgi); 728 break; 729 case HAL_TX_RATE_STATS_PKT_TYPE_11BE: 730 if (ts->mcs > ATH12K_EHT_MCS_MAX) { 731 ath12k_warn(ab, "Invalid EHT mcs index %d\n", ts->mcs); 732 return; 733 } 734 735 txrate.mcs = ts->mcs; 736 txrate.flags = RATE_INFO_FLAGS_EHT_MCS; 737 txrate.eht_gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(ts->sgi); 738 break; 739 default: 740 ath12k_warn(ab, "Invalid tx pkt type: %d\n", ts->pkt_type); 741 return; 742 } 743 744 txrate.bw = ath12k_mac_bw_to_mac80211_bw(ts->bw); 745 746 if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 747 txrate.bw = RATE_INFO_BW_HE_RU; 748 ru_tones = ath12k_mac_he_convert_tones_to_ru_tones(ts->tones); 749 txrate.he_ru_alloc = 750 ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 751 } 752 753 if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11BE) { 754 txrate.bw = RATE_INFO_BW_EHT_RU; 755 txrate.eht_ru_alloc = 756 ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(ts->tones); 757 } 758 759 spin_lock_bh(&ab->base_lock); 760 arsta->txrate = txrate; 761 spin_unlock_bh(&ab->base_lock); 762 } 763 764 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 765 struct ath12k_tx_desc_params *desc_params, 766 struct hal_tx_status *ts, 767 int ring) 768 { 769 struct ath12k_base *ab = ar->ab; 770 struct ath12k_hw *ah = ar->ah; 771 struct ieee80211_tx_info *info; 772 struct ath12k_link_vif *arvif; 773 struct ath12k_skb_cb *skb_cb; 774 struct ieee80211_vif *vif; 775 struct ath12k_vif *ahvif; 776 struct sk_buff *msdu = desc_params->skb; 777 778 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 779 /* Must not happen */ 780 return; 781 } 782 783 skb_cb = ATH12K_SKB_CB(msdu); 784 ab->device_stats.tx_completed[ring]++; 785 786 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 787 if (skb_cb->paddr_ext_desc) { 788 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 789 desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 790 dev_kfree_skb_any(desc_params->skb_ext_desc); 791 } 792 793 rcu_read_lock(); 794 795 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 796 ieee80211_free_txskb(ah->hw, msdu); 797 goto exit; 798 } 799 800 if (!skb_cb->vif) { 801 ieee80211_free_txskb(ah->hw, msdu); 802 goto exit; 803 } 804 805 vif = skb_cb->vif; 806 if (vif) { 807 ahvif = ath12k_vif_to_ahvif(vif); 808 arvif = rcu_dereference(ahvif->link[skb_cb->link_id]); 809 if (arvif) { 810 spin_lock_bh(&arvif->link_stats_lock); 811 arvif->link_stats.tx_completed++; 812 spin_unlock_bh(&arvif->link_stats_lock); 813 } 814 } 815 816 info = IEEE80211_SKB_CB(msdu); 817 memset(&info->status, 0, sizeof(info->status)); 818 819 /* skip tx rate update from ieee80211_status*/ 820 info->status.rates[0].idx = -1; 821 822 switch (ts->status) { 823 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED: 824 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 825 info->flags |= IEEE80211_TX_STAT_ACK; 826 info->status.ack_signal = ts->ack_rssi; 827 828 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 829 ab->wmi_ab.svc_map)) 830 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 831 832 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 833 } 834 break; 835 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: 836 if (info->flags & IEEE80211_TX_CTL_NO_ACK) { 837 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 838 break; 839 } 840 fallthrough; 841 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: 842 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: 843 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: 844 /* The failure status is due to internal firmware tx failure 845 * hence drop the frame; do not update the status of frame to 846 * the upper layer 847 */ 848 ieee80211_free_txskb(ah->hw, msdu); 849 goto exit; 850 default: 851 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", 852 ts->status); 853 break; 854 } 855 856 /* NOTE: Tx rate status reporting. Tx completion status does not have 857 * necessary information (for example nss) to build the tx rate. 858 * Might end up reporting it out-of-band from HTT stats. 859 */ 860 861 ath12k_dp_tx_update_txcompl(ar, ts); 862 863 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 864 865 exit: 866 rcu_read_unlock(); 867 } 868 869 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 870 struct hal_wbm_completion_ring_tx *desc, 871 struct hal_tx_status *ts) 872 { 873 u32 info0 = le32_to_cpu(desc->rate_stats.info0); 874 875 ts->buf_rel_source = 876 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 877 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 878 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 879 return; 880 881 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 882 return; 883 884 ts->status = le32_get_bits(desc->info0, 885 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 886 887 ts->ppdu_id = le32_get_bits(desc->info1, 888 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 889 890 ts->peer_id = le32_get_bits(desc->info3, HAL_WBM_COMPL_TX_INFO3_PEER_ID); 891 892 if (info0 & HAL_TX_RATE_STATS_INFO0_VALID) { 893 ts->pkt_type = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_PKT_TYPE); 894 ts->mcs = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_MCS); 895 ts->sgi = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_SGI); 896 ts->bw = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_BW); 897 ts->tones = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_TONES_IN_RU); 898 ts->ofdma = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_OFDMA_TX); 899 } 900 } 901 902 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 903 { 904 struct ath12k *ar; 905 struct ath12k_dp *dp = &ab->dp; 906 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 907 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 908 struct ath12k_tx_desc_info *tx_desc = NULL; 909 struct hal_tx_status ts = { 0 }; 910 struct ath12k_tx_desc_params desc_params; 911 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 912 struct hal_wbm_release_ring *desc; 913 u8 pdev_id; 914 u64 desc_va; 915 enum hal_wbm_rel_src_module buf_rel_source; 916 enum hal_wbm_tqm_rel_reason rel_status; 917 918 spin_lock_bh(&status_ring->lock); 919 920 ath12k_hal_srng_access_begin(ab, status_ring); 921 922 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 923 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 924 if (!desc) 925 break; 926 927 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 928 desc, sizeof(*desc)); 929 tx_ring->tx_status_head = 930 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 931 } 932 933 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 934 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 935 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 936 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 937 } 938 939 ath12k_hal_srng_access_end(ab, status_ring); 940 941 spin_unlock_bh(&status_ring->lock); 942 943 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 944 struct hal_wbm_completion_ring_tx *tx_status; 945 u32 desc_id; 946 947 tx_ring->tx_status_tail = 948 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 949 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 950 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 951 952 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 953 /* HW done cookie conversion */ 954 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 955 le32_to_cpu(tx_status->buf_va_lo)); 956 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 957 } else { 958 /* SW does cookie conversion to VA */ 959 desc_id = le32_get_bits(tx_status->buf_va_hi, 960 BUFFER_ADDR_INFO1_SW_COOKIE); 961 962 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 963 } 964 if (!tx_desc) { 965 ath12k_warn(ab, "unable to retrieve tx_desc!"); 966 continue; 967 } 968 969 desc_params.mac_id = tx_desc->mac_id; 970 desc_params.skb = tx_desc->skb; 971 desc_params.skb_ext_desc = tx_desc->skb_ext_desc; 972 973 /* Find the HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE value */ 974 buf_rel_source = le32_get_bits(tx_status->info0, 975 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE); 976 ab->device_stats.tx_wbm_rel_source[buf_rel_source]++; 977 978 rel_status = le32_get_bits(tx_status->info0, 979 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 980 ab->device_stats.tqm_rel_reason[rel_status]++; 981 982 /* Release descriptor as soon as extracting necessary info 983 * to reduce contention 984 */ 985 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 986 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 987 ath12k_dp_tx_process_htt_tx_complete(ab, (void *)tx_status, 988 tx_ring, &desc_params); 989 continue; 990 } 991 992 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, desc_params.mac_id); 993 ar = ab->pdevs[pdev_id].ar; 994 995 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 996 wake_up(&ar->dp.tx_empty_waitq); 997 998 ath12k_dp_tx_complete_msdu(ar, &desc_params, &ts, 999 tx_ring->tcl_data_ring_id); 1000 } 1001 } 1002 1003 static int 1004 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 1005 int mac_id, u32 ring_id, 1006 enum hal_ring_type ring_type, 1007 enum htt_srng_ring_type *htt_ring_type, 1008 enum htt_srng_ring_id *htt_ring_id) 1009 { 1010 int ret = 0; 1011 1012 switch (ring_type) { 1013 case HAL_RXDMA_BUF: 1014 /* for some targets, host fills rx buffer to fw and fw fills to 1015 * rxbuf ring for each rxdma 1016 */ 1017 if (!ab->hw_params->rx_mac_buf_ring) { 1018 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 1019 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 1020 ret = -EINVAL; 1021 } 1022 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 1023 *htt_ring_type = HTT_SW_TO_HW_RING; 1024 } else { 1025 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 1026 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 1027 *htt_ring_type = HTT_SW_TO_SW_RING; 1028 } else { 1029 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 1030 *htt_ring_type = HTT_SW_TO_HW_RING; 1031 } 1032 } 1033 break; 1034 case HAL_RXDMA_DST: 1035 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 1036 *htt_ring_type = HTT_HW_TO_SW_RING; 1037 break; 1038 case HAL_RXDMA_MONITOR_BUF: 1039 *htt_ring_id = HTT_RX_MON_HOST2MON_BUF_RING; 1040 *htt_ring_type = HTT_SW_TO_HW_RING; 1041 break; 1042 case HAL_RXDMA_MONITOR_STATUS: 1043 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 1044 *htt_ring_type = HTT_SW_TO_HW_RING; 1045 break; 1046 case HAL_RXDMA_MONITOR_DST: 1047 *htt_ring_id = HTT_RX_MON_MON2HOST_DEST_RING; 1048 *htt_ring_type = HTT_HW_TO_SW_RING; 1049 break; 1050 case HAL_RXDMA_MONITOR_DESC: 1051 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 1052 *htt_ring_type = HTT_SW_TO_HW_RING; 1053 break; 1054 default: 1055 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 1056 ret = -EINVAL; 1057 } 1058 return ret; 1059 } 1060 1061 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1062 int mac_id, enum hal_ring_type ring_type) 1063 { 1064 struct htt_srng_setup_cmd *cmd; 1065 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1066 struct hal_srng_params params; 1067 struct sk_buff *skb; 1068 u32 ring_entry_sz; 1069 int len = sizeof(*cmd); 1070 dma_addr_t hp_addr, tp_addr; 1071 enum htt_srng_ring_type htt_ring_type; 1072 enum htt_srng_ring_id htt_ring_id; 1073 int ret; 1074 1075 skb = ath12k_htc_alloc_skb(ab, len); 1076 if (!skb) 1077 return -ENOMEM; 1078 1079 memset(¶ms, 0, sizeof(params)); 1080 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1081 1082 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 1083 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 1084 1085 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1086 ring_type, &htt_ring_type, 1087 &htt_ring_id); 1088 if (ret) 1089 goto err_free; 1090 1091 skb_put(skb, len); 1092 cmd = (struct htt_srng_setup_cmd *)skb->data; 1093 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 1094 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 1095 if (htt_ring_type == HTT_SW_TO_HW_RING || 1096 htt_ring_type == HTT_HW_TO_SW_RING) 1097 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 1098 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 1099 else 1100 cmd->info0 |= le32_encode_bits(mac_id, 1101 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 1102 cmd->info0 |= le32_encode_bits(htt_ring_type, 1103 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 1104 cmd->info0 |= le32_encode_bits(htt_ring_id, 1105 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 1106 1107 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 1108 HAL_ADDR_LSB_REG_MASK); 1109 1110 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 1111 HAL_ADDR_MSB_REG_SHIFT); 1112 1113 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 1114 if (ret < 0) 1115 goto err_free; 1116 1117 ring_entry_sz = ret; 1118 1119 ring_entry_sz >>= 2; 1120 cmd->info1 = le32_encode_bits(ring_entry_sz, 1121 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 1122 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 1123 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 1124 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1125 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 1126 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1127 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 1128 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 1129 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 1130 if (htt_ring_type == HTT_SW_TO_HW_RING) 1131 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 1132 1133 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 1134 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 1135 1136 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 1137 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 1138 1139 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 1140 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 1141 cmd->msi_data = cpu_to_le32(params.msi_data); 1142 1143 cmd->intr_info = 1144 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 1145 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 1146 cmd->intr_info |= 1147 le32_encode_bits(params.intr_timer_thres_us >> 3, 1148 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 1149 1150 cmd->info2 = 0; 1151 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 1152 cmd->info2 = le32_encode_bits(params.low_threshold, 1153 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 1154 } 1155 1156 ath12k_dbg(ab, ATH12K_DBG_HAL, 1157 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 1158 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 1159 cmd->msi_data); 1160 1161 ath12k_dbg(ab, ATH12K_DBG_HAL, 1162 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 1163 ring_id, ring_type, cmd->intr_info, cmd->info2); 1164 1165 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1166 if (ret) 1167 goto err_free; 1168 1169 return 0; 1170 1171 err_free: 1172 dev_kfree_skb_any(skb); 1173 1174 return ret; 1175 } 1176 1177 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 1178 1179 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 1180 { 1181 struct ath12k_dp *dp = &ab->dp; 1182 struct sk_buff *skb; 1183 struct htt_ver_req_cmd *cmd; 1184 int len = sizeof(*cmd); 1185 int ret; 1186 1187 init_completion(&dp->htt_tgt_version_received); 1188 1189 skb = ath12k_htc_alloc_skb(ab, len); 1190 if (!skb) 1191 return -ENOMEM; 1192 1193 skb_put(skb, len); 1194 cmd = (struct htt_ver_req_cmd *)skb->data; 1195 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 1196 HTT_OPTION_TAG); 1197 1198 cmd->tcl_metadata_version = le32_encode_bits(HTT_TAG_TCL_METADATA_VERSION, 1199 HTT_OPTION_TAG) | 1200 le32_encode_bits(HTT_TCL_METADATA_VER_SZ, 1201 HTT_OPTION_LEN) | 1202 le32_encode_bits(HTT_OPTION_TCL_METADATA_VER_V2, 1203 HTT_OPTION_VALUE); 1204 1205 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1206 if (ret) { 1207 dev_kfree_skb_any(skb); 1208 return ret; 1209 } 1210 1211 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 1212 HTT_TARGET_VERSION_TIMEOUT_HZ); 1213 if (ret == 0) { 1214 ath12k_warn(ab, "htt target version request timed out\n"); 1215 return -ETIMEDOUT; 1216 } 1217 1218 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 1219 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 1220 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 1221 return -EOPNOTSUPP; 1222 } 1223 1224 return 0; 1225 } 1226 1227 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 1228 { 1229 struct ath12k_base *ab = ar->ab; 1230 struct ath12k_dp *dp = &ab->dp; 1231 struct sk_buff *skb; 1232 struct htt_ppdu_stats_cfg_cmd *cmd; 1233 int len = sizeof(*cmd); 1234 u8 pdev_mask; 1235 int ret; 1236 int i; 1237 1238 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1239 skb = ath12k_htc_alloc_skb(ab, len); 1240 if (!skb) 1241 return -ENOMEM; 1242 1243 skb_put(skb, len); 1244 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 1245 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 1246 HTT_PPDU_STATS_CFG_MSG_TYPE); 1247 1248 pdev_mask = 1 << (i + 1); 1249 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 1250 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 1251 1252 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1253 if (ret) { 1254 dev_kfree_skb_any(skb); 1255 return ret; 1256 } 1257 } 1258 1259 return 0; 1260 } 1261 1262 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1263 int mac_id, enum hal_ring_type ring_type, 1264 int rx_buf_size, 1265 struct htt_rx_ring_tlv_filter *tlv_filter) 1266 { 1267 struct htt_rx_ring_selection_cfg_cmd *cmd; 1268 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1269 struct hal_srng_params params; 1270 struct sk_buff *skb; 1271 int len = sizeof(*cmd); 1272 enum htt_srng_ring_type htt_ring_type; 1273 enum htt_srng_ring_id htt_ring_id; 1274 int ret; 1275 1276 skb = ath12k_htc_alloc_skb(ab, len); 1277 if (!skb) 1278 return -ENOMEM; 1279 1280 memset(¶ms, 0, sizeof(params)); 1281 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1282 1283 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1284 ring_type, &htt_ring_type, 1285 &htt_ring_id); 1286 if (ret) 1287 goto err_free; 1288 1289 skb_put(skb, len); 1290 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 1291 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 1292 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1293 if (htt_ring_type == HTT_SW_TO_HW_RING || 1294 htt_ring_type == HTT_HW_TO_SW_RING) 1295 cmd->info0 |= 1296 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1297 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1298 else 1299 cmd->info0 |= 1300 le32_encode_bits(mac_id, 1301 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1302 cmd->info0 |= le32_encode_bits(htt_ring_id, 1303 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1304 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1305 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 1306 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1307 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 1308 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 1309 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID); 1310 cmd->info0 |= 1311 le32_encode_bits(tlv_filter->drop_threshold_valid, 1312 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL); 1313 cmd->info0 |= le32_encode_bits(!tlv_filter->rxmon_disable, 1314 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON); 1315 1316 cmd->info1 = le32_encode_bits(rx_buf_size, 1317 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 1318 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_mgmt, 1319 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1320 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_ctrl, 1321 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1322 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_data, 1323 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1324 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 1325 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 1326 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 1327 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 1328 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 1329 1330 cmd->info2 = le32_encode_bits(tlv_filter->rx_drop_threshold, 1331 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD); 1332 cmd->info2 |= 1333 le32_encode_bits(tlv_filter->enable_log_mgmt_type, 1334 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE); 1335 cmd->info2 |= 1336 le32_encode_bits(tlv_filter->enable_log_ctrl_type, 1337 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE); 1338 cmd->info2 |= 1339 le32_encode_bits(tlv_filter->enable_log_data_type, 1340 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE); 1341 1342 cmd->info3 = 1343 le32_encode_bits(tlv_filter->enable_rx_tlv_offset, 1344 HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET); 1345 cmd->info3 |= 1346 le32_encode_bits(tlv_filter->rx_tlv_offset, 1347 HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET); 1348 1349 if (tlv_filter->offset_valid) { 1350 cmd->rx_packet_offset = 1351 le32_encode_bits(tlv_filter->rx_packet_offset, 1352 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 1353 1354 cmd->rx_packet_offset |= 1355 le32_encode_bits(tlv_filter->rx_header_offset, 1356 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 1357 1358 cmd->rx_mpdu_offset = 1359 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 1360 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 1361 1362 cmd->rx_mpdu_offset |= 1363 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 1364 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 1365 1366 cmd->rx_msdu_offset = 1367 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 1368 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 1369 1370 cmd->rx_msdu_offset |= 1371 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 1372 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 1373 1374 cmd->rx_attn_offset = 1375 le32_encode_bits(tlv_filter->rx_attn_offset, 1376 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 1377 } 1378 1379 if (tlv_filter->rx_mpdu_start_wmask > 0 && 1380 tlv_filter->rx_msdu_end_wmask > 0) { 1381 cmd->info2 |= 1382 le32_encode_bits(true, 1383 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET); 1384 cmd->rx_mpdu_start_end_mask = 1385 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask, 1386 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK); 1387 /* mpdu_end is not used for any hardwares so far 1388 * please assign it in future if any chip is 1389 * using through hal ops 1390 */ 1391 cmd->rx_mpdu_start_end_mask |= 1392 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask, 1393 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK); 1394 cmd->rx_msdu_end_word_mask = 1395 le32_encode_bits(tlv_filter->rx_msdu_end_wmask, 1396 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK); 1397 } 1398 1399 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1400 if (ret) 1401 goto err_free; 1402 1403 return 0; 1404 1405 err_free: 1406 dev_kfree_skb_any(skb); 1407 1408 return ret; 1409 } 1410 1411 int 1412 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 1413 struct htt_ext_stats_cfg_params *cfg_params, 1414 u64 cookie) 1415 { 1416 struct ath12k_base *ab = ar->ab; 1417 struct ath12k_dp *dp = &ab->dp; 1418 struct sk_buff *skb; 1419 struct htt_ext_stats_cfg_cmd *cmd; 1420 int len = sizeof(*cmd); 1421 int ret; 1422 u32 pdev_id; 1423 1424 skb = ath12k_htc_alloc_skb(ab, len); 1425 if (!skb) 1426 return -ENOMEM; 1427 1428 skb_put(skb, len); 1429 1430 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1431 memset(cmd, 0, sizeof(*cmd)); 1432 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1433 1434 pdev_id = ath12k_mac_get_target_pdev_id(ar); 1435 cmd->hdr.pdev_mask = 1 << pdev_id; 1436 1437 cmd->hdr.stats_type = type; 1438 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 1439 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 1440 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 1441 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1442 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1443 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1444 1445 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1446 if (ret) { 1447 ath12k_warn(ab, "failed to send htt type stats request: %d", 1448 ret); 1449 dev_kfree_skb_any(skb); 1450 return ret; 1451 } 1452 1453 return 0; 1454 } 1455 1456 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1457 { 1458 struct ath12k_base *ab = ar->ab; 1459 int ret; 1460 1461 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset); 1462 if (ret) { 1463 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1464 return ret; 1465 } 1466 1467 return 0; 1468 } 1469 1470 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1471 { 1472 struct ath12k_base *ab = ar->ab; 1473 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1474 int ret, ring_id, i; 1475 1476 tlv_filter.offset_valid = false; 1477 1478 if (!reset) { 1479 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING; 1480 1481 tlv_filter.drop_threshold_valid = true; 1482 tlv_filter.rx_drop_threshold = HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE; 1483 1484 tlv_filter.enable_log_mgmt_type = true; 1485 tlv_filter.enable_log_ctrl_type = true; 1486 tlv_filter.enable_log_data_type = true; 1487 1488 tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH; 1489 tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH; 1490 tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH; 1491 1492 tlv_filter.enable_rx_tlv_offset = true; 1493 tlv_filter.rx_tlv_offset = HTT_RX_RING_PKT_TLV_OFFSET; 1494 1495 tlv_filter.pkt_filter_flags0 = 1496 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1497 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1498 tlv_filter.pkt_filter_flags1 = 1499 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1500 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1501 tlv_filter.pkt_filter_flags2 = 1502 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1503 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1504 tlv_filter.pkt_filter_flags3 = 1505 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1506 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1507 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1508 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1509 } else { 1510 tlv_filter = ath12k_mac_mon_status_filter_default; 1511 1512 if (ath12k_debugfs_is_extd_rx_stats_enabled(ar)) 1513 tlv_filter.rx_filter = ath12k_debugfs_rx_filter(ar); 1514 } 1515 1516 if (ab->hw_params->rxdma1_enable) { 1517 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1518 ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; 1519 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1520 ar->dp.mac_id + i, 1521 HAL_RXDMA_MONITOR_DST, 1522 DP_RXDMA_REFILL_RING_SIZE, 1523 &tlv_filter); 1524 if (ret) { 1525 ath12k_err(ab, 1526 "failed to setup filter for monitor buf %d\n", 1527 ret); 1528 return ret; 1529 } 1530 } 1531 return 0; 1532 } 1533 1534 if (!reset) { 1535 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1536 ring_id = ab->dp.rx_mac_buf_ring[i].ring_id; 1537 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1538 i, 1539 HAL_RXDMA_BUF, 1540 DP_RXDMA_REFILL_RING_SIZE, 1541 &tlv_filter); 1542 if (ret) { 1543 ath12k_err(ab, 1544 "failed to setup filter for mon rx buf %d\n", 1545 ret); 1546 return ret; 1547 } 1548 } 1549 } 1550 1551 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1552 ring_id = ab->dp.rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1553 if (!reset) { 1554 tlv_filter.rx_filter = 1555 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1556 } 1557 1558 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1559 i, 1560 HAL_RXDMA_MONITOR_STATUS, 1561 RX_MON_STATUS_BUF_SIZE, 1562 &tlv_filter); 1563 if (ret) { 1564 ath12k_err(ab, 1565 "failed to setup filter for mon status buf %d\n", 1566 ret); 1567 return ret; 1568 } 1569 } 1570 1571 return 0; 1572 } 1573 1574 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1575 int mac_id, enum hal_ring_type ring_type, 1576 int tx_buf_size, 1577 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1578 { 1579 struct htt_tx_ring_selection_cfg_cmd *cmd; 1580 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1581 struct hal_srng_params params; 1582 struct sk_buff *skb; 1583 int len = sizeof(*cmd); 1584 enum htt_srng_ring_type htt_ring_type; 1585 enum htt_srng_ring_id htt_ring_id; 1586 int ret; 1587 1588 skb = ath12k_htc_alloc_skb(ab, len); 1589 if (!skb) 1590 return -ENOMEM; 1591 1592 memset(¶ms, 0, sizeof(params)); 1593 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1594 1595 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1596 ring_type, &htt_ring_type, 1597 &htt_ring_id); 1598 1599 if (ret) 1600 goto err_free; 1601 1602 skb_put(skb, len); 1603 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1604 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1605 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1606 if (htt_ring_type == HTT_SW_TO_HW_RING || 1607 htt_ring_type == HTT_HW_TO_SW_RING) 1608 cmd->info0 |= 1609 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1610 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1611 else 1612 cmd->info0 |= 1613 le32_encode_bits(mac_id, 1614 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1615 cmd->info0 |= le32_encode_bits(htt_ring_id, 1616 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1617 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1618 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1619 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1620 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1621 1622 cmd->info1 |= 1623 le32_encode_bits(tx_buf_size, 1624 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1625 1626 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1627 cmd->info1 |= 1628 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1629 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1630 cmd->info1 |= 1631 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1632 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1633 cmd->info2 |= 1634 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1635 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1636 } 1637 1638 if (htt_tlv_filter->tx_mon_data_filter) { 1639 cmd->info1 |= 1640 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1641 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1642 cmd->info1 |= 1643 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1644 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1645 cmd->info2 |= 1646 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1647 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1648 } 1649 1650 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1651 cmd->info1 |= 1652 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1653 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1654 cmd->info1 |= 1655 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1656 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1657 cmd->info2 |= 1658 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1659 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1660 } 1661 1662 cmd->tlv_filter_mask_in0 = 1663 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1664 cmd->tlv_filter_mask_in1 = 1665 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1666 cmd->tlv_filter_mask_in2 = 1667 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1668 cmd->tlv_filter_mask_in3 = 1669 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1670 1671 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1672 if (ret) 1673 goto err_free; 1674 1675 return 0; 1676 1677 err_free: 1678 dev_kfree_skb_any(skb); 1679 return ret; 1680 } 1681