1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 21 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22 23 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 24 struct hal_rx_desc *desc) 25 { 26 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) 27 return HAL_ENCRYPT_TYPE_OPEN; 28 29 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); 30 } 31 32 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 33 struct hal_rx_desc *desc) 34 { 35 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); 36 } 37 38 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 39 struct hal_rx_desc *desc) 40 { 41 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); 42 } 43 44 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 45 struct hal_rx_desc *desc) 46 { 47 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 48 } 49 50 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 51 struct hal_rx_desc *desc) 52 { 53 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); 54 } 55 56 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 57 struct sk_buff *skb) 58 { 59 struct ieee80211_hdr *hdr; 60 61 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 62 return ieee80211_has_morefrags(hdr->frame_control); 63 } 64 65 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 66 struct sk_buff *skb) 67 { 68 struct ieee80211_hdr *hdr; 69 70 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 71 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 72 } 73 74 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 75 struct hal_rx_desc *desc) 76 { 77 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc); 78 } 79 80 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 81 struct hal_rx_desc *desc) 82 { 83 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc); 84 } 85 86 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 87 struct hal_rx_desc *desc) 88 { 89 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc); 90 } 91 92 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 93 struct hal_rx_desc *desc) 94 { 95 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc); 96 } 97 98 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 99 struct hal_rx_desc *desc) 100 { 101 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc); 102 } 103 104 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 105 struct hal_rx_desc *desc) 106 { 107 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc); 108 } 109 110 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 111 struct hal_rx_desc *desc) 112 { 113 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc); 114 } 115 116 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 117 struct hal_rx_desc *desc) 118 { 119 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc); 120 } 121 122 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 123 struct hal_rx_desc *desc) 124 { 125 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc); 126 } 127 128 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 129 struct hal_rx_desc *desc) 130 { 131 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc); 132 } 133 134 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 135 struct hal_rx_desc *desc) 136 { 137 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc); 138 } 139 140 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 141 struct hal_rx_desc *desc) 142 { 143 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc); 144 } 145 146 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 147 struct hal_rx_desc *desc) 148 { 149 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc)); 150 } 151 152 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 153 struct hal_rx_desc *desc) 154 { 155 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc); 156 } 157 158 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 159 struct hal_rx_desc *desc) 160 { 161 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc); 162 } 163 164 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 165 struct hal_rx_desc *desc) 166 { 167 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc); 168 } 169 170 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 171 struct hal_rx_desc *desc) 172 { 173 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc); 174 } 175 176 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 177 struct hal_rx_desc *desc) 178 { 179 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc); 180 } 181 182 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 183 struct hal_rx_desc *fdesc, 184 struct hal_rx_desc *ldesc) 185 { 186 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 187 } 188 189 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 190 struct hal_rx_desc *desc, 191 u16 len) 192 { 193 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len); 194 } 195 196 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 197 struct hal_rx_desc *desc) 198 { 199 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 200 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc)); 201 } 202 203 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 204 struct hal_rx_desc *desc) 205 { 206 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc); 207 } 208 209 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 210 struct hal_rx_desc *desc) 211 { 212 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc); 213 } 214 215 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 216 struct hal_rx_desc *desc, 217 struct ieee80211_hdr *hdr) 218 { 219 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr); 220 } 221 222 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 223 struct hal_rx_desc *desc, 224 u8 *crypto_hdr, 225 enum hal_encrypt_type enctype) 226 { 227 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 228 } 229 230 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab, 231 struct hal_rx_desc *desc) 232 { 233 return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc); 234 } 235 236 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, 237 struct hal_rx_desc *desc) 238 { 239 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc); 240 } 241 242 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list) 243 { 244 struct sk_buff *skb; 245 246 while ((skb = __skb_dequeue(skb_list))) 247 dev_kfree_skb_any(skb); 248 } 249 250 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 251 struct list_head *head, 252 size_t count) 253 { 254 struct list_head *cur; 255 struct ath12k_rx_desc_info *rx_desc; 256 size_t nodes = 0; 257 258 if (!count) { 259 INIT_LIST_HEAD(list); 260 goto out; 261 } 262 263 list_for_each(cur, head) { 264 if (!count) 265 break; 266 267 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 268 rx_desc->in_use = true; 269 270 count--; 271 nodes++; 272 } 273 274 list_cut_before(list, head, cur); 275 out: 276 return nodes; 277 } 278 279 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 280 struct list_head *used_list) 281 { 282 struct ath12k_rx_desc_info *rx_desc, *safe; 283 284 /* Reset the use flag */ 285 list_for_each_entry_safe(rx_desc, safe, used_list, list) 286 rx_desc->in_use = false; 287 288 spin_lock_bh(&dp->rx_desc_lock); 289 list_splice_tail(used_list, &dp->rx_desc_free_list); 290 spin_unlock_bh(&dp->rx_desc_lock); 291 } 292 293 /* Returns number of Rx buffers replenished */ 294 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, 295 struct dp_rxdma_ring *rx_ring, 296 struct list_head *used_list, 297 int req_entries) 298 { 299 struct ath12k_buffer_addr *desc; 300 struct hal_srng *srng; 301 struct sk_buff *skb; 302 int num_free; 303 int num_remain; 304 u32 cookie; 305 dma_addr_t paddr; 306 struct ath12k_dp *dp = &ab->dp; 307 struct ath12k_rx_desc_info *rx_desc; 308 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; 309 310 req_entries = min(req_entries, rx_ring->bufs_max); 311 312 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 313 314 spin_lock_bh(&srng->lock); 315 316 ath12k_hal_srng_access_begin(ab, srng); 317 318 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 319 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 320 req_entries = num_free; 321 322 req_entries = min(num_free, req_entries); 323 num_remain = req_entries; 324 325 if (!num_remain) 326 goto out; 327 328 /* Get the descriptor from free list */ 329 if (list_empty(used_list)) { 330 spin_lock_bh(&dp->rx_desc_lock); 331 req_entries = ath12k_dp_list_cut_nodes(used_list, 332 &dp->rx_desc_free_list, 333 num_remain); 334 spin_unlock_bh(&dp->rx_desc_lock); 335 num_remain = req_entries; 336 } 337 338 while (num_remain > 0) { 339 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 340 DP_RX_BUFFER_ALIGN_SIZE); 341 if (!skb) 342 break; 343 344 if (!IS_ALIGNED((unsigned long)skb->data, 345 DP_RX_BUFFER_ALIGN_SIZE)) { 346 skb_pull(skb, 347 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 348 skb->data); 349 } 350 351 paddr = dma_map_single(ab->dev, skb->data, 352 skb->len + skb_tailroom(skb), 353 DMA_FROM_DEVICE); 354 if (dma_mapping_error(ab->dev, paddr)) 355 goto fail_free_skb; 356 357 rx_desc = list_first_entry_or_null(used_list, 358 struct ath12k_rx_desc_info, 359 list); 360 if (!rx_desc) 361 goto fail_dma_unmap; 362 363 rx_desc->skb = skb; 364 cookie = rx_desc->cookie; 365 366 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 367 if (!desc) 368 goto fail_dma_unmap; 369 370 list_del(&rx_desc->list); 371 ATH12K_SKB_RXCB(skb)->paddr = paddr; 372 373 num_remain--; 374 375 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 376 } 377 378 goto out; 379 380 fail_dma_unmap: 381 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 382 DMA_FROM_DEVICE); 383 fail_free_skb: 384 dev_kfree_skb_any(skb); 385 out: 386 ath12k_hal_srng_access_end(ab, srng); 387 388 if (!list_empty(used_list)) 389 ath12k_dp_rx_enqueue_free(dp, used_list); 390 391 spin_unlock_bh(&srng->lock); 392 393 return req_entries - num_remain; 394 } 395 396 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 397 struct dp_rxdma_mon_ring *rx_ring) 398 { 399 struct sk_buff *skb; 400 int buf_id; 401 402 spin_lock_bh(&rx_ring->idr_lock); 403 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 404 idr_remove(&rx_ring->bufs_idr, buf_id); 405 /* TODO: Understand where internal driver does this dma_unmap 406 * of rxdma_buffer. 407 */ 408 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 409 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 410 dev_kfree_skb_any(skb); 411 } 412 413 idr_destroy(&rx_ring->bufs_idr); 414 spin_unlock_bh(&rx_ring->idr_lock); 415 416 return 0; 417 } 418 419 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 420 { 421 struct ath12k_dp *dp = &ab->dp; 422 423 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 424 425 return 0; 426 } 427 428 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 429 struct dp_rxdma_mon_ring *rx_ring, 430 u32 ringtype) 431 { 432 int num_entries; 433 434 num_entries = rx_ring->refill_buf_ring.size / 435 ath12k_hal_srng_get_entrysize(ab, ringtype); 436 437 rx_ring->bufs_max = num_entries; 438 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 439 440 return 0; 441 } 442 443 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 444 struct dp_rxdma_ring *rx_ring) 445 { 446 LIST_HEAD(list); 447 448 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 449 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 450 451 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 452 453 return 0; 454 } 455 456 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 457 { 458 struct ath12k_dp *dp = &ab->dp; 459 int ret; 460 461 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 462 if (ret) { 463 ath12k_warn(ab, 464 "failed to setup HAL_RXDMA_BUF\n"); 465 return ret; 466 } 467 468 if (ab->hw_params->rxdma1_enable) { 469 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 470 &dp->rxdma_mon_buf_ring, 471 HAL_RXDMA_MONITOR_BUF); 472 if (ret) { 473 ath12k_warn(ab, 474 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 475 return ret; 476 } 477 } 478 479 return 0; 480 } 481 482 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 483 { 484 struct ath12k_pdev_dp *dp = &ar->dp; 485 struct ath12k_base *ab = ar->ab; 486 int i; 487 488 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 489 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 490 } 491 492 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 493 { 494 struct ath12k_dp *dp = &ab->dp; 495 int i; 496 497 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 498 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 499 } 500 501 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 502 { 503 struct ath12k_dp *dp = &ab->dp; 504 int ret; 505 int i; 506 507 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 508 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 509 HAL_REO_DST, i, 0, 510 DP_REO_DST_RING_SIZE); 511 if (ret) { 512 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 513 goto err_reo_cleanup; 514 } 515 } 516 517 return 0; 518 519 err_reo_cleanup: 520 ath12k_dp_rx_pdev_reo_cleanup(ab); 521 522 return ret; 523 } 524 525 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 526 { 527 struct ath12k_pdev_dp *dp = &ar->dp; 528 struct ath12k_base *ab = ar->ab; 529 int i; 530 int ret; 531 u32 mac_id = dp->mac_id; 532 533 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 534 ret = ath12k_dp_srng_setup(ar->ab, 535 &dp->rxdma_mon_dst_ring[i], 536 HAL_RXDMA_MONITOR_DST, 537 0, mac_id + i, 538 DP_RXDMA_MONITOR_DST_RING_SIZE); 539 if (ret) { 540 ath12k_warn(ar->ab, 541 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 542 return ret; 543 } 544 } 545 546 return 0; 547 } 548 549 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 550 { 551 struct ath12k_dp *dp = &ab->dp; 552 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 553 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 554 555 spin_lock_bh(&dp->reo_cmd_lock); 556 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 557 list_del(&cmd->list); 558 dma_unmap_single(ab->dev, cmd->data.paddr, 559 cmd->data.size, DMA_BIDIRECTIONAL); 560 kfree(cmd->data.vaddr); 561 kfree(cmd); 562 } 563 564 list_for_each_entry_safe(cmd_cache, tmp_cache, 565 &dp->reo_cmd_cache_flush_list, list) { 566 list_del(&cmd_cache->list); 567 dp->reo_cmd_cache_flush_count--; 568 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 569 cmd_cache->data.size, DMA_BIDIRECTIONAL); 570 kfree(cmd_cache->data.vaddr); 571 kfree(cmd_cache); 572 } 573 spin_unlock_bh(&dp->reo_cmd_lock); 574 } 575 576 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 577 enum hal_reo_cmd_status status) 578 { 579 struct ath12k_dp_rx_tid *rx_tid = ctx; 580 581 if (status != HAL_REO_CMD_SUCCESS) 582 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 583 rx_tid->tid, status); 584 585 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 586 DMA_BIDIRECTIONAL); 587 kfree(rx_tid->vaddr); 588 rx_tid->vaddr = NULL; 589 } 590 591 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 592 enum hal_reo_cmd_type type, 593 struct ath12k_hal_reo_cmd *cmd, 594 void (*cb)(struct ath12k_dp *dp, void *ctx, 595 enum hal_reo_cmd_status status)) 596 { 597 struct ath12k_dp *dp = &ab->dp; 598 struct ath12k_dp_rx_reo_cmd *dp_cmd; 599 struct hal_srng *cmd_ring; 600 int cmd_num; 601 602 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 603 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 604 605 /* cmd_num should start from 1, during failure return the error code */ 606 if (cmd_num < 0) 607 return cmd_num; 608 609 /* reo cmd ring descriptors has cmd_num starting from 1 */ 610 if (cmd_num == 0) 611 return -EINVAL; 612 613 if (!cb) 614 return 0; 615 616 /* Can this be optimized so that we keep the pending command list only 617 * for tid delete command to free up the resource on the command status 618 * indication? 619 */ 620 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 621 622 if (!dp_cmd) 623 return -ENOMEM; 624 625 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 626 dp_cmd->cmd_num = cmd_num; 627 dp_cmd->handler = cb; 628 629 spin_lock_bh(&dp->reo_cmd_lock); 630 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 631 spin_unlock_bh(&dp->reo_cmd_lock); 632 633 return 0; 634 } 635 636 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 637 struct ath12k_dp_rx_tid *rx_tid) 638 { 639 struct ath12k_hal_reo_cmd cmd = {0}; 640 unsigned long tot_desc_sz, desc_sz; 641 int ret; 642 643 tot_desc_sz = rx_tid->size; 644 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 645 646 while (tot_desc_sz > desc_sz) { 647 tot_desc_sz -= desc_sz; 648 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 649 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 650 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 651 HAL_REO_CMD_FLUSH_CACHE, &cmd, 652 NULL); 653 if (ret) 654 ath12k_warn(ab, 655 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 656 rx_tid->tid, ret); 657 } 658 659 memset(&cmd, 0, sizeof(cmd)); 660 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 661 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 662 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 663 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 664 HAL_REO_CMD_FLUSH_CACHE, 665 &cmd, ath12k_dp_reo_cmd_free); 666 if (ret) { 667 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 668 rx_tid->tid, ret); 669 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 670 DMA_BIDIRECTIONAL); 671 kfree(rx_tid->vaddr); 672 rx_tid->vaddr = NULL; 673 } 674 } 675 676 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 677 enum hal_reo_cmd_status status) 678 { 679 struct ath12k_base *ab = dp->ab; 680 struct ath12k_dp_rx_tid *rx_tid = ctx; 681 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 682 683 if (status == HAL_REO_CMD_DRAIN) { 684 goto free_desc; 685 } else if (status != HAL_REO_CMD_SUCCESS) { 686 /* Shouldn't happen! Cleanup in case of other failure? */ 687 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 688 rx_tid->tid, status); 689 return; 690 } 691 692 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 693 if (!elem) 694 goto free_desc; 695 696 elem->ts = jiffies; 697 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 698 699 spin_lock_bh(&dp->reo_cmd_lock); 700 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 701 dp->reo_cmd_cache_flush_count++; 702 703 /* Flush and invalidate aged REO desc from HW cache */ 704 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 705 list) { 706 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 707 time_after(jiffies, elem->ts + 708 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 709 list_del(&elem->list); 710 dp->reo_cmd_cache_flush_count--; 711 712 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 713 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 714 * is used in only two contexts, one is in this function called 715 * from napi and the other in ath12k_dp_free during core destroy. 716 * Before dp_free, the irqs would be disabled and would wait to 717 * synchronize. Hence there wouldn’t be any race against add or 718 * delete to this list. Hence unlock-lock is safe here. 719 */ 720 spin_unlock_bh(&dp->reo_cmd_lock); 721 722 ath12k_dp_reo_cache_flush(ab, &elem->data); 723 kfree(elem); 724 spin_lock_bh(&dp->reo_cmd_lock); 725 } 726 } 727 spin_unlock_bh(&dp->reo_cmd_lock); 728 729 return; 730 free_desc: 731 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 732 DMA_BIDIRECTIONAL); 733 kfree(rx_tid->vaddr); 734 rx_tid->vaddr = NULL; 735 } 736 737 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 738 dma_addr_t paddr) 739 { 740 struct ath12k_reo_queue_ref *qref; 741 struct ath12k_dp *dp = &ab->dp; 742 743 if (!ab->hw_params->reoq_lut_support) 744 return; 745 746 /* TODO: based on ML peer or not, select the LUT. below assumes non 747 * ML peer 748 */ 749 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 750 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 751 752 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 753 BUFFER_ADDR_INFO0_ADDR); 754 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 755 BUFFER_ADDR_INFO1_ADDR) | 756 u32_encode_bits(tid, DP_REO_QREF_NUM); 757 } 758 759 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 760 { 761 struct ath12k_reo_queue_ref *qref; 762 struct ath12k_dp *dp = &ab->dp; 763 764 if (!ab->hw_params->reoq_lut_support) 765 return; 766 767 /* TODO: based on ML peer or not, select the LUT. below assumes non 768 * ML peer 769 */ 770 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 771 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 772 773 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 774 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 775 u32_encode_bits(tid, DP_REO_QREF_NUM); 776 } 777 778 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 779 struct ath12k_peer *peer, u8 tid) 780 { 781 struct ath12k_hal_reo_cmd cmd = {0}; 782 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 783 int ret; 784 785 if (!rx_tid->active) 786 return; 787 788 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 789 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 790 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 791 cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 792 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 793 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 794 ath12k_dp_rx_tid_del_func); 795 if (ret) { 796 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 797 tid, ret); 798 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 799 DMA_BIDIRECTIONAL); 800 kfree(rx_tid->vaddr); 801 rx_tid->vaddr = NULL; 802 } 803 804 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 805 806 rx_tid->active = false; 807 } 808 809 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted 810 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind 811 * that. 812 */ 813 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 814 struct hal_reo_dest_ring *ring, 815 enum hal_wbm_rel_bm_act action) 816 { 817 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring; 818 struct hal_wbm_release_ring *desc; 819 struct ath12k_dp *dp = &ab->dp; 820 struct hal_srng *srng; 821 int ret = 0; 822 823 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 824 825 spin_lock_bh(&srng->lock); 826 827 ath12k_hal_srng_access_begin(ab, srng); 828 829 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 830 if (!desc) { 831 ret = -ENOBUFS; 832 goto exit; 833 } 834 835 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action); 836 837 exit: 838 ath12k_hal_srng_access_end(ab, srng); 839 840 spin_unlock_bh(&srng->lock); 841 842 return ret; 843 } 844 845 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 846 bool rel_link_desc) 847 { 848 struct ath12k_base *ab = rx_tid->ab; 849 850 lockdep_assert_held(&ab->base_lock); 851 852 if (rx_tid->dst_ring_desc) { 853 if (rel_link_desc) 854 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc, 855 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 856 kfree(rx_tid->dst_ring_desc); 857 rx_tid->dst_ring_desc = NULL; 858 } 859 860 rx_tid->cur_sn = 0; 861 rx_tid->last_frag_no = 0; 862 rx_tid->rx_frag_bitmap = 0; 863 __skb_queue_purge(&rx_tid->rx_frags); 864 } 865 866 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 867 { 868 struct ath12k_dp_rx_tid *rx_tid; 869 int i; 870 871 lockdep_assert_held(&ar->ab->base_lock); 872 873 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 874 rx_tid = &peer->rx_tid[i]; 875 876 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 877 ath12k_dp_rx_frags_cleanup(rx_tid, true); 878 879 spin_unlock_bh(&ar->ab->base_lock); 880 del_timer_sync(&rx_tid->frag_timer); 881 spin_lock_bh(&ar->ab->base_lock); 882 } 883 } 884 885 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 886 struct ath12k_peer *peer, 887 struct ath12k_dp_rx_tid *rx_tid, 888 u32 ba_win_sz, u16 ssn, 889 bool update_ssn) 890 { 891 struct ath12k_hal_reo_cmd cmd = {0}; 892 int ret; 893 894 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 895 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 896 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 897 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 898 cmd.ba_window_size = ba_win_sz; 899 900 if (update_ssn) { 901 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 902 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 903 } 904 905 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 906 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 907 NULL); 908 if (ret) { 909 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 910 rx_tid->tid, ret); 911 return ret; 912 } 913 914 rx_tid->ba_win_sz = ba_win_sz; 915 916 return 0; 917 } 918 919 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 920 u8 tid, u32 ba_win_sz, u16 ssn, 921 enum hal_pn_type pn_type) 922 { 923 struct ath12k_base *ab = ar->ab; 924 struct ath12k_dp *dp = &ab->dp; 925 struct hal_rx_reo_queue *addr_aligned; 926 struct ath12k_peer *peer; 927 struct ath12k_dp_rx_tid *rx_tid; 928 u32 hw_desc_sz; 929 void *vaddr; 930 dma_addr_t paddr; 931 int ret; 932 933 spin_lock_bh(&ab->base_lock); 934 935 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 936 if (!peer) { 937 spin_unlock_bh(&ab->base_lock); 938 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 939 return -ENOENT; 940 } 941 942 if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) { 943 spin_unlock_bh(&ab->base_lock); 944 ath12k_warn(ab, "reo qref table is not setup\n"); 945 return -EINVAL; 946 } 947 948 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 949 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 950 peer->peer_id, tid); 951 spin_unlock_bh(&ab->base_lock); 952 return -EINVAL; 953 } 954 955 rx_tid = &peer->rx_tid[tid]; 956 /* Update the tid queue if it is already setup */ 957 if (rx_tid->active) { 958 paddr = rx_tid->paddr; 959 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 960 ba_win_sz, ssn, true); 961 spin_unlock_bh(&ab->base_lock); 962 if (ret) { 963 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 964 return ret; 965 } 966 967 if (!ab->hw_params->reoq_lut_support) { 968 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 969 peer_mac, 970 paddr, tid, 1, 971 ba_win_sz); 972 if (ret) { 973 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 974 tid, ret); 975 return ret; 976 } 977 } 978 979 return 0; 980 } 981 982 rx_tid->tid = tid; 983 984 rx_tid->ba_win_sz = ba_win_sz; 985 986 /* TODO: Optimize the memory allocation for qos tid based on 987 * the actual BA window size in REO tid update path. 988 */ 989 if (tid == HAL_DESC_REO_NON_QOS_TID) 990 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 991 else 992 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 993 994 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 995 if (!vaddr) { 996 spin_unlock_bh(&ab->base_lock); 997 return -ENOMEM; 998 } 999 1000 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1001 1002 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1003 ssn, pn_type); 1004 1005 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1006 DMA_BIDIRECTIONAL); 1007 1008 ret = dma_mapping_error(ab->dev, paddr); 1009 if (ret) { 1010 spin_unlock_bh(&ab->base_lock); 1011 goto err_mem_free; 1012 } 1013 1014 rx_tid->vaddr = vaddr; 1015 rx_tid->paddr = paddr; 1016 rx_tid->size = hw_desc_sz; 1017 rx_tid->active = true; 1018 1019 if (ab->hw_params->reoq_lut_support) { 1020 /* Update the REO queue LUT at the corresponding peer id 1021 * and tid with qaddr. 1022 */ 1023 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr); 1024 spin_unlock_bh(&ab->base_lock); 1025 } else { 1026 spin_unlock_bh(&ab->base_lock); 1027 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1028 paddr, tid, 1, ba_win_sz); 1029 } 1030 1031 return ret; 1032 1033 err_mem_free: 1034 kfree(vaddr); 1035 1036 return ret; 1037 } 1038 1039 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1040 struct ieee80211_ampdu_params *params) 1041 { 1042 struct ath12k_base *ab = ar->ab; 1043 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta); 1044 int vdev_id = arsta->arvif->vdev_id; 1045 int ret; 1046 1047 ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id, 1048 params->tid, params->buf_size, 1049 params->ssn, arsta->pn_type); 1050 if (ret) 1051 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1052 1053 return ret; 1054 } 1055 1056 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1057 struct ieee80211_ampdu_params *params) 1058 { 1059 struct ath12k_base *ab = ar->ab; 1060 struct ath12k_peer *peer; 1061 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta); 1062 int vdev_id = arsta->arvif->vdev_id; 1063 bool active; 1064 int ret; 1065 1066 spin_lock_bh(&ab->base_lock); 1067 1068 peer = ath12k_peer_find(ab, vdev_id, params->sta->addr); 1069 if (!peer) { 1070 spin_unlock_bh(&ab->base_lock); 1071 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1072 return -ENOENT; 1073 } 1074 1075 active = peer->rx_tid[params->tid].active; 1076 1077 if (!active) { 1078 spin_unlock_bh(&ab->base_lock); 1079 return 0; 1080 } 1081 1082 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1083 spin_unlock_bh(&ab->base_lock); 1084 if (ret) { 1085 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1086 params->tid, ret); 1087 return ret; 1088 } 1089 1090 return ret; 1091 } 1092 1093 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif, 1094 const u8 *peer_addr, 1095 enum set_key_cmd key_cmd, 1096 struct ieee80211_key_conf *key) 1097 { 1098 struct ath12k *ar = arvif->ar; 1099 struct ath12k_base *ab = ar->ab; 1100 struct ath12k_hal_reo_cmd cmd = {0}; 1101 struct ath12k_peer *peer; 1102 struct ath12k_dp_rx_tid *rx_tid; 1103 u8 tid; 1104 int ret = 0; 1105 1106 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1107 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1108 * for now. 1109 */ 1110 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1111 return 0; 1112 1113 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1114 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1115 HAL_REO_CMD_UPD0_PN_SIZE | 1116 HAL_REO_CMD_UPD0_PN_VALID | 1117 HAL_REO_CMD_UPD0_PN_CHECK | 1118 HAL_REO_CMD_UPD0_SVLD; 1119 1120 switch (key->cipher) { 1121 case WLAN_CIPHER_SUITE_TKIP: 1122 case WLAN_CIPHER_SUITE_CCMP: 1123 case WLAN_CIPHER_SUITE_CCMP_256: 1124 case WLAN_CIPHER_SUITE_GCMP: 1125 case WLAN_CIPHER_SUITE_GCMP_256: 1126 if (key_cmd == SET_KEY) { 1127 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1128 cmd.pn_size = 48; 1129 } 1130 break; 1131 default: 1132 break; 1133 } 1134 1135 spin_lock_bh(&ab->base_lock); 1136 1137 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1138 if (!peer) { 1139 spin_unlock_bh(&ab->base_lock); 1140 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1141 peer_addr); 1142 return -ENOENT; 1143 } 1144 1145 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1146 rx_tid = &peer->rx_tid[tid]; 1147 if (!rx_tid->active) 1148 continue; 1149 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1150 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1151 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1152 HAL_REO_CMD_UPDATE_RX_QUEUE, 1153 &cmd, NULL); 1154 if (ret) { 1155 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1156 tid, peer_addr, ret); 1157 break; 1158 } 1159 } 1160 1161 spin_unlock_bh(&ab->base_lock); 1162 1163 return ret; 1164 } 1165 1166 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1167 u16 peer_id) 1168 { 1169 int i; 1170 1171 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1172 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1173 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1174 return i; 1175 } else { 1176 return i; 1177 } 1178 } 1179 1180 return -EINVAL; 1181 } 1182 1183 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1184 u16 tag, u16 len, const void *ptr, 1185 void *data) 1186 { 1187 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1188 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1189 const struct htt_ppdu_stats_user_rate *user_rate; 1190 struct htt_ppdu_stats_info *ppdu_info; 1191 struct htt_ppdu_user_stats *user_stats; 1192 int cur_user; 1193 u16 peer_id; 1194 1195 ppdu_info = data; 1196 1197 switch (tag) { 1198 case HTT_PPDU_STATS_TAG_COMMON: 1199 if (len < sizeof(struct htt_ppdu_stats_common)) { 1200 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1201 len, tag); 1202 return -EINVAL; 1203 } 1204 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1205 sizeof(struct htt_ppdu_stats_common)); 1206 break; 1207 case HTT_PPDU_STATS_TAG_USR_RATE: 1208 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1209 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1210 len, tag); 1211 return -EINVAL; 1212 } 1213 user_rate = ptr; 1214 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1215 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1216 peer_id); 1217 if (cur_user < 0) 1218 return -EINVAL; 1219 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1220 user_stats->peer_id = peer_id; 1221 user_stats->is_valid_peer_id = true; 1222 memcpy(&user_stats->rate, ptr, 1223 sizeof(struct htt_ppdu_stats_user_rate)); 1224 user_stats->tlv_flags |= BIT(tag); 1225 break; 1226 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1227 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1228 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1229 len, tag); 1230 return -EINVAL; 1231 } 1232 1233 cmplt_cmn = ptr; 1234 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1235 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1236 peer_id); 1237 if (cur_user < 0) 1238 return -EINVAL; 1239 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1240 user_stats->peer_id = peer_id; 1241 user_stats->is_valid_peer_id = true; 1242 memcpy(&user_stats->cmpltn_cmn, ptr, 1243 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1244 user_stats->tlv_flags |= BIT(tag); 1245 break; 1246 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1247 if (len < 1248 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1249 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1250 len, tag); 1251 return -EINVAL; 1252 } 1253 1254 ba_status = ptr; 1255 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1256 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1257 peer_id); 1258 if (cur_user < 0) 1259 return -EINVAL; 1260 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1261 user_stats->peer_id = peer_id; 1262 user_stats->is_valid_peer_id = true; 1263 memcpy(&user_stats->ack_ba, ptr, 1264 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1265 user_stats->tlv_flags |= BIT(tag); 1266 break; 1267 } 1268 return 0; 1269 } 1270 1271 static int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1272 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1273 const void *ptr, void *data), 1274 void *data) 1275 { 1276 const struct htt_tlv *tlv; 1277 const void *begin = ptr; 1278 u16 tlv_tag, tlv_len; 1279 int ret = -EINVAL; 1280 1281 while (len > 0) { 1282 if (len < sizeof(*tlv)) { 1283 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1284 ptr - begin, len, sizeof(*tlv)); 1285 return -EINVAL; 1286 } 1287 tlv = (struct htt_tlv *)ptr; 1288 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1289 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1290 ptr += sizeof(*tlv); 1291 len -= sizeof(*tlv); 1292 1293 if (tlv_len > len) { 1294 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1295 tlv_tag, ptr - begin, len, tlv_len); 1296 return -EINVAL; 1297 } 1298 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1299 if (ret == -ENOMEM) 1300 return ret; 1301 1302 ptr += tlv_len; 1303 len -= tlv_len; 1304 } 1305 return 0; 1306 } 1307 1308 static void 1309 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1310 struct htt_ppdu_stats *ppdu_stats, u8 user) 1311 { 1312 struct ath12k_base *ab = ar->ab; 1313 struct ath12k_peer *peer; 1314 struct ieee80211_sta *sta; 1315 struct ath12k_sta *arsta; 1316 struct htt_ppdu_stats_user_rate *user_rate; 1317 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1318 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1319 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1320 int ret; 1321 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1322 u32 v, succ_bytes = 0; 1323 u16 tones, rate = 0, succ_pkts = 0; 1324 u32 tx_duration = 0; 1325 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1326 bool is_ampdu = false; 1327 1328 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1329 return; 1330 1331 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1332 is_ampdu = 1333 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1334 1335 if (usr_stats->tlv_flags & 1336 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1337 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1338 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1339 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1340 tid = le32_get_bits(usr_stats->ack_ba.info, 1341 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1342 } 1343 1344 if (common->fes_duration_us) 1345 tx_duration = le32_to_cpu(common->fes_duration_us); 1346 1347 user_rate = &usr_stats->rate; 1348 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1349 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1350 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1351 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1352 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1353 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1354 1355 /* Note: If host configured fixed rates and in some other special 1356 * cases, the broadcast/management frames are sent in different rates. 1357 * Firmware rate's control to be skipped for this? 1358 */ 1359 1360 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1361 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1362 return; 1363 } 1364 1365 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1366 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1367 return; 1368 } 1369 1370 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1371 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1372 mcs, nss); 1373 return; 1374 } 1375 1376 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1377 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1378 flags, 1379 &rate_idx, 1380 &rate); 1381 if (ret < 0) 1382 return; 1383 } 1384 1385 rcu_read_lock(); 1386 spin_lock_bh(&ab->base_lock); 1387 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1388 1389 if (!peer || !peer->sta) { 1390 spin_unlock_bh(&ab->base_lock); 1391 rcu_read_unlock(); 1392 return; 1393 } 1394 1395 sta = peer->sta; 1396 arsta = ath12k_sta_to_arsta(sta); 1397 1398 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1399 1400 switch (flags) { 1401 case WMI_RATE_PREAMBLE_OFDM: 1402 arsta->txrate.legacy = rate; 1403 break; 1404 case WMI_RATE_PREAMBLE_CCK: 1405 arsta->txrate.legacy = rate; 1406 break; 1407 case WMI_RATE_PREAMBLE_HT: 1408 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1409 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1410 if (sgi) 1411 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1412 break; 1413 case WMI_RATE_PREAMBLE_VHT: 1414 arsta->txrate.mcs = mcs; 1415 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1416 if (sgi) 1417 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1418 break; 1419 case WMI_RATE_PREAMBLE_HE: 1420 arsta->txrate.mcs = mcs; 1421 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1422 arsta->txrate.he_dcm = dcm; 1423 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1424 tones = le16_to_cpu(user_rate->ru_end) - 1425 le16_to_cpu(user_rate->ru_start) + 1; 1426 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1427 arsta->txrate.he_ru_alloc = v; 1428 break; 1429 } 1430 1431 arsta->txrate.nss = nss; 1432 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1433 arsta->tx_duration += tx_duration; 1434 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1435 1436 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1437 * So skip peer stats update for mgmt packets. 1438 */ 1439 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1440 memset(peer_stats, 0, sizeof(*peer_stats)); 1441 peer_stats->succ_pkts = succ_pkts; 1442 peer_stats->succ_bytes = succ_bytes; 1443 peer_stats->is_ampdu = is_ampdu; 1444 peer_stats->duration = tx_duration; 1445 peer_stats->ba_fails = 1446 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1447 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1448 } 1449 1450 spin_unlock_bh(&ab->base_lock); 1451 rcu_read_unlock(); 1452 } 1453 1454 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1455 struct htt_ppdu_stats *ppdu_stats) 1456 { 1457 u8 user; 1458 1459 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1460 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1461 } 1462 1463 static 1464 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1465 u32 ppdu_id) 1466 { 1467 struct htt_ppdu_stats_info *ppdu_info; 1468 1469 lockdep_assert_held(&ar->data_lock); 1470 if (!list_empty(&ar->ppdu_stats_info)) { 1471 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1472 if (ppdu_info->ppdu_id == ppdu_id) 1473 return ppdu_info; 1474 } 1475 1476 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1477 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1478 typeof(*ppdu_info), list); 1479 list_del(&ppdu_info->list); 1480 ar->ppdu_stat_list_depth--; 1481 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1482 kfree(ppdu_info); 1483 } 1484 } 1485 1486 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1487 if (!ppdu_info) 1488 return NULL; 1489 1490 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1491 ar->ppdu_stat_list_depth++; 1492 1493 return ppdu_info; 1494 } 1495 1496 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1497 struct htt_ppdu_user_stats *usr_stats) 1498 { 1499 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1500 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1501 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1502 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1503 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1504 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1505 peer->ppdu_stats_delayba.resp_rate_flags = 1506 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1507 1508 peer->delayba_flag = true; 1509 } 1510 1511 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1512 struct htt_ppdu_user_stats *usr_stats) 1513 { 1514 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1515 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1516 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1517 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1518 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1519 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1520 usr_stats->rate.resp_rate_flags = 1521 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1522 1523 peer->delayba_flag = false; 1524 } 1525 1526 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1527 struct sk_buff *skb) 1528 { 1529 struct ath12k_htt_ppdu_stats_msg *msg; 1530 struct htt_ppdu_stats_info *ppdu_info; 1531 struct ath12k_peer *peer = NULL; 1532 struct htt_ppdu_user_stats *usr_stats = NULL; 1533 u32 peer_id = 0; 1534 struct ath12k *ar; 1535 int ret, i; 1536 u8 pdev_id; 1537 u32 ppdu_id, len; 1538 1539 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1540 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1541 if (len > (skb->len - struct_size(msg, data, 0))) { 1542 ath12k_warn(ab, 1543 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1544 len, skb->len); 1545 return -EINVAL; 1546 } 1547 1548 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1549 ppdu_id = le32_to_cpu(msg->ppdu_id); 1550 1551 rcu_read_lock(); 1552 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1553 if (!ar) { 1554 ret = -EINVAL; 1555 goto exit; 1556 } 1557 1558 spin_lock_bh(&ar->data_lock); 1559 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1560 if (!ppdu_info) { 1561 spin_unlock_bh(&ar->data_lock); 1562 ret = -EINVAL; 1563 goto exit; 1564 } 1565 1566 ppdu_info->ppdu_id = ppdu_id; 1567 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1568 ath12k_htt_tlv_ppdu_stats_parse, 1569 (void *)ppdu_info); 1570 if (ret) { 1571 spin_unlock_bh(&ar->data_lock); 1572 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1573 goto exit; 1574 } 1575 1576 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1577 spin_unlock_bh(&ar->data_lock); 1578 ath12k_warn(ab, 1579 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1580 ppdu_info->ppdu_stats.common.num_users, 1581 HTT_PPDU_STATS_MAX_USERS); 1582 ret = -EINVAL; 1583 goto exit; 1584 } 1585 1586 /* back up data rate tlv for all peers */ 1587 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1588 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1589 ppdu_info->delay_ba) { 1590 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1591 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1592 spin_lock_bh(&ab->base_lock); 1593 peer = ath12k_peer_find_by_id(ab, peer_id); 1594 if (!peer) { 1595 spin_unlock_bh(&ab->base_lock); 1596 continue; 1597 } 1598 1599 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1600 if (usr_stats->delay_ba) 1601 ath12k_copy_to_delay_stats(peer, usr_stats); 1602 spin_unlock_bh(&ab->base_lock); 1603 } 1604 } 1605 1606 /* restore all peers' data rate tlv to mu-bar tlv */ 1607 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1608 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1609 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1610 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1611 spin_lock_bh(&ab->base_lock); 1612 peer = ath12k_peer_find_by_id(ab, peer_id); 1613 if (!peer) { 1614 spin_unlock_bh(&ab->base_lock); 1615 continue; 1616 } 1617 1618 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1619 if (peer->delayba_flag) 1620 ath12k_copy_to_bar(peer, usr_stats); 1621 spin_unlock_bh(&ab->base_lock); 1622 } 1623 } 1624 1625 spin_unlock_bh(&ar->data_lock); 1626 1627 exit: 1628 rcu_read_unlock(); 1629 1630 return ret; 1631 } 1632 1633 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1634 struct sk_buff *skb) 1635 { 1636 struct ath12k_htt_mlo_offset_msg *msg; 1637 struct ath12k_pdev *pdev; 1638 struct ath12k *ar; 1639 u8 pdev_id; 1640 1641 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1642 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1643 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1644 1645 rcu_read_lock(); 1646 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1647 if (!ar) { 1648 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id); 1649 goto exit; 1650 } 1651 1652 spin_lock_bh(&ar->data_lock); 1653 pdev = ar->pdev; 1654 1655 pdev->timestamp.info = __le32_to_cpu(msg->info); 1656 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1657 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1658 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1659 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1660 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1661 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1662 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1663 1664 spin_unlock_bh(&ar->data_lock); 1665 exit: 1666 rcu_read_unlock(); 1667 } 1668 1669 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1670 struct sk_buff *skb) 1671 { 1672 struct ath12k_dp *dp = &ab->dp; 1673 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1674 enum htt_t2h_msg_type type; 1675 u16 peer_id; 1676 u8 vdev_id; 1677 u8 mac_addr[ETH_ALEN]; 1678 u16 peer_mac_h16; 1679 u16 ast_hash = 0; 1680 u16 hw_peer_id; 1681 1682 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1683 1684 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1685 1686 switch (type) { 1687 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1688 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1689 HTT_T2H_VERSION_CONF_MAJOR); 1690 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1691 HTT_T2H_VERSION_CONF_MINOR); 1692 complete(&dp->htt_tgt_version_received); 1693 break; 1694 /* TODO: remove unused peer map versions after testing */ 1695 case HTT_T2H_MSG_TYPE_PEER_MAP: 1696 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1697 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1698 peer_id = le32_get_bits(resp->peer_map_ev.info, 1699 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1700 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1701 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1702 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1703 peer_mac_h16, mac_addr); 1704 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1705 break; 1706 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1707 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1708 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1709 peer_id = le32_get_bits(resp->peer_map_ev.info, 1710 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1711 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1712 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1713 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1714 peer_mac_h16, mac_addr); 1715 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1716 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1717 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1718 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1719 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1720 hw_peer_id); 1721 break; 1722 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1723 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1724 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1725 peer_id = le32_get_bits(resp->peer_map_ev.info, 1726 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1727 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1728 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1729 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1730 peer_mac_h16, mac_addr); 1731 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1732 peer_id); 1733 break; 1734 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1735 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1736 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1737 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1738 ath12k_peer_unmap_event(ab, peer_id); 1739 break; 1740 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1741 ath12k_htt_pull_ppdu_stats(ab, skb); 1742 break; 1743 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1744 break; 1745 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 1746 ath12k_htt_mlo_offset_event_handler(ab, skb); 1747 break; 1748 default: 1749 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 1750 type); 1751 break; 1752 } 1753 1754 dev_kfree_skb_any(skb); 1755 } 1756 1757 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 1758 struct sk_buff_head *msdu_list, 1759 struct sk_buff *first, struct sk_buff *last, 1760 u8 l3pad_bytes, int msdu_len) 1761 { 1762 struct ath12k_base *ab = ar->ab; 1763 struct sk_buff *skb; 1764 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1765 int buf_first_hdr_len, buf_first_len; 1766 struct hal_rx_desc *ldesc; 1767 int space_extra, rem_len, buf_len; 1768 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 1769 1770 /* As the msdu is spread across multiple rx buffers, 1771 * find the offset to the start of msdu for computing 1772 * the length of the msdu in the first buffer. 1773 */ 1774 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1775 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1776 1777 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1778 skb_put(first, buf_first_hdr_len + msdu_len); 1779 skb_pull(first, buf_first_hdr_len); 1780 return 0; 1781 } 1782 1783 ldesc = (struct hal_rx_desc *)last->data; 1784 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 1785 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 1786 1787 /* MSDU spans over multiple buffers because the length of the MSDU 1788 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1789 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1790 */ 1791 skb_put(first, DP_RX_BUFFER_SIZE); 1792 skb_pull(first, buf_first_hdr_len); 1793 1794 /* When an MSDU spread over multiple buffers MSDU_END 1795 * tlvs are valid only in the last buffer. Copy those tlvs. 1796 */ 1797 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1798 1799 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1800 if (space_extra > 0 && 1801 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1802 /* Free up all buffers of the MSDU */ 1803 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1804 rxcb = ATH12K_SKB_RXCB(skb); 1805 if (!rxcb->is_continuation) { 1806 dev_kfree_skb_any(skb); 1807 break; 1808 } 1809 dev_kfree_skb_any(skb); 1810 } 1811 return -ENOMEM; 1812 } 1813 1814 rem_len = msdu_len - buf_first_len; 1815 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1816 rxcb = ATH12K_SKB_RXCB(skb); 1817 if (rxcb->is_continuation) 1818 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1819 else 1820 buf_len = rem_len; 1821 1822 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1823 WARN_ON_ONCE(1); 1824 dev_kfree_skb_any(skb); 1825 return -EINVAL; 1826 } 1827 1828 skb_put(skb, buf_len + hal_rx_desc_sz); 1829 skb_pull(skb, hal_rx_desc_sz); 1830 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1831 buf_len); 1832 dev_kfree_skb_any(skb); 1833 1834 rem_len -= buf_len; 1835 if (!rxcb->is_continuation) 1836 break; 1837 } 1838 1839 return 0; 1840 } 1841 1842 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1843 struct sk_buff *first) 1844 { 1845 struct sk_buff *skb; 1846 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1847 1848 if (!rxcb->is_continuation) 1849 return first; 1850 1851 skb_queue_walk(msdu_list, skb) { 1852 rxcb = ATH12K_SKB_RXCB(skb); 1853 if (!rxcb->is_continuation) 1854 return skb; 1855 } 1856 1857 return NULL; 1858 } 1859 1860 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu) 1861 { 1862 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1863 struct ath12k_base *ab = ar->ab; 1864 bool ip_csum_fail, l4_csum_fail; 1865 1866 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc); 1867 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc); 1868 1869 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1870 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1871 } 1872 1873 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, 1874 enum hal_encrypt_type enctype) 1875 { 1876 switch (enctype) { 1877 case HAL_ENCRYPT_TYPE_OPEN: 1878 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1879 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1880 return 0; 1881 case HAL_ENCRYPT_TYPE_CCMP_128: 1882 return IEEE80211_CCMP_MIC_LEN; 1883 case HAL_ENCRYPT_TYPE_CCMP_256: 1884 return IEEE80211_CCMP_256_MIC_LEN; 1885 case HAL_ENCRYPT_TYPE_GCMP_128: 1886 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1887 return IEEE80211_GCMP_MIC_LEN; 1888 case HAL_ENCRYPT_TYPE_WEP_40: 1889 case HAL_ENCRYPT_TYPE_WEP_104: 1890 case HAL_ENCRYPT_TYPE_WEP_128: 1891 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1892 case HAL_ENCRYPT_TYPE_WAPI: 1893 break; 1894 } 1895 1896 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1897 return 0; 1898 } 1899 1900 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 1901 enum hal_encrypt_type enctype) 1902 { 1903 switch (enctype) { 1904 case HAL_ENCRYPT_TYPE_OPEN: 1905 return 0; 1906 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1907 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1908 return IEEE80211_TKIP_IV_LEN; 1909 case HAL_ENCRYPT_TYPE_CCMP_128: 1910 return IEEE80211_CCMP_HDR_LEN; 1911 case HAL_ENCRYPT_TYPE_CCMP_256: 1912 return IEEE80211_CCMP_256_HDR_LEN; 1913 case HAL_ENCRYPT_TYPE_GCMP_128: 1914 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1915 return IEEE80211_GCMP_HDR_LEN; 1916 case HAL_ENCRYPT_TYPE_WEP_40: 1917 case HAL_ENCRYPT_TYPE_WEP_104: 1918 case HAL_ENCRYPT_TYPE_WEP_128: 1919 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1920 case HAL_ENCRYPT_TYPE_WAPI: 1921 break; 1922 } 1923 1924 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1925 return 0; 1926 } 1927 1928 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 1929 enum hal_encrypt_type enctype) 1930 { 1931 switch (enctype) { 1932 case HAL_ENCRYPT_TYPE_OPEN: 1933 case HAL_ENCRYPT_TYPE_CCMP_128: 1934 case HAL_ENCRYPT_TYPE_CCMP_256: 1935 case HAL_ENCRYPT_TYPE_GCMP_128: 1936 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1937 return 0; 1938 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1939 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1940 return IEEE80211_TKIP_ICV_LEN; 1941 case HAL_ENCRYPT_TYPE_WEP_40: 1942 case HAL_ENCRYPT_TYPE_WEP_104: 1943 case HAL_ENCRYPT_TYPE_WEP_128: 1944 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1945 case HAL_ENCRYPT_TYPE_WAPI: 1946 break; 1947 } 1948 1949 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1950 return 0; 1951 } 1952 1953 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 1954 struct sk_buff *msdu, 1955 enum hal_encrypt_type enctype, 1956 struct ieee80211_rx_status *status) 1957 { 1958 struct ath12k_base *ab = ar->ab; 1959 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1960 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1961 struct ieee80211_hdr *hdr; 1962 size_t hdr_len; 1963 u8 *crypto_hdr; 1964 u16 qos_ctl; 1965 1966 /* pull decapped header */ 1967 hdr = (struct ieee80211_hdr *)msdu->data; 1968 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1969 skb_pull(msdu, hdr_len); 1970 1971 /* Rebuild qos header */ 1972 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1973 1974 /* Reset the order bit as the HT_Control header is stripped */ 1975 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 1976 1977 qos_ctl = rxcb->tid; 1978 1979 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 1980 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 1981 1982 /* TODO: Add other QoS ctl fields when required */ 1983 1984 /* copy decap header before overwriting for reuse below */ 1985 memcpy(decap_hdr, hdr, hdr_len); 1986 1987 /* Rebuild crypto header for mac80211 use */ 1988 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 1989 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 1990 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 1991 rxcb->rx_desc, crypto_hdr, 1992 enctype); 1993 } 1994 1995 memcpy(skb_push(msdu, 1996 IEEE80211_QOS_CTL_LEN), &qos_ctl, 1997 IEEE80211_QOS_CTL_LEN); 1998 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 1999 } 2000 2001 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2002 enum hal_encrypt_type enctype, 2003 struct ieee80211_rx_status *status, 2004 bool decrypted) 2005 { 2006 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2007 struct ieee80211_hdr *hdr; 2008 size_t hdr_len; 2009 size_t crypto_len; 2010 2011 if (!rxcb->is_first_msdu || 2012 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2013 WARN_ON_ONCE(1); 2014 return; 2015 } 2016 2017 skb_trim(msdu, msdu->len - FCS_LEN); 2018 2019 if (!decrypted) 2020 return; 2021 2022 hdr = (void *)msdu->data; 2023 2024 /* Tail */ 2025 if (status->flag & RX_FLAG_IV_STRIPPED) { 2026 skb_trim(msdu, msdu->len - 2027 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2028 2029 skb_trim(msdu, msdu->len - 2030 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2031 } else { 2032 /* MIC */ 2033 if (status->flag & RX_FLAG_MIC_STRIPPED) 2034 skb_trim(msdu, msdu->len - 2035 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2036 2037 /* ICV */ 2038 if (status->flag & RX_FLAG_ICV_STRIPPED) 2039 skb_trim(msdu, msdu->len - 2040 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2041 } 2042 2043 /* MMIC */ 2044 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2045 !ieee80211_has_morefrags(hdr->frame_control) && 2046 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2047 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2048 2049 /* Head */ 2050 if (status->flag & RX_FLAG_IV_STRIPPED) { 2051 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2052 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2053 2054 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2055 skb_pull(msdu, crypto_len); 2056 } 2057 } 2058 2059 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2060 struct sk_buff *msdu, 2061 struct ath12k_skb_rxcb *rxcb, 2062 struct ieee80211_rx_status *status, 2063 enum hal_encrypt_type enctype) 2064 { 2065 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2066 struct ath12k_base *ab = ar->ab; 2067 size_t hdr_len, crypto_len; 2068 struct ieee80211_hdr *hdr; 2069 u16 qos_ctl; 2070 __le16 fc; 2071 u8 *crypto_hdr; 2072 2073 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2074 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2075 crypto_hdr = skb_push(msdu, crypto_len); 2076 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2077 } 2078 2079 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc)); 2080 hdr_len = ieee80211_hdrlen(fc); 2081 skb_push(msdu, hdr_len); 2082 hdr = (struct ieee80211_hdr *)msdu->data; 2083 hdr->frame_control = fc; 2084 2085 /* Get wifi header from rx_desc */ 2086 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr); 2087 2088 if (rxcb->is_mcbc) 2089 status->flag &= ~RX_FLAG_PN_VALIDATED; 2090 2091 /* Add QOS header */ 2092 if (ieee80211_is_data_qos(hdr->frame_control)) { 2093 qos_ctl = rxcb->tid; 2094 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc)) 2095 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2096 2097 /* TODO: Add other QoS ctl fields when required */ 2098 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN), 2099 &qos_ctl, IEEE80211_QOS_CTL_LEN); 2100 } 2101 } 2102 2103 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2104 struct sk_buff *msdu, 2105 enum hal_encrypt_type enctype, 2106 struct ieee80211_rx_status *status) 2107 { 2108 struct ieee80211_hdr *hdr; 2109 struct ethhdr *eth; 2110 u8 da[ETH_ALEN]; 2111 u8 sa[ETH_ALEN]; 2112 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2113 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2114 2115 eth = (struct ethhdr *)msdu->data; 2116 ether_addr_copy(da, eth->h_dest); 2117 ether_addr_copy(sa, eth->h_source); 2118 rfc.snap_type = eth->h_proto; 2119 skb_pull(msdu, sizeof(*eth)); 2120 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2121 sizeof(rfc)); 2122 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2123 2124 /* original 802.11 header has a different DA and in 2125 * case of 4addr it may also have different SA 2126 */ 2127 hdr = (struct ieee80211_hdr *)msdu->data; 2128 ether_addr_copy(ieee80211_get_DA(hdr), da); 2129 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2130 } 2131 2132 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2133 struct hal_rx_desc *rx_desc, 2134 enum hal_encrypt_type enctype, 2135 struct ieee80211_rx_status *status, 2136 bool decrypted) 2137 { 2138 struct ath12k_base *ab = ar->ab; 2139 u8 decap; 2140 struct ethhdr *ehdr; 2141 2142 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2143 2144 switch (decap) { 2145 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2146 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2147 break; 2148 case DP_RX_DECAP_TYPE_RAW: 2149 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2150 decrypted); 2151 break; 2152 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2153 ehdr = (struct ethhdr *)msdu->data; 2154 2155 /* mac80211 allows fast path only for authorized STA */ 2156 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2157 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2158 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2159 break; 2160 } 2161 2162 /* PN for mcast packets will be validated in mac80211; 2163 * remove eth header and add 802.11 header. 2164 */ 2165 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2166 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2167 break; 2168 case DP_RX_DECAP_TYPE_8023: 2169 /* TODO: Handle undecap for these formats */ 2170 break; 2171 } 2172 } 2173 2174 struct ath12k_peer * 2175 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu) 2176 { 2177 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2178 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2179 struct ath12k_peer *peer = NULL; 2180 2181 lockdep_assert_held(&ab->base_lock); 2182 2183 if (rxcb->peer_id) 2184 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2185 2186 if (peer) 2187 return peer; 2188 2189 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2190 return NULL; 2191 2192 peer = ath12k_peer_find_by_addr(ab, 2193 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, 2194 rx_desc)); 2195 return peer; 2196 } 2197 2198 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2199 struct sk_buff *msdu, 2200 struct hal_rx_desc *rx_desc, 2201 struct ieee80211_rx_status *rx_status) 2202 { 2203 bool fill_crypto_hdr; 2204 struct ath12k_base *ab = ar->ab; 2205 struct ath12k_skb_rxcb *rxcb; 2206 enum hal_encrypt_type enctype; 2207 bool is_decrypted = false; 2208 struct ieee80211_hdr *hdr; 2209 struct ath12k_peer *peer; 2210 u32 err_bitmap; 2211 2212 /* PN for multicast packets will be checked in mac80211 */ 2213 rxcb = ATH12K_SKB_RXCB(msdu); 2214 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc); 2215 rxcb->is_mcbc = fill_crypto_hdr; 2216 2217 if (rxcb->is_mcbc) 2218 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc); 2219 2220 spin_lock_bh(&ar->ab->base_lock); 2221 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 2222 if (peer) { 2223 if (rxcb->is_mcbc) 2224 enctype = peer->sec_type_grp; 2225 else 2226 enctype = peer->sec_type; 2227 } else { 2228 enctype = HAL_ENCRYPT_TYPE_OPEN; 2229 } 2230 spin_unlock_bh(&ar->ab->base_lock); 2231 2232 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2233 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2234 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2235 2236 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2237 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2238 RX_FLAG_MMIC_ERROR | 2239 RX_FLAG_DECRYPTED | 2240 RX_FLAG_IV_STRIPPED | 2241 RX_FLAG_MMIC_STRIPPED); 2242 2243 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2244 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2245 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2246 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2247 2248 if (is_decrypted) { 2249 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2250 2251 if (fill_crypto_hdr) 2252 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2253 RX_FLAG_ICV_STRIPPED; 2254 else 2255 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2256 RX_FLAG_PN_VALIDATED; 2257 } 2258 2259 ath12k_dp_rx_h_csum_offload(ar, msdu); 2260 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2261 enctype, rx_status, is_decrypted); 2262 2263 if (!is_decrypted || fill_crypto_hdr) 2264 return; 2265 2266 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) != 2267 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2268 hdr = (void *)msdu->data; 2269 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2270 } 2271 } 2272 2273 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2274 struct ieee80211_rx_status *rx_status) 2275 { 2276 struct ath12k_base *ab = ar->ab; 2277 struct ieee80211_supported_band *sband; 2278 enum rx_msdu_start_pkt_type pkt_type; 2279 u8 bw; 2280 u8 rate_mcs, nss; 2281 u8 sgi; 2282 bool is_cck; 2283 2284 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2285 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2286 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2287 nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2288 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2289 2290 switch (pkt_type) { 2291 case RX_MSDU_START_PKT_TYPE_11A: 2292 case RX_MSDU_START_PKT_TYPE_11B: 2293 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2294 sband = &ar->mac.sbands[rx_status->band]; 2295 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2296 is_cck); 2297 break; 2298 case RX_MSDU_START_PKT_TYPE_11N: 2299 rx_status->encoding = RX_ENC_HT; 2300 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2301 ath12k_warn(ar->ab, 2302 "Received with invalid mcs in HT mode %d\n", 2303 rate_mcs); 2304 break; 2305 } 2306 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2307 if (sgi) 2308 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2309 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2310 break; 2311 case RX_MSDU_START_PKT_TYPE_11AC: 2312 rx_status->encoding = RX_ENC_VHT; 2313 rx_status->rate_idx = rate_mcs; 2314 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2315 ath12k_warn(ar->ab, 2316 "Received with invalid mcs in VHT mode %d\n", 2317 rate_mcs); 2318 break; 2319 } 2320 rx_status->nss = nss; 2321 if (sgi) 2322 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2323 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2324 break; 2325 case RX_MSDU_START_PKT_TYPE_11AX: 2326 rx_status->rate_idx = rate_mcs; 2327 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2328 ath12k_warn(ar->ab, 2329 "Received with invalid mcs in HE mode %d\n", 2330 rate_mcs); 2331 break; 2332 } 2333 rx_status->encoding = RX_ENC_HE; 2334 rx_status->nss = nss; 2335 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2336 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2337 break; 2338 } 2339 } 2340 2341 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2342 struct ieee80211_rx_status *rx_status) 2343 { 2344 struct ath12k_base *ab = ar->ab; 2345 u8 channel_num; 2346 u32 center_freq, meta_data; 2347 struct ieee80211_channel *channel; 2348 2349 rx_status->freq = 0; 2350 rx_status->rate_idx = 0; 2351 rx_status->nss = 0; 2352 rx_status->encoding = RX_ENC_LEGACY; 2353 rx_status->bw = RATE_INFO_BW_20; 2354 rx_status->enc_flags = 0; 2355 2356 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2357 2358 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2359 channel_num = meta_data; 2360 center_freq = meta_data >> 16; 2361 2362 if (center_freq >= ATH12K_MIN_6G_FREQ && 2363 center_freq <= ATH12K_MAX_6G_FREQ) { 2364 rx_status->band = NL80211_BAND_6GHZ; 2365 rx_status->freq = center_freq; 2366 } else if (channel_num >= 1 && channel_num <= 14) { 2367 rx_status->band = NL80211_BAND_2GHZ; 2368 } else if (channel_num >= 36 && channel_num <= 173) { 2369 rx_status->band = NL80211_BAND_5GHZ; 2370 } else { 2371 spin_lock_bh(&ar->data_lock); 2372 channel = ar->rx_channel; 2373 if (channel) { 2374 rx_status->band = channel->band; 2375 channel_num = 2376 ieee80211_frequency_to_channel(channel->center_freq); 2377 } 2378 spin_unlock_bh(&ar->data_lock); 2379 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2380 rx_desc, sizeof(*rx_desc)); 2381 } 2382 2383 if (rx_status->band != NL80211_BAND_6GHZ) 2384 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2385 rx_status->band); 2386 2387 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status); 2388 } 2389 2390 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2391 struct sk_buff *msdu, 2392 struct ieee80211_rx_status *status) 2393 { 2394 struct ath12k_base *ab = ar->ab; 2395 static const struct ieee80211_radiotap_he known = { 2396 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2397 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2398 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2399 }; 2400 struct ieee80211_radiotap_he *he; 2401 struct ieee80211_rx_status *rx_status; 2402 struct ieee80211_sta *pubsta; 2403 struct ath12k_peer *peer; 2404 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2405 u8 decap = DP_RX_DECAP_TYPE_RAW; 2406 bool is_mcbc = rxcb->is_mcbc; 2407 bool is_eapol = rxcb->is_eapol; 2408 2409 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) && 2410 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2411 he = skb_push(msdu, sizeof(known)); 2412 memcpy(he, &known, sizeof(known)); 2413 status->flag |= RX_FLAG_RADIOTAP_HE; 2414 } 2415 2416 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2417 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc); 2418 2419 spin_lock_bh(&ab->base_lock); 2420 peer = ath12k_dp_rx_h_find_peer(ab, msdu); 2421 2422 pubsta = peer ? peer->sta : NULL; 2423 2424 spin_unlock_bh(&ab->base_lock); 2425 2426 ath12k_dbg(ab, ATH12K_DBG_DATA, 2427 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2428 msdu, 2429 msdu->len, 2430 peer ? peer->addr : NULL, 2431 rxcb->tid, 2432 is_mcbc ? "mcast" : "ucast", 2433 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2434 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2435 (status->encoding == RX_ENC_HT) ? "ht" : "", 2436 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2437 (status->encoding == RX_ENC_HE) ? "he" : "", 2438 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2439 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2440 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2441 (status->bw == RATE_INFO_BW_320) ? "320" : "", 2442 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2443 status->rate_idx, 2444 status->nss, 2445 status->freq, 2446 status->band, status->flag, 2447 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2448 !!(status->flag & RX_FLAG_MMIC_ERROR), 2449 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2450 2451 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2452 msdu->data, msdu->len); 2453 2454 rx_status = IEEE80211_SKB_RXCB(msdu); 2455 *rx_status = *status; 2456 2457 /* TODO: trace rx packet */ 2458 2459 /* PN for multicast packets are not validate in HW, 2460 * so skip 802.3 rx path 2461 * Also, fast_rx expects the STA to be authorized, hence 2462 * eapol packets are sent in slow path. 2463 */ 2464 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2465 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2466 rx_status->flag |= RX_FLAG_8023; 2467 2468 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 2469 } 2470 2471 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2472 struct sk_buff *msdu, 2473 struct sk_buff_head *msdu_list, 2474 struct ieee80211_rx_status *rx_status) 2475 { 2476 struct ath12k_base *ab = ar->ab; 2477 struct hal_rx_desc *rx_desc, *lrx_desc; 2478 struct ath12k_skb_rxcb *rxcb; 2479 struct sk_buff *last_buf; 2480 u8 l3_pad_bytes; 2481 u16 msdu_len; 2482 int ret; 2483 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2484 2485 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2486 if (!last_buf) { 2487 ath12k_warn(ab, 2488 "No valid Rx buffer to access MSDU_END tlv\n"); 2489 ret = -EIO; 2490 goto free_out; 2491 } 2492 2493 rx_desc = (struct hal_rx_desc *)msdu->data; 2494 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2495 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2496 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2497 ret = -EIO; 2498 goto free_out; 2499 } 2500 2501 rxcb = ATH12K_SKB_RXCB(msdu); 2502 rxcb->rx_desc = rx_desc; 2503 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2504 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2505 2506 if (rxcb->is_frag) { 2507 skb_pull(msdu, hal_rx_desc_sz); 2508 } else if (!rxcb->is_continuation) { 2509 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2510 ret = -EINVAL; 2511 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2512 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2513 sizeof(*rx_desc)); 2514 goto free_out; 2515 } 2516 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2517 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2518 } else { 2519 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2520 msdu, last_buf, 2521 l3_pad_bytes, msdu_len); 2522 if (ret) { 2523 ath12k_warn(ab, 2524 "failed to coalesce msdu rx buffer%d\n", ret); 2525 goto free_out; 2526 } 2527 } 2528 2529 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2530 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2531 2532 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2533 2534 return 0; 2535 2536 free_out: 2537 return ret; 2538 } 2539 2540 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2541 struct napi_struct *napi, 2542 struct sk_buff_head *msdu_list, 2543 int ring_id) 2544 { 2545 struct ieee80211_rx_status rx_status = {0}; 2546 struct ath12k_skb_rxcb *rxcb; 2547 struct sk_buff *msdu; 2548 struct ath12k *ar; 2549 u8 mac_id, pdev_id; 2550 int ret; 2551 2552 if (skb_queue_empty(msdu_list)) 2553 return; 2554 2555 rcu_read_lock(); 2556 2557 while ((msdu = __skb_dequeue(msdu_list))) { 2558 rxcb = ATH12K_SKB_RXCB(msdu); 2559 mac_id = rxcb->mac_id; 2560 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 2561 ar = ab->pdevs[pdev_id].ar; 2562 if (!rcu_dereference(ab->pdevs_active[pdev_id])) { 2563 dev_kfree_skb_any(msdu); 2564 continue; 2565 } 2566 2567 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 2568 dev_kfree_skb_any(msdu); 2569 continue; 2570 } 2571 2572 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2573 if (ret) { 2574 ath12k_dbg(ab, ATH12K_DBG_DATA, 2575 "Unable to process msdu %d", ret); 2576 dev_kfree_skb_any(msdu); 2577 continue; 2578 } 2579 2580 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2581 } 2582 2583 rcu_read_unlock(); 2584 } 2585 2586 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2587 struct napi_struct *napi, int budget) 2588 { 2589 LIST_HEAD(rx_desc_used_list); 2590 struct ath12k_rx_desc_info *desc_info; 2591 struct ath12k_dp *dp = &ab->dp; 2592 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2593 struct hal_reo_dest_ring *desc; 2594 int num_buffs_reaped = 0; 2595 struct sk_buff_head msdu_list; 2596 struct ath12k_skb_rxcb *rxcb; 2597 int total_msdu_reaped = 0; 2598 struct hal_srng *srng; 2599 struct sk_buff *msdu; 2600 bool done = false; 2601 int mac_id; 2602 u64 desc_va; 2603 2604 __skb_queue_head_init(&msdu_list); 2605 2606 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2607 2608 spin_lock_bh(&srng->lock); 2609 2610 try_again: 2611 ath12k_hal_srng_access_begin(ab, srng); 2612 2613 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2614 enum hal_reo_dest_ring_push_reason push_reason; 2615 u32 cookie; 2616 2617 cookie = le32_get_bits(desc->buf_addr_info.info1, 2618 BUFFER_ADDR_INFO1_SW_COOKIE); 2619 2620 mac_id = le32_get_bits(desc->info0, 2621 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2622 2623 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2624 le32_to_cpu(desc->buf_va_lo)); 2625 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2626 2627 /* retry manual desc retrieval */ 2628 if (!desc_info) { 2629 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 2630 if (!desc_info) { 2631 ath12k_warn(ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n", 2632 cookie); 2633 continue; 2634 } 2635 } 2636 2637 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 2638 ath12k_warn(ab, "Check HW CC implementation"); 2639 2640 msdu = desc_info->skb; 2641 desc_info->skb = NULL; 2642 2643 list_add_tail(&desc_info->list, &rx_desc_used_list); 2644 2645 rxcb = ATH12K_SKB_RXCB(msdu); 2646 dma_unmap_single(ab->dev, rxcb->paddr, 2647 msdu->len + skb_tailroom(msdu), 2648 DMA_FROM_DEVICE); 2649 2650 num_buffs_reaped++; 2651 2652 push_reason = le32_get_bits(desc->info0, 2653 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 2654 if (push_reason != 2655 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2656 dev_kfree_skb_any(msdu); 2657 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2658 continue; 2659 } 2660 2661 rxcb->is_first_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2662 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2663 rxcb->is_last_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2664 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2665 rxcb->is_continuation = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2666 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2667 rxcb->mac_id = mac_id; 2668 rxcb->peer_id = le32_get_bits(desc->rx_mpdu_info.peer_meta_data, 2669 RX_MPDU_DESC_META_DATA_PEER_ID); 2670 rxcb->tid = le32_get_bits(desc->rx_mpdu_info.info0, 2671 RX_MPDU_DESC_INFO0_TID); 2672 2673 __skb_queue_tail(&msdu_list, msdu); 2674 2675 if (!rxcb->is_continuation) { 2676 total_msdu_reaped++; 2677 done = true; 2678 } else { 2679 done = false; 2680 } 2681 2682 if (total_msdu_reaped >= budget) 2683 break; 2684 } 2685 2686 /* Hw might have updated the head pointer after we cached it. 2687 * In this case, even though there are entries in the ring we'll 2688 * get rx_desc NULL. Give the read another try with updated cached 2689 * head pointer so that we can reap complete MPDU in the current 2690 * rx processing. 2691 */ 2692 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 2693 ath12k_hal_srng_access_end(ab, srng); 2694 goto try_again; 2695 } 2696 2697 ath12k_hal_srng_access_end(ab, srng); 2698 2699 spin_unlock_bh(&srng->lock); 2700 2701 if (!total_msdu_reaped) 2702 goto exit; 2703 2704 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 2705 num_buffs_reaped); 2706 2707 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2708 ring_id); 2709 2710 exit: 2711 return total_msdu_reaped; 2712 } 2713 2714 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 2715 { 2716 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2717 2718 spin_lock_bh(&rx_tid->ab->base_lock); 2719 if (rx_tid->last_frag_no && 2720 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2721 spin_unlock_bh(&rx_tid->ab->base_lock); 2722 return; 2723 } 2724 ath12k_dp_rx_frags_cleanup(rx_tid, true); 2725 spin_unlock_bh(&rx_tid->ab->base_lock); 2726 } 2727 2728 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 2729 { 2730 struct ath12k_base *ab = ar->ab; 2731 struct crypto_shash *tfm; 2732 struct ath12k_peer *peer; 2733 struct ath12k_dp_rx_tid *rx_tid; 2734 int i; 2735 2736 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2737 if (IS_ERR(tfm)) 2738 return PTR_ERR(tfm); 2739 2740 spin_lock_bh(&ab->base_lock); 2741 2742 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 2743 if (!peer) { 2744 spin_unlock_bh(&ab->base_lock); 2745 crypto_free_shash(tfm); 2746 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 2747 return -ENOENT; 2748 } 2749 2750 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 2751 rx_tid = &peer->rx_tid[i]; 2752 rx_tid->ab = ab; 2753 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 2754 skb_queue_head_init(&rx_tid->rx_frags); 2755 } 2756 2757 peer->tfm_mmic = tfm; 2758 peer->dp_setup_done = true; 2759 spin_unlock_bh(&ab->base_lock); 2760 2761 return 0; 2762 } 2763 2764 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 2765 struct ieee80211_hdr *hdr, u8 *data, 2766 size_t data_len, u8 *mic) 2767 { 2768 SHASH_DESC_ON_STACK(desc, tfm); 2769 u8 mic_hdr[16] = {0}; 2770 u8 tid = 0; 2771 int ret; 2772 2773 if (!tfm) 2774 return -EINVAL; 2775 2776 desc->tfm = tfm; 2777 2778 ret = crypto_shash_setkey(tfm, key, 8); 2779 if (ret) 2780 goto out; 2781 2782 ret = crypto_shash_init(desc); 2783 if (ret) 2784 goto out; 2785 2786 /* TKIP MIC header */ 2787 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 2788 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 2789 if (ieee80211_is_data_qos(hdr->frame_control)) 2790 tid = ieee80211_get_tid(hdr); 2791 mic_hdr[12] = tid; 2792 2793 ret = crypto_shash_update(desc, mic_hdr, 16); 2794 if (ret) 2795 goto out; 2796 ret = crypto_shash_update(desc, data, data_len); 2797 if (ret) 2798 goto out; 2799 ret = crypto_shash_final(desc, mic); 2800 out: 2801 shash_desc_zero(desc); 2802 return ret; 2803 } 2804 2805 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 2806 struct sk_buff *msdu) 2807 { 2808 struct ath12k_base *ab = ar->ab; 2809 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 2810 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 2811 struct ieee80211_key_conf *key_conf; 2812 struct ieee80211_hdr *hdr; 2813 u8 mic[IEEE80211_CCMP_MIC_LEN]; 2814 int head_len, tail_len, ret; 2815 size_t data_len; 2816 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2817 u8 *key, *data; 2818 u8 key_idx; 2819 2820 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 2821 return 0; 2822 2823 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2824 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2825 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 2826 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 2827 2828 if (!is_multicast_ether_addr(hdr->addr1)) 2829 key_idx = peer->ucast_keyidx; 2830 else 2831 key_idx = peer->mcast_keyidx; 2832 2833 key_conf = peer->keys[key_idx]; 2834 2835 data = msdu->data + head_len; 2836 data_len = msdu->len - head_len - tail_len; 2837 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 2838 2839 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 2840 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 2841 goto mic_fail; 2842 2843 return 0; 2844 2845 mic_fail: 2846 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 2847 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 2848 2849 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 2850 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 2851 skb_pull(msdu, hal_rx_desc_sz); 2852 2853 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 2854 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2855 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 2856 ieee80211_rx(ath12k_ar_to_hw(ar), msdu); 2857 return -EINVAL; 2858 } 2859 2860 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 2861 enum hal_encrypt_type enctype, u32 flags) 2862 { 2863 struct ieee80211_hdr *hdr; 2864 size_t hdr_len; 2865 size_t crypto_len; 2866 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2867 2868 if (!flags) 2869 return; 2870 2871 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2872 2873 if (flags & RX_FLAG_MIC_STRIPPED) 2874 skb_trim(msdu, msdu->len - 2875 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2876 2877 if (flags & RX_FLAG_ICV_STRIPPED) 2878 skb_trim(msdu, msdu->len - 2879 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2880 2881 if (flags & RX_FLAG_IV_STRIPPED) { 2882 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2883 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2884 2885 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 2886 msdu->data + hal_rx_desc_sz, hdr_len); 2887 skb_pull(msdu, crypto_len); 2888 } 2889 } 2890 2891 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 2892 struct ath12k_peer *peer, 2893 struct ath12k_dp_rx_tid *rx_tid, 2894 struct sk_buff **defrag_skb) 2895 { 2896 struct ath12k_base *ab = ar->ab; 2897 struct hal_rx_desc *rx_desc; 2898 struct sk_buff *skb, *first_frag, *last_frag; 2899 struct ieee80211_hdr *hdr; 2900 enum hal_encrypt_type enctype; 2901 bool is_decrypted = false; 2902 int msdu_len = 0; 2903 int extra_space; 2904 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2905 2906 first_frag = skb_peek(&rx_tid->rx_frags); 2907 last_frag = skb_peek_tail(&rx_tid->rx_frags); 2908 2909 skb_queue_walk(&rx_tid->rx_frags, skb) { 2910 flags = 0; 2911 rx_desc = (struct hal_rx_desc *)skb->data; 2912 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 2913 2914 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 2915 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 2916 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 2917 rx_desc); 2918 2919 if (is_decrypted) { 2920 if (skb != first_frag) 2921 flags |= RX_FLAG_IV_STRIPPED; 2922 if (skb != last_frag) 2923 flags |= RX_FLAG_ICV_STRIPPED | 2924 RX_FLAG_MIC_STRIPPED; 2925 } 2926 2927 /* RX fragments are always raw packets */ 2928 if (skb != last_frag) 2929 skb_trim(skb, skb->len - FCS_LEN); 2930 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 2931 2932 if (skb != first_frag) 2933 skb_pull(skb, hal_rx_desc_sz + 2934 ieee80211_hdrlen(hdr->frame_control)); 2935 msdu_len += skb->len; 2936 } 2937 2938 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 2939 if (extra_space > 0 && 2940 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 2941 return -ENOMEM; 2942 2943 __skb_unlink(first_frag, &rx_tid->rx_frags); 2944 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 2945 skb_put_data(first_frag, skb->data, skb->len); 2946 dev_kfree_skb_any(skb); 2947 } 2948 2949 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 2950 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 2951 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 2952 2953 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 2954 first_frag = NULL; 2955 2956 *defrag_skb = first_frag; 2957 return 0; 2958 } 2959 2960 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 2961 struct ath12k_dp_rx_tid *rx_tid, 2962 struct sk_buff *defrag_skb) 2963 { 2964 struct ath12k_base *ab = ar->ab; 2965 struct ath12k_dp *dp = &ab->dp; 2966 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 2967 struct hal_reo_entrance_ring *reo_ent_ring; 2968 struct hal_reo_dest_ring *reo_dest_ring; 2969 struct dp_link_desc_bank *link_desc_banks; 2970 struct hal_rx_msdu_link *msdu_link; 2971 struct hal_rx_msdu_details *msdu0; 2972 struct hal_srng *srng; 2973 dma_addr_t link_paddr, buf_paddr; 2974 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 2975 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi; 2976 int ret; 2977 struct ath12k_rx_desc_info *desc_info; 2978 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm; 2979 u8 dst_ind; 2980 2981 hal_rx_desc_sz = ab->hal.hal_desc_sz; 2982 link_desc_banks = dp->link_desc_banks; 2983 reo_dest_ring = rx_tid->dst_ring_desc; 2984 2985 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 2986 &link_paddr, &cookie); 2987 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 2988 2989 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 2990 (link_paddr - link_desc_banks[desc_bank].paddr)); 2991 msdu0 = &msdu_link->msdu_link[0]; 2992 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 2993 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 2994 2995 memset(msdu0, 0, sizeof(*msdu0)); 2996 2997 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 2998 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 2999 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3000 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3001 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3002 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3003 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3004 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3005 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3006 3007 /* change msdu len in hal rx desc */ 3008 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3009 3010 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3011 defrag_skb->len + skb_tailroom(defrag_skb), 3012 DMA_TO_DEVICE); 3013 if (dma_mapping_error(ab->dev, buf_paddr)) 3014 return -ENOMEM; 3015 3016 spin_lock_bh(&dp->rx_desc_lock); 3017 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3018 struct ath12k_rx_desc_info, 3019 list); 3020 if (!desc_info) { 3021 spin_unlock_bh(&dp->rx_desc_lock); 3022 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3023 ret = -ENOMEM; 3024 goto err_unmap_dma; 3025 } 3026 3027 desc_info->skb = defrag_skb; 3028 desc_info->in_use = true; 3029 3030 list_del(&desc_info->list); 3031 spin_unlock_bh(&dp->rx_desc_lock); 3032 3033 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3034 3035 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3036 desc_info->cookie, 3037 HAL_RX_BUF_RBM_SW3_BM); 3038 3039 /* Fill mpdu details into reo entrance ring */ 3040 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3041 3042 spin_lock_bh(&srng->lock); 3043 ath12k_hal_srng_access_begin(ab, srng); 3044 3045 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3046 if (!reo_ent_ring) { 3047 ath12k_hal_srng_access_end(ab, srng); 3048 spin_unlock_bh(&srng->lock); 3049 ret = -ENOSPC; 3050 goto err_free_desc; 3051 } 3052 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3053 3054 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3055 cookie, 3056 idle_link_rbm); 3057 3058 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3059 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3060 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3061 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3062 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3063 3064 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3065 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3066 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3067 3068 reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr)); 3069 queue_addr_hi = upper_32_bits(rx_tid->paddr); 3070 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi, 3071 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) | 3072 le32_encode_bits(dst_ind, 3073 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3074 3075 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3076 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3077 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3078 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3079 reo_ent_ring->info2 = 3080 cpu_to_le32(u32_get_bits(dest_ring_info0, 3081 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3082 3083 ath12k_hal_srng_access_end(ab, srng); 3084 spin_unlock_bh(&srng->lock); 3085 3086 return 0; 3087 3088 err_free_desc: 3089 spin_lock_bh(&dp->rx_desc_lock); 3090 desc_info->in_use = false; 3091 desc_info->skb = NULL; 3092 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3093 spin_unlock_bh(&dp->rx_desc_lock); 3094 err_unmap_dma: 3095 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3096 DMA_TO_DEVICE); 3097 return ret; 3098 } 3099 3100 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3101 struct sk_buff *a, struct sk_buff *b) 3102 { 3103 int frag1, frag2; 3104 3105 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3106 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3107 3108 return frag1 - frag2; 3109 } 3110 3111 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3112 struct sk_buff_head *frag_list, 3113 struct sk_buff *cur_frag) 3114 { 3115 struct sk_buff *skb; 3116 int cmp; 3117 3118 skb_queue_walk(frag_list, skb) { 3119 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3120 if (cmp < 0) 3121 continue; 3122 __skb_queue_before(frag_list, skb, cur_frag); 3123 return; 3124 } 3125 __skb_queue_tail(frag_list, cur_frag); 3126 } 3127 3128 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3129 { 3130 struct ieee80211_hdr *hdr; 3131 u64 pn = 0; 3132 u8 *ehdr; 3133 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3134 3135 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3136 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3137 3138 pn = ehdr[0]; 3139 pn |= (u64)ehdr[1] << 8; 3140 pn |= (u64)ehdr[4] << 16; 3141 pn |= (u64)ehdr[5] << 24; 3142 pn |= (u64)ehdr[6] << 32; 3143 pn |= (u64)ehdr[7] << 40; 3144 3145 return pn; 3146 } 3147 3148 static bool 3149 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3150 { 3151 struct ath12k_base *ab = ar->ab; 3152 enum hal_encrypt_type encrypt_type; 3153 struct sk_buff *first_frag, *skb; 3154 struct hal_rx_desc *desc; 3155 u64 last_pn; 3156 u64 cur_pn; 3157 3158 first_frag = skb_peek(&rx_tid->rx_frags); 3159 desc = (struct hal_rx_desc *)first_frag->data; 3160 3161 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3162 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3163 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3164 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3165 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3166 return true; 3167 3168 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3169 skb_queue_walk(&rx_tid->rx_frags, skb) { 3170 if (skb == first_frag) 3171 continue; 3172 3173 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3174 if (cur_pn != last_pn + 1) 3175 return false; 3176 last_pn = cur_pn; 3177 } 3178 return true; 3179 } 3180 3181 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3182 struct sk_buff *msdu, 3183 struct hal_reo_dest_ring *ring_desc) 3184 { 3185 struct ath12k_base *ab = ar->ab; 3186 struct hal_rx_desc *rx_desc; 3187 struct ath12k_peer *peer; 3188 struct ath12k_dp_rx_tid *rx_tid; 3189 struct sk_buff *defrag_skb = NULL; 3190 u32 peer_id; 3191 u16 seqno, frag_no; 3192 u8 tid; 3193 int ret = 0; 3194 bool more_frags; 3195 3196 rx_desc = (struct hal_rx_desc *)msdu->data; 3197 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3198 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3199 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3200 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3201 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3202 3203 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3204 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3205 tid > IEEE80211_NUM_TIDS) 3206 return -EINVAL; 3207 3208 /* received unfragmented packet in reo 3209 * exception ring, this shouldn't happen 3210 * as these packets typically come from 3211 * reo2sw srngs. 3212 */ 3213 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3214 return -EINVAL; 3215 3216 spin_lock_bh(&ab->base_lock); 3217 peer = ath12k_peer_find_by_id(ab, peer_id); 3218 if (!peer) { 3219 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3220 peer_id); 3221 ret = -ENOENT; 3222 goto out_unlock; 3223 } 3224 3225 if (!peer->dp_setup_done) { 3226 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3227 peer->addr, peer_id); 3228 ret = -ENOENT; 3229 goto out_unlock; 3230 } 3231 3232 rx_tid = &peer->rx_tid[tid]; 3233 3234 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3235 skb_queue_empty(&rx_tid->rx_frags)) { 3236 /* Flush stored fragments and start a new sequence */ 3237 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3238 rx_tid->cur_sn = seqno; 3239 } 3240 3241 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3242 /* Fragment already present */ 3243 ret = -EINVAL; 3244 goto out_unlock; 3245 } 3246 3247 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3248 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3249 else 3250 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3251 3252 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3253 if (!more_frags) 3254 rx_tid->last_frag_no = frag_no; 3255 3256 if (frag_no == 0) { 3257 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3258 sizeof(*rx_tid->dst_ring_desc), 3259 GFP_ATOMIC); 3260 if (!rx_tid->dst_ring_desc) { 3261 ret = -ENOMEM; 3262 goto out_unlock; 3263 } 3264 } else { 3265 ath12k_dp_rx_link_desc_return(ab, ring_desc, 3266 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3267 } 3268 3269 if (!rx_tid->last_frag_no || 3270 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3271 mod_timer(&rx_tid->frag_timer, jiffies + 3272 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3273 goto out_unlock; 3274 } 3275 3276 spin_unlock_bh(&ab->base_lock); 3277 del_timer_sync(&rx_tid->frag_timer); 3278 spin_lock_bh(&ab->base_lock); 3279 3280 peer = ath12k_peer_find_by_id(ab, peer_id); 3281 if (!peer) 3282 goto err_frags_cleanup; 3283 3284 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3285 goto err_frags_cleanup; 3286 3287 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3288 goto err_frags_cleanup; 3289 3290 if (!defrag_skb) 3291 goto err_frags_cleanup; 3292 3293 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3294 goto err_frags_cleanup; 3295 3296 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3297 goto out_unlock; 3298 3299 err_frags_cleanup: 3300 dev_kfree_skb_any(defrag_skb); 3301 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3302 out_unlock: 3303 spin_unlock_bh(&ab->base_lock); 3304 return ret; 3305 } 3306 3307 static int 3308 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3309 struct list_head *used_list, 3310 bool drop, u32 cookie) 3311 { 3312 struct ath12k_base *ab = ar->ab; 3313 struct sk_buff *msdu; 3314 struct ath12k_skb_rxcb *rxcb; 3315 struct hal_rx_desc *rx_desc; 3316 u16 msdu_len; 3317 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3318 struct ath12k_rx_desc_info *desc_info; 3319 u64 desc_va; 3320 3321 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3322 le32_to_cpu(desc->buf_va_lo)); 3323 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3324 3325 /* retry manual desc retrieval */ 3326 if (!desc_info) { 3327 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3328 if (!desc_info) { 3329 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n", 3330 cookie); 3331 return -EINVAL; 3332 } 3333 } 3334 3335 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3336 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3337 3338 msdu = desc_info->skb; 3339 desc_info->skb = NULL; 3340 3341 list_add_tail(&desc_info->list, used_list); 3342 3343 rxcb = ATH12K_SKB_RXCB(msdu); 3344 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3345 msdu->len + skb_tailroom(msdu), 3346 DMA_FROM_DEVICE); 3347 3348 if (drop) { 3349 dev_kfree_skb_any(msdu); 3350 return 0; 3351 } 3352 3353 rcu_read_lock(); 3354 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3355 dev_kfree_skb_any(msdu); 3356 goto exit; 3357 } 3358 3359 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3360 dev_kfree_skb_any(msdu); 3361 goto exit; 3362 } 3363 3364 rx_desc = (struct hal_rx_desc *)msdu->data; 3365 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3366 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3367 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3368 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3369 sizeof(*rx_desc)); 3370 dev_kfree_skb_any(msdu); 3371 goto exit; 3372 } 3373 3374 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3375 3376 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3377 dev_kfree_skb_any(msdu); 3378 ath12k_dp_rx_link_desc_return(ar->ab, desc, 3379 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3380 } 3381 exit: 3382 rcu_read_unlock(); 3383 return 0; 3384 } 3385 3386 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3387 int budget) 3388 { 3389 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3390 struct dp_link_desc_bank *link_desc_banks; 3391 enum hal_rx_buf_return_buf_manager rbm; 3392 struct hal_rx_msdu_link *link_desc_va; 3393 int tot_n_bufs_reaped, quota, ret, i; 3394 struct hal_reo_dest_ring *reo_desc; 3395 struct dp_rxdma_ring *rx_ring; 3396 struct dp_srng *reo_except; 3397 LIST_HEAD(rx_desc_used_list); 3398 u32 desc_bank, num_msdus; 3399 struct hal_srng *srng; 3400 struct ath12k_dp *dp; 3401 int mac_id; 3402 struct ath12k *ar; 3403 dma_addr_t paddr; 3404 bool is_frag; 3405 bool drop = false; 3406 int pdev_id; 3407 3408 tot_n_bufs_reaped = 0; 3409 quota = budget; 3410 3411 dp = &ab->dp; 3412 reo_except = &dp->reo_except_ring; 3413 link_desc_banks = dp->link_desc_banks; 3414 3415 srng = &ab->hal.srng_list[reo_except->ring_id]; 3416 3417 spin_lock_bh(&srng->lock); 3418 3419 ath12k_hal_srng_access_begin(ab, srng); 3420 3421 while (budget && 3422 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3423 ab->soc_stats.err_ring_pkts++; 3424 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3425 &desc_bank); 3426 if (ret) { 3427 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3428 ret); 3429 continue; 3430 } 3431 link_desc_va = link_desc_banks[desc_bank].vaddr + 3432 (paddr - link_desc_banks[desc_bank].paddr); 3433 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3434 &rbm); 3435 if (rbm != dp->idle_link_rbm && 3436 rbm != HAL_RX_BUF_RBM_SW3_BM && 3437 rbm != ab->hw_params->hal_params->rx_buf_rbm) { 3438 ab->soc_stats.invalid_rbm++; 3439 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3440 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3441 HAL_WBM_REL_BM_ACT_REL_MSDU); 3442 continue; 3443 } 3444 3445 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3446 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3447 3448 /* Process only rx fragments with one msdu per link desc below, and drop 3449 * msdu's indicated due to error reasons. 3450 */ 3451 if (!is_frag || num_msdus > 1) { 3452 drop = true; 3453 /* Return the link desc back to wbm idle list */ 3454 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3455 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3456 } 3457 3458 for (i = 0; i < num_msdus; i++) { 3459 mac_id = le32_get_bits(reo_desc->info0, 3460 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3461 3462 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3463 ar = ab->pdevs[pdev_id].ar; 3464 3465 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, 3466 &rx_desc_used_list, 3467 drop, 3468 msdu_cookies[i])) 3469 tot_n_bufs_reaped++; 3470 } 3471 3472 if (tot_n_bufs_reaped >= quota) { 3473 tot_n_bufs_reaped = quota; 3474 goto exit; 3475 } 3476 3477 budget = quota - tot_n_bufs_reaped; 3478 } 3479 3480 exit: 3481 ath12k_hal_srng_access_end(ab, srng); 3482 3483 spin_unlock_bh(&srng->lock); 3484 3485 rx_ring = &dp->rx_refill_buf_ring; 3486 3487 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3488 tot_n_bufs_reaped); 3489 3490 return tot_n_bufs_reaped; 3491 } 3492 3493 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3494 int msdu_len, 3495 struct sk_buff_head *msdu_list) 3496 { 3497 struct sk_buff *skb, *tmp; 3498 struct ath12k_skb_rxcb *rxcb; 3499 int n_buffs; 3500 3501 n_buffs = DIV_ROUND_UP(msdu_len, 3502 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz)); 3503 3504 skb_queue_walk_safe(msdu_list, skb, tmp) { 3505 rxcb = ATH12K_SKB_RXCB(skb); 3506 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3507 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3508 if (!n_buffs) 3509 break; 3510 __skb_unlink(skb, msdu_list); 3511 dev_kfree_skb_any(skb); 3512 n_buffs--; 3513 } 3514 } 3515 } 3516 3517 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 3518 struct ieee80211_rx_status *status, 3519 struct sk_buff_head *msdu_list) 3520 { 3521 struct ath12k_base *ab = ar->ab; 3522 u16 msdu_len; 3523 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3524 u8 l3pad_bytes; 3525 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3526 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3527 3528 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3529 3530 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3531 /* First buffer will be freed by the caller, so deduct it's length */ 3532 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3533 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3534 return -EINVAL; 3535 } 3536 3537 /* Even after cleaning up the sg buffers in the msdu list with above check 3538 * any msdu received with continuation flag needs to be dropped as invalid. 3539 * This protects against some random err frame with continuation flag. 3540 */ 3541 if (rxcb->is_continuation) 3542 return -EINVAL; 3543 3544 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 3545 ath12k_warn(ar->ab, 3546 "msdu_done bit not set in null_q_des processing\n"); 3547 __skb_queue_purge(msdu_list); 3548 return -EIO; 3549 } 3550 3551 /* Handle NULL queue descriptor violations arising out a missing 3552 * REO queue for a given peer or a given TID. This typically 3553 * may happen if a packet is received on a QOS enabled TID before the 3554 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3555 * it may also happen for MC/BC frames if they are not routed to the 3556 * non-QOS TID queue, in the absence of any other default TID queue. 3557 * This error can show up both in a REO destination or WBM release ring. 3558 */ 3559 3560 if (rxcb->is_frag) { 3561 skb_pull(msdu, hal_rx_desc_sz); 3562 } else { 3563 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3564 3565 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3566 return -EINVAL; 3567 3568 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3569 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3570 } 3571 ath12k_dp_rx_h_ppdu(ar, desc, status); 3572 3573 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status); 3574 3575 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc); 3576 3577 /* Please note that caller will having the access to msdu and completing 3578 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3579 */ 3580 3581 return 0; 3582 } 3583 3584 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 3585 struct ieee80211_rx_status *status, 3586 struct sk_buff_head *msdu_list) 3587 { 3588 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3589 bool drop = false; 3590 3591 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3592 3593 switch (rxcb->err_code) { 3594 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3595 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3596 drop = true; 3597 break; 3598 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3599 /* TODO: Do not drop PN failed packets in the driver; 3600 * instead, it is good to drop such packets in mac80211 3601 * after incrementing the replay counters. 3602 */ 3603 fallthrough; 3604 default: 3605 /* TODO: Review other errors and process them to mac80211 3606 * as appropriate. 3607 */ 3608 drop = true; 3609 break; 3610 } 3611 3612 return drop; 3613 } 3614 3615 static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 3616 struct ieee80211_rx_status *status) 3617 { 3618 struct ath12k_base *ab = ar->ab; 3619 u16 msdu_len; 3620 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3621 u8 l3pad_bytes; 3622 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3623 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3624 3625 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 3626 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 3627 3628 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3629 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3630 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3631 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3632 3633 ath12k_dp_rx_h_ppdu(ar, desc, status); 3634 3635 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3636 RX_FLAG_DECRYPTED); 3637 3638 ath12k_dp_rx_h_undecap(ar, msdu, desc, 3639 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3640 } 3641 3642 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 3643 struct ieee80211_rx_status *status) 3644 { 3645 struct ath12k_base *ab = ar->ab; 3646 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3647 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3648 bool drop = false; 3649 u32 err_bitmap; 3650 3651 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3652 3653 switch (rxcb->err_code) { 3654 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 3655 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3656 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 3657 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 3658 ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3659 break; 3660 } 3661 fallthrough; 3662 default: 3663 /* TODO: Review other rxdma error code to check if anything is 3664 * worth reporting to mac80211 3665 */ 3666 drop = true; 3667 break; 3668 } 3669 3670 return drop; 3671 } 3672 3673 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 3674 struct napi_struct *napi, 3675 struct sk_buff *msdu, 3676 struct sk_buff_head *msdu_list) 3677 { 3678 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3679 struct ieee80211_rx_status rxs = {0}; 3680 bool drop = true; 3681 3682 switch (rxcb->err_rel_src) { 3683 case HAL_WBM_REL_SRC_MODULE_REO: 3684 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3685 break; 3686 case HAL_WBM_REL_SRC_MODULE_RXDMA: 3687 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3688 break; 3689 default: 3690 /* msdu will get freed */ 3691 break; 3692 } 3693 3694 if (drop) { 3695 dev_kfree_skb_any(msdu); 3696 return; 3697 } 3698 3699 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 3700 } 3701 3702 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 3703 struct napi_struct *napi, int budget) 3704 { 3705 LIST_HEAD(rx_desc_used_list); 3706 struct ath12k *ar; 3707 struct ath12k_dp *dp = &ab->dp; 3708 struct dp_rxdma_ring *rx_ring; 3709 struct hal_rx_wbm_rel_info err_info; 3710 struct hal_srng *srng; 3711 struct sk_buff *msdu; 3712 struct sk_buff_head msdu_list, scatter_msdu_list; 3713 struct ath12k_skb_rxcb *rxcb; 3714 void *rx_desc; 3715 u8 mac_id; 3716 int num_buffs_reaped = 0; 3717 struct ath12k_rx_desc_info *desc_info; 3718 int ret, pdev_id; 3719 struct hal_rx_desc *msdu_data; 3720 3721 __skb_queue_head_init(&msdu_list); 3722 __skb_queue_head_init(&scatter_msdu_list); 3723 3724 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3725 rx_ring = &dp->rx_refill_buf_ring; 3726 spin_lock_bh(&srng->lock); 3727 3728 ath12k_hal_srng_access_begin(ab, srng); 3729 3730 while (budget) { 3731 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 3732 if (!rx_desc) 3733 break; 3734 3735 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3736 if (ret) { 3737 ath12k_warn(ab, 3738 "failed to parse rx error in wbm_rel ring desc %d\n", 3739 ret); 3740 continue; 3741 } 3742 3743 desc_info = err_info.rx_desc; 3744 3745 /* retry manual desc retrieval if hw cc is not done */ 3746 if (!desc_info) { 3747 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 3748 if (!desc_info) { 3749 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n", 3750 err_info.cookie); 3751 continue; 3752 } 3753 } 3754 3755 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3756 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 3757 3758 msdu = desc_info->skb; 3759 desc_info->skb = NULL; 3760 3761 list_add_tail(&desc_info->list, &rx_desc_used_list); 3762 3763 rxcb = ATH12K_SKB_RXCB(msdu); 3764 dma_unmap_single(ab->dev, rxcb->paddr, 3765 msdu->len + skb_tailroom(msdu), 3766 DMA_FROM_DEVICE); 3767 3768 num_buffs_reaped++; 3769 3770 if (!err_info.continuation) 3771 budget--; 3772 3773 if (err_info.push_reason != 3774 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3775 dev_kfree_skb_any(msdu); 3776 continue; 3777 } 3778 3779 msdu_data = (struct hal_rx_desc *)msdu->data; 3780 rxcb->err_rel_src = err_info.err_rel_src; 3781 rxcb->err_code = err_info.err_code; 3782 rxcb->is_first_msdu = err_info.first_msdu; 3783 rxcb->is_last_msdu = err_info.last_msdu; 3784 rxcb->is_continuation = err_info.continuation; 3785 rxcb->rx_desc = msdu_data; 3786 3787 if (err_info.continuation) { 3788 __skb_queue_tail(&scatter_msdu_list, msdu); 3789 continue; 3790 } 3791 3792 mac_id = ath12k_dp_rx_get_msdu_src_link(ab, 3793 msdu_data); 3794 if (mac_id >= MAX_RADIOS) { 3795 dev_kfree_skb_any(msdu); 3796 3797 /* In any case continuation bit is set 3798 * in the previous record, cleanup scatter_msdu_list 3799 */ 3800 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 3801 continue; 3802 } 3803 3804 if (!skb_queue_empty(&scatter_msdu_list)) { 3805 struct sk_buff *msdu; 3806 3807 skb_queue_walk(&scatter_msdu_list, msdu) { 3808 rxcb = ATH12K_SKB_RXCB(msdu); 3809 rxcb->mac_id = mac_id; 3810 } 3811 3812 skb_queue_splice_tail_init(&scatter_msdu_list, 3813 &msdu_list); 3814 } 3815 3816 rxcb = ATH12K_SKB_RXCB(msdu); 3817 rxcb->mac_id = mac_id; 3818 __skb_queue_tail(&msdu_list, msdu); 3819 } 3820 3821 /* In any case continuation bit is set in the 3822 * last record, cleanup scatter_msdu_list 3823 */ 3824 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 3825 3826 ath12k_hal_srng_access_end(ab, srng); 3827 3828 spin_unlock_bh(&srng->lock); 3829 3830 if (!num_buffs_reaped) 3831 goto done; 3832 3833 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3834 num_buffs_reaped); 3835 3836 rcu_read_lock(); 3837 while ((msdu = __skb_dequeue(&msdu_list))) { 3838 rxcb = ATH12K_SKB_RXCB(msdu); 3839 mac_id = rxcb->mac_id; 3840 3841 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3842 ar = ab->pdevs[pdev_id].ar; 3843 3844 if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) { 3845 dev_kfree_skb_any(msdu); 3846 continue; 3847 } 3848 3849 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3850 dev_kfree_skb_any(msdu); 3851 continue; 3852 } 3853 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); 3854 } 3855 rcu_read_unlock(); 3856 done: 3857 return num_buffs_reaped; 3858 } 3859 3860 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 3861 { 3862 struct ath12k_dp *dp = &ab->dp; 3863 struct hal_tlv_64_hdr *hdr; 3864 struct hal_srng *srng; 3865 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 3866 bool found = false; 3867 u16 tag; 3868 struct hal_reo_status reo_status; 3869 3870 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 3871 3872 memset(&reo_status, 0, sizeof(reo_status)); 3873 3874 spin_lock_bh(&srng->lock); 3875 3876 ath12k_hal_srng_access_begin(ab, srng); 3877 3878 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3879 tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 3880 3881 switch (tag) { 3882 case HAL_REO_GET_QUEUE_STATS_STATUS: 3883 ath12k_hal_reo_status_queue_stats(ab, hdr, 3884 &reo_status); 3885 break; 3886 case HAL_REO_FLUSH_QUEUE_STATUS: 3887 ath12k_hal_reo_flush_queue_status(ab, hdr, 3888 &reo_status); 3889 break; 3890 case HAL_REO_FLUSH_CACHE_STATUS: 3891 ath12k_hal_reo_flush_cache_status(ab, hdr, 3892 &reo_status); 3893 break; 3894 case HAL_REO_UNBLOCK_CACHE_STATUS: 3895 ath12k_hal_reo_unblk_cache_status(ab, hdr, 3896 &reo_status); 3897 break; 3898 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 3899 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 3900 &reo_status); 3901 break; 3902 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 3903 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 3904 &reo_status); 3905 break; 3906 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 3907 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 3908 &reo_status); 3909 break; 3910 default: 3911 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 3912 continue; 3913 } 3914 3915 spin_lock_bh(&dp->reo_cmd_lock); 3916 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 3917 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 3918 found = true; 3919 list_del(&cmd->list); 3920 break; 3921 } 3922 } 3923 spin_unlock_bh(&dp->reo_cmd_lock); 3924 3925 if (found) { 3926 cmd->handler(dp, (void *)&cmd->data, 3927 reo_status.uniform_hdr.cmd_status); 3928 kfree(cmd); 3929 } 3930 3931 found = false; 3932 } 3933 3934 ath12k_hal_srng_access_end(ab, srng); 3935 3936 spin_unlock_bh(&srng->lock); 3937 } 3938 3939 void ath12k_dp_rx_free(struct ath12k_base *ab) 3940 { 3941 struct ath12k_dp *dp = &ab->dp; 3942 int i; 3943 3944 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 3945 3946 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 3947 if (ab->hw_params->rx_mac_buf_ring) 3948 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 3949 } 3950 3951 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 3952 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 3953 3954 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 3955 3956 ath12k_dp_rxdma_buf_free(ab); 3957 } 3958 3959 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 3960 { 3961 struct ath12k *ar = ab->pdevs[mac_id].ar; 3962 3963 ath12k_dp_rx_pdev_srng_free(ar); 3964 } 3965 3966 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 3967 { 3968 struct ath12k_dp *dp = &ab->dp; 3969 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 3970 u32 ring_id; 3971 int ret; 3972 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3973 3974 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 3975 3976 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 3977 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 3978 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 3979 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 3980 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 3981 tlv_filter.offset_valid = true; 3982 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 3983 3984 tlv_filter.rx_mpdu_start_offset = 3985 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 3986 tlv_filter.rx_msdu_end_offset = 3987 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 3988 3989 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 3990 tlv_filter.rx_mpdu_start_wmask = 3991 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); 3992 tlv_filter.rx_msdu_end_wmask = 3993 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); 3994 ath12k_dbg(ab, ATH12K_DBG_DATA, 3995 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", 3996 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); 3997 } 3998 3999 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 4000 HAL_RXDMA_BUF, 4001 DP_RXDMA_REFILL_RING_SIZE, 4002 &tlv_filter); 4003 4004 return ret; 4005 } 4006 4007 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 4008 { 4009 struct ath12k_dp *dp = &ab->dp; 4010 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4011 u32 ring_id; 4012 int ret = 0; 4013 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4014 int i; 4015 4016 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4017 4018 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4019 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4020 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4021 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4022 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4023 tlv_filter.offset_valid = true; 4024 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4025 4026 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4027 4028 tlv_filter.rx_mpdu_start_offset = 4029 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4030 tlv_filter.rx_msdu_end_offset = 4031 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4032 4033 /* TODO: Selectively subscribe to required qwords within msdu_end 4034 * and mpdu_start and setup the mask in below msg 4035 * and modify the rx_desc struct 4036 */ 4037 4038 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4039 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4040 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4041 HAL_RXDMA_BUF, 4042 DP_RXDMA_REFILL_RING_SIZE, 4043 &tlv_filter); 4044 } 4045 4046 return ret; 4047 } 4048 4049 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4050 { 4051 struct ath12k_dp *dp = &ab->dp; 4052 u32 ring_id; 4053 int i, ret; 4054 4055 /* TODO: Need to verify the HTT setup for QCN9224 */ 4056 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4057 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4058 if (ret) { 4059 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4060 ret); 4061 return ret; 4062 } 4063 4064 if (ab->hw_params->rx_mac_buf_ring) { 4065 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4066 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4067 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4068 i, HAL_RXDMA_BUF); 4069 if (ret) { 4070 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4071 i, ret); 4072 return ret; 4073 } 4074 } 4075 } 4076 4077 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4078 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4079 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4080 i, HAL_RXDMA_DST); 4081 if (ret) { 4082 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4083 i, ret); 4084 return ret; 4085 } 4086 } 4087 4088 if (ab->hw_params->rxdma1_enable) { 4089 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4090 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4091 0, HAL_RXDMA_MONITOR_BUF); 4092 if (ret) { 4093 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4094 ret); 4095 return ret; 4096 } 4097 } 4098 4099 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4100 if (ret) { 4101 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4102 return ret; 4103 } 4104 4105 return 0; 4106 } 4107 4108 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4109 { 4110 struct ath12k_dp *dp = &ab->dp; 4111 int i, ret; 4112 4113 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4114 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4115 4116 ret = ath12k_dp_srng_setup(ab, 4117 &dp->rx_refill_buf_ring.refill_buf_ring, 4118 HAL_RXDMA_BUF, 0, 0, 4119 DP_RXDMA_BUF_RING_SIZE); 4120 if (ret) { 4121 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4122 return ret; 4123 } 4124 4125 if (ab->hw_params->rx_mac_buf_ring) { 4126 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4127 ret = ath12k_dp_srng_setup(ab, 4128 &dp->rx_mac_buf_ring[i], 4129 HAL_RXDMA_BUF, 1, 4130 i, DP_RX_MAC_BUF_RING_SIZE); 4131 if (ret) { 4132 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4133 i); 4134 return ret; 4135 } 4136 } 4137 } 4138 4139 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4140 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4141 HAL_RXDMA_DST, 0, i, 4142 DP_RXDMA_ERR_DST_RING_SIZE); 4143 if (ret) { 4144 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4145 return ret; 4146 } 4147 } 4148 4149 if (ab->hw_params->rxdma1_enable) { 4150 ret = ath12k_dp_srng_setup(ab, 4151 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4152 HAL_RXDMA_MONITOR_BUF, 0, 0, 4153 DP_RXDMA_MONITOR_BUF_RING_SIZE); 4154 if (ret) { 4155 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4156 return ret; 4157 } 4158 } 4159 4160 ret = ath12k_dp_rxdma_buf_setup(ab); 4161 if (ret) { 4162 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4163 return ret; 4164 } 4165 4166 return 0; 4167 } 4168 4169 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4170 { 4171 struct ath12k *ar = ab->pdevs[mac_id].ar; 4172 struct ath12k_pdev_dp *dp = &ar->dp; 4173 u32 ring_id; 4174 int i; 4175 int ret; 4176 4177 if (!ab->hw_params->rxdma1_enable) 4178 goto out; 4179 4180 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4181 if (ret) { 4182 ath12k_warn(ab, "failed to setup rx srngs\n"); 4183 return ret; 4184 } 4185 4186 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4187 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4188 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4189 mac_id + i, 4190 HAL_RXDMA_MONITOR_DST); 4191 if (ret) { 4192 ath12k_warn(ab, 4193 "failed to configure rxdma_mon_dst_ring %d %d\n", 4194 i, ret); 4195 return ret; 4196 } 4197 } 4198 out: 4199 return 0; 4200 } 4201 4202 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4203 { 4204 struct ath12k_pdev_dp *dp = &ar->dp; 4205 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4206 4207 skb_queue_head_init(&pmon->rx_status_q); 4208 4209 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4210 4211 memset(&pmon->rx_mon_stats, 0, 4212 sizeof(pmon->rx_mon_stats)); 4213 return 0; 4214 } 4215 4216 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4217 { 4218 struct ath12k_pdev_dp *dp = &ar->dp; 4219 struct ath12k_mon_data *pmon = &dp->mon_data; 4220 int ret = 0; 4221 4222 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4223 if (ret) { 4224 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4225 return ret; 4226 } 4227 4228 /* if rxdma1_enable is false, no need to setup 4229 * rxdma_mon_desc_ring. 4230 */ 4231 if (!ar->ab->hw_params->rxdma1_enable) 4232 return 0; 4233 4234 pmon->mon_last_linkdesc_paddr = 0; 4235 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4236 spin_lock_init(&pmon->mon_lock); 4237 4238 return 0; 4239 } 4240