1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 #include "debugfs_htt_stats.h" 21 22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 23 24 static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 25 struct ath12k_dp_rx_tid_rxq *rx_tid); 26 27 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 28 struct hal_rx_desc *desc) 29 { 30 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) 31 return HAL_ENCRYPT_TYPE_OPEN; 32 33 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); 34 } 35 36 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 37 struct hal_rx_desc *desc) 38 { 39 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); 40 } 41 42 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 43 struct hal_rx_desc *desc) 44 { 45 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); 46 } 47 48 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 49 struct hal_rx_desc *desc) 50 { 51 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 52 } 53 54 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 55 struct hal_rx_desc *desc) 56 { 57 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); 58 } 59 60 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 61 struct sk_buff *skb) 62 { 63 struct ieee80211_hdr *hdr; 64 65 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 66 return ieee80211_has_morefrags(hdr->frame_control); 67 } 68 69 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 70 struct sk_buff *skb) 71 { 72 struct ieee80211_hdr *hdr; 73 74 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 75 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 76 } 77 78 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 79 struct hal_rx_desc *desc) 80 { 81 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc); 82 } 83 84 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 85 struct hal_rx_desc *desc) 86 { 87 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc); 88 } 89 90 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 91 struct hal_rx_desc *desc) 92 { 93 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc); 94 } 95 96 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 97 struct hal_rx_desc *desc) 98 { 99 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc); 100 } 101 102 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 103 struct hal_rx_desc *desc) 104 { 105 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc); 106 } 107 108 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 109 struct hal_rx_desc *desc) 110 { 111 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc); 112 } 113 114 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 115 struct hal_rx_desc *desc) 116 { 117 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc); 118 } 119 120 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 121 struct hal_rx_desc *desc) 122 { 123 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc); 124 } 125 126 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 127 struct hal_rx_desc *desc) 128 { 129 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc); 130 } 131 132 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 133 struct hal_rx_desc *desc) 134 { 135 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc); 136 } 137 138 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 139 struct hal_rx_desc *desc) 140 { 141 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc); 142 } 143 144 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 145 struct hal_rx_desc *desc) 146 { 147 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc); 148 } 149 150 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 151 struct hal_rx_desc *desc) 152 { 153 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc)); 154 } 155 156 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 157 struct hal_rx_desc *desc) 158 { 159 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc); 160 } 161 162 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 163 struct hal_rx_desc *desc) 164 { 165 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc); 166 } 167 168 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 169 struct hal_rx_desc *desc) 170 { 171 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc); 172 } 173 174 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 175 struct hal_rx_desc *desc) 176 { 177 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc); 178 } 179 180 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 181 struct hal_rx_desc *desc) 182 { 183 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc); 184 } 185 186 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 187 struct hal_rx_desc *fdesc, 188 struct hal_rx_desc *ldesc) 189 { 190 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 191 } 192 193 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 194 struct hal_rx_desc *desc, 195 u16 len) 196 { 197 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len); 198 } 199 200 u32 ath12k_dp_rxdesc_get_ppduid(struct ath12k_base *ab, 201 struct hal_rx_desc *rx_desc) 202 { 203 return ab->hal_rx_ops->rx_desc_get_mpdu_ppdu_id(rx_desc); 204 } 205 206 bool ath12k_dp_rxdesc_mpdu_valid(struct ath12k_base *ab, 207 struct hal_rx_desc *rx_desc) 208 { 209 u32 tlv_tag; 210 211 tlv_tag = ab->hal_rx_ops->rx_desc_get_mpdu_start_tag(rx_desc); 212 213 return tlv_tag == HAL_RX_MPDU_START; 214 } 215 216 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 217 struct hal_rx_desc *desc) 218 { 219 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 220 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc)); 221 } 222 223 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 224 struct hal_rx_desc *desc) 225 { 226 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc); 227 } 228 229 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 230 struct hal_rx_desc *desc) 231 { 232 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc); 233 } 234 235 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 236 struct hal_rx_desc *desc, 237 struct ieee80211_hdr *hdr) 238 { 239 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr); 240 } 241 242 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 243 struct hal_rx_desc *desc, 244 u8 *crypto_hdr, 245 enum hal_encrypt_type enctype) 246 { 247 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 248 } 249 250 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, 251 struct hal_rx_desc *desc) 252 { 253 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc); 254 } 255 256 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list) 257 { 258 struct sk_buff *skb; 259 260 while ((skb = __skb_dequeue(skb_list))) 261 dev_kfree_skb_any(skb); 262 } 263 264 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 265 struct list_head *head, 266 size_t count) 267 { 268 struct list_head *cur; 269 struct ath12k_rx_desc_info *rx_desc; 270 size_t nodes = 0; 271 272 if (!count) { 273 INIT_LIST_HEAD(list); 274 goto out; 275 } 276 277 list_for_each(cur, head) { 278 if (!count) 279 break; 280 281 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 282 rx_desc->in_use = true; 283 284 count--; 285 nodes++; 286 } 287 288 list_cut_before(list, head, cur); 289 out: 290 return nodes; 291 } 292 293 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 294 struct list_head *used_list) 295 { 296 struct ath12k_rx_desc_info *rx_desc, *safe; 297 298 /* Reset the use flag */ 299 list_for_each_entry_safe(rx_desc, safe, used_list, list) 300 rx_desc->in_use = false; 301 302 spin_lock_bh(&dp->rx_desc_lock); 303 list_splice_tail(used_list, &dp->rx_desc_free_list); 304 spin_unlock_bh(&dp->rx_desc_lock); 305 } 306 307 /* Returns number of Rx buffers replenished */ 308 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, 309 struct dp_rxdma_ring *rx_ring, 310 struct list_head *used_list, 311 int req_entries) 312 { 313 struct ath12k_buffer_addr *desc; 314 struct hal_srng *srng; 315 struct sk_buff *skb; 316 int num_free; 317 int num_remain; 318 u32 cookie; 319 dma_addr_t paddr; 320 struct ath12k_dp *dp = &ab->dp; 321 struct ath12k_rx_desc_info *rx_desc; 322 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; 323 324 req_entries = min(req_entries, rx_ring->bufs_max); 325 326 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 327 328 spin_lock_bh(&srng->lock); 329 330 ath12k_hal_srng_access_begin(ab, srng); 331 332 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 333 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 334 req_entries = num_free; 335 336 req_entries = min(num_free, req_entries); 337 num_remain = req_entries; 338 339 if (!num_remain) 340 goto out; 341 342 /* Get the descriptor from free list */ 343 if (list_empty(used_list)) { 344 spin_lock_bh(&dp->rx_desc_lock); 345 req_entries = ath12k_dp_list_cut_nodes(used_list, 346 &dp->rx_desc_free_list, 347 num_remain); 348 spin_unlock_bh(&dp->rx_desc_lock); 349 num_remain = req_entries; 350 } 351 352 while (num_remain > 0) { 353 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 354 DP_RX_BUFFER_ALIGN_SIZE); 355 if (!skb) 356 break; 357 358 if (!IS_ALIGNED((unsigned long)skb->data, 359 DP_RX_BUFFER_ALIGN_SIZE)) { 360 skb_pull(skb, 361 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 362 skb->data); 363 } 364 365 paddr = dma_map_single(ab->dev, skb->data, 366 skb->len + skb_tailroom(skb), 367 DMA_FROM_DEVICE); 368 if (dma_mapping_error(ab->dev, paddr)) 369 goto fail_free_skb; 370 371 rx_desc = list_first_entry_or_null(used_list, 372 struct ath12k_rx_desc_info, 373 list); 374 if (!rx_desc) 375 goto fail_dma_unmap; 376 377 rx_desc->skb = skb; 378 cookie = rx_desc->cookie; 379 380 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 381 if (!desc) 382 goto fail_dma_unmap; 383 384 list_del(&rx_desc->list); 385 ATH12K_SKB_RXCB(skb)->paddr = paddr; 386 387 num_remain--; 388 389 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 390 } 391 392 goto out; 393 394 fail_dma_unmap: 395 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 396 DMA_FROM_DEVICE); 397 fail_free_skb: 398 dev_kfree_skb_any(skb); 399 out: 400 ath12k_hal_srng_access_end(ab, srng); 401 402 if (!list_empty(used_list)) 403 ath12k_dp_rx_enqueue_free(dp, used_list); 404 405 spin_unlock_bh(&srng->lock); 406 407 return req_entries - num_remain; 408 } 409 410 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 411 struct dp_rxdma_mon_ring *rx_ring) 412 { 413 struct sk_buff *skb; 414 int buf_id; 415 416 spin_lock_bh(&rx_ring->idr_lock); 417 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 418 idr_remove(&rx_ring->bufs_idr, buf_id); 419 /* TODO: Understand where internal driver does this dma_unmap 420 * of rxdma_buffer. 421 */ 422 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 423 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 424 dev_kfree_skb_any(skb); 425 } 426 427 idr_destroy(&rx_ring->bufs_idr); 428 spin_unlock_bh(&rx_ring->idr_lock); 429 430 return 0; 431 } 432 433 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 434 { 435 struct ath12k_dp *dp = &ab->dp; 436 int i; 437 438 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 439 440 if (ab->hw_params->rxdma1_enable) 441 return 0; 442 443 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 444 ath12k_dp_rxdma_mon_buf_ring_free(ab, 445 &dp->rx_mon_status_refill_ring[i]); 446 447 return 0; 448 } 449 450 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 451 struct dp_rxdma_mon_ring *rx_ring, 452 u32 ringtype) 453 { 454 int num_entries; 455 456 num_entries = rx_ring->refill_buf_ring.size / 457 ath12k_hal_srng_get_entrysize(ab, ringtype); 458 459 rx_ring->bufs_max = num_entries; 460 461 if (ringtype == HAL_RXDMA_MONITOR_STATUS) 462 ath12k_dp_mon_status_bufs_replenish(ab, rx_ring, 463 num_entries); 464 else 465 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 466 467 return 0; 468 } 469 470 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 471 struct dp_rxdma_ring *rx_ring) 472 { 473 LIST_HEAD(list); 474 475 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 476 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 477 478 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 479 480 return 0; 481 } 482 483 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 484 { 485 struct ath12k_dp *dp = &ab->dp; 486 struct dp_rxdma_mon_ring *mon_ring; 487 int ret, i; 488 489 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 490 if (ret) { 491 ath12k_warn(ab, 492 "failed to setup HAL_RXDMA_BUF\n"); 493 return ret; 494 } 495 496 if (ab->hw_params->rxdma1_enable) { 497 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 498 &dp->rxdma_mon_buf_ring, 499 HAL_RXDMA_MONITOR_BUF); 500 if (ret) 501 ath12k_warn(ab, 502 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 503 return ret; 504 } 505 506 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 507 mon_ring = &dp->rx_mon_status_refill_ring[i]; 508 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, mon_ring, 509 HAL_RXDMA_MONITOR_STATUS); 510 if (ret) { 511 ath12k_warn(ab, 512 "failed to setup HAL_RXDMA_MONITOR_STATUS\n"); 513 return ret; 514 } 515 } 516 517 return 0; 518 } 519 520 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 521 { 522 struct ath12k_pdev_dp *dp = &ar->dp; 523 struct ath12k_base *ab = ar->ab; 524 int i; 525 526 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 527 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 528 } 529 530 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 531 { 532 struct ath12k_dp *dp = &ab->dp; 533 int i; 534 535 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 536 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 537 } 538 539 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 540 { 541 struct ath12k_dp *dp = &ab->dp; 542 int ret; 543 int i; 544 545 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 546 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 547 HAL_REO_DST, i, 0, 548 DP_REO_DST_RING_SIZE); 549 if (ret) { 550 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 551 goto err_reo_cleanup; 552 } 553 } 554 555 return 0; 556 557 err_reo_cleanup: 558 ath12k_dp_rx_pdev_reo_cleanup(ab); 559 560 return ret; 561 } 562 563 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 564 { 565 struct ath12k_pdev_dp *dp = &ar->dp; 566 struct ath12k_base *ab = ar->ab; 567 int i; 568 int ret; 569 u32 mac_id = dp->mac_id; 570 571 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 572 ret = ath12k_dp_srng_setup(ar->ab, 573 &dp->rxdma_mon_dst_ring[i], 574 HAL_RXDMA_MONITOR_DST, 575 0, mac_id + i, 576 DP_RXDMA_MONITOR_DST_RING_SIZE(ab)); 577 if (ret) { 578 ath12k_warn(ar->ab, 579 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 580 return ret; 581 } 582 } 583 584 return 0; 585 } 586 587 static void ath12k_dp_init_rx_tid_rxq(struct ath12k_dp_rx_tid_rxq *rx_tid_rxq, 588 struct ath12k_dp_rx_tid *rx_tid) 589 { 590 rx_tid_rxq->tid = rx_tid->tid; 591 rx_tid_rxq->active = rx_tid->active; 592 rx_tid_rxq->qbuf = rx_tid->qbuf; 593 } 594 595 static void ath12k_dp_rx_tid_cleanup(struct ath12k_base *ab, 596 struct ath12k_reoq_buf *tid_qbuf) 597 { 598 if (tid_qbuf->vaddr) { 599 dma_unmap_single(ab->dev, tid_qbuf->paddr_aligned, 600 tid_qbuf->size, DMA_BIDIRECTIONAL); 601 kfree(tid_qbuf->vaddr); 602 tid_qbuf->vaddr = NULL; 603 } 604 } 605 606 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 607 { 608 struct ath12k_dp *dp = &ab->dp; 609 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 610 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 611 struct dp_reo_update_rx_queue_elem *cmd_queue, *tmp_queue; 612 613 spin_lock_bh(&dp->reo_rxq_flush_lock); 614 list_for_each_entry_safe(cmd_queue, tmp_queue, &dp->reo_cmd_update_rx_queue_list, 615 list) { 616 list_del(&cmd_queue->list); 617 ath12k_dp_rx_tid_cleanup(ab, &cmd_queue->rx_tid.qbuf); 618 kfree(cmd_queue); 619 } 620 list_for_each_entry_safe(cmd_cache, tmp_cache, 621 &dp->reo_cmd_cache_flush_list, list) { 622 list_del(&cmd_cache->list); 623 dp->reo_cmd_cache_flush_count--; 624 ath12k_dp_rx_tid_cleanup(ab, &cmd_cache->data.qbuf); 625 kfree(cmd_cache); 626 } 627 spin_unlock_bh(&dp->reo_rxq_flush_lock); 628 629 spin_lock_bh(&dp->reo_cmd_lock); 630 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 631 list_del(&cmd->list); 632 ath12k_dp_rx_tid_cleanup(ab, &cmd->data.qbuf); 633 kfree(cmd); 634 } 635 spin_unlock_bh(&dp->reo_cmd_lock); 636 } 637 638 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 639 enum hal_reo_cmd_status status) 640 { 641 struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 642 643 if (status != HAL_REO_CMD_SUCCESS) 644 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 645 rx_tid->tid, status); 646 647 ath12k_dp_rx_tid_cleanup(dp->ab, &rx_tid->qbuf); 648 } 649 650 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, 651 struct ath12k_dp_rx_tid_rxq *rx_tid, 652 enum hal_reo_cmd_type type, 653 struct ath12k_hal_reo_cmd *cmd, 654 void (*cb)(struct ath12k_dp *dp, void *ctx, 655 enum hal_reo_cmd_status status)) 656 { 657 struct ath12k_dp *dp = &ab->dp; 658 struct ath12k_dp_rx_reo_cmd *dp_cmd; 659 struct hal_srng *cmd_ring; 660 int cmd_num; 661 662 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 663 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 664 665 /* cmd_num should start from 1, during failure return the error code */ 666 if (cmd_num < 0) 667 return cmd_num; 668 669 /* reo cmd ring descriptors has cmd_num starting from 1 */ 670 if (cmd_num == 0) 671 return -EINVAL; 672 673 if (!cb) 674 return 0; 675 676 /* Can this be optimized so that we keep the pending command list only 677 * for tid delete command to free up the resource on the command status 678 * indication? 679 */ 680 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 681 682 if (!dp_cmd) 683 return -ENOMEM; 684 685 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 686 dp_cmd->cmd_num = cmd_num; 687 dp_cmd->handler = cb; 688 689 spin_lock_bh(&dp->reo_cmd_lock); 690 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 691 spin_unlock_bh(&dp->reo_cmd_lock); 692 693 return 0; 694 } 695 696 static int ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 697 struct ath12k_dp_rx_tid_rxq *rx_tid) 698 { 699 struct ath12k_hal_reo_cmd cmd = {}; 700 int ret; 701 702 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 703 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 704 /* HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS - all pending MPDUs 705 *in the bitmap will be forwarded/flushed to REO output rings 706 */ 707 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS | 708 HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS; 709 710 /* For all QoS TIDs (except NON_QOS), the driver allocates a maximum 711 * window size of 1024. In such cases, the driver can issue a single 712 * 1KB descriptor flush command instead of sending multiple 128-byte 713 * flush commands for each QoS TID, improving efficiency. 714 */ 715 716 if (rx_tid->tid != HAL_DESC_REO_NON_QOS_TID) 717 cmd.flag |= HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC; 718 719 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 720 HAL_REO_CMD_FLUSH_CACHE, 721 &cmd, ath12k_dp_reo_cmd_free); 722 return ret; 723 } 724 725 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 726 { 727 struct ath12k_reo_queue_ref *qref; 728 struct ath12k_dp *dp = &ab->dp; 729 bool ml_peer = false; 730 731 if (!ab->hw_params->reoq_lut_support) 732 return; 733 734 if (peer_id & ATH12K_PEER_ML_ID_VALID) { 735 peer_id &= ~ATH12K_PEER_ML_ID_VALID; 736 ml_peer = true; 737 } 738 739 if (ml_peer) 740 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 741 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 742 else 743 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 744 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 745 746 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 747 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 748 u32_encode_bits(tid, DP_REO_QREF_NUM); 749 } 750 751 static void ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(struct ath12k_dp *dp) 752 { 753 struct ath12k_base *ab = dp->ab; 754 struct dp_reo_update_rx_queue_elem *elem, *tmp; 755 756 spin_lock_bh(&dp->reo_rxq_flush_lock); 757 758 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_update_rx_queue_list, list) { 759 if (elem->rx_tid.active) 760 continue; 761 762 if (ath12k_dp_rx_tid_delete_handler(ab, &elem->rx_tid)) 763 break; 764 765 ath12k_peer_rx_tid_qref_reset(ab, 766 elem->is_ml_peer ? elem->ml_peer_id : 767 elem->peer_id, 768 elem->rx_tid.tid); 769 770 if (ab->hw_params->reoq_lut_support) 771 ath12k_hal_reo_shared_qaddr_cache_clear(ab); 772 773 list_del(&elem->list); 774 kfree(elem); 775 } 776 777 spin_unlock_bh(&dp->reo_rxq_flush_lock); 778 } 779 780 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 781 enum hal_reo_cmd_status status) 782 { 783 struct ath12k_base *ab = dp->ab; 784 struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 785 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 786 787 if (status == HAL_REO_CMD_DRAIN) { 788 goto free_desc; 789 } else if (status != HAL_REO_CMD_SUCCESS) { 790 /* Shouldn't happen! Cleanup in case of other failure? */ 791 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 792 rx_tid->tid, status); 793 return; 794 } 795 796 /* Retry the HAL_REO_CMD_UPDATE_RX_QUEUE command for entries 797 * in the pending queue list marked TID as inactive 798 */ 799 spin_lock_bh(&dp->ab->base_lock); 800 ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(dp); 801 spin_unlock_bh(&dp->ab->base_lock); 802 803 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 804 if (!elem) 805 goto free_desc; 806 807 elem->ts = jiffies; 808 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 809 810 spin_lock_bh(&dp->reo_rxq_flush_lock); 811 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 812 dp->reo_cmd_cache_flush_count++; 813 814 /* Flush and invalidate aged REO desc from HW cache */ 815 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 816 list) { 817 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 818 time_after(jiffies, elem->ts + 819 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 820 /* The reo_cmd_cache_flush_list is used in only two contexts, 821 * one is in this function called from napi and the 822 * other in ath12k_dp_free during core destroy. 823 * If cache command sent is success, delete the element in 824 * the cache list. ath12k_dp_rx_reo_cmd_list_cleanup 825 * will be called during core destroy. 826 */ 827 828 if (ath12k_dp_reo_cache_flush(ab, &elem->data)) 829 break; 830 831 list_del(&elem->list); 832 dp->reo_cmd_cache_flush_count--; 833 kfree(elem); 834 } 835 } 836 spin_unlock_bh(&dp->reo_rxq_flush_lock); 837 838 return; 839 free_desc: 840 ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 841 } 842 843 static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 844 struct ath12k_dp_rx_tid_rxq *rx_tid) 845 { 846 struct ath12k_hal_reo_cmd cmd = {}; 847 848 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 849 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 850 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 851 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 852 /* Observed flush cache failure, to avoid that set vld bit during delete */ 853 cmd.upd1 |= HAL_REO_CMD_UPD1_VLD; 854 855 return ath12k_dp_reo_cmd_send(ab, rx_tid, 856 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 857 ath12k_dp_rx_tid_del_func); 858 } 859 860 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 861 dma_addr_t paddr) 862 { 863 struct ath12k_reo_queue_ref *qref; 864 struct ath12k_dp *dp = &ab->dp; 865 bool ml_peer = false; 866 867 if (!ab->hw_params->reoq_lut_support) 868 return; 869 870 if (peer_id & ATH12K_PEER_ML_ID_VALID) { 871 peer_id &= ~ATH12K_PEER_ML_ID_VALID; 872 ml_peer = true; 873 } 874 875 if (ml_peer) 876 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 877 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 878 else 879 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 880 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 881 882 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 883 BUFFER_ADDR_INFO0_ADDR); 884 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 885 BUFFER_ADDR_INFO1_ADDR) | 886 u32_encode_bits(tid, DP_REO_QREF_NUM); 887 ath12k_hal_reo_shared_qaddr_cache_clear(ab); 888 } 889 890 static void ath12k_dp_mark_tid_as_inactive(struct ath12k_dp *dp, int peer_id, u8 tid) 891 { 892 struct dp_reo_update_rx_queue_elem *elem; 893 struct ath12k_dp_rx_tid_rxq *rx_tid; 894 895 spin_lock_bh(&dp->reo_rxq_flush_lock); 896 list_for_each_entry(elem, &dp->reo_cmd_update_rx_queue_list, list) { 897 if (elem->peer_id == peer_id) { 898 rx_tid = &elem->rx_tid; 899 if (rx_tid->tid == tid) { 900 rx_tid->active = false; 901 break; 902 } 903 } 904 } 905 spin_unlock_bh(&dp->reo_rxq_flush_lock); 906 } 907 908 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 909 struct ath12k_peer *peer, u8 tid) 910 { 911 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 912 struct ath12k_base *ab = ar->ab; 913 struct ath12k_dp *dp = &ab->dp; 914 915 if (!rx_tid->active) 916 return; 917 918 rx_tid->active = false; 919 920 ath12k_dp_mark_tid_as_inactive(dp, peer->peer_id, tid); 921 ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(dp); 922 } 923 924 int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 925 struct ath12k_buffer_addr *buf_addr_info, 926 enum hal_wbm_rel_bm_act action) 927 { 928 struct hal_wbm_release_ring *desc; 929 struct ath12k_dp *dp = &ab->dp; 930 struct hal_srng *srng; 931 int ret = 0; 932 933 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 934 935 spin_lock_bh(&srng->lock); 936 937 ath12k_hal_srng_access_begin(ab, srng); 938 939 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 940 if (!desc) { 941 ret = -ENOBUFS; 942 goto exit; 943 } 944 945 ath12k_hal_rx_msdu_link_desc_set(ab, desc, buf_addr_info, action); 946 947 exit: 948 ath12k_hal_srng_access_end(ab, srng); 949 950 spin_unlock_bh(&srng->lock); 951 952 return ret; 953 } 954 955 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 956 bool rel_link_desc) 957 { 958 struct ath12k_buffer_addr *buf_addr_info; 959 struct ath12k_base *ab = rx_tid->ab; 960 961 lockdep_assert_held(&ab->base_lock); 962 963 if (rx_tid->dst_ring_desc) { 964 if (rel_link_desc) { 965 buf_addr_info = &rx_tid->dst_ring_desc->buf_addr_info; 966 ath12k_dp_rx_link_desc_return(ab, buf_addr_info, 967 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 968 } 969 kfree(rx_tid->dst_ring_desc); 970 rx_tid->dst_ring_desc = NULL; 971 } 972 973 rx_tid->cur_sn = 0; 974 rx_tid->last_frag_no = 0; 975 rx_tid->rx_frag_bitmap = 0; 976 __skb_queue_purge(&rx_tid->rx_frags); 977 } 978 979 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 980 { 981 struct ath12k_dp_rx_tid *rx_tid; 982 int i; 983 984 lockdep_assert_held(&ar->ab->base_lock); 985 986 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 987 rx_tid = &peer->rx_tid[i]; 988 989 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 990 ath12k_dp_rx_frags_cleanup(rx_tid, true); 991 992 spin_unlock_bh(&ar->ab->base_lock); 993 timer_delete_sync(&rx_tid->frag_timer); 994 spin_lock_bh(&ar->ab->base_lock); 995 } 996 } 997 998 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 999 struct ath12k_peer *peer, 1000 struct ath12k_dp_rx_tid *rx_tid, 1001 u32 ba_win_sz, u16 ssn, 1002 bool update_ssn) 1003 { 1004 struct ath12k_hal_reo_cmd cmd = {}; 1005 int ret; 1006 struct ath12k_dp_rx_tid_rxq rx_tid_rxq; 1007 1008 ath12k_dp_init_rx_tid_rxq(&rx_tid_rxq, rx_tid); 1009 1010 cmd.addr_lo = lower_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1011 cmd.addr_hi = upper_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1012 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1013 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 1014 cmd.ba_window_size = ba_win_sz; 1015 1016 if (update_ssn) { 1017 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 1018 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 1019 } 1020 1021 ret = ath12k_dp_reo_cmd_send(ar->ab, &rx_tid_rxq, 1022 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 1023 NULL); 1024 if (ret) { 1025 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 1026 rx_tid_rxq.tid, ret); 1027 return ret; 1028 } 1029 1030 rx_tid->ba_win_sz = ba_win_sz; 1031 1032 return 0; 1033 } 1034 1035 static int ath12k_dp_rx_assign_reoq(struct ath12k_base *ab, 1036 struct ath12k_sta *ahsta, 1037 struct ath12k_dp_rx_tid *rx_tid, 1038 u16 ssn, enum hal_pn_type pn_type) 1039 { 1040 u32 ba_win_sz = rx_tid->ba_win_sz; 1041 struct ath12k_reoq_buf *buf; 1042 void *vaddr, *vaddr_aligned; 1043 dma_addr_t paddr_aligned; 1044 u8 tid = rx_tid->tid; 1045 u32 hw_desc_sz; 1046 int ret; 1047 1048 buf = &ahsta->reoq_bufs[tid]; 1049 if (!buf->vaddr) { 1050 /* TODO: Optimize the memory allocation for qos tid based on 1051 * the actual BA window size in REO tid update path. 1052 */ 1053 if (tid == HAL_DESC_REO_NON_QOS_TID) 1054 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 1055 else 1056 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1057 1058 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1059 if (!vaddr) 1060 return -ENOMEM; 1061 1062 vaddr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1063 1064 ath12k_hal_reo_qdesc_setup(vaddr_aligned, tid, ba_win_sz, 1065 ssn, pn_type); 1066 1067 paddr_aligned = dma_map_single(ab->dev, vaddr_aligned, hw_desc_sz, 1068 DMA_BIDIRECTIONAL); 1069 ret = dma_mapping_error(ab->dev, paddr_aligned); 1070 if (ret) { 1071 kfree(vaddr); 1072 return ret; 1073 } 1074 1075 buf->vaddr = vaddr; 1076 buf->paddr_aligned = paddr_aligned; 1077 buf->size = hw_desc_sz; 1078 } 1079 1080 rx_tid->qbuf = *buf; 1081 rx_tid->active = true; 1082 1083 return 0; 1084 } 1085 1086 static int ath12k_dp_prepare_reo_update_elem(struct ath12k_dp *dp, 1087 struct ath12k_peer *peer, 1088 struct ath12k_dp_rx_tid *rx_tid) 1089 { 1090 struct dp_reo_update_rx_queue_elem *elem; 1091 1092 lockdep_assert_held(&dp->ab->base_lock); 1093 1094 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 1095 if (!elem) 1096 return -ENOMEM; 1097 1098 elem->peer_id = peer->peer_id; 1099 elem->is_ml_peer = peer->mlo; 1100 elem->ml_peer_id = peer->ml_id; 1101 1102 ath12k_dp_init_rx_tid_rxq(&elem->rx_tid, rx_tid); 1103 1104 spin_lock_bh(&dp->reo_rxq_flush_lock); 1105 list_add_tail(&elem->list, &dp->reo_cmd_update_rx_queue_list); 1106 spin_unlock_bh(&dp->reo_rxq_flush_lock); 1107 1108 return 0; 1109 } 1110 1111 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 1112 u8 tid, u32 ba_win_sz, u16 ssn, 1113 enum hal_pn_type pn_type) 1114 { 1115 struct ath12k_base *ab = ar->ab; 1116 struct ath12k_dp *dp = &ab->dp; 1117 struct ath12k_peer *peer; 1118 struct ath12k_sta *ahsta; 1119 struct ath12k_dp_rx_tid *rx_tid; 1120 dma_addr_t paddr_aligned; 1121 int ret; 1122 1123 spin_lock_bh(&ab->base_lock); 1124 1125 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 1126 if (!peer) { 1127 spin_unlock_bh(&ab->base_lock); 1128 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 1129 return -ENOENT; 1130 } 1131 1132 if (ab->hw_params->dp_primary_link_only && 1133 !peer->primary_link) { 1134 spin_unlock_bh(&ab->base_lock); 1135 return 0; 1136 } 1137 1138 if (ab->hw_params->reoq_lut_support && 1139 (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) { 1140 spin_unlock_bh(&ab->base_lock); 1141 ath12k_warn(ab, "reo qref table is not setup\n"); 1142 return -EINVAL; 1143 } 1144 1145 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 1146 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 1147 peer->peer_id, tid); 1148 spin_unlock_bh(&ab->base_lock); 1149 return -EINVAL; 1150 } 1151 1152 rx_tid = &peer->rx_tid[tid]; 1153 /* Update the tid queue if it is already setup */ 1154 if (rx_tid->active) { 1155 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1156 ba_win_sz, ssn, true); 1157 spin_unlock_bh(&ab->base_lock); 1158 if (ret) { 1159 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 1160 return ret; 1161 } 1162 1163 if (!ab->hw_params->reoq_lut_support) { 1164 paddr_aligned = rx_tid->qbuf.paddr_aligned; 1165 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1166 peer_mac, 1167 paddr_aligned, tid, 1168 1, ba_win_sz); 1169 if (ret) { 1170 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 1171 tid, ret); 1172 return ret; 1173 } 1174 } 1175 1176 return 0; 1177 } 1178 1179 rx_tid->tid = tid; 1180 1181 rx_tid->ba_win_sz = ba_win_sz; 1182 1183 ahsta = ath12k_sta_to_ahsta(peer->sta); 1184 ret = ath12k_dp_rx_assign_reoq(ab, ahsta, rx_tid, ssn, pn_type); 1185 if (ret) { 1186 spin_unlock_bh(&ab->base_lock); 1187 ath12k_warn(ab, "failed to assign reoq buf for rx tid %u\n", tid); 1188 return ret; 1189 } 1190 1191 /* Pre-allocate the update_rxq_list for the corresponding tid 1192 * This will be used during the tid delete. The reason we are not 1193 * allocating during tid delete is that, if any alloc fail in update_rxq_list 1194 * we may not be able to delete the tid vaddr/paddr and may lead to leak 1195 */ 1196 ret = ath12k_dp_prepare_reo_update_elem(dp, peer, rx_tid); 1197 if (ret) { 1198 ath12k_warn(ab, "failed to alloc update_rxq_list for rx tid %u\n", tid); 1199 ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 1200 spin_unlock_bh(&ab->base_lock); 1201 return ret; 1202 } 1203 1204 paddr_aligned = rx_tid->qbuf.paddr_aligned; 1205 if (ab->hw_params->reoq_lut_support) { 1206 /* Update the REO queue LUT at the corresponding peer id 1207 * and tid with qaddr. 1208 */ 1209 if (peer->mlo) 1210 ath12k_peer_rx_tid_qref_setup(ab, peer->ml_id, tid, 1211 paddr_aligned); 1212 else 1213 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, 1214 paddr_aligned); 1215 1216 spin_unlock_bh(&ab->base_lock); 1217 } else { 1218 spin_unlock_bh(&ab->base_lock); 1219 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1220 paddr_aligned, tid, 1, 1221 ba_win_sz); 1222 } 1223 1224 return ret; 1225 } 1226 1227 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1228 struct ieee80211_ampdu_params *params, 1229 u8 link_id) 1230 { 1231 struct ath12k_base *ab = ar->ab; 1232 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 1233 struct ath12k_link_sta *arsta; 1234 int vdev_id; 1235 int ret; 1236 1237 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 1238 1239 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 1240 ahsta->link[link_id]); 1241 if (!arsta) 1242 return -ENOLINK; 1243 1244 vdev_id = arsta->arvif->vdev_id; 1245 1246 ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id, 1247 params->tid, params->buf_size, 1248 params->ssn, arsta->ahsta->pn_type); 1249 if (ret) 1250 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1251 1252 return ret; 1253 } 1254 1255 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1256 struct ieee80211_ampdu_params *params, 1257 u8 link_id) 1258 { 1259 struct ath12k_base *ab = ar->ab; 1260 struct ath12k_peer *peer; 1261 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 1262 struct ath12k_link_sta *arsta; 1263 int vdev_id; 1264 bool active; 1265 int ret; 1266 1267 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 1268 1269 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 1270 ahsta->link[link_id]); 1271 if (!arsta) 1272 return -ENOLINK; 1273 1274 vdev_id = arsta->arvif->vdev_id; 1275 1276 spin_lock_bh(&ab->base_lock); 1277 1278 peer = ath12k_peer_find(ab, vdev_id, arsta->addr); 1279 if (!peer) { 1280 spin_unlock_bh(&ab->base_lock); 1281 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1282 return -ENOENT; 1283 } 1284 1285 active = peer->rx_tid[params->tid].active; 1286 1287 if (!active) { 1288 spin_unlock_bh(&ab->base_lock); 1289 return 0; 1290 } 1291 1292 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1293 spin_unlock_bh(&ab->base_lock); 1294 if (ret) { 1295 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1296 params->tid, ret); 1297 return ret; 1298 } 1299 1300 return ret; 1301 } 1302 1303 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, 1304 const u8 *peer_addr, 1305 enum set_key_cmd key_cmd, 1306 struct ieee80211_key_conf *key) 1307 { 1308 struct ath12k *ar = arvif->ar; 1309 struct ath12k_base *ab = ar->ab; 1310 struct ath12k_hal_reo_cmd cmd = {}; 1311 struct ath12k_peer *peer; 1312 struct ath12k_dp_rx_tid *rx_tid; 1313 struct ath12k_dp_rx_tid_rxq rx_tid_rxq; 1314 u8 tid; 1315 int ret = 0; 1316 1317 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1318 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1319 * for now. 1320 */ 1321 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1322 return 0; 1323 1324 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1325 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1326 HAL_REO_CMD_UPD0_PN_SIZE | 1327 HAL_REO_CMD_UPD0_PN_VALID | 1328 HAL_REO_CMD_UPD0_PN_CHECK | 1329 HAL_REO_CMD_UPD0_SVLD; 1330 1331 switch (key->cipher) { 1332 case WLAN_CIPHER_SUITE_TKIP: 1333 case WLAN_CIPHER_SUITE_CCMP: 1334 case WLAN_CIPHER_SUITE_CCMP_256: 1335 case WLAN_CIPHER_SUITE_GCMP: 1336 case WLAN_CIPHER_SUITE_GCMP_256: 1337 if (key_cmd == SET_KEY) { 1338 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1339 cmd.pn_size = 48; 1340 } 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 spin_lock_bh(&ab->base_lock); 1347 1348 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1349 if (!peer) { 1350 spin_unlock_bh(&ab->base_lock); 1351 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1352 peer_addr); 1353 return -ENOENT; 1354 } 1355 1356 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1357 rx_tid = &peer->rx_tid[tid]; 1358 if (!rx_tid->active) 1359 continue; 1360 1361 ath12k_dp_init_rx_tid_rxq(&rx_tid_rxq, rx_tid); 1362 cmd.addr_lo = lower_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1363 cmd.addr_hi = upper_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1364 ret = ath12k_dp_reo_cmd_send(ab, &rx_tid_rxq, 1365 HAL_REO_CMD_UPDATE_RX_QUEUE, 1366 &cmd, NULL); 1367 if (ret) { 1368 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1369 tid, peer_addr, ret); 1370 break; 1371 } 1372 } 1373 1374 spin_unlock_bh(&ab->base_lock); 1375 1376 return ret; 1377 } 1378 1379 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1380 u16 peer_id) 1381 { 1382 int i; 1383 1384 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1385 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1386 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1387 return i; 1388 } else { 1389 return i; 1390 } 1391 } 1392 1393 return -EINVAL; 1394 } 1395 1396 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1397 u16 tag, u16 len, const void *ptr, 1398 void *data) 1399 { 1400 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1401 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1402 const struct htt_ppdu_stats_user_rate *user_rate; 1403 struct htt_ppdu_stats_info *ppdu_info; 1404 struct htt_ppdu_user_stats *user_stats; 1405 int cur_user; 1406 u16 peer_id; 1407 1408 ppdu_info = data; 1409 1410 switch (tag) { 1411 case HTT_PPDU_STATS_TAG_COMMON: 1412 if (len < sizeof(struct htt_ppdu_stats_common)) { 1413 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1414 len, tag); 1415 return -EINVAL; 1416 } 1417 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1418 sizeof(struct htt_ppdu_stats_common)); 1419 break; 1420 case HTT_PPDU_STATS_TAG_USR_RATE: 1421 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1422 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1423 len, tag); 1424 return -EINVAL; 1425 } 1426 user_rate = ptr; 1427 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1428 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1429 peer_id); 1430 if (cur_user < 0) 1431 return -EINVAL; 1432 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1433 user_stats->peer_id = peer_id; 1434 user_stats->is_valid_peer_id = true; 1435 memcpy(&user_stats->rate, ptr, 1436 sizeof(struct htt_ppdu_stats_user_rate)); 1437 user_stats->tlv_flags |= BIT(tag); 1438 break; 1439 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1440 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1441 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1442 len, tag); 1443 return -EINVAL; 1444 } 1445 1446 cmplt_cmn = ptr; 1447 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1448 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1449 peer_id); 1450 if (cur_user < 0) 1451 return -EINVAL; 1452 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1453 user_stats->peer_id = peer_id; 1454 user_stats->is_valid_peer_id = true; 1455 memcpy(&user_stats->cmpltn_cmn, ptr, 1456 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1457 user_stats->tlv_flags |= BIT(tag); 1458 break; 1459 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1460 if (len < 1461 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1462 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1463 len, tag); 1464 return -EINVAL; 1465 } 1466 1467 ba_status = ptr; 1468 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1469 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1470 peer_id); 1471 if (cur_user < 0) 1472 return -EINVAL; 1473 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1474 user_stats->peer_id = peer_id; 1475 user_stats->is_valid_peer_id = true; 1476 memcpy(&user_stats->ack_ba, ptr, 1477 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1478 user_stats->tlv_flags |= BIT(tag); 1479 break; 1480 } 1481 return 0; 1482 } 1483 1484 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1485 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1486 const void *ptr, void *data), 1487 void *data) 1488 { 1489 const struct htt_tlv *tlv; 1490 const void *begin = ptr; 1491 u16 tlv_tag, tlv_len; 1492 int ret = -EINVAL; 1493 1494 while (len > 0) { 1495 if (len < sizeof(*tlv)) { 1496 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1497 ptr - begin, len, sizeof(*tlv)); 1498 return -EINVAL; 1499 } 1500 tlv = (struct htt_tlv *)ptr; 1501 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1502 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1503 ptr += sizeof(*tlv); 1504 len -= sizeof(*tlv); 1505 1506 if (tlv_len > len) { 1507 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1508 tlv_tag, ptr - begin, len, tlv_len); 1509 return -EINVAL; 1510 } 1511 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1512 if (ret == -ENOMEM) 1513 return ret; 1514 1515 ptr += tlv_len; 1516 len -= tlv_len; 1517 } 1518 return 0; 1519 } 1520 1521 static void 1522 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1523 struct htt_ppdu_stats *ppdu_stats, u8 user) 1524 { 1525 struct ath12k_base *ab = ar->ab; 1526 struct ath12k_peer *peer; 1527 struct ath12k_link_sta *arsta; 1528 struct htt_ppdu_stats_user_rate *user_rate; 1529 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1530 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1531 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1532 int ret; 1533 u8 flags, mcs, nss, bw, sgi, dcm, ppdu_type, rate_idx = 0; 1534 u32 v, succ_bytes = 0; 1535 u16 tones, rate = 0, succ_pkts = 0; 1536 u32 tx_duration = 0; 1537 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1538 u16 tx_retry_failed = 0, tx_retry_count = 0; 1539 bool is_ampdu = false, is_ofdma; 1540 1541 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1542 return; 1543 1544 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) { 1545 is_ampdu = 1546 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1547 tx_retry_failed = 1548 __le16_to_cpu(usr_stats->cmpltn_cmn.mpdu_tried) - 1549 __le16_to_cpu(usr_stats->cmpltn_cmn.mpdu_success); 1550 tx_retry_count = 1551 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1552 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1553 } 1554 1555 if (usr_stats->tlv_flags & 1556 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1557 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1558 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1559 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1560 tid = le32_get_bits(usr_stats->ack_ba.info, 1561 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1562 } 1563 1564 if (common->fes_duration_us) 1565 tx_duration = le32_to_cpu(common->fes_duration_us); 1566 1567 user_rate = &usr_stats->rate; 1568 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1569 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1570 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1571 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1572 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1573 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1574 1575 ppdu_type = HTT_USR_RATE_PPDU_TYPE(user_rate->info1); 1576 is_ofdma = (ppdu_type == HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA) || 1577 (ppdu_type == HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA); 1578 1579 /* Note: If host configured fixed rates and in some other special 1580 * cases, the broadcast/management frames are sent in different rates. 1581 * Firmware rate's control to be skipped for this? 1582 */ 1583 1584 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1585 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1586 return; 1587 } 1588 1589 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1590 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1591 return; 1592 } 1593 1594 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1595 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1596 mcs, nss); 1597 return; 1598 } 1599 1600 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1601 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1602 flags, 1603 &rate_idx, 1604 &rate); 1605 if (ret < 0) 1606 return; 1607 } 1608 1609 rcu_read_lock(); 1610 spin_lock_bh(&ab->base_lock); 1611 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1612 1613 if (!peer || !peer->sta) { 1614 spin_unlock_bh(&ab->base_lock); 1615 rcu_read_unlock(); 1616 return; 1617 } 1618 1619 arsta = ath12k_peer_get_link_sta(ab, peer); 1620 if (!arsta) { 1621 spin_unlock_bh(&ab->base_lock); 1622 rcu_read_unlock(); 1623 return; 1624 } 1625 1626 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1627 1628 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1629 1630 switch (flags) { 1631 case WMI_RATE_PREAMBLE_OFDM: 1632 arsta->txrate.legacy = rate; 1633 break; 1634 case WMI_RATE_PREAMBLE_CCK: 1635 arsta->txrate.legacy = rate; 1636 break; 1637 case WMI_RATE_PREAMBLE_HT: 1638 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1639 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1640 if (sgi) 1641 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1642 break; 1643 case WMI_RATE_PREAMBLE_VHT: 1644 arsta->txrate.mcs = mcs; 1645 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1646 if (sgi) 1647 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1648 break; 1649 case WMI_RATE_PREAMBLE_HE: 1650 arsta->txrate.mcs = mcs; 1651 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1652 arsta->txrate.he_dcm = dcm; 1653 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1654 tones = le16_to_cpu(user_rate->ru_end) - 1655 le16_to_cpu(user_rate->ru_start) + 1; 1656 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1657 arsta->txrate.he_ru_alloc = v; 1658 if (is_ofdma) 1659 arsta->txrate.bw = RATE_INFO_BW_HE_RU; 1660 break; 1661 case WMI_RATE_PREAMBLE_EHT: 1662 arsta->txrate.mcs = mcs; 1663 arsta->txrate.flags = RATE_INFO_FLAGS_EHT_MCS; 1664 arsta->txrate.he_dcm = dcm; 1665 arsta->txrate.eht_gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi); 1666 tones = le16_to_cpu(user_rate->ru_end) - 1667 le16_to_cpu(user_rate->ru_start) + 1; 1668 v = ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(tones); 1669 arsta->txrate.eht_ru_alloc = v; 1670 if (is_ofdma) 1671 arsta->txrate.bw = RATE_INFO_BW_EHT_RU; 1672 break; 1673 } 1674 1675 arsta->tx_retry_failed += tx_retry_failed; 1676 arsta->tx_retry_count += tx_retry_count; 1677 arsta->txrate.nss = nss; 1678 arsta->tx_duration += tx_duration; 1679 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1680 1681 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1682 * So skip peer stats update for mgmt packets. 1683 */ 1684 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1685 memset(peer_stats, 0, sizeof(*peer_stats)); 1686 peer_stats->succ_pkts = succ_pkts; 1687 peer_stats->succ_bytes = succ_bytes; 1688 peer_stats->is_ampdu = is_ampdu; 1689 peer_stats->duration = tx_duration; 1690 peer_stats->ba_fails = 1691 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1692 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1693 } 1694 1695 spin_unlock_bh(&ab->base_lock); 1696 rcu_read_unlock(); 1697 } 1698 1699 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1700 struct htt_ppdu_stats *ppdu_stats) 1701 { 1702 u8 user; 1703 1704 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1705 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1706 } 1707 1708 static 1709 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1710 u32 ppdu_id) 1711 { 1712 struct htt_ppdu_stats_info *ppdu_info; 1713 1714 lockdep_assert_held(&ar->data_lock); 1715 if (!list_empty(&ar->ppdu_stats_info)) { 1716 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1717 if (ppdu_info->ppdu_id == ppdu_id) 1718 return ppdu_info; 1719 } 1720 1721 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1722 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1723 typeof(*ppdu_info), list); 1724 list_del(&ppdu_info->list); 1725 ar->ppdu_stat_list_depth--; 1726 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1727 kfree(ppdu_info); 1728 } 1729 } 1730 1731 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1732 if (!ppdu_info) 1733 return NULL; 1734 1735 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1736 ar->ppdu_stat_list_depth++; 1737 1738 return ppdu_info; 1739 } 1740 1741 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1742 struct htt_ppdu_user_stats *usr_stats) 1743 { 1744 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1745 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1746 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1747 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1748 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1749 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1750 peer->ppdu_stats_delayba.resp_rate_flags = 1751 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1752 1753 peer->delayba_flag = true; 1754 } 1755 1756 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1757 struct htt_ppdu_user_stats *usr_stats) 1758 { 1759 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1760 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1761 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1762 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1763 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1764 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1765 usr_stats->rate.resp_rate_flags = 1766 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1767 1768 peer->delayba_flag = false; 1769 } 1770 1771 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1772 struct sk_buff *skb) 1773 { 1774 struct ath12k_htt_ppdu_stats_msg *msg; 1775 struct htt_ppdu_stats_info *ppdu_info; 1776 struct ath12k_peer *peer = NULL; 1777 struct htt_ppdu_user_stats *usr_stats = NULL; 1778 u32 peer_id = 0; 1779 struct ath12k *ar; 1780 int ret, i; 1781 u8 pdev_id; 1782 u32 ppdu_id, len; 1783 1784 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1785 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1786 if (len > (skb->len - struct_size(msg, data, 0))) { 1787 ath12k_warn(ab, 1788 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1789 len, skb->len); 1790 return -EINVAL; 1791 } 1792 1793 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1794 ppdu_id = le32_to_cpu(msg->ppdu_id); 1795 1796 rcu_read_lock(); 1797 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1798 if (!ar) { 1799 ret = -EINVAL; 1800 goto exit; 1801 } 1802 1803 spin_lock_bh(&ar->data_lock); 1804 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1805 if (!ppdu_info) { 1806 spin_unlock_bh(&ar->data_lock); 1807 ret = -EINVAL; 1808 goto exit; 1809 } 1810 1811 ppdu_info->ppdu_id = ppdu_id; 1812 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1813 ath12k_htt_tlv_ppdu_stats_parse, 1814 (void *)ppdu_info); 1815 if (ret) { 1816 spin_unlock_bh(&ar->data_lock); 1817 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1818 goto exit; 1819 } 1820 1821 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1822 spin_unlock_bh(&ar->data_lock); 1823 ath12k_warn(ab, 1824 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1825 ppdu_info->ppdu_stats.common.num_users, 1826 HTT_PPDU_STATS_MAX_USERS); 1827 ret = -EINVAL; 1828 goto exit; 1829 } 1830 1831 /* back up data rate tlv for all peers */ 1832 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1833 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1834 ppdu_info->delay_ba) { 1835 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1836 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1837 spin_lock_bh(&ab->base_lock); 1838 peer = ath12k_peer_find_by_id(ab, peer_id); 1839 if (!peer) { 1840 spin_unlock_bh(&ab->base_lock); 1841 continue; 1842 } 1843 1844 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1845 if (usr_stats->delay_ba) 1846 ath12k_copy_to_delay_stats(peer, usr_stats); 1847 spin_unlock_bh(&ab->base_lock); 1848 } 1849 } 1850 1851 /* restore all peers' data rate tlv to mu-bar tlv */ 1852 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1853 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1854 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1855 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1856 spin_lock_bh(&ab->base_lock); 1857 peer = ath12k_peer_find_by_id(ab, peer_id); 1858 if (!peer) { 1859 spin_unlock_bh(&ab->base_lock); 1860 continue; 1861 } 1862 1863 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1864 if (peer->delayba_flag) 1865 ath12k_copy_to_bar(peer, usr_stats); 1866 spin_unlock_bh(&ab->base_lock); 1867 } 1868 } 1869 1870 spin_unlock_bh(&ar->data_lock); 1871 1872 exit: 1873 rcu_read_unlock(); 1874 1875 return ret; 1876 } 1877 1878 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1879 struct sk_buff *skb) 1880 { 1881 struct ath12k_htt_mlo_offset_msg *msg; 1882 struct ath12k_pdev *pdev; 1883 struct ath12k *ar; 1884 u8 pdev_id; 1885 1886 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1887 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1888 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1889 1890 rcu_read_lock(); 1891 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1892 if (!ar) { 1893 /* It is possible that the ar is not yet active (started). 1894 * The above function will only look for the active pdev 1895 * and hence %NULL return is possible. Just silently 1896 * discard this message 1897 */ 1898 goto exit; 1899 } 1900 1901 spin_lock_bh(&ar->data_lock); 1902 pdev = ar->pdev; 1903 1904 pdev->timestamp.info = __le32_to_cpu(msg->info); 1905 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1906 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1907 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1908 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1909 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1910 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1911 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1912 1913 spin_unlock_bh(&ar->data_lock); 1914 exit: 1915 rcu_read_unlock(); 1916 } 1917 1918 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1919 struct sk_buff *skb) 1920 { 1921 struct ath12k_dp *dp = &ab->dp; 1922 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1923 enum htt_t2h_msg_type type; 1924 u16 peer_id; 1925 u8 vdev_id; 1926 u8 mac_addr[ETH_ALEN]; 1927 u16 peer_mac_h16; 1928 u16 ast_hash = 0; 1929 u16 hw_peer_id; 1930 1931 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1932 1933 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1934 1935 switch (type) { 1936 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1937 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1938 HTT_T2H_VERSION_CONF_MAJOR); 1939 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1940 HTT_T2H_VERSION_CONF_MINOR); 1941 complete(&dp->htt_tgt_version_received); 1942 break; 1943 /* TODO: remove unused peer map versions after testing */ 1944 case HTT_T2H_MSG_TYPE_PEER_MAP: 1945 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1946 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1947 peer_id = le32_get_bits(resp->peer_map_ev.info, 1948 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1949 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1950 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1951 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1952 peer_mac_h16, mac_addr); 1953 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1954 break; 1955 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1956 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1957 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1958 peer_id = le32_get_bits(resp->peer_map_ev.info, 1959 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1960 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1961 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1962 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1963 peer_mac_h16, mac_addr); 1964 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1965 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1966 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1967 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1968 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1969 hw_peer_id); 1970 break; 1971 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1972 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1973 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1974 peer_id = le32_get_bits(resp->peer_map_ev.info, 1975 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1976 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1977 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1978 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1979 peer_mac_h16, mac_addr); 1980 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1981 HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL); 1982 hw_peer_id = le32_get_bits(resp->peer_map_ev.info2, 1983 HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID); 1984 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1985 hw_peer_id); 1986 break; 1987 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1988 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1989 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1990 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1991 ath12k_peer_unmap_event(ab, peer_id); 1992 break; 1993 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1994 ath12k_htt_pull_ppdu_stats(ab, skb); 1995 break; 1996 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1997 ath12k_debugfs_htt_ext_stats_handler(ab, skb); 1998 break; 1999 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 2000 ath12k_htt_mlo_offset_event_handler(ab, skb); 2001 break; 2002 default: 2003 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 2004 type); 2005 break; 2006 } 2007 2008 dev_kfree_skb_any(skb); 2009 } 2010 2011 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 2012 struct sk_buff_head *msdu_list, 2013 struct sk_buff *first, struct sk_buff *last, 2014 u8 l3pad_bytes, int msdu_len) 2015 { 2016 struct ath12k_base *ab = ar->ab; 2017 struct sk_buff *skb; 2018 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 2019 int buf_first_hdr_len, buf_first_len; 2020 struct hal_rx_desc *ldesc; 2021 int space_extra, rem_len, buf_len; 2022 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2023 bool is_continuation; 2024 2025 /* As the msdu is spread across multiple rx buffers, 2026 * find the offset to the start of msdu for computing 2027 * the length of the msdu in the first buffer. 2028 */ 2029 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 2030 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 2031 2032 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 2033 skb_put(first, buf_first_hdr_len + msdu_len); 2034 skb_pull(first, buf_first_hdr_len); 2035 return 0; 2036 } 2037 2038 ldesc = (struct hal_rx_desc *)last->data; 2039 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 2040 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 2041 2042 /* MSDU spans over multiple buffers because the length of the MSDU 2043 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 2044 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 2045 */ 2046 skb_put(first, DP_RX_BUFFER_SIZE); 2047 skb_pull(first, buf_first_hdr_len); 2048 2049 /* When an MSDU spread over multiple buffers MSDU_END 2050 * tlvs are valid only in the last buffer. Copy those tlvs. 2051 */ 2052 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 2053 2054 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 2055 if (space_extra > 0 && 2056 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 2057 /* Free up all buffers of the MSDU */ 2058 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 2059 rxcb = ATH12K_SKB_RXCB(skb); 2060 if (!rxcb->is_continuation) { 2061 dev_kfree_skb_any(skb); 2062 break; 2063 } 2064 dev_kfree_skb_any(skb); 2065 } 2066 return -ENOMEM; 2067 } 2068 2069 rem_len = msdu_len - buf_first_len; 2070 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 2071 rxcb = ATH12K_SKB_RXCB(skb); 2072 is_continuation = rxcb->is_continuation; 2073 if (is_continuation) 2074 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 2075 else 2076 buf_len = rem_len; 2077 2078 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 2079 WARN_ON_ONCE(1); 2080 dev_kfree_skb_any(skb); 2081 return -EINVAL; 2082 } 2083 2084 skb_put(skb, buf_len + hal_rx_desc_sz); 2085 skb_pull(skb, hal_rx_desc_sz); 2086 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 2087 buf_len); 2088 dev_kfree_skb_any(skb); 2089 2090 rem_len -= buf_len; 2091 if (!is_continuation) 2092 break; 2093 } 2094 2095 return 0; 2096 } 2097 2098 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 2099 struct sk_buff *first) 2100 { 2101 struct sk_buff *skb; 2102 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 2103 2104 if (!rxcb->is_continuation) 2105 return first; 2106 2107 skb_queue_walk(msdu_list, skb) { 2108 rxcb = ATH12K_SKB_RXCB(skb); 2109 if (!rxcb->is_continuation) 2110 return skb; 2111 } 2112 2113 return NULL; 2114 } 2115 2116 static void ath12k_dp_rx_h_csum_offload(struct sk_buff *msdu, 2117 struct ath12k_dp_rx_info *rx_info) 2118 { 2119 msdu->ip_summed = (rx_info->ip_csum_fail || rx_info->l4_csum_fail) ? 2120 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 2121 } 2122 2123 int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, enum hal_encrypt_type enctype) 2124 { 2125 switch (enctype) { 2126 case HAL_ENCRYPT_TYPE_OPEN: 2127 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 2128 case HAL_ENCRYPT_TYPE_TKIP_MIC: 2129 return 0; 2130 case HAL_ENCRYPT_TYPE_CCMP_128: 2131 return IEEE80211_CCMP_MIC_LEN; 2132 case HAL_ENCRYPT_TYPE_CCMP_256: 2133 return IEEE80211_CCMP_256_MIC_LEN; 2134 case HAL_ENCRYPT_TYPE_GCMP_128: 2135 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 2136 return IEEE80211_GCMP_MIC_LEN; 2137 case HAL_ENCRYPT_TYPE_WEP_40: 2138 case HAL_ENCRYPT_TYPE_WEP_104: 2139 case HAL_ENCRYPT_TYPE_WEP_128: 2140 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 2141 case HAL_ENCRYPT_TYPE_WAPI: 2142 break; 2143 } 2144 2145 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 2146 return 0; 2147 } 2148 2149 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 2150 enum hal_encrypt_type enctype) 2151 { 2152 switch (enctype) { 2153 case HAL_ENCRYPT_TYPE_OPEN: 2154 return 0; 2155 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 2156 case HAL_ENCRYPT_TYPE_TKIP_MIC: 2157 return IEEE80211_TKIP_IV_LEN; 2158 case HAL_ENCRYPT_TYPE_CCMP_128: 2159 return IEEE80211_CCMP_HDR_LEN; 2160 case HAL_ENCRYPT_TYPE_CCMP_256: 2161 return IEEE80211_CCMP_256_HDR_LEN; 2162 case HAL_ENCRYPT_TYPE_GCMP_128: 2163 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 2164 return IEEE80211_GCMP_HDR_LEN; 2165 case HAL_ENCRYPT_TYPE_WEP_40: 2166 case HAL_ENCRYPT_TYPE_WEP_104: 2167 case HAL_ENCRYPT_TYPE_WEP_128: 2168 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 2169 case HAL_ENCRYPT_TYPE_WAPI: 2170 break; 2171 } 2172 2173 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 2174 return 0; 2175 } 2176 2177 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 2178 enum hal_encrypt_type enctype) 2179 { 2180 switch (enctype) { 2181 case HAL_ENCRYPT_TYPE_OPEN: 2182 case HAL_ENCRYPT_TYPE_CCMP_128: 2183 case HAL_ENCRYPT_TYPE_CCMP_256: 2184 case HAL_ENCRYPT_TYPE_GCMP_128: 2185 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 2186 return 0; 2187 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 2188 case HAL_ENCRYPT_TYPE_TKIP_MIC: 2189 return IEEE80211_TKIP_ICV_LEN; 2190 case HAL_ENCRYPT_TYPE_WEP_40: 2191 case HAL_ENCRYPT_TYPE_WEP_104: 2192 case HAL_ENCRYPT_TYPE_WEP_128: 2193 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 2194 case HAL_ENCRYPT_TYPE_WAPI: 2195 break; 2196 } 2197 2198 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 2199 return 0; 2200 } 2201 2202 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 2203 struct sk_buff *msdu, 2204 enum hal_encrypt_type enctype, 2205 struct ieee80211_rx_status *status) 2206 { 2207 struct ath12k_base *ab = ar->ab; 2208 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2209 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 2210 struct ieee80211_hdr *hdr; 2211 size_t hdr_len; 2212 u8 *crypto_hdr; 2213 u16 qos_ctl; 2214 2215 /* pull decapped header */ 2216 hdr = (struct ieee80211_hdr *)msdu->data; 2217 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2218 skb_pull(msdu, hdr_len); 2219 2220 /* Rebuild qos header */ 2221 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 2222 2223 /* Reset the order bit as the HT_Control header is stripped */ 2224 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2225 2226 qos_ctl = rxcb->tid; 2227 2228 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 2229 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2230 2231 /* TODO: Add other QoS ctl fields when required */ 2232 2233 /* copy decap header before overwriting for reuse below */ 2234 memcpy(decap_hdr, hdr, hdr_len); 2235 2236 /* Rebuild crypto header for mac80211 use */ 2237 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2238 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 2239 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 2240 rxcb->rx_desc, crypto_hdr, 2241 enctype); 2242 } 2243 2244 memcpy(skb_push(msdu, 2245 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2246 IEEE80211_QOS_CTL_LEN); 2247 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2248 } 2249 2250 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2251 enum hal_encrypt_type enctype, 2252 struct ieee80211_rx_status *status, 2253 bool decrypted) 2254 { 2255 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2256 struct ieee80211_hdr *hdr; 2257 size_t hdr_len; 2258 size_t crypto_len; 2259 2260 if (!rxcb->is_first_msdu || 2261 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2262 WARN_ON_ONCE(1); 2263 return; 2264 } 2265 2266 skb_trim(msdu, msdu->len - FCS_LEN); 2267 2268 if (!decrypted) 2269 return; 2270 2271 hdr = (void *)msdu->data; 2272 2273 /* Tail */ 2274 if (status->flag & RX_FLAG_IV_STRIPPED) { 2275 skb_trim(msdu, msdu->len - 2276 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2277 2278 skb_trim(msdu, msdu->len - 2279 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2280 } else { 2281 /* MIC */ 2282 if (status->flag & RX_FLAG_MIC_STRIPPED) 2283 skb_trim(msdu, msdu->len - 2284 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2285 2286 /* ICV */ 2287 if (status->flag & RX_FLAG_ICV_STRIPPED) 2288 skb_trim(msdu, msdu->len - 2289 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2290 } 2291 2292 /* MMIC */ 2293 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2294 !ieee80211_has_morefrags(hdr->frame_control) && 2295 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2296 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2297 2298 /* Head */ 2299 if (status->flag & RX_FLAG_IV_STRIPPED) { 2300 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2301 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2302 2303 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2304 skb_pull(msdu, crypto_len); 2305 } 2306 } 2307 2308 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2309 struct sk_buff *msdu, 2310 struct ath12k_skb_rxcb *rxcb, 2311 struct ieee80211_rx_status *status, 2312 enum hal_encrypt_type enctype) 2313 { 2314 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2315 struct ath12k_base *ab = ar->ab; 2316 size_t hdr_len, crypto_len; 2317 struct ieee80211_hdr hdr; 2318 __le16 qos_ctl; 2319 u8 *crypto_hdr, mesh_ctrl; 2320 2321 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, &hdr); 2322 hdr_len = ieee80211_hdrlen(hdr.frame_control); 2323 mesh_ctrl = ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc); 2324 2325 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2326 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2327 crypto_hdr = skb_push(msdu, crypto_len); 2328 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2329 } 2330 2331 skb_push(msdu, hdr_len); 2332 memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr))); 2333 2334 if (rxcb->is_mcbc) 2335 status->flag &= ~RX_FLAG_PN_VALIDATED; 2336 2337 /* Add QOS header */ 2338 if (ieee80211_is_data_qos(hdr.frame_control)) { 2339 struct ieee80211_hdr *qos_ptr = (struct ieee80211_hdr *)msdu->data; 2340 2341 qos_ctl = cpu_to_le16(rxcb->tid & IEEE80211_QOS_CTL_TID_MASK); 2342 if (mesh_ctrl) 2343 qos_ctl |= cpu_to_le16(IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT); 2344 2345 memcpy(ieee80211_get_qos_ctl(qos_ptr), &qos_ctl, IEEE80211_QOS_CTL_LEN); 2346 } 2347 } 2348 2349 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2350 struct sk_buff *msdu, 2351 enum hal_encrypt_type enctype, 2352 struct ieee80211_rx_status *status) 2353 { 2354 struct ieee80211_hdr *hdr; 2355 struct ethhdr *eth; 2356 u8 da[ETH_ALEN]; 2357 u8 sa[ETH_ALEN]; 2358 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2359 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2360 2361 eth = (struct ethhdr *)msdu->data; 2362 ether_addr_copy(da, eth->h_dest); 2363 ether_addr_copy(sa, eth->h_source); 2364 rfc.snap_type = eth->h_proto; 2365 skb_pull(msdu, sizeof(*eth)); 2366 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2367 sizeof(rfc)); 2368 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2369 2370 /* original 802.11 header has a different DA and in 2371 * case of 4addr it may also have different SA 2372 */ 2373 hdr = (struct ieee80211_hdr *)msdu->data; 2374 ether_addr_copy(ieee80211_get_DA(hdr), da); 2375 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2376 } 2377 2378 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2379 struct hal_rx_desc *rx_desc, 2380 enum hal_encrypt_type enctype, 2381 struct ieee80211_rx_status *status, 2382 bool decrypted) 2383 { 2384 struct ath12k_base *ab = ar->ab; 2385 u8 decap; 2386 struct ethhdr *ehdr; 2387 2388 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2389 2390 switch (decap) { 2391 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2392 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2393 break; 2394 case DP_RX_DECAP_TYPE_RAW: 2395 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2396 decrypted); 2397 break; 2398 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2399 ehdr = (struct ethhdr *)msdu->data; 2400 2401 /* mac80211 allows fast path only for authorized STA */ 2402 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2403 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2404 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2405 break; 2406 } 2407 2408 /* PN for mcast packets will be validated in mac80211; 2409 * remove eth header and add 802.11 header. 2410 */ 2411 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2412 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2413 break; 2414 case DP_RX_DECAP_TYPE_8023: 2415 /* TODO: Handle undecap for these formats */ 2416 break; 2417 } 2418 } 2419 2420 struct ath12k_peer * 2421 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu, 2422 struct ath12k_dp_rx_info *rx_info) 2423 { 2424 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2425 struct ath12k_peer *peer = NULL; 2426 2427 lockdep_assert_held(&ab->base_lock); 2428 2429 if (rxcb->peer_id) 2430 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2431 2432 if (peer) 2433 return peer; 2434 2435 if (rx_info->addr2_present) 2436 peer = ath12k_peer_find_by_addr(ab, rx_info->addr2); 2437 2438 return peer; 2439 } 2440 2441 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2442 struct sk_buff *msdu, 2443 struct hal_rx_desc *rx_desc, 2444 struct ath12k_dp_rx_info *rx_info) 2445 { 2446 struct ath12k_base *ab = ar->ab; 2447 struct ath12k_skb_rxcb *rxcb; 2448 enum hal_encrypt_type enctype; 2449 bool is_decrypted = false; 2450 struct ieee80211_hdr *hdr; 2451 struct ath12k_peer *peer; 2452 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 2453 u32 err_bitmap; 2454 2455 /* PN for multicast packets will be checked in mac80211 */ 2456 rxcb = ATH12K_SKB_RXCB(msdu); 2457 rxcb->is_mcbc = rx_info->is_mcbc; 2458 2459 if (rxcb->is_mcbc) 2460 rxcb->peer_id = rx_info->peer_id; 2461 2462 spin_lock_bh(&ar->ab->base_lock); 2463 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu, rx_info); 2464 if (peer) { 2465 /* resetting mcbc bit because mcbc packets are unicast 2466 * packets only for AP as STA sends unicast packets. 2467 */ 2468 rxcb->is_mcbc = rxcb->is_mcbc && !peer->ucast_ra_only; 2469 2470 if (rxcb->is_mcbc) 2471 enctype = peer->sec_type_grp; 2472 else 2473 enctype = peer->sec_type; 2474 } else { 2475 enctype = HAL_ENCRYPT_TYPE_OPEN; 2476 } 2477 spin_unlock_bh(&ar->ab->base_lock); 2478 2479 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2480 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2481 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2482 2483 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2484 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2485 RX_FLAG_MMIC_ERROR | 2486 RX_FLAG_DECRYPTED | 2487 RX_FLAG_IV_STRIPPED | 2488 RX_FLAG_MMIC_STRIPPED); 2489 2490 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2491 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2492 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2493 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2494 2495 if (is_decrypted) { 2496 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2497 2498 if (rx_info->is_mcbc) 2499 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2500 RX_FLAG_ICV_STRIPPED; 2501 else 2502 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2503 RX_FLAG_PN_VALIDATED; 2504 } 2505 2506 ath12k_dp_rx_h_csum_offload(msdu, rx_info); 2507 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2508 enctype, rx_status, is_decrypted); 2509 2510 if (!is_decrypted || rx_info->is_mcbc) 2511 return; 2512 2513 if (rx_info->decap_type != DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2514 hdr = (void *)msdu->data; 2515 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2516 } 2517 } 2518 2519 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info) 2520 { 2521 struct ieee80211_supported_band *sband; 2522 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 2523 enum rx_msdu_start_pkt_type pkt_type = rx_info->pkt_type; 2524 u8 bw = rx_info->bw, sgi = rx_info->sgi; 2525 u8 rate_mcs = rx_info->rate_mcs, nss = rx_info->nss; 2526 bool is_cck; 2527 2528 switch (pkt_type) { 2529 case RX_MSDU_START_PKT_TYPE_11A: 2530 case RX_MSDU_START_PKT_TYPE_11B: 2531 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2532 sband = &ar->mac.sbands[rx_status->band]; 2533 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2534 is_cck); 2535 break; 2536 case RX_MSDU_START_PKT_TYPE_11N: 2537 rx_status->encoding = RX_ENC_HT; 2538 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2539 ath12k_warn(ar->ab, 2540 "Received with invalid mcs in HT mode %d\n", 2541 rate_mcs); 2542 break; 2543 } 2544 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2545 if (sgi) 2546 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2547 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2548 break; 2549 case RX_MSDU_START_PKT_TYPE_11AC: 2550 rx_status->encoding = RX_ENC_VHT; 2551 rx_status->rate_idx = rate_mcs; 2552 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2553 ath12k_warn(ar->ab, 2554 "Received with invalid mcs in VHT mode %d\n", 2555 rate_mcs); 2556 break; 2557 } 2558 rx_status->nss = nss; 2559 if (sgi) 2560 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2561 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2562 break; 2563 case RX_MSDU_START_PKT_TYPE_11AX: 2564 rx_status->rate_idx = rate_mcs; 2565 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2566 ath12k_warn(ar->ab, 2567 "Received with invalid mcs in HE mode %d\n", 2568 rate_mcs); 2569 break; 2570 } 2571 rx_status->encoding = RX_ENC_HE; 2572 rx_status->nss = nss; 2573 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2574 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2575 break; 2576 case RX_MSDU_START_PKT_TYPE_11BE: 2577 rx_status->rate_idx = rate_mcs; 2578 2579 if (rate_mcs > ATH12K_EHT_MCS_MAX) { 2580 ath12k_warn(ar->ab, 2581 "Received with invalid mcs in EHT mode %d\n", 2582 rate_mcs); 2583 break; 2584 } 2585 2586 rx_status->encoding = RX_ENC_EHT; 2587 rx_status->nss = nss; 2588 rx_status->eht.gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi); 2589 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2590 break; 2591 default: 2592 break; 2593 } 2594 } 2595 2596 void ath12k_dp_rx_h_fetch_info(struct ath12k_base *ab, struct hal_rx_desc *rx_desc, 2597 struct ath12k_dp_rx_info *rx_info) 2598 { 2599 rx_info->ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rx_desc); 2600 rx_info->l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rx_desc); 2601 rx_info->is_mcbc = ath12k_dp_rx_h_is_da_mcbc(ab, rx_desc); 2602 rx_info->decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2603 rx_info->pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2604 rx_info->sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2605 rx_info->rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2606 rx_info->bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2607 rx_info->nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2608 rx_info->tid = ath12k_dp_rx_h_tid(ab, rx_desc); 2609 rx_info->peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 2610 rx_info->phy_meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2611 2612 if (ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)) { 2613 ether_addr_copy(rx_info->addr2, 2614 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, rx_desc)); 2615 rx_info->addr2_present = true; 2616 } 2617 2618 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2619 rx_desc, sizeof(*rx_desc)); 2620 } 2621 2622 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info) 2623 { 2624 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 2625 u8 channel_num; 2626 u32 center_freq, meta_data; 2627 struct ieee80211_channel *channel; 2628 2629 rx_status->freq = 0; 2630 rx_status->rate_idx = 0; 2631 rx_status->nss = 0; 2632 rx_status->encoding = RX_ENC_LEGACY; 2633 rx_status->bw = RATE_INFO_BW_20; 2634 rx_status->enc_flags = 0; 2635 2636 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2637 2638 meta_data = rx_info->phy_meta_data; 2639 channel_num = meta_data; 2640 center_freq = meta_data >> 16; 2641 2642 rx_status->band = NUM_NL80211_BANDS; 2643 2644 if (center_freq >= ATH12K_MIN_6GHZ_FREQ && 2645 center_freq <= ATH12K_MAX_6GHZ_FREQ) { 2646 rx_status->band = NL80211_BAND_6GHZ; 2647 rx_status->freq = center_freq; 2648 } else if (channel_num >= 1 && channel_num <= 14) { 2649 rx_status->band = NL80211_BAND_2GHZ; 2650 } else if (channel_num >= 36 && channel_num <= 173) { 2651 rx_status->band = NL80211_BAND_5GHZ; 2652 } 2653 2654 if (unlikely(rx_status->band == NUM_NL80211_BANDS || 2655 !ath12k_ar_to_hw(ar)->wiphy->bands[rx_status->band])) { 2656 ath12k_warn(ar->ab, "sband is NULL for status band %d channel_num %d center_freq %d pdev_id %d\n", 2657 rx_status->band, channel_num, center_freq, ar->pdev_idx); 2658 2659 spin_lock_bh(&ar->data_lock); 2660 channel = ar->rx_channel; 2661 if (channel) { 2662 rx_status->band = channel->band; 2663 channel_num = 2664 ieee80211_frequency_to_channel(channel->center_freq); 2665 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2666 rx_status->band); 2667 } else { 2668 ath12k_err(ar->ab, "unable to determine channel, band for rx packet"); 2669 } 2670 spin_unlock_bh(&ar->data_lock); 2671 goto h_rate; 2672 } 2673 2674 if (rx_status->band != NL80211_BAND_6GHZ) 2675 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2676 rx_status->band); 2677 2678 h_rate: 2679 ath12k_dp_rx_h_rate(ar, rx_info); 2680 } 2681 2682 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2683 struct sk_buff *msdu, 2684 struct ath12k_dp_rx_info *rx_info) 2685 { 2686 struct ath12k_base *ab = ar->ab; 2687 struct ieee80211_rx_status *rx_status; 2688 struct ieee80211_sta *pubsta; 2689 struct ath12k_peer *peer; 2690 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2691 struct ieee80211_rx_status *status = rx_info->rx_status; 2692 u8 decap = rx_info->decap_type; 2693 bool is_mcbc = rxcb->is_mcbc; 2694 bool is_eapol = rxcb->is_eapol; 2695 2696 spin_lock_bh(&ab->base_lock); 2697 peer = ath12k_dp_rx_h_find_peer(ab, msdu, rx_info); 2698 2699 pubsta = peer ? peer->sta : NULL; 2700 2701 if (pubsta && pubsta->valid_links) { 2702 status->link_valid = 1; 2703 status->link_id = peer->link_id; 2704 } 2705 2706 spin_unlock_bh(&ab->base_lock); 2707 2708 ath12k_dbg(ab, ATH12K_DBG_DATA, 2709 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2710 msdu, 2711 msdu->len, 2712 peer ? peer->addr : NULL, 2713 rxcb->tid, 2714 is_mcbc ? "mcast" : "ucast", 2715 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2716 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2717 (status->encoding == RX_ENC_HT) ? "ht" : "", 2718 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2719 (status->encoding == RX_ENC_HE) ? "he" : "", 2720 (status->encoding == RX_ENC_EHT) ? "eht" : "", 2721 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2722 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2723 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2724 (status->bw == RATE_INFO_BW_320) ? "320" : "", 2725 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2726 status->rate_idx, 2727 status->nss, 2728 status->freq, 2729 status->band, status->flag, 2730 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2731 !!(status->flag & RX_FLAG_MMIC_ERROR), 2732 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2733 2734 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2735 msdu->data, msdu->len); 2736 2737 rx_status = IEEE80211_SKB_RXCB(msdu); 2738 *rx_status = *status; 2739 2740 /* TODO: trace rx packet */ 2741 2742 /* PN for multicast packets are not validate in HW, 2743 * so skip 802.3 rx path 2744 * Also, fast_rx expects the STA to be authorized, hence 2745 * eapol packets are sent in slow path. 2746 */ 2747 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2748 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2749 rx_status->flag |= RX_FLAG_8023; 2750 2751 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 2752 } 2753 2754 static bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base *ab, 2755 struct hal_rx_desc *rx_desc, 2756 struct sk_buff *msdu) 2757 { 2758 struct ieee80211_hdr *hdr; 2759 u8 decap_type; 2760 u32 hdr_len; 2761 2762 decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2763 if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI) 2764 return true; 2765 2766 hdr = (struct ieee80211_hdr *)msdu->data; 2767 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2768 2769 if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN))) 2770 return true; 2771 2772 ab->device_stats.invalid_rbm++; 2773 WARN_ON_ONCE(1); 2774 return false; 2775 } 2776 2777 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2778 struct sk_buff *msdu, 2779 struct sk_buff_head *msdu_list, 2780 struct ath12k_dp_rx_info *rx_info) 2781 { 2782 struct ath12k_base *ab = ar->ab; 2783 struct hal_rx_desc *rx_desc, *lrx_desc; 2784 struct ath12k_skb_rxcb *rxcb; 2785 struct sk_buff *last_buf; 2786 u8 l3_pad_bytes; 2787 u16 msdu_len; 2788 int ret; 2789 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2790 2791 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2792 if (!last_buf) { 2793 ath12k_warn(ab, 2794 "No valid Rx buffer to access MSDU_END tlv\n"); 2795 ret = -EIO; 2796 goto free_out; 2797 } 2798 2799 rx_desc = (struct hal_rx_desc *)msdu->data; 2800 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2801 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2802 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2803 ret = -EIO; 2804 goto free_out; 2805 } 2806 2807 rxcb = ATH12K_SKB_RXCB(msdu); 2808 rxcb->rx_desc = rx_desc; 2809 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2810 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2811 2812 if (rxcb->is_frag) { 2813 skb_pull(msdu, hal_rx_desc_sz); 2814 } else if (!rxcb->is_continuation) { 2815 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2816 ret = -EINVAL; 2817 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2818 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2819 sizeof(*rx_desc)); 2820 goto free_out; 2821 } 2822 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2823 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2824 } else { 2825 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2826 msdu, last_buf, 2827 l3_pad_bytes, msdu_len); 2828 if (ret) { 2829 ath12k_warn(ab, 2830 "failed to coalesce msdu rx buffer%d\n", ret); 2831 goto free_out; 2832 } 2833 } 2834 2835 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) { 2836 ret = -EINVAL; 2837 goto free_out; 2838 } 2839 2840 ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); 2841 ath12k_dp_rx_h_ppdu(ar, rx_info); 2842 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_info); 2843 2844 rx_info->rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2845 2846 return 0; 2847 2848 free_out: 2849 return ret; 2850 } 2851 2852 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2853 struct napi_struct *napi, 2854 struct sk_buff_head *msdu_list, 2855 int ring_id) 2856 { 2857 struct ath12k_hw_group *ag = ab->ag; 2858 struct ieee80211_rx_status rx_status = {}; 2859 struct ath12k_skb_rxcb *rxcb; 2860 struct sk_buff *msdu; 2861 struct ath12k *ar; 2862 struct ath12k_hw_link *hw_links = ag->hw_links; 2863 struct ath12k_base *partner_ab; 2864 struct ath12k_dp_rx_info rx_info; 2865 u8 hw_link_id, pdev_id; 2866 int ret; 2867 2868 if (skb_queue_empty(msdu_list)) 2869 return; 2870 2871 rx_info.addr2_present = false; 2872 rx_info.rx_status = &rx_status; 2873 2874 rcu_read_lock(); 2875 2876 while ((msdu = __skb_dequeue(msdu_list))) { 2877 rxcb = ATH12K_SKB_RXCB(msdu); 2878 hw_link_id = rxcb->hw_link_id; 2879 partner_ab = ath12k_ag_to_ab(ag, 2880 hw_links[hw_link_id].device_id); 2881 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params, 2882 hw_links[hw_link_id].pdev_idx); 2883 ar = partner_ab->pdevs[pdev_id].ar; 2884 if (!rcu_dereference(partner_ab->pdevs_active[pdev_id])) { 2885 dev_kfree_skb_any(msdu); 2886 continue; 2887 } 2888 2889 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) { 2890 dev_kfree_skb_any(msdu); 2891 continue; 2892 } 2893 2894 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_info); 2895 if (ret) { 2896 ath12k_dbg(ab, ATH12K_DBG_DATA, 2897 "Unable to process msdu %d", ret); 2898 dev_kfree_skb_any(msdu); 2899 continue; 2900 } 2901 2902 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_info); 2903 } 2904 2905 rcu_read_unlock(); 2906 } 2907 2908 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab, 2909 enum ath12k_peer_metadata_version ver, 2910 __le32 peer_metadata) 2911 { 2912 switch (ver) { 2913 default: 2914 ath12k_warn(ab, "Unknown peer metadata version: %d", ver); 2915 fallthrough; 2916 case ATH12K_PEER_METADATA_V0: 2917 return le32_get_bits(peer_metadata, 2918 RX_MPDU_DESC_META_DATA_V0_PEER_ID); 2919 case ATH12K_PEER_METADATA_V1: 2920 return le32_get_bits(peer_metadata, 2921 RX_MPDU_DESC_META_DATA_V1_PEER_ID); 2922 case ATH12K_PEER_METADATA_V1A: 2923 return le32_get_bits(peer_metadata, 2924 RX_MPDU_DESC_META_DATA_V1A_PEER_ID); 2925 case ATH12K_PEER_METADATA_V1B: 2926 return le32_get_bits(peer_metadata, 2927 RX_MPDU_DESC_META_DATA_V1B_PEER_ID); 2928 } 2929 } 2930 2931 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2932 struct napi_struct *napi, int budget) 2933 { 2934 struct ath12k_hw_group *ag = ab->ag; 2935 struct list_head rx_desc_used_list[ATH12K_MAX_DEVICES]; 2936 struct ath12k_hw_link *hw_links = ag->hw_links; 2937 int num_buffs_reaped[ATH12K_MAX_DEVICES] = {}; 2938 struct ath12k_rx_desc_info *desc_info; 2939 struct ath12k_dp *dp = &ab->dp; 2940 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2941 struct hal_reo_dest_ring *desc; 2942 struct ath12k_base *partner_ab; 2943 struct sk_buff_head msdu_list; 2944 struct ath12k_skb_rxcb *rxcb; 2945 int total_msdu_reaped = 0; 2946 u8 hw_link_id, device_id; 2947 struct hal_srng *srng; 2948 struct sk_buff *msdu; 2949 bool done = false; 2950 u64 desc_va; 2951 2952 __skb_queue_head_init(&msdu_list); 2953 2954 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) 2955 INIT_LIST_HEAD(&rx_desc_used_list[device_id]); 2956 2957 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2958 2959 spin_lock_bh(&srng->lock); 2960 2961 try_again: 2962 ath12k_hal_srng_access_begin(ab, srng); 2963 2964 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2965 struct rx_mpdu_desc *mpdu_info; 2966 struct rx_msdu_desc *msdu_info; 2967 enum hal_reo_dest_ring_push_reason push_reason; 2968 u32 cookie; 2969 2970 cookie = le32_get_bits(desc->buf_addr_info.info1, 2971 BUFFER_ADDR_INFO1_SW_COOKIE); 2972 2973 hw_link_id = le32_get_bits(desc->info0, 2974 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2975 2976 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2977 le32_to_cpu(desc->buf_va_lo)); 2978 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2979 2980 device_id = hw_links[hw_link_id].device_id; 2981 partner_ab = ath12k_ag_to_ab(ag, device_id); 2982 if (unlikely(!partner_ab)) { 2983 if (desc_info->skb) { 2984 dev_kfree_skb_any(desc_info->skb); 2985 desc_info->skb = NULL; 2986 } 2987 2988 continue; 2989 } 2990 2991 /* retry manual desc retrieval */ 2992 if (!desc_info) { 2993 desc_info = ath12k_dp_get_rx_desc(partner_ab, cookie); 2994 if (!desc_info) { 2995 ath12k_warn(partner_ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n", 2996 cookie); 2997 continue; 2998 } 2999 } 3000 3001 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3002 ath12k_warn(ab, "Check HW CC implementation"); 3003 3004 msdu = desc_info->skb; 3005 desc_info->skb = NULL; 3006 3007 list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]); 3008 3009 rxcb = ATH12K_SKB_RXCB(msdu); 3010 dma_unmap_single(partner_ab->dev, rxcb->paddr, 3011 msdu->len + skb_tailroom(msdu), 3012 DMA_FROM_DEVICE); 3013 3014 num_buffs_reaped[device_id]++; 3015 ab->device_stats.reo_rx[ring_id][ab->device_id]++; 3016 3017 push_reason = le32_get_bits(desc->info0, 3018 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 3019 if (push_reason != 3020 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 3021 dev_kfree_skb_any(msdu); 3022 ab->device_stats.hal_reo_error[ring_id]++; 3023 continue; 3024 } 3025 3026 msdu_info = &desc->rx_msdu_info; 3027 mpdu_info = &desc->rx_mpdu_info; 3028 3029 rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) & 3030 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 3031 rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) & 3032 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 3033 rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) & 3034 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 3035 rxcb->hw_link_id = hw_link_id; 3036 rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver, 3037 mpdu_info->peer_meta_data); 3038 rxcb->tid = le32_get_bits(mpdu_info->info0, 3039 RX_MPDU_DESC_INFO0_TID); 3040 3041 __skb_queue_tail(&msdu_list, msdu); 3042 3043 if (!rxcb->is_continuation) { 3044 total_msdu_reaped++; 3045 done = true; 3046 } else { 3047 done = false; 3048 } 3049 3050 if (total_msdu_reaped >= budget) 3051 break; 3052 } 3053 3054 /* Hw might have updated the head pointer after we cached it. 3055 * In this case, even though there are entries in the ring we'll 3056 * get rx_desc NULL. Give the read another try with updated cached 3057 * head pointer so that we can reap complete MPDU in the current 3058 * rx processing. 3059 */ 3060 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 3061 ath12k_hal_srng_access_end(ab, srng); 3062 goto try_again; 3063 } 3064 3065 ath12k_hal_srng_access_end(ab, srng); 3066 3067 spin_unlock_bh(&srng->lock); 3068 3069 if (!total_msdu_reaped) 3070 goto exit; 3071 3072 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) { 3073 if (!num_buffs_reaped[device_id]) 3074 continue; 3075 3076 partner_ab = ath12k_ag_to_ab(ag, device_id); 3077 rx_ring = &partner_ab->dp.rx_refill_buf_ring; 3078 3079 ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring, 3080 &rx_desc_used_list[device_id], 3081 num_buffs_reaped[device_id]); 3082 } 3083 3084 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 3085 ring_id); 3086 3087 exit: 3088 return total_msdu_reaped; 3089 } 3090 3091 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 3092 { 3093 struct ath12k_dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer, 3094 frag_timer); 3095 3096 spin_lock_bh(&rx_tid->ab->base_lock); 3097 if (rx_tid->last_frag_no && 3098 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 3099 spin_unlock_bh(&rx_tid->ab->base_lock); 3100 return; 3101 } 3102 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3103 spin_unlock_bh(&rx_tid->ab->base_lock); 3104 } 3105 3106 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 3107 { 3108 struct ath12k_base *ab = ar->ab; 3109 struct crypto_shash *tfm; 3110 struct ath12k_peer *peer; 3111 struct ath12k_dp_rx_tid *rx_tid; 3112 int i; 3113 3114 tfm = crypto_alloc_shash("michael_mic", 0, 0); 3115 if (IS_ERR(tfm)) 3116 return PTR_ERR(tfm); 3117 3118 spin_lock_bh(&ab->base_lock); 3119 3120 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 3121 if (!peer) { 3122 spin_unlock_bh(&ab->base_lock); 3123 crypto_free_shash(tfm); 3124 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 3125 return -ENOENT; 3126 } 3127 3128 if (!peer->primary_link) { 3129 spin_unlock_bh(&ab->base_lock); 3130 crypto_free_shash(tfm); 3131 return 0; 3132 } 3133 3134 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3135 rx_tid = &peer->rx_tid[i]; 3136 rx_tid->ab = ab; 3137 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 3138 skb_queue_head_init(&rx_tid->rx_frags); 3139 } 3140 3141 peer->tfm_mmic = tfm; 3142 peer->dp_setup_done = true; 3143 spin_unlock_bh(&ab->base_lock); 3144 3145 return 0; 3146 } 3147 3148 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3149 struct ieee80211_hdr *hdr, u8 *data, 3150 size_t data_len, u8 *mic) 3151 { 3152 SHASH_DESC_ON_STACK(desc, tfm); 3153 u8 mic_hdr[16] = {}; 3154 u8 tid = 0; 3155 int ret; 3156 3157 if (!tfm) 3158 return -EINVAL; 3159 3160 desc->tfm = tfm; 3161 3162 ret = crypto_shash_setkey(tfm, key, 8); 3163 if (ret) 3164 goto out; 3165 3166 ret = crypto_shash_init(desc); 3167 if (ret) 3168 goto out; 3169 3170 /* TKIP MIC header */ 3171 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3172 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3173 if (ieee80211_is_data_qos(hdr->frame_control)) 3174 tid = ieee80211_get_tid(hdr); 3175 mic_hdr[12] = tid; 3176 3177 ret = crypto_shash_update(desc, mic_hdr, 16); 3178 if (ret) 3179 goto out; 3180 ret = crypto_shash_update(desc, data, data_len); 3181 if (ret) 3182 goto out; 3183 ret = crypto_shash_final(desc, mic); 3184 out: 3185 shash_desc_zero(desc); 3186 return ret; 3187 } 3188 3189 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 3190 struct sk_buff *msdu) 3191 { 3192 struct ath12k_base *ab = ar->ab; 3193 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3194 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3195 struct ieee80211_key_conf *key_conf; 3196 struct ieee80211_hdr *hdr; 3197 struct ath12k_dp_rx_info rx_info; 3198 u8 mic[IEEE80211_CCMP_MIC_LEN]; 3199 int head_len, tail_len, ret; 3200 size_t data_len; 3201 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3202 u8 *key, *data; 3203 u8 key_idx; 3204 3205 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 3206 return 0; 3207 3208 rx_info.addr2_present = false; 3209 rx_info.rx_status = rxs; 3210 3211 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3212 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3213 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 3214 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3215 3216 if (!is_multicast_ether_addr(hdr->addr1)) 3217 key_idx = peer->ucast_keyidx; 3218 else 3219 key_idx = peer->mcast_keyidx; 3220 3221 key_conf = peer->keys[key_idx]; 3222 3223 data = msdu->data + head_len; 3224 data_len = msdu->len - head_len - tail_len; 3225 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3226 3227 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3228 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3229 goto mic_fail; 3230 3231 return 0; 3232 3233 mic_fail: 3234 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 3235 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 3236 3237 ath12k_dp_rx_h_fetch_info(ab, rx_desc, &rx_info); 3238 3239 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3240 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3241 skb_pull(msdu, hal_rx_desc_sz); 3242 3243 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) 3244 return -EINVAL; 3245 3246 ath12k_dp_rx_h_ppdu(ar, &rx_info); 3247 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 3248 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3249 ieee80211_rx(ath12k_ar_to_hw(ar), msdu); 3250 return -EINVAL; 3251 } 3252 3253 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 3254 enum hal_encrypt_type enctype, u32 flags) 3255 { 3256 struct ieee80211_hdr *hdr; 3257 size_t hdr_len; 3258 size_t crypto_len; 3259 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3260 3261 if (!flags) 3262 return; 3263 3264 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3265 3266 if (flags & RX_FLAG_MIC_STRIPPED) 3267 skb_trim(msdu, msdu->len - 3268 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 3269 3270 if (flags & RX_FLAG_ICV_STRIPPED) 3271 skb_trim(msdu, msdu->len - 3272 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 3273 3274 if (flags & RX_FLAG_IV_STRIPPED) { 3275 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3276 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 3277 3278 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 3279 msdu->data + hal_rx_desc_sz, hdr_len); 3280 skb_pull(msdu, crypto_len); 3281 } 3282 } 3283 3284 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 3285 struct ath12k_peer *peer, 3286 struct ath12k_dp_rx_tid *rx_tid, 3287 struct sk_buff **defrag_skb) 3288 { 3289 struct ath12k_base *ab = ar->ab; 3290 struct hal_rx_desc *rx_desc; 3291 struct sk_buff *skb, *first_frag, *last_frag; 3292 struct ieee80211_hdr *hdr; 3293 enum hal_encrypt_type enctype; 3294 bool is_decrypted = false; 3295 int msdu_len = 0; 3296 int extra_space; 3297 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3298 3299 first_frag = skb_peek(&rx_tid->rx_frags); 3300 last_frag = skb_peek_tail(&rx_tid->rx_frags); 3301 3302 skb_queue_walk(&rx_tid->rx_frags, skb) { 3303 flags = 0; 3304 rx_desc = (struct hal_rx_desc *)skb->data; 3305 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3306 3307 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 3308 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 3309 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 3310 rx_desc); 3311 3312 if (is_decrypted) { 3313 if (skb != first_frag) 3314 flags |= RX_FLAG_IV_STRIPPED; 3315 if (skb != last_frag) 3316 flags |= RX_FLAG_ICV_STRIPPED | 3317 RX_FLAG_MIC_STRIPPED; 3318 } 3319 3320 /* RX fragments are always raw packets */ 3321 if (skb != last_frag) 3322 skb_trim(skb, skb->len - FCS_LEN); 3323 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3324 3325 if (skb != first_frag) 3326 skb_pull(skb, hal_rx_desc_sz + 3327 ieee80211_hdrlen(hdr->frame_control)); 3328 msdu_len += skb->len; 3329 } 3330 3331 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3332 if (extra_space > 0 && 3333 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3334 return -ENOMEM; 3335 3336 __skb_unlink(first_frag, &rx_tid->rx_frags); 3337 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3338 skb_put_data(first_frag, skb->data, skb->len); 3339 dev_kfree_skb_any(skb); 3340 } 3341 3342 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3343 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3344 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 3345 3346 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3347 first_frag = NULL; 3348 3349 *defrag_skb = first_frag; 3350 return 0; 3351 } 3352 3353 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 3354 struct ath12k_dp_rx_tid *rx_tid, 3355 struct sk_buff *defrag_skb) 3356 { 3357 struct ath12k_base *ab = ar->ab; 3358 struct ath12k_dp *dp = &ab->dp; 3359 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3360 struct hal_reo_entrance_ring *reo_ent_ring; 3361 struct hal_reo_dest_ring *reo_dest_ring; 3362 struct dp_link_desc_bank *link_desc_banks; 3363 struct hal_rx_msdu_link *msdu_link; 3364 struct hal_rx_msdu_details *msdu0; 3365 struct hal_srng *srng; 3366 dma_addr_t link_paddr, buf_paddr; 3367 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 3368 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi; 3369 int ret; 3370 struct ath12k_rx_desc_info *desc_info; 3371 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm; 3372 u8 dst_ind; 3373 3374 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3375 link_desc_banks = dp->link_desc_banks; 3376 reo_dest_ring = rx_tid->dst_ring_desc; 3377 3378 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 3379 &link_paddr, &cookie); 3380 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 3381 3382 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3383 (link_paddr - link_desc_banks[desc_bank].paddr)); 3384 msdu0 = &msdu_link->msdu_link[0]; 3385 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 3386 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 3387 3388 memset(msdu0, 0, sizeof(*msdu0)); 3389 3390 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 3391 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 3392 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3393 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3394 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3395 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3396 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3397 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3398 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3399 3400 /* change msdu len in hal rx desc */ 3401 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3402 3403 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3404 defrag_skb->len + skb_tailroom(defrag_skb), 3405 DMA_TO_DEVICE); 3406 if (dma_mapping_error(ab->dev, buf_paddr)) 3407 return -ENOMEM; 3408 3409 spin_lock_bh(&dp->rx_desc_lock); 3410 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3411 struct ath12k_rx_desc_info, 3412 list); 3413 if (!desc_info) { 3414 spin_unlock_bh(&dp->rx_desc_lock); 3415 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3416 ret = -ENOMEM; 3417 goto err_unmap_dma; 3418 } 3419 3420 desc_info->skb = defrag_skb; 3421 desc_info->in_use = true; 3422 3423 list_del(&desc_info->list); 3424 spin_unlock_bh(&dp->rx_desc_lock); 3425 3426 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3427 3428 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3429 desc_info->cookie, 3430 HAL_RX_BUF_RBM_SW3_BM); 3431 3432 /* Fill mpdu details into reo entrance ring */ 3433 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3434 3435 spin_lock_bh(&srng->lock); 3436 ath12k_hal_srng_access_begin(ab, srng); 3437 3438 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3439 if (!reo_ent_ring) { 3440 ath12k_hal_srng_access_end(ab, srng); 3441 spin_unlock_bh(&srng->lock); 3442 ret = -ENOSPC; 3443 goto err_free_desc; 3444 } 3445 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3446 3447 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3448 cookie, 3449 idle_link_rbm); 3450 3451 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3452 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3453 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3454 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3455 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3456 3457 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3458 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3459 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3460 3461 if (ab->hw_params->reoq_lut_support) { 3462 reo_ent_ring->queue_addr_lo = reo_dest_ring->rx_mpdu_info.peer_meta_data; 3463 queue_addr_hi = 0; 3464 } else { 3465 reo_ent_ring->queue_addr_lo = 3466 cpu_to_le32(lower_32_bits(rx_tid->qbuf.paddr_aligned)); 3467 queue_addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 3468 } 3469 3470 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi, 3471 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) | 3472 le32_encode_bits(dst_ind, 3473 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3474 3475 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3476 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3477 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3478 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3479 reo_ent_ring->info2 = 3480 cpu_to_le32(u32_get_bits(dest_ring_info0, 3481 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3482 3483 ath12k_hal_srng_access_end(ab, srng); 3484 spin_unlock_bh(&srng->lock); 3485 3486 return 0; 3487 3488 err_free_desc: 3489 spin_lock_bh(&dp->rx_desc_lock); 3490 desc_info->in_use = false; 3491 desc_info->skb = NULL; 3492 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3493 spin_unlock_bh(&dp->rx_desc_lock); 3494 err_unmap_dma: 3495 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3496 DMA_TO_DEVICE); 3497 return ret; 3498 } 3499 3500 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3501 struct sk_buff *a, struct sk_buff *b) 3502 { 3503 int frag1, frag2; 3504 3505 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3506 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3507 3508 return frag1 - frag2; 3509 } 3510 3511 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3512 struct sk_buff_head *frag_list, 3513 struct sk_buff *cur_frag) 3514 { 3515 struct sk_buff *skb; 3516 int cmp; 3517 3518 skb_queue_walk(frag_list, skb) { 3519 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3520 if (cmp < 0) 3521 continue; 3522 __skb_queue_before(frag_list, skb, cur_frag); 3523 return; 3524 } 3525 __skb_queue_tail(frag_list, cur_frag); 3526 } 3527 3528 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3529 { 3530 struct ieee80211_hdr *hdr; 3531 u64 pn = 0; 3532 u8 *ehdr; 3533 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3534 3535 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3536 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3537 3538 pn = ehdr[0]; 3539 pn |= (u64)ehdr[1] << 8; 3540 pn |= (u64)ehdr[4] << 16; 3541 pn |= (u64)ehdr[5] << 24; 3542 pn |= (u64)ehdr[6] << 32; 3543 pn |= (u64)ehdr[7] << 40; 3544 3545 return pn; 3546 } 3547 3548 static bool 3549 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3550 { 3551 struct ath12k_base *ab = ar->ab; 3552 enum hal_encrypt_type encrypt_type; 3553 struct sk_buff *first_frag, *skb; 3554 struct hal_rx_desc *desc; 3555 u64 last_pn; 3556 u64 cur_pn; 3557 3558 first_frag = skb_peek(&rx_tid->rx_frags); 3559 desc = (struct hal_rx_desc *)first_frag->data; 3560 3561 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3562 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3563 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3564 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3565 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3566 return true; 3567 3568 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3569 skb_queue_walk(&rx_tid->rx_frags, skb) { 3570 if (skb == first_frag) 3571 continue; 3572 3573 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3574 if (cur_pn != last_pn + 1) 3575 return false; 3576 last_pn = cur_pn; 3577 } 3578 return true; 3579 } 3580 3581 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3582 struct sk_buff *msdu, 3583 struct hal_reo_dest_ring *ring_desc) 3584 { 3585 struct ath12k_base *ab = ar->ab; 3586 struct hal_rx_desc *rx_desc; 3587 struct ath12k_peer *peer; 3588 struct ath12k_dp_rx_tid *rx_tid; 3589 struct sk_buff *defrag_skb = NULL; 3590 u32 peer_id; 3591 u16 seqno, frag_no; 3592 u8 tid; 3593 int ret = 0; 3594 bool more_frags; 3595 3596 rx_desc = (struct hal_rx_desc *)msdu->data; 3597 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3598 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3599 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3600 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3601 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3602 3603 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3604 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3605 tid > IEEE80211_NUM_TIDS) 3606 return -EINVAL; 3607 3608 /* received unfragmented packet in reo 3609 * exception ring, this shouldn't happen 3610 * as these packets typically come from 3611 * reo2sw srngs. 3612 */ 3613 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3614 return -EINVAL; 3615 3616 spin_lock_bh(&ab->base_lock); 3617 peer = ath12k_peer_find_by_id(ab, peer_id); 3618 if (!peer) { 3619 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3620 peer_id); 3621 ret = -ENOENT; 3622 goto out_unlock; 3623 } 3624 3625 if (!peer->dp_setup_done) { 3626 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3627 peer->addr, peer_id); 3628 ret = -ENOENT; 3629 goto out_unlock; 3630 } 3631 3632 rx_tid = &peer->rx_tid[tid]; 3633 3634 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3635 skb_queue_empty(&rx_tid->rx_frags)) { 3636 /* Flush stored fragments and start a new sequence */ 3637 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3638 rx_tid->cur_sn = seqno; 3639 } 3640 3641 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3642 /* Fragment already present */ 3643 ret = -EINVAL; 3644 goto out_unlock; 3645 } 3646 3647 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3648 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3649 else 3650 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3651 3652 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3653 if (!more_frags) 3654 rx_tid->last_frag_no = frag_no; 3655 3656 if (frag_no == 0) { 3657 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3658 sizeof(*rx_tid->dst_ring_desc), 3659 GFP_ATOMIC); 3660 if (!rx_tid->dst_ring_desc) { 3661 ret = -ENOMEM; 3662 goto out_unlock; 3663 } 3664 } else { 3665 ath12k_dp_rx_link_desc_return(ab, &ring_desc->buf_addr_info, 3666 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3667 } 3668 3669 if (!rx_tid->last_frag_no || 3670 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3671 mod_timer(&rx_tid->frag_timer, jiffies + 3672 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3673 goto out_unlock; 3674 } 3675 3676 spin_unlock_bh(&ab->base_lock); 3677 timer_delete_sync(&rx_tid->frag_timer); 3678 spin_lock_bh(&ab->base_lock); 3679 3680 peer = ath12k_peer_find_by_id(ab, peer_id); 3681 if (!peer) 3682 goto err_frags_cleanup; 3683 3684 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3685 goto err_frags_cleanup; 3686 3687 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3688 goto err_frags_cleanup; 3689 3690 if (!defrag_skb) 3691 goto err_frags_cleanup; 3692 3693 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3694 goto err_frags_cleanup; 3695 3696 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3697 goto out_unlock; 3698 3699 err_frags_cleanup: 3700 dev_kfree_skb_any(defrag_skb); 3701 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3702 out_unlock: 3703 spin_unlock_bh(&ab->base_lock); 3704 return ret; 3705 } 3706 3707 static int 3708 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3709 struct list_head *used_list, 3710 bool drop, u32 cookie) 3711 { 3712 struct ath12k_base *ab = ar->ab; 3713 struct sk_buff *msdu; 3714 struct ath12k_skb_rxcb *rxcb; 3715 struct hal_rx_desc *rx_desc; 3716 u16 msdu_len; 3717 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3718 struct ath12k_rx_desc_info *desc_info; 3719 u64 desc_va; 3720 3721 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3722 le32_to_cpu(desc->buf_va_lo)); 3723 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3724 3725 /* retry manual desc retrieval */ 3726 if (!desc_info) { 3727 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3728 if (!desc_info) { 3729 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n", 3730 cookie); 3731 return -EINVAL; 3732 } 3733 } 3734 3735 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3736 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3737 3738 msdu = desc_info->skb; 3739 desc_info->skb = NULL; 3740 3741 list_add_tail(&desc_info->list, used_list); 3742 3743 rxcb = ATH12K_SKB_RXCB(msdu); 3744 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3745 msdu->len + skb_tailroom(msdu), 3746 DMA_FROM_DEVICE); 3747 3748 if (drop) { 3749 dev_kfree_skb_any(msdu); 3750 return 0; 3751 } 3752 3753 rcu_read_lock(); 3754 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3755 dev_kfree_skb_any(msdu); 3756 goto exit; 3757 } 3758 3759 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) { 3760 dev_kfree_skb_any(msdu); 3761 goto exit; 3762 } 3763 3764 rx_desc = (struct hal_rx_desc *)msdu->data; 3765 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3766 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3767 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3768 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3769 sizeof(*rx_desc)); 3770 dev_kfree_skb_any(msdu); 3771 goto exit; 3772 } 3773 3774 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3775 3776 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3777 dev_kfree_skb_any(msdu); 3778 ath12k_dp_rx_link_desc_return(ar->ab, &desc->buf_addr_info, 3779 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3780 } 3781 exit: 3782 rcu_read_unlock(); 3783 return 0; 3784 } 3785 3786 static int ath12k_dp_h_msdu_buffer_type(struct ath12k_base *ab, 3787 struct list_head *list, 3788 struct hal_reo_dest_ring *desc) 3789 { 3790 struct ath12k_rx_desc_info *desc_info; 3791 struct ath12k_skb_rxcb *rxcb; 3792 struct sk_buff *msdu; 3793 u64 desc_va; 3794 3795 ab->device_stats.reo_excep_msdu_buf_type++; 3796 3797 desc_va = (u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3798 le32_to_cpu(desc->buf_va_lo); 3799 desc_info = (struct ath12k_rx_desc_info *)(uintptr_t)desc_va; 3800 if (!desc_info) { 3801 u32 cookie; 3802 3803 cookie = le32_get_bits(desc->buf_addr_info.info1, 3804 BUFFER_ADDR_INFO1_SW_COOKIE); 3805 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3806 if (!desc_info) { 3807 ath12k_warn(ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n", 3808 cookie); 3809 return -EINVAL; 3810 } 3811 } 3812 3813 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) { 3814 ath12k_warn(ab, "rx exception, magic check failed with value: %u\n", 3815 desc_info->magic); 3816 return -EINVAL; 3817 } 3818 3819 msdu = desc_info->skb; 3820 desc_info->skb = NULL; 3821 list_add_tail(&desc_info->list, list); 3822 rxcb = ATH12K_SKB_RXCB(msdu); 3823 dma_unmap_single(ab->dev, rxcb->paddr, msdu->len + skb_tailroom(msdu), 3824 DMA_FROM_DEVICE); 3825 dev_kfree_skb_any(msdu); 3826 3827 return 0; 3828 } 3829 3830 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3831 int budget) 3832 { 3833 struct ath12k_hw_group *ag = ab->ag; 3834 struct list_head rx_desc_used_list[ATH12K_MAX_DEVICES]; 3835 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3836 int num_buffs_reaped[ATH12K_MAX_DEVICES] = {}; 3837 struct dp_link_desc_bank *link_desc_banks; 3838 enum hal_rx_buf_return_buf_manager rbm; 3839 struct hal_rx_msdu_link *link_desc_va; 3840 int tot_n_bufs_reaped, quota, ret, i; 3841 struct hal_reo_dest_ring *reo_desc; 3842 struct dp_rxdma_ring *rx_ring; 3843 struct dp_srng *reo_except; 3844 struct ath12k_hw_link *hw_links = ag->hw_links; 3845 struct ath12k_base *partner_ab; 3846 u8 hw_link_id, device_id; 3847 u32 desc_bank, num_msdus; 3848 struct hal_srng *srng; 3849 struct ath12k *ar; 3850 dma_addr_t paddr; 3851 bool is_frag; 3852 bool drop; 3853 int pdev_id; 3854 3855 tot_n_bufs_reaped = 0; 3856 quota = budget; 3857 3858 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) 3859 INIT_LIST_HEAD(&rx_desc_used_list[device_id]); 3860 3861 reo_except = &ab->dp.reo_except_ring; 3862 3863 srng = &ab->hal.srng_list[reo_except->ring_id]; 3864 3865 spin_lock_bh(&srng->lock); 3866 3867 ath12k_hal_srng_access_begin(ab, srng); 3868 3869 while (budget && 3870 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3871 drop = false; 3872 ab->device_stats.err_ring_pkts++; 3873 3874 hw_link_id = le32_get_bits(reo_desc->info0, 3875 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3876 device_id = hw_links[hw_link_id].device_id; 3877 partner_ab = ath12k_ag_to_ab(ag, device_id); 3878 3879 /* Below case is added to handle data packet from un-associated clients. 3880 * As it is expected that AST lookup will fail for 3881 * un-associated station's data packets. 3882 */ 3883 if (le32_get_bits(reo_desc->info0, HAL_REO_DEST_RING_INFO0_BUFFER_TYPE) == 3884 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU) { 3885 if (!ath12k_dp_h_msdu_buffer_type(partner_ab, 3886 &rx_desc_used_list[device_id], 3887 reo_desc)) { 3888 num_buffs_reaped[device_id]++; 3889 tot_n_bufs_reaped++; 3890 } 3891 goto next_desc; 3892 } 3893 3894 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3895 &desc_bank); 3896 if (ret) { 3897 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3898 ret); 3899 continue; 3900 } 3901 3902 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params, 3903 hw_links[hw_link_id].pdev_idx); 3904 ar = partner_ab->pdevs[pdev_id].ar; 3905 3906 link_desc_banks = partner_ab->dp.link_desc_banks; 3907 link_desc_va = link_desc_banks[desc_bank].vaddr + 3908 (paddr - link_desc_banks[desc_bank].paddr); 3909 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3910 &rbm); 3911 if (rbm != partner_ab->dp.idle_link_rbm && 3912 rbm != HAL_RX_BUF_RBM_SW3_BM && 3913 rbm != partner_ab->hw_params->hal_params->rx_buf_rbm) { 3914 ab->device_stats.invalid_rbm++; 3915 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3916 ath12k_dp_rx_link_desc_return(partner_ab, 3917 &reo_desc->buf_addr_info, 3918 HAL_WBM_REL_BM_ACT_REL_MSDU); 3919 continue; 3920 } 3921 3922 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3923 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3924 3925 /* Process only rx fragments with one msdu per link desc below, and drop 3926 * msdu's indicated due to error reasons. 3927 * Dynamic fragmentation not supported in Multi-link client, so drop the 3928 * partner device buffers. 3929 */ 3930 if (!is_frag || num_msdus > 1 || 3931 partner_ab->device_id != ab->device_id) { 3932 drop = true; 3933 3934 /* Return the link desc back to wbm idle list */ 3935 ath12k_dp_rx_link_desc_return(partner_ab, 3936 &reo_desc->buf_addr_info, 3937 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3938 } 3939 3940 for (i = 0; i < num_msdus; i++) { 3941 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, 3942 &rx_desc_used_list[device_id], 3943 drop, 3944 msdu_cookies[i])) { 3945 num_buffs_reaped[device_id]++; 3946 tot_n_bufs_reaped++; 3947 } 3948 } 3949 3950 next_desc: 3951 if (tot_n_bufs_reaped >= quota) { 3952 tot_n_bufs_reaped = quota; 3953 goto exit; 3954 } 3955 3956 budget = quota - tot_n_bufs_reaped; 3957 } 3958 3959 exit: 3960 ath12k_hal_srng_access_end(ab, srng); 3961 3962 spin_unlock_bh(&srng->lock); 3963 3964 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) { 3965 if (!num_buffs_reaped[device_id]) 3966 continue; 3967 3968 partner_ab = ath12k_ag_to_ab(ag, device_id); 3969 rx_ring = &partner_ab->dp.rx_refill_buf_ring; 3970 3971 ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring, 3972 &rx_desc_used_list[device_id], 3973 num_buffs_reaped[device_id]); 3974 } 3975 3976 return tot_n_bufs_reaped; 3977 } 3978 3979 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3980 int msdu_len, 3981 struct sk_buff_head *msdu_list) 3982 { 3983 struct sk_buff *skb, *tmp; 3984 struct ath12k_skb_rxcb *rxcb; 3985 int n_buffs; 3986 3987 n_buffs = DIV_ROUND_UP(msdu_len, 3988 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz)); 3989 3990 skb_queue_walk_safe(msdu_list, skb, tmp) { 3991 rxcb = ATH12K_SKB_RXCB(skb); 3992 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3993 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3994 if (!n_buffs) 3995 break; 3996 __skb_unlink(skb, msdu_list); 3997 dev_kfree_skb_any(skb); 3998 n_buffs--; 3999 } 4000 } 4001 } 4002 4003 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 4004 struct ath12k_dp_rx_info *rx_info, 4005 struct sk_buff_head *msdu_list) 4006 { 4007 struct ath12k_base *ab = ar->ab; 4008 u16 msdu_len; 4009 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 4010 u8 l3pad_bytes; 4011 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 4012 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 4013 4014 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 4015 4016 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 4017 /* First buffer will be freed by the caller, so deduct it's length */ 4018 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 4019 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 4020 return -EINVAL; 4021 } 4022 4023 /* Even after cleaning up the sg buffers in the msdu list with above check 4024 * any msdu received with continuation flag needs to be dropped as invalid. 4025 * This protects against some random err frame with continuation flag. 4026 */ 4027 if (rxcb->is_continuation) 4028 return -EINVAL; 4029 4030 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 4031 ath12k_warn(ar->ab, 4032 "msdu_done bit not set in null_q_des processing\n"); 4033 __skb_queue_purge(msdu_list); 4034 return -EIO; 4035 } 4036 4037 /* Handle NULL queue descriptor violations arising out a missing 4038 * REO queue for a given peer or a given TID. This typically 4039 * may happen if a packet is received on a QOS enabled TID before the 4040 * ADDBA negotiation for that TID, when the TID queue is setup. Or 4041 * it may also happen for MC/BC frames if they are not routed to the 4042 * non-QOS TID queue, in the absence of any other default TID queue. 4043 * This error can show up both in a REO destination or WBM release ring. 4044 */ 4045 4046 if (rxcb->is_frag) { 4047 skb_pull(msdu, hal_rx_desc_sz); 4048 } else { 4049 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 4050 4051 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 4052 return -EINVAL; 4053 4054 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 4055 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 4056 } 4057 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu))) 4058 return -EINVAL; 4059 4060 ath12k_dp_rx_h_fetch_info(ab, desc, rx_info); 4061 ath12k_dp_rx_h_ppdu(ar, rx_info); 4062 ath12k_dp_rx_h_mpdu(ar, msdu, desc, rx_info); 4063 4064 rxcb->tid = rx_info->tid; 4065 4066 /* Please note that caller will having the access to msdu and completing 4067 * rx with mac80211. Need not worry about cleaning up amsdu_list. 4068 */ 4069 4070 return 0; 4071 } 4072 4073 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 4074 struct ath12k_dp_rx_info *rx_info, 4075 struct sk_buff_head *msdu_list) 4076 { 4077 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 4078 bool drop = false; 4079 4080 ar->ab->device_stats.reo_error[rxcb->err_code]++; 4081 4082 switch (rxcb->err_code) { 4083 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 4084 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, rx_info, msdu_list)) 4085 drop = true; 4086 break; 4087 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 4088 /* TODO: Do not drop PN failed packets in the driver; 4089 * instead, it is good to drop such packets in mac80211 4090 * after incrementing the replay counters. 4091 */ 4092 fallthrough; 4093 default: 4094 /* TODO: Review other errors and process them to mac80211 4095 * as appropriate. 4096 */ 4097 drop = true; 4098 break; 4099 } 4100 4101 return drop; 4102 } 4103 4104 static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 4105 struct ath12k_dp_rx_info *rx_info) 4106 { 4107 struct ath12k_base *ab = ar->ab; 4108 u16 msdu_len; 4109 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 4110 u8 l3pad_bytes; 4111 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 4112 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 4113 4114 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 4115 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 4116 4117 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 4118 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 4119 4120 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) { 4121 ath12k_dbg(ab, ATH12K_DBG_DATA, 4122 "invalid msdu len in tkip mic err %u\n", msdu_len); 4123 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", desc, 4124 sizeof(*desc)); 4125 return true; 4126 } 4127 4128 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 4129 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 4130 4131 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu))) 4132 return true; 4133 4134 ath12k_dp_rx_h_ppdu(ar, rx_info); 4135 4136 rx_info->rx_status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 4137 RX_FLAG_DECRYPTED); 4138 4139 ath12k_dp_rx_h_undecap(ar, msdu, desc, 4140 HAL_ENCRYPT_TYPE_TKIP_MIC, rx_info->rx_status, false); 4141 return false; 4142 } 4143 4144 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 4145 struct ath12k_dp_rx_info *rx_info) 4146 { 4147 struct ath12k_base *ab = ar->ab; 4148 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 4149 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 4150 bool drop = false; 4151 u32 err_bitmap; 4152 4153 ar->ab->device_stats.rxdma_error[rxcb->err_code]++; 4154 4155 switch (rxcb->err_code) { 4156 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 4157 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 4158 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 4159 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 4160 ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); 4161 drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, rx_info); 4162 break; 4163 } 4164 fallthrough; 4165 default: 4166 /* TODO: Review other rxdma error code to check if anything is 4167 * worth reporting to mac80211 4168 */ 4169 drop = true; 4170 break; 4171 } 4172 4173 return drop; 4174 } 4175 4176 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 4177 struct napi_struct *napi, 4178 struct sk_buff *msdu, 4179 struct sk_buff_head *msdu_list) 4180 { 4181 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 4182 struct ieee80211_rx_status rxs = {}; 4183 struct ath12k_dp_rx_info rx_info; 4184 bool drop = true; 4185 4186 rx_info.addr2_present = false; 4187 rx_info.rx_status = &rxs; 4188 4189 switch (rxcb->err_rel_src) { 4190 case HAL_WBM_REL_SRC_MODULE_REO: 4191 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rx_info, msdu_list); 4192 break; 4193 case HAL_WBM_REL_SRC_MODULE_RXDMA: 4194 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rx_info); 4195 break; 4196 default: 4197 /* msdu will get freed */ 4198 break; 4199 } 4200 4201 if (drop) { 4202 dev_kfree_skb_any(msdu); 4203 return; 4204 } 4205 4206 rx_info.rx_status->flag |= RX_FLAG_SKIP_MONITOR; 4207 4208 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_info); 4209 } 4210 4211 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 4212 struct napi_struct *napi, int budget) 4213 { 4214 struct list_head rx_desc_used_list[ATH12K_MAX_DEVICES]; 4215 struct ath12k_hw_group *ag = ab->ag; 4216 struct ath12k *ar; 4217 struct ath12k_dp *dp = &ab->dp; 4218 struct dp_rxdma_ring *rx_ring; 4219 struct hal_rx_wbm_rel_info err_info; 4220 struct hal_srng *srng; 4221 struct sk_buff *msdu; 4222 struct sk_buff_head msdu_list, scatter_msdu_list; 4223 struct ath12k_skb_rxcb *rxcb; 4224 void *rx_desc; 4225 int num_buffs_reaped[ATH12K_MAX_DEVICES] = {}; 4226 int total_num_buffs_reaped = 0; 4227 struct ath12k_rx_desc_info *desc_info; 4228 struct ath12k_device_dp_stats *device_stats = &ab->device_stats; 4229 struct ath12k_hw_link *hw_links = ag->hw_links; 4230 struct ath12k_base *partner_ab; 4231 u8 hw_link_id, device_id; 4232 int ret, pdev_id; 4233 struct hal_rx_desc *msdu_data; 4234 4235 __skb_queue_head_init(&msdu_list); 4236 __skb_queue_head_init(&scatter_msdu_list); 4237 4238 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) 4239 INIT_LIST_HEAD(&rx_desc_used_list[device_id]); 4240 4241 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 4242 spin_lock_bh(&srng->lock); 4243 4244 ath12k_hal_srng_access_begin(ab, srng); 4245 4246 while (budget) { 4247 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 4248 if (!rx_desc) 4249 break; 4250 4251 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 4252 if (ret) { 4253 ath12k_warn(ab, 4254 "failed to parse rx error in wbm_rel ring desc %d\n", 4255 ret); 4256 continue; 4257 } 4258 4259 desc_info = err_info.rx_desc; 4260 4261 /* retry manual desc retrieval if hw cc is not done */ 4262 if (!desc_info) { 4263 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 4264 if (!desc_info) { 4265 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n", 4266 err_info.cookie); 4267 continue; 4268 } 4269 } 4270 4271 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 4272 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 4273 4274 msdu = desc_info->skb; 4275 desc_info->skb = NULL; 4276 4277 device_id = desc_info->device_id; 4278 partner_ab = ath12k_ag_to_ab(ag, device_id); 4279 if (unlikely(!partner_ab)) { 4280 dev_kfree_skb_any(msdu); 4281 4282 /* In any case continuation bit is set 4283 * in the previous record, cleanup scatter_msdu_list 4284 */ 4285 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 4286 continue; 4287 } 4288 4289 list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]); 4290 4291 rxcb = ATH12K_SKB_RXCB(msdu); 4292 dma_unmap_single(partner_ab->dev, rxcb->paddr, 4293 msdu->len + skb_tailroom(msdu), 4294 DMA_FROM_DEVICE); 4295 4296 num_buffs_reaped[device_id]++; 4297 total_num_buffs_reaped++; 4298 4299 if (!err_info.continuation) 4300 budget--; 4301 4302 if (err_info.push_reason != 4303 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4304 dev_kfree_skb_any(msdu); 4305 continue; 4306 } 4307 4308 msdu_data = (struct hal_rx_desc *)msdu->data; 4309 rxcb->err_rel_src = err_info.err_rel_src; 4310 rxcb->err_code = err_info.err_code; 4311 rxcb->is_first_msdu = err_info.first_msdu; 4312 rxcb->is_last_msdu = err_info.last_msdu; 4313 rxcb->is_continuation = err_info.continuation; 4314 rxcb->rx_desc = msdu_data; 4315 4316 if (err_info.continuation) { 4317 __skb_queue_tail(&scatter_msdu_list, msdu); 4318 continue; 4319 } 4320 4321 hw_link_id = ath12k_dp_rx_get_msdu_src_link(partner_ab, 4322 msdu_data); 4323 if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) { 4324 dev_kfree_skb_any(msdu); 4325 4326 /* In any case continuation bit is set 4327 * in the previous record, cleanup scatter_msdu_list 4328 */ 4329 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 4330 continue; 4331 } 4332 4333 if (!skb_queue_empty(&scatter_msdu_list)) { 4334 struct sk_buff *msdu; 4335 4336 skb_queue_walk(&scatter_msdu_list, msdu) { 4337 rxcb = ATH12K_SKB_RXCB(msdu); 4338 rxcb->hw_link_id = hw_link_id; 4339 } 4340 4341 skb_queue_splice_tail_init(&scatter_msdu_list, 4342 &msdu_list); 4343 } 4344 4345 rxcb = ATH12K_SKB_RXCB(msdu); 4346 rxcb->hw_link_id = hw_link_id; 4347 __skb_queue_tail(&msdu_list, msdu); 4348 } 4349 4350 /* In any case continuation bit is set in the 4351 * last record, cleanup scatter_msdu_list 4352 */ 4353 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 4354 4355 ath12k_hal_srng_access_end(ab, srng); 4356 4357 spin_unlock_bh(&srng->lock); 4358 4359 if (!total_num_buffs_reaped) 4360 goto done; 4361 4362 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) { 4363 if (!num_buffs_reaped[device_id]) 4364 continue; 4365 4366 partner_ab = ath12k_ag_to_ab(ag, device_id); 4367 rx_ring = &partner_ab->dp.rx_refill_buf_ring; 4368 4369 ath12k_dp_rx_bufs_replenish(ab, rx_ring, 4370 &rx_desc_used_list[device_id], 4371 num_buffs_reaped[device_id]); 4372 } 4373 4374 rcu_read_lock(); 4375 while ((msdu = __skb_dequeue(&msdu_list))) { 4376 rxcb = ATH12K_SKB_RXCB(msdu); 4377 hw_link_id = rxcb->hw_link_id; 4378 4379 device_id = hw_links[hw_link_id].device_id; 4380 partner_ab = ath12k_ag_to_ab(ag, device_id); 4381 if (unlikely(!partner_ab)) { 4382 ath12k_dbg(ab, ATH12K_DBG_DATA, 4383 "Unable to process WBM error msdu due to invalid hw link id %d device id %d\n", 4384 hw_link_id, device_id); 4385 dev_kfree_skb_any(msdu); 4386 continue; 4387 } 4388 4389 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params, 4390 hw_links[hw_link_id].pdev_idx); 4391 ar = partner_ab->pdevs[pdev_id].ar; 4392 4393 if (!ar || !rcu_dereference(ar->ab->pdevs_active[pdev_id])) { 4394 dev_kfree_skb_any(msdu); 4395 continue; 4396 } 4397 4398 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) { 4399 dev_kfree_skb_any(msdu); 4400 continue; 4401 } 4402 4403 if (rxcb->err_rel_src < HAL_WBM_REL_SRC_MODULE_MAX) { 4404 device_id = ar->ab->device_id; 4405 device_stats->rx_wbm_rel_source[rxcb->err_rel_src][device_id]++; 4406 } 4407 4408 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); 4409 } 4410 rcu_read_unlock(); 4411 done: 4412 return total_num_buffs_reaped; 4413 } 4414 4415 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 4416 { 4417 struct ath12k_dp *dp = &ab->dp; 4418 struct hal_tlv_64_hdr *hdr; 4419 struct hal_srng *srng; 4420 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 4421 bool found = false; 4422 u16 tag; 4423 struct hal_reo_status reo_status; 4424 4425 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4426 4427 memset(&reo_status, 0, sizeof(reo_status)); 4428 4429 spin_lock_bh(&srng->lock); 4430 4431 ath12k_hal_srng_access_begin(ab, srng); 4432 4433 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 4434 tag = le64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 4435 4436 switch (tag) { 4437 case HAL_REO_GET_QUEUE_STATS_STATUS: 4438 ath12k_hal_reo_status_queue_stats(ab, hdr, 4439 &reo_status); 4440 break; 4441 case HAL_REO_FLUSH_QUEUE_STATUS: 4442 ath12k_hal_reo_flush_queue_status(ab, hdr, 4443 &reo_status); 4444 break; 4445 case HAL_REO_FLUSH_CACHE_STATUS: 4446 ath12k_hal_reo_flush_cache_status(ab, hdr, 4447 &reo_status); 4448 break; 4449 case HAL_REO_UNBLOCK_CACHE_STATUS: 4450 ath12k_hal_reo_unblk_cache_status(ab, hdr, 4451 &reo_status); 4452 break; 4453 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4454 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 4455 &reo_status); 4456 break; 4457 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4458 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 4459 &reo_status); 4460 break; 4461 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4462 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 4463 &reo_status); 4464 break; 4465 default: 4466 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 4467 continue; 4468 } 4469 4470 spin_lock_bh(&dp->reo_cmd_lock); 4471 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4472 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4473 found = true; 4474 list_del(&cmd->list); 4475 break; 4476 } 4477 } 4478 spin_unlock_bh(&dp->reo_cmd_lock); 4479 4480 if (found) { 4481 cmd->handler(dp, (void *)&cmd->data, 4482 reo_status.uniform_hdr.cmd_status); 4483 kfree(cmd); 4484 } 4485 4486 found = false; 4487 } 4488 4489 ath12k_hal_srng_access_end(ab, srng); 4490 4491 spin_unlock_bh(&srng->lock); 4492 } 4493 4494 void ath12k_dp_rx_free(struct ath12k_base *ab) 4495 { 4496 struct ath12k_dp *dp = &ab->dp; 4497 struct dp_srng *srng; 4498 int i; 4499 4500 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 4501 4502 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4503 if (ab->hw_params->rx_mac_buf_ring) 4504 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 4505 if (!ab->hw_params->rxdma1_enable) { 4506 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 4507 ath12k_dp_srng_cleanup(ab, srng); 4508 } 4509 } 4510 4511 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 4512 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 4513 4514 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 4515 4516 ath12k_dp_rxdma_buf_free(ab); 4517 } 4518 4519 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 4520 { 4521 struct ath12k *ar = ab->pdevs[mac_id].ar; 4522 4523 ath12k_dp_rx_pdev_srng_free(ar); 4524 } 4525 4526 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 4527 { 4528 struct ath12k_dp *dp = &ab->dp; 4529 struct htt_rx_ring_tlv_filter tlv_filter = {}; 4530 u32 ring_id; 4531 int ret; 4532 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4533 4534 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4535 4536 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4537 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4538 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4539 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4540 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4541 tlv_filter.offset_valid = true; 4542 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4543 4544 tlv_filter.rx_mpdu_start_offset = 4545 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4546 tlv_filter.rx_msdu_end_offset = 4547 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4548 4549 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 4550 tlv_filter.rx_mpdu_start_wmask = 4551 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); 4552 tlv_filter.rx_msdu_end_wmask = 4553 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); 4554 ath12k_dbg(ab, ATH12K_DBG_DATA, 4555 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", 4556 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); 4557 } 4558 4559 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 4560 HAL_RXDMA_BUF, 4561 DP_RXDMA_REFILL_RING_SIZE, 4562 &tlv_filter); 4563 4564 return ret; 4565 } 4566 4567 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 4568 { 4569 struct ath12k_dp *dp = &ab->dp; 4570 struct htt_rx_ring_tlv_filter tlv_filter = {}; 4571 u32 ring_id; 4572 int ret = 0; 4573 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4574 int i; 4575 4576 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4577 4578 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4579 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4580 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4581 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4582 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4583 tlv_filter.offset_valid = true; 4584 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4585 4586 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4587 4588 tlv_filter.rx_mpdu_start_offset = 4589 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4590 tlv_filter.rx_msdu_end_offset = 4591 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4592 4593 /* TODO: Selectively subscribe to required qwords within msdu_end 4594 * and mpdu_start and setup the mask in below msg 4595 * and modify the rx_desc struct 4596 */ 4597 4598 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4599 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4600 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4601 HAL_RXDMA_BUF, 4602 DP_RXDMA_REFILL_RING_SIZE, 4603 &tlv_filter); 4604 } 4605 4606 return ret; 4607 } 4608 4609 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4610 { 4611 struct ath12k_dp *dp = &ab->dp; 4612 u32 ring_id; 4613 int i, ret; 4614 4615 /* TODO: Need to verify the HTT setup for QCN9224 */ 4616 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4617 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4618 if (ret) { 4619 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4620 ret); 4621 return ret; 4622 } 4623 4624 if (ab->hw_params->rx_mac_buf_ring) { 4625 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4626 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4627 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4628 i, HAL_RXDMA_BUF); 4629 if (ret) { 4630 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4631 i, ret); 4632 return ret; 4633 } 4634 } 4635 } 4636 4637 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4638 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4639 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4640 i, HAL_RXDMA_DST); 4641 if (ret) { 4642 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4643 i, ret); 4644 return ret; 4645 } 4646 } 4647 4648 if (ab->hw_params->rxdma1_enable) { 4649 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4650 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4651 0, HAL_RXDMA_MONITOR_BUF); 4652 if (ret) { 4653 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4654 ret); 4655 return ret; 4656 } 4657 } else { 4658 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4659 ring_id = 4660 dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 4661 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, i, 4662 HAL_RXDMA_MONITOR_STATUS); 4663 if (ret) { 4664 ath12k_warn(ab, 4665 "failed to configure mon_status_refill_ring%d %d\n", 4666 i, ret); 4667 return ret; 4668 } 4669 } 4670 } 4671 4672 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4673 if (ret) { 4674 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4675 return ret; 4676 } 4677 4678 return 0; 4679 } 4680 4681 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4682 { 4683 struct ath12k_dp *dp = &ab->dp; 4684 struct dp_srng *srng; 4685 int i, ret; 4686 4687 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4688 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4689 4690 ret = ath12k_dp_srng_setup(ab, 4691 &dp->rx_refill_buf_ring.refill_buf_ring, 4692 HAL_RXDMA_BUF, 0, 0, 4693 DP_RXDMA_BUF_RING_SIZE); 4694 if (ret) { 4695 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4696 return ret; 4697 } 4698 4699 if (ab->hw_params->rx_mac_buf_ring) { 4700 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4701 ret = ath12k_dp_srng_setup(ab, 4702 &dp->rx_mac_buf_ring[i], 4703 HAL_RXDMA_BUF, 1, 4704 i, DP_RX_MAC_BUF_RING_SIZE); 4705 if (ret) { 4706 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4707 i); 4708 return ret; 4709 } 4710 } 4711 } 4712 4713 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4714 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4715 HAL_RXDMA_DST, 0, i, 4716 DP_RXDMA_ERR_DST_RING_SIZE); 4717 if (ret) { 4718 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4719 return ret; 4720 } 4721 } 4722 4723 if (ab->hw_params->rxdma1_enable) { 4724 ret = ath12k_dp_srng_setup(ab, 4725 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4726 HAL_RXDMA_MONITOR_BUF, 0, 0, 4727 DP_RXDMA_MONITOR_BUF_RING_SIZE(ab)); 4728 if (ret) { 4729 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4730 return ret; 4731 } 4732 } else { 4733 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4734 idr_init(&dp->rx_mon_status_refill_ring[i].bufs_idr); 4735 spin_lock_init(&dp->rx_mon_status_refill_ring[i].idr_lock); 4736 } 4737 4738 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4739 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 4740 ret = ath12k_dp_srng_setup(ab, srng, 4741 HAL_RXDMA_MONITOR_STATUS, 0, i, 4742 DP_RXDMA_MON_STATUS_RING_SIZE); 4743 if (ret) { 4744 ath12k_warn(ab, "failed to setup mon status ring %d\n", 4745 i); 4746 return ret; 4747 } 4748 } 4749 } 4750 4751 ret = ath12k_dp_rxdma_buf_setup(ab); 4752 if (ret) { 4753 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4754 return ret; 4755 } 4756 4757 return 0; 4758 } 4759 4760 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4761 { 4762 struct ath12k *ar = ab->pdevs[mac_id].ar; 4763 struct ath12k_pdev_dp *dp = &ar->dp; 4764 u32 ring_id; 4765 int i; 4766 int ret; 4767 4768 if (!ab->hw_params->rxdma1_enable) 4769 goto out; 4770 4771 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4772 if (ret) { 4773 ath12k_warn(ab, "failed to setup rx srngs\n"); 4774 return ret; 4775 } 4776 4777 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4778 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4779 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4780 mac_id + i, 4781 HAL_RXDMA_MONITOR_DST); 4782 if (ret) { 4783 ath12k_warn(ab, 4784 "failed to configure rxdma_mon_dst_ring %d %d\n", 4785 i, ret); 4786 return ret; 4787 } 4788 } 4789 out: 4790 return 0; 4791 } 4792 4793 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4794 { 4795 struct ath12k_pdev_dp *dp = &ar->dp; 4796 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4797 4798 skb_queue_head_init(&pmon->rx_status_q); 4799 4800 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4801 4802 memset(&pmon->rx_mon_stats, 0, 4803 sizeof(pmon->rx_mon_stats)); 4804 return 0; 4805 } 4806 4807 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4808 { 4809 struct ath12k_pdev_dp *dp = &ar->dp; 4810 struct ath12k_mon_data *pmon = &dp->mon_data; 4811 int ret = 0; 4812 4813 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4814 if (ret) { 4815 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4816 return ret; 4817 } 4818 4819 pmon->mon_last_linkdesc_paddr = 0; 4820 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4821 spin_lock_init(&pmon->mon_lock); 4822 4823 if (!ar->ab->hw_params->rxdma1_enable) 4824 return 0; 4825 4826 INIT_LIST_HEAD(&pmon->dp_rx_mon_mpdu_list); 4827 pmon->mon_mpdu = NULL; 4828 4829 return 0; 4830 } 4831