1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 21 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22 23 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 24 struct hal_rx_desc *desc) 25 { 26 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) 27 return HAL_ENCRYPT_TYPE_OPEN; 28 29 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); 30 } 31 32 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 33 struct hal_rx_desc *desc) 34 { 35 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); 36 } 37 38 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 39 struct hal_rx_desc *desc) 40 { 41 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); 42 } 43 44 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 45 struct hal_rx_desc *desc) 46 { 47 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 48 } 49 50 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 51 struct hal_rx_desc *desc) 52 { 53 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); 54 } 55 56 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 57 struct sk_buff *skb) 58 { 59 struct ieee80211_hdr *hdr; 60 61 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 62 return ieee80211_has_morefrags(hdr->frame_control); 63 } 64 65 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 66 struct sk_buff *skb) 67 { 68 struct ieee80211_hdr *hdr; 69 70 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 71 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 72 } 73 74 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 75 struct hal_rx_desc *desc) 76 { 77 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc); 78 } 79 80 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 81 struct hal_rx_desc *desc) 82 { 83 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc); 84 } 85 86 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 87 struct hal_rx_desc *desc) 88 { 89 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc); 90 } 91 92 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 93 struct hal_rx_desc *desc) 94 { 95 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc); 96 } 97 98 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 99 struct hal_rx_desc *desc) 100 { 101 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc); 102 } 103 104 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 105 struct hal_rx_desc *desc) 106 { 107 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc); 108 } 109 110 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 111 struct hal_rx_desc *desc) 112 { 113 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc); 114 } 115 116 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 117 struct hal_rx_desc *desc) 118 { 119 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc); 120 } 121 122 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 123 struct hal_rx_desc *desc) 124 { 125 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc); 126 } 127 128 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 129 struct hal_rx_desc *desc) 130 { 131 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc); 132 } 133 134 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 135 struct hal_rx_desc *desc) 136 { 137 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc); 138 } 139 140 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 141 struct hal_rx_desc *desc) 142 { 143 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc); 144 } 145 146 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 147 struct hal_rx_desc *desc) 148 { 149 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc)); 150 } 151 152 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 153 struct hal_rx_desc *desc) 154 { 155 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc); 156 } 157 158 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 159 struct hal_rx_desc *desc) 160 { 161 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc); 162 } 163 164 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 165 struct hal_rx_desc *desc) 166 { 167 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc); 168 } 169 170 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 171 struct hal_rx_desc *desc) 172 { 173 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc); 174 } 175 176 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 177 struct hal_rx_desc *desc) 178 { 179 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc); 180 } 181 182 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 183 struct hal_rx_desc *fdesc, 184 struct hal_rx_desc *ldesc) 185 { 186 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 187 } 188 189 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 190 struct hal_rx_desc *desc, 191 u16 len) 192 { 193 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len); 194 } 195 196 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 197 struct hal_rx_desc *desc) 198 { 199 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 200 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc)); 201 } 202 203 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 204 struct hal_rx_desc *desc) 205 { 206 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc); 207 } 208 209 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 210 struct hal_rx_desc *desc) 211 { 212 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc); 213 } 214 215 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 216 struct hal_rx_desc *desc, 217 struct ieee80211_hdr *hdr) 218 { 219 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr); 220 } 221 222 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 223 struct hal_rx_desc *desc, 224 u8 *crypto_hdr, 225 enum hal_encrypt_type enctype) 226 { 227 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 228 } 229 230 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab, 231 struct hal_rx_desc *desc) 232 { 233 return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc); 234 } 235 236 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, 237 struct hal_rx_desc *desc) 238 { 239 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc); 240 } 241 242 static int ath12k_dp_purge_mon_ring(struct ath12k_base *ab) 243 { 244 int i, reaped = 0; 245 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS); 246 247 do { 248 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) 249 reaped += ath12k_dp_mon_process_ring(ab, i, NULL, 250 DP_MON_SERVICE_BUDGET, 251 ATH12K_DP_RX_MONITOR_MODE); 252 253 /* nothing more to reap */ 254 if (reaped < DP_MON_SERVICE_BUDGET) 255 return 0; 256 257 } while (time_before(jiffies, timeout)); 258 259 ath12k_warn(ab, "dp mon ring purge timeout"); 260 261 return -ETIMEDOUT; 262 } 263 264 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 265 struct list_head *head, 266 size_t count) 267 { 268 struct list_head *cur; 269 struct ath12k_rx_desc_info *rx_desc; 270 size_t nodes = 0; 271 272 if (!count) { 273 INIT_LIST_HEAD(list); 274 goto out; 275 } 276 277 list_for_each(cur, head) { 278 if (!count) 279 break; 280 281 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 282 rx_desc->in_use = true; 283 284 count--; 285 nodes++; 286 } 287 288 list_cut_before(list, head, cur); 289 out: 290 return nodes; 291 } 292 293 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 294 struct list_head *used_list) 295 { 296 struct ath12k_rx_desc_info *rx_desc, *safe; 297 298 /* Reset the use flag */ 299 list_for_each_entry_safe(rx_desc, safe, used_list, list) 300 rx_desc->in_use = false; 301 302 spin_lock_bh(&dp->rx_desc_lock); 303 list_splice_tail(used_list, &dp->rx_desc_free_list); 304 spin_unlock_bh(&dp->rx_desc_lock); 305 } 306 307 /* Returns number of Rx buffers replenished */ 308 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, 309 struct dp_rxdma_ring *rx_ring, 310 struct list_head *used_list, 311 int req_entries) 312 { 313 struct ath12k_buffer_addr *desc; 314 struct hal_srng *srng; 315 struct sk_buff *skb; 316 int num_free; 317 int num_remain; 318 u32 cookie; 319 dma_addr_t paddr; 320 struct ath12k_dp *dp = &ab->dp; 321 struct ath12k_rx_desc_info *rx_desc; 322 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; 323 324 req_entries = min(req_entries, rx_ring->bufs_max); 325 326 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 327 328 spin_lock_bh(&srng->lock); 329 330 ath12k_hal_srng_access_begin(ab, srng); 331 332 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 333 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 334 req_entries = num_free; 335 336 req_entries = min(num_free, req_entries); 337 num_remain = req_entries; 338 339 if (!num_remain) 340 goto out; 341 342 /* Get the descriptor from free list */ 343 if (list_empty(used_list)) { 344 spin_lock_bh(&dp->rx_desc_lock); 345 req_entries = ath12k_dp_list_cut_nodes(used_list, 346 &dp->rx_desc_free_list, 347 num_remain); 348 spin_unlock_bh(&dp->rx_desc_lock); 349 num_remain = req_entries; 350 } 351 352 while (num_remain > 0) { 353 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 354 DP_RX_BUFFER_ALIGN_SIZE); 355 if (!skb) 356 break; 357 358 if (!IS_ALIGNED((unsigned long)skb->data, 359 DP_RX_BUFFER_ALIGN_SIZE)) { 360 skb_pull(skb, 361 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 362 skb->data); 363 } 364 365 paddr = dma_map_single(ab->dev, skb->data, 366 skb->len + skb_tailroom(skb), 367 DMA_FROM_DEVICE); 368 if (dma_mapping_error(ab->dev, paddr)) 369 goto fail_free_skb; 370 371 rx_desc = list_first_entry_or_null(used_list, 372 struct ath12k_rx_desc_info, 373 list); 374 if (!rx_desc) 375 goto fail_dma_unmap; 376 377 rx_desc->skb = skb; 378 cookie = rx_desc->cookie; 379 380 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 381 if (!desc) 382 goto fail_dma_unmap; 383 384 list_del(&rx_desc->list); 385 ATH12K_SKB_RXCB(skb)->paddr = paddr; 386 387 num_remain--; 388 389 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 390 } 391 392 goto out; 393 394 fail_dma_unmap: 395 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 396 DMA_FROM_DEVICE); 397 fail_free_skb: 398 dev_kfree_skb_any(skb); 399 out: 400 ath12k_hal_srng_access_end(ab, srng); 401 402 if (!list_empty(used_list)) 403 ath12k_dp_rx_enqueue_free(dp, used_list); 404 405 spin_unlock_bh(&srng->lock); 406 407 return req_entries - num_remain; 408 } 409 410 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 411 struct dp_rxdma_mon_ring *rx_ring) 412 { 413 struct sk_buff *skb; 414 int buf_id; 415 416 spin_lock_bh(&rx_ring->idr_lock); 417 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 418 idr_remove(&rx_ring->bufs_idr, buf_id); 419 /* TODO: Understand where internal driver does this dma_unmap 420 * of rxdma_buffer. 421 */ 422 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 423 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 424 dev_kfree_skb_any(skb); 425 } 426 427 idr_destroy(&rx_ring->bufs_idr); 428 spin_unlock_bh(&rx_ring->idr_lock); 429 430 return 0; 431 } 432 433 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 434 { 435 struct ath12k_dp *dp = &ab->dp; 436 437 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 438 439 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->tx_mon_buf_ring); 440 441 return 0; 442 } 443 444 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 445 struct dp_rxdma_mon_ring *rx_ring, 446 u32 ringtype) 447 { 448 int num_entries; 449 450 num_entries = rx_ring->refill_buf_ring.size / 451 ath12k_hal_srng_get_entrysize(ab, ringtype); 452 453 rx_ring->bufs_max = num_entries; 454 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 455 456 return 0; 457 } 458 459 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 460 struct dp_rxdma_ring *rx_ring) 461 { 462 LIST_HEAD(list); 463 464 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 465 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 466 467 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 468 469 return 0; 470 } 471 472 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 473 { 474 struct ath12k_dp *dp = &ab->dp; 475 int ret; 476 477 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 478 if (ret) { 479 ath12k_warn(ab, 480 "failed to setup HAL_RXDMA_BUF\n"); 481 return ret; 482 } 483 484 if (ab->hw_params->rxdma1_enable) { 485 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 486 &dp->rxdma_mon_buf_ring, 487 HAL_RXDMA_MONITOR_BUF); 488 if (ret) { 489 ath12k_warn(ab, 490 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 491 return ret; 492 } 493 494 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 495 &dp->tx_mon_buf_ring, 496 HAL_TX_MONITOR_BUF); 497 if (ret) { 498 ath12k_warn(ab, 499 "failed to setup HAL_TX_MONITOR_BUF\n"); 500 return ret; 501 } 502 } 503 504 return 0; 505 } 506 507 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 508 { 509 struct ath12k_pdev_dp *dp = &ar->dp; 510 struct ath12k_base *ab = ar->ab; 511 int i; 512 513 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 514 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 515 ath12k_dp_srng_cleanup(ab, &dp->tx_mon_dst_ring[i]); 516 } 517 } 518 519 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 520 { 521 struct ath12k_dp *dp = &ab->dp; 522 int i; 523 524 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 525 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 526 } 527 528 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 529 { 530 struct ath12k_dp *dp = &ab->dp; 531 int ret; 532 int i; 533 534 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 535 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 536 HAL_REO_DST, i, 0, 537 DP_REO_DST_RING_SIZE); 538 if (ret) { 539 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 540 goto err_reo_cleanup; 541 } 542 } 543 544 return 0; 545 546 err_reo_cleanup: 547 ath12k_dp_rx_pdev_reo_cleanup(ab); 548 549 return ret; 550 } 551 552 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 553 { 554 struct ath12k_pdev_dp *dp = &ar->dp; 555 struct ath12k_base *ab = ar->ab; 556 int i; 557 int ret; 558 u32 mac_id = dp->mac_id; 559 560 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 561 ret = ath12k_dp_srng_setup(ar->ab, 562 &dp->rxdma_mon_dst_ring[i], 563 HAL_RXDMA_MONITOR_DST, 564 0, mac_id + i, 565 DP_RXDMA_MONITOR_DST_RING_SIZE); 566 if (ret) { 567 ath12k_warn(ar->ab, 568 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 569 return ret; 570 } 571 572 ret = ath12k_dp_srng_setup(ar->ab, 573 &dp->tx_mon_dst_ring[i], 574 HAL_TX_MONITOR_DST, 575 0, mac_id + i, 576 DP_TX_MONITOR_DEST_RING_SIZE); 577 if (ret) { 578 ath12k_warn(ar->ab, 579 "failed to setup HAL_TX_MONITOR_DST\n"); 580 return ret; 581 } 582 } 583 584 return 0; 585 } 586 587 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 588 { 589 struct ath12k_dp *dp = &ab->dp; 590 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 591 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 592 593 spin_lock_bh(&dp->reo_cmd_lock); 594 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 595 list_del(&cmd->list); 596 dma_unmap_single(ab->dev, cmd->data.paddr, 597 cmd->data.size, DMA_BIDIRECTIONAL); 598 kfree(cmd->data.vaddr); 599 kfree(cmd); 600 } 601 602 list_for_each_entry_safe(cmd_cache, tmp_cache, 603 &dp->reo_cmd_cache_flush_list, list) { 604 list_del(&cmd_cache->list); 605 dp->reo_cmd_cache_flush_count--; 606 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 607 cmd_cache->data.size, DMA_BIDIRECTIONAL); 608 kfree(cmd_cache->data.vaddr); 609 kfree(cmd_cache); 610 } 611 spin_unlock_bh(&dp->reo_cmd_lock); 612 } 613 614 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 615 enum hal_reo_cmd_status status) 616 { 617 struct ath12k_dp_rx_tid *rx_tid = ctx; 618 619 if (status != HAL_REO_CMD_SUCCESS) 620 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 621 rx_tid->tid, status); 622 623 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 624 DMA_BIDIRECTIONAL); 625 kfree(rx_tid->vaddr); 626 rx_tid->vaddr = NULL; 627 } 628 629 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 630 enum hal_reo_cmd_type type, 631 struct ath12k_hal_reo_cmd *cmd, 632 void (*cb)(struct ath12k_dp *dp, void *ctx, 633 enum hal_reo_cmd_status status)) 634 { 635 struct ath12k_dp *dp = &ab->dp; 636 struct ath12k_dp_rx_reo_cmd *dp_cmd; 637 struct hal_srng *cmd_ring; 638 int cmd_num; 639 640 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 641 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 642 643 /* cmd_num should start from 1, during failure return the error code */ 644 if (cmd_num < 0) 645 return cmd_num; 646 647 /* reo cmd ring descriptors has cmd_num starting from 1 */ 648 if (cmd_num == 0) 649 return -EINVAL; 650 651 if (!cb) 652 return 0; 653 654 /* Can this be optimized so that we keep the pending command list only 655 * for tid delete command to free up the resource on the command status 656 * indication? 657 */ 658 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 659 660 if (!dp_cmd) 661 return -ENOMEM; 662 663 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 664 dp_cmd->cmd_num = cmd_num; 665 dp_cmd->handler = cb; 666 667 spin_lock_bh(&dp->reo_cmd_lock); 668 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 669 spin_unlock_bh(&dp->reo_cmd_lock); 670 671 return 0; 672 } 673 674 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 675 struct ath12k_dp_rx_tid *rx_tid) 676 { 677 struct ath12k_hal_reo_cmd cmd = {0}; 678 unsigned long tot_desc_sz, desc_sz; 679 int ret; 680 681 tot_desc_sz = rx_tid->size; 682 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 683 684 while (tot_desc_sz > desc_sz) { 685 tot_desc_sz -= desc_sz; 686 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 687 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 688 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 689 HAL_REO_CMD_FLUSH_CACHE, &cmd, 690 NULL); 691 if (ret) 692 ath12k_warn(ab, 693 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 694 rx_tid->tid, ret); 695 } 696 697 memset(&cmd, 0, sizeof(cmd)); 698 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 699 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 700 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 701 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 702 HAL_REO_CMD_FLUSH_CACHE, 703 &cmd, ath12k_dp_reo_cmd_free); 704 if (ret) { 705 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 706 rx_tid->tid, ret); 707 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 708 DMA_BIDIRECTIONAL); 709 kfree(rx_tid->vaddr); 710 rx_tid->vaddr = NULL; 711 } 712 } 713 714 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 715 enum hal_reo_cmd_status status) 716 { 717 struct ath12k_base *ab = dp->ab; 718 struct ath12k_dp_rx_tid *rx_tid = ctx; 719 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 720 721 if (status == HAL_REO_CMD_DRAIN) { 722 goto free_desc; 723 } else if (status != HAL_REO_CMD_SUCCESS) { 724 /* Shouldn't happen! Cleanup in case of other failure? */ 725 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 726 rx_tid->tid, status); 727 return; 728 } 729 730 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 731 if (!elem) 732 goto free_desc; 733 734 elem->ts = jiffies; 735 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 736 737 spin_lock_bh(&dp->reo_cmd_lock); 738 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 739 dp->reo_cmd_cache_flush_count++; 740 741 /* Flush and invalidate aged REO desc from HW cache */ 742 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 743 list) { 744 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 745 time_after(jiffies, elem->ts + 746 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 747 list_del(&elem->list); 748 dp->reo_cmd_cache_flush_count--; 749 750 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 751 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 752 * is used in only two contexts, one is in this function called 753 * from napi and the other in ath12k_dp_free during core destroy. 754 * Before dp_free, the irqs would be disabled and would wait to 755 * synchronize. Hence there wouldn’t be any race against add or 756 * delete to this list. Hence unlock-lock is safe here. 757 */ 758 spin_unlock_bh(&dp->reo_cmd_lock); 759 760 ath12k_dp_reo_cache_flush(ab, &elem->data); 761 kfree(elem); 762 spin_lock_bh(&dp->reo_cmd_lock); 763 } 764 } 765 spin_unlock_bh(&dp->reo_cmd_lock); 766 767 return; 768 free_desc: 769 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 770 DMA_BIDIRECTIONAL); 771 kfree(rx_tid->vaddr); 772 rx_tid->vaddr = NULL; 773 } 774 775 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 776 dma_addr_t paddr) 777 { 778 struct ath12k_reo_queue_ref *qref; 779 struct ath12k_dp *dp = &ab->dp; 780 781 if (!ab->hw_params->reoq_lut_support) 782 return; 783 784 /* TODO: based on ML peer or not, select the LUT. below assumes non 785 * ML peer 786 */ 787 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 788 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 789 790 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 791 BUFFER_ADDR_INFO0_ADDR); 792 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 793 BUFFER_ADDR_INFO1_ADDR) | 794 u32_encode_bits(tid, DP_REO_QREF_NUM); 795 } 796 797 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 798 { 799 struct ath12k_reo_queue_ref *qref; 800 struct ath12k_dp *dp = &ab->dp; 801 802 if (!ab->hw_params->reoq_lut_support) 803 return; 804 805 /* TODO: based on ML peer or not, select the LUT. below assumes non 806 * ML peer 807 */ 808 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 809 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 810 811 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 812 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 813 u32_encode_bits(tid, DP_REO_QREF_NUM); 814 } 815 816 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 817 struct ath12k_peer *peer, u8 tid) 818 { 819 struct ath12k_hal_reo_cmd cmd = {0}; 820 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 821 int ret; 822 823 if (!rx_tid->active) 824 return; 825 826 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 827 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 828 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 829 cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 830 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 831 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 832 ath12k_dp_rx_tid_del_func); 833 if (ret) { 834 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 835 tid, ret); 836 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 837 DMA_BIDIRECTIONAL); 838 kfree(rx_tid->vaddr); 839 rx_tid->vaddr = NULL; 840 } 841 842 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 843 844 rx_tid->active = false; 845 } 846 847 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted 848 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind 849 * that. 850 */ 851 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 852 struct hal_reo_dest_ring *ring, 853 enum hal_wbm_rel_bm_act action) 854 { 855 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring; 856 struct hal_wbm_release_ring *desc; 857 struct ath12k_dp *dp = &ab->dp; 858 struct hal_srng *srng; 859 int ret = 0; 860 861 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 862 863 spin_lock_bh(&srng->lock); 864 865 ath12k_hal_srng_access_begin(ab, srng); 866 867 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 868 if (!desc) { 869 ret = -ENOBUFS; 870 goto exit; 871 } 872 873 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action); 874 875 exit: 876 ath12k_hal_srng_access_end(ab, srng); 877 878 spin_unlock_bh(&srng->lock); 879 880 return ret; 881 } 882 883 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 884 bool rel_link_desc) 885 { 886 struct ath12k_base *ab = rx_tid->ab; 887 888 lockdep_assert_held(&ab->base_lock); 889 890 if (rx_tid->dst_ring_desc) { 891 if (rel_link_desc) 892 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc, 893 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 894 kfree(rx_tid->dst_ring_desc); 895 rx_tid->dst_ring_desc = NULL; 896 } 897 898 rx_tid->cur_sn = 0; 899 rx_tid->last_frag_no = 0; 900 rx_tid->rx_frag_bitmap = 0; 901 __skb_queue_purge(&rx_tid->rx_frags); 902 } 903 904 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 905 { 906 struct ath12k_dp_rx_tid *rx_tid; 907 int i; 908 909 lockdep_assert_held(&ar->ab->base_lock); 910 911 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 912 rx_tid = &peer->rx_tid[i]; 913 914 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 915 ath12k_dp_rx_frags_cleanup(rx_tid, true); 916 917 spin_unlock_bh(&ar->ab->base_lock); 918 del_timer_sync(&rx_tid->frag_timer); 919 spin_lock_bh(&ar->ab->base_lock); 920 } 921 } 922 923 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 924 struct ath12k_peer *peer, 925 struct ath12k_dp_rx_tid *rx_tid, 926 u32 ba_win_sz, u16 ssn, 927 bool update_ssn) 928 { 929 struct ath12k_hal_reo_cmd cmd = {0}; 930 int ret; 931 932 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 933 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 934 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 935 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 936 cmd.ba_window_size = ba_win_sz; 937 938 if (update_ssn) { 939 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 940 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 941 } 942 943 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 944 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 945 NULL); 946 if (ret) { 947 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 948 rx_tid->tid, ret); 949 return ret; 950 } 951 952 rx_tid->ba_win_sz = ba_win_sz; 953 954 return 0; 955 } 956 957 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 958 u8 tid, u32 ba_win_sz, u16 ssn, 959 enum hal_pn_type pn_type) 960 { 961 struct ath12k_base *ab = ar->ab; 962 struct ath12k_dp *dp = &ab->dp; 963 struct hal_rx_reo_queue *addr_aligned; 964 struct ath12k_peer *peer; 965 struct ath12k_dp_rx_tid *rx_tid; 966 u32 hw_desc_sz; 967 void *vaddr; 968 dma_addr_t paddr; 969 int ret; 970 971 spin_lock_bh(&ab->base_lock); 972 973 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 974 if (!peer) { 975 spin_unlock_bh(&ab->base_lock); 976 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 977 return -ENOENT; 978 } 979 980 if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) { 981 spin_unlock_bh(&ab->base_lock); 982 ath12k_warn(ab, "reo qref table is not setup\n"); 983 return -EINVAL; 984 } 985 986 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 987 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 988 peer->peer_id, tid); 989 spin_unlock_bh(&ab->base_lock); 990 return -EINVAL; 991 } 992 993 rx_tid = &peer->rx_tid[tid]; 994 /* Update the tid queue if it is already setup */ 995 if (rx_tid->active) { 996 paddr = rx_tid->paddr; 997 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 998 ba_win_sz, ssn, true); 999 spin_unlock_bh(&ab->base_lock); 1000 if (ret) { 1001 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 1002 return ret; 1003 } 1004 1005 if (!ab->hw_params->reoq_lut_support) { 1006 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1007 peer_mac, 1008 paddr, tid, 1, 1009 ba_win_sz); 1010 if (ret) { 1011 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 1012 tid, ret); 1013 return ret; 1014 } 1015 } 1016 1017 return 0; 1018 } 1019 1020 rx_tid->tid = tid; 1021 1022 rx_tid->ba_win_sz = ba_win_sz; 1023 1024 /* TODO: Optimize the memory allocation for qos tid based on 1025 * the actual BA window size in REO tid update path. 1026 */ 1027 if (tid == HAL_DESC_REO_NON_QOS_TID) 1028 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 1029 else 1030 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1031 1032 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1033 if (!vaddr) { 1034 spin_unlock_bh(&ab->base_lock); 1035 return -ENOMEM; 1036 } 1037 1038 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1039 1040 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1041 ssn, pn_type); 1042 1043 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1044 DMA_BIDIRECTIONAL); 1045 1046 ret = dma_mapping_error(ab->dev, paddr); 1047 if (ret) { 1048 spin_unlock_bh(&ab->base_lock); 1049 goto err_mem_free; 1050 } 1051 1052 rx_tid->vaddr = vaddr; 1053 rx_tid->paddr = paddr; 1054 rx_tid->size = hw_desc_sz; 1055 rx_tid->active = true; 1056 1057 if (ab->hw_params->reoq_lut_support) { 1058 /* Update the REO queue LUT at the corresponding peer id 1059 * and tid with qaddr. 1060 */ 1061 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr); 1062 spin_unlock_bh(&ab->base_lock); 1063 } else { 1064 spin_unlock_bh(&ab->base_lock); 1065 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1066 paddr, tid, 1, ba_win_sz); 1067 } 1068 1069 return ret; 1070 1071 err_mem_free: 1072 kfree(vaddr); 1073 1074 return ret; 1075 } 1076 1077 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1078 struct ieee80211_ampdu_params *params) 1079 { 1080 struct ath12k_base *ab = ar->ab; 1081 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta); 1082 int vdev_id = arsta->arvif->vdev_id; 1083 int ret; 1084 1085 ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id, 1086 params->tid, params->buf_size, 1087 params->ssn, arsta->pn_type); 1088 if (ret) 1089 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1090 1091 return ret; 1092 } 1093 1094 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1095 struct ieee80211_ampdu_params *params) 1096 { 1097 struct ath12k_base *ab = ar->ab; 1098 struct ath12k_peer *peer; 1099 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta); 1100 int vdev_id = arsta->arvif->vdev_id; 1101 bool active; 1102 int ret; 1103 1104 spin_lock_bh(&ab->base_lock); 1105 1106 peer = ath12k_peer_find(ab, vdev_id, params->sta->addr); 1107 if (!peer) { 1108 spin_unlock_bh(&ab->base_lock); 1109 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1110 return -ENOENT; 1111 } 1112 1113 active = peer->rx_tid[params->tid].active; 1114 1115 if (!active) { 1116 spin_unlock_bh(&ab->base_lock); 1117 return 0; 1118 } 1119 1120 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1121 spin_unlock_bh(&ab->base_lock); 1122 if (ret) { 1123 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1124 params->tid, ret); 1125 return ret; 1126 } 1127 1128 return ret; 1129 } 1130 1131 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif, 1132 const u8 *peer_addr, 1133 enum set_key_cmd key_cmd, 1134 struct ieee80211_key_conf *key) 1135 { 1136 struct ath12k *ar = arvif->ar; 1137 struct ath12k_base *ab = ar->ab; 1138 struct ath12k_hal_reo_cmd cmd = {0}; 1139 struct ath12k_peer *peer; 1140 struct ath12k_dp_rx_tid *rx_tid; 1141 u8 tid; 1142 int ret = 0; 1143 1144 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1145 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1146 * for now. 1147 */ 1148 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1149 return 0; 1150 1151 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1152 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1153 HAL_REO_CMD_UPD0_PN_SIZE | 1154 HAL_REO_CMD_UPD0_PN_VALID | 1155 HAL_REO_CMD_UPD0_PN_CHECK | 1156 HAL_REO_CMD_UPD0_SVLD; 1157 1158 switch (key->cipher) { 1159 case WLAN_CIPHER_SUITE_TKIP: 1160 case WLAN_CIPHER_SUITE_CCMP: 1161 case WLAN_CIPHER_SUITE_CCMP_256: 1162 case WLAN_CIPHER_SUITE_GCMP: 1163 case WLAN_CIPHER_SUITE_GCMP_256: 1164 if (key_cmd == SET_KEY) { 1165 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1166 cmd.pn_size = 48; 1167 } 1168 break; 1169 default: 1170 break; 1171 } 1172 1173 spin_lock_bh(&ab->base_lock); 1174 1175 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1176 if (!peer) { 1177 spin_unlock_bh(&ab->base_lock); 1178 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1179 peer_addr); 1180 return -ENOENT; 1181 } 1182 1183 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1184 rx_tid = &peer->rx_tid[tid]; 1185 if (!rx_tid->active) 1186 continue; 1187 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1188 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1189 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1190 HAL_REO_CMD_UPDATE_RX_QUEUE, 1191 &cmd, NULL); 1192 if (ret) { 1193 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1194 tid, peer_addr, ret); 1195 break; 1196 } 1197 } 1198 1199 spin_unlock_bh(&ab->base_lock); 1200 1201 return ret; 1202 } 1203 1204 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1205 u16 peer_id) 1206 { 1207 int i; 1208 1209 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1210 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1211 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1212 return i; 1213 } else { 1214 return i; 1215 } 1216 } 1217 1218 return -EINVAL; 1219 } 1220 1221 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1222 u16 tag, u16 len, const void *ptr, 1223 void *data) 1224 { 1225 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1226 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1227 const struct htt_ppdu_stats_user_rate *user_rate; 1228 struct htt_ppdu_stats_info *ppdu_info; 1229 struct htt_ppdu_user_stats *user_stats; 1230 int cur_user; 1231 u16 peer_id; 1232 1233 ppdu_info = data; 1234 1235 switch (tag) { 1236 case HTT_PPDU_STATS_TAG_COMMON: 1237 if (len < sizeof(struct htt_ppdu_stats_common)) { 1238 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1239 len, tag); 1240 return -EINVAL; 1241 } 1242 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1243 sizeof(struct htt_ppdu_stats_common)); 1244 break; 1245 case HTT_PPDU_STATS_TAG_USR_RATE: 1246 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1247 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1248 len, tag); 1249 return -EINVAL; 1250 } 1251 user_rate = ptr; 1252 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1253 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1254 peer_id); 1255 if (cur_user < 0) 1256 return -EINVAL; 1257 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1258 user_stats->peer_id = peer_id; 1259 user_stats->is_valid_peer_id = true; 1260 memcpy(&user_stats->rate, ptr, 1261 sizeof(struct htt_ppdu_stats_user_rate)); 1262 user_stats->tlv_flags |= BIT(tag); 1263 break; 1264 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1265 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1266 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1267 len, tag); 1268 return -EINVAL; 1269 } 1270 1271 cmplt_cmn = ptr; 1272 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1273 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1274 peer_id); 1275 if (cur_user < 0) 1276 return -EINVAL; 1277 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1278 user_stats->peer_id = peer_id; 1279 user_stats->is_valid_peer_id = true; 1280 memcpy(&user_stats->cmpltn_cmn, ptr, 1281 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1282 user_stats->tlv_flags |= BIT(tag); 1283 break; 1284 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1285 if (len < 1286 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1287 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1288 len, tag); 1289 return -EINVAL; 1290 } 1291 1292 ba_status = ptr; 1293 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1294 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1295 peer_id); 1296 if (cur_user < 0) 1297 return -EINVAL; 1298 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1299 user_stats->peer_id = peer_id; 1300 user_stats->is_valid_peer_id = true; 1301 memcpy(&user_stats->ack_ba, ptr, 1302 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1303 user_stats->tlv_flags |= BIT(tag); 1304 break; 1305 } 1306 return 0; 1307 } 1308 1309 static int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1310 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1311 const void *ptr, void *data), 1312 void *data) 1313 { 1314 const struct htt_tlv *tlv; 1315 const void *begin = ptr; 1316 u16 tlv_tag, tlv_len; 1317 int ret = -EINVAL; 1318 1319 while (len > 0) { 1320 if (len < sizeof(*tlv)) { 1321 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1322 ptr - begin, len, sizeof(*tlv)); 1323 return -EINVAL; 1324 } 1325 tlv = (struct htt_tlv *)ptr; 1326 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1327 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1328 ptr += sizeof(*tlv); 1329 len -= sizeof(*tlv); 1330 1331 if (tlv_len > len) { 1332 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1333 tlv_tag, ptr - begin, len, tlv_len); 1334 return -EINVAL; 1335 } 1336 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1337 if (ret == -ENOMEM) 1338 return ret; 1339 1340 ptr += tlv_len; 1341 len -= tlv_len; 1342 } 1343 return 0; 1344 } 1345 1346 static void 1347 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1348 struct htt_ppdu_stats *ppdu_stats, u8 user) 1349 { 1350 struct ath12k_base *ab = ar->ab; 1351 struct ath12k_peer *peer; 1352 struct ieee80211_sta *sta; 1353 struct ath12k_sta *arsta; 1354 struct htt_ppdu_stats_user_rate *user_rate; 1355 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1356 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1357 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1358 int ret; 1359 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1360 u32 v, succ_bytes = 0; 1361 u16 tones, rate = 0, succ_pkts = 0; 1362 u32 tx_duration = 0; 1363 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1364 bool is_ampdu = false; 1365 1366 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1367 return; 1368 1369 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1370 is_ampdu = 1371 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1372 1373 if (usr_stats->tlv_flags & 1374 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1375 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1376 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1377 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1378 tid = le32_get_bits(usr_stats->ack_ba.info, 1379 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1380 } 1381 1382 if (common->fes_duration_us) 1383 tx_duration = le32_to_cpu(common->fes_duration_us); 1384 1385 user_rate = &usr_stats->rate; 1386 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1387 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1388 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1389 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1390 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1391 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1392 1393 /* Note: If host configured fixed rates and in some other special 1394 * cases, the broadcast/management frames are sent in different rates. 1395 * Firmware rate's control to be skipped for this? 1396 */ 1397 1398 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1399 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1400 return; 1401 } 1402 1403 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1404 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1405 return; 1406 } 1407 1408 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1409 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1410 mcs, nss); 1411 return; 1412 } 1413 1414 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1415 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1416 flags, 1417 &rate_idx, 1418 &rate); 1419 if (ret < 0) 1420 return; 1421 } 1422 1423 rcu_read_lock(); 1424 spin_lock_bh(&ab->base_lock); 1425 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1426 1427 if (!peer || !peer->sta) { 1428 spin_unlock_bh(&ab->base_lock); 1429 rcu_read_unlock(); 1430 return; 1431 } 1432 1433 sta = peer->sta; 1434 arsta = ath12k_sta_to_arsta(sta); 1435 1436 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1437 1438 switch (flags) { 1439 case WMI_RATE_PREAMBLE_OFDM: 1440 arsta->txrate.legacy = rate; 1441 break; 1442 case WMI_RATE_PREAMBLE_CCK: 1443 arsta->txrate.legacy = rate; 1444 break; 1445 case WMI_RATE_PREAMBLE_HT: 1446 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1447 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1448 if (sgi) 1449 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1450 break; 1451 case WMI_RATE_PREAMBLE_VHT: 1452 arsta->txrate.mcs = mcs; 1453 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1454 if (sgi) 1455 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1456 break; 1457 case WMI_RATE_PREAMBLE_HE: 1458 arsta->txrate.mcs = mcs; 1459 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1460 arsta->txrate.he_dcm = dcm; 1461 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1462 tones = le16_to_cpu(user_rate->ru_end) - 1463 le16_to_cpu(user_rate->ru_start) + 1; 1464 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1465 arsta->txrate.he_ru_alloc = v; 1466 break; 1467 } 1468 1469 arsta->txrate.nss = nss; 1470 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1471 arsta->tx_duration += tx_duration; 1472 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1473 1474 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1475 * So skip peer stats update for mgmt packets. 1476 */ 1477 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1478 memset(peer_stats, 0, sizeof(*peer_stats)); 1479 peer_stats->succ_pkts = succ_pkts; 1480 peer_stats->succ_bytes = succ_bytes; 1481 peer_stats->is_ampdu = is_ampdu; 1482 peer_stats->duration = tx_duration; 1483 peer_stats->ba_fails = 1484 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1485 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1486 } 1487 1488 spin_unlock_bh(&ab->base_lock); 1489 rcu_read_unlock(); 1490 } 1491 1492 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1493 struct htt_ppdu_stats *ppdu_stats) 1494 { 1495 u8 user; 1496 1497 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1498 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1499 } 1500 1501 static 1502 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1503 u32 ppdu_id) 1504 { 1505 struct htt_ppdu_stats_info *ppdu_info; 1506 1507 lockdep_assert_held(&ar->data_lock); 1508 if (!list_empty(&ar->ppdu_stats_info)) { 1509 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1510 if (ppdu_info->ppdu_id == ppdu_id) 1511 return ppdu_info; 1512 } 1513 1514 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1515 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1516 typeof(*ppdu_info), list); 1517 list_del(&ppdu_info->list); 1518 ar->ppdu_stat_list_depth--; 1519 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1520 kfree(ppdu_info); 1521 } 1522 } 1523 1524 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1525 if (!ppdu_info) 1526 return NULL; 1527 1528 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1529 ar->ppdu_stat_list_depth++; 1530 1531 return ppdu_info; 1532 } 1533 1534 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1535 struct htt_ppdu_user_stats *usr_stats) 1536 { 1537 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1538 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1539 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1540 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1541 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1542 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1543 peer->ppdu_stats_delayba.resp_rate_flags = 1544 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1545 1546 peer->delayba_flag = true; 1547 } 1548 1549 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1550 struct htt_ppdu_user_stats *usr_stats) 1551 { 1552 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1553 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1554 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1555 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1556 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1557 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1558 usr_stats->rate.resp_rate_flags = 1559 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1560 1561 peer->delayba_flag = false; 1562 } 1563 1564 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1565 struct sk_buff *skb) 1566 { 1567 struct ath12k_htt_ppdu_stats_msg *msg; 1568 struct htt_ppdu_stats_info *ppdu_info; 1569 struct ath12k_peer *peer = NULL; 1570 struct htt_ppdu_user_stats *usr_stats = NULL; 1571 u32 peer_id = 0; 1572 struct ath12k *ar; 1573 int ret, i; 1574 u8 pdev_id; 1575 u32 ppdu_id, len; 1576 1577 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1578 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1579 if (len > (skb->len - struct_size(msg, data, 0))) { 1580 ath12k_warn(ab, 1581 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1582 len, skb->len); 1583 return -EINVAL; 1584 } 1585 1586 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1587 ppdu_id = le32_to_cpu(msg->ppdu_id); 1588 1589 rcu_read_lock(); 1590 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1591 if (!ar) { 1592 ret = -EINVAL; 1593 goto exit; 1594 } 1595 1596 spin_lock_bh(&ar->data_lock); 1597 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1598 if (!ppdu_info) { 1599 spin_unlock_bh(&ar->data_lock); 1600 ret = -EINVAL; 1601 goto exit; 1602 } 1603 1604 ppdu_info->ppdu_id = ppdu_id; 1605 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1606 ath12k_htt_tlv_ppdu_stats_parse, 1607 (void *)ppdu_info); 1608 if (ret) { 1609 spin_unlock_bh(&ar->data_lock); 1610 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1611 goto exit; 1612 } 1613 1614 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1615 spin_unlock_bh(&ar->data_lock); 1616 ath12k_warn(ab, 1617 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1618 ppdu_info->ppdu_stats.common.num_users, 1619 HTT_PPDU_STATS_MAX_USERS); 1620 ret = -EINVAL; 1621 goto exit; 1622 } 1623 1624 /* back up data rate tlv for all peers */ 1625 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1626 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1627 ppdu_info->delay_ba) { 1628 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1629 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1630 spin_lock_bh(&ab->base_lock); 1631 peer = ath12k_peer_find_by_id(ab, peer_id); 1632 if (!peer) { 1633 spin_unlock_bh(&ab->base_lock); 1634 continue; 1635 } 1636 1637 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1638 if (usr_stats->delay_ba) 1639 ath12k_copy_to_delay_stats(peer, usr_stats); 1640 spin_unlock_bh(&ab->base_lock); 1641 } 1642 } 1643 1644 /* restore all peers' data rate tlv to mu-bar tlv */ 1645 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1646 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1647 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1648 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1649 spin_lock_bh(&ab->base_lock); 1650 peer = ath12k_peer_find_by_id(ab, peer_id); 1651 if (!peer) { 1652 spin_unlock_bh(&ab->base_lock); 1653 continue; 1654 } 1655 1656 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1657 if (peer->delayba_flag) 1658 ath12k_copy_to_bar(peer, usr_stats); 1659 spin_unlock_bh(&ab->base_lock); 1660 } 1661 } 1662 1663 spin_unlock_bh(&ar->data_lock); 1664 1665 exit: 1666 rcu_read_unlock(); 1667 1668 return ret; 1669 } 1670 1671 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1672 struct sk_buff *skb) 1673 { 1674 struct ath12k_htt_mlo_offset_msg *msg; 1675 struct ath12k_pdev *pdev; 1676 struct ath12k *ar; 1677 u8 pdev_id; 1678 1679 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1680 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1681 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1682 1683 rcu_read_lock(); 1684 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1685 if (!ar) { 1686 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id); 1687 goto exit; 1688 } 1689 1690 spin_lock_bh(&ar->data_lock); 1691 pdev = ar->pdev; 1692 1693 pdev->timestamp.info = __le32_to_cpu(msg->info); 1694 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1695 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1696 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1697 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1698 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1699 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1700 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1701 1702 spin_unlock_bh(&ar->data_lock); 1703 exit: 1704 rcu_read_unlock(); 1705 } 1706 1707 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1708 struct sk_buff *skb) 1709 { 1710 struct ath12k_dp *dp = &ab->dp; 1711 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1712 enum htt_t2h_msg_type type; 1713 u16 peer_id; 1714 u8 vdev_id; 1715 u8 mac_addr[ETH_ALEN]; 1716 u16 peer_mac_h16; 1717 u16 ast_hash = 0; 1718 u16 hw_peer_id; 1719 1720 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1721 1722 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1723 1724 switch (type) { 1725 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1726 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1727 HTT_T2H_VERSION_CONF_MAJOR); 1728 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1729 HTT_T2H_VERSION_CONF_MINOR); 1730 complete(&dp->htt_tgt_version_received); 1731 break; 1732 /* TODO: remove unused peer map versions after testing */ 1733 case HTT_T2H_MSG_TYPE_PEER_MAP: 1734 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1735 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1736 peer_id = le32_get_bits(resp->peer_map_ev.info, 1737 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1738 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1739 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1740 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1741 peer_mac_h16, mac_addr); 1742 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1743 break; 1744 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1745 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1746 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1747 peer_id = le32_get_bits(resp->peer_map_ev.info, 1748 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1749 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1750 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1751 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1752 peer_mac_h16, mac_addr); 1753 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1754 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1755 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1756 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1757 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1758 hw_peer_id); 1759 break; 1760 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1761 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1762 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1763 peer_id = le32_get_bits(resp->peer_map_ev.info, 1764 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1765 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1766 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1767 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1768 peer_mac_h16, mac_addr); 1769 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1770 peer_id); 1771 break; 1772 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1773 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1774 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1775 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1776 ath12k_peer_unmap_event(ab, peer_id); 1777 break; 1778 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1779 ath12k_htt_pull_ppdu_stats(ab, skb); 1780 break; 1781 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1782 break; 1783 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 1784 ath12k_htt_mlo_offset_event_handler(ab, skb); 1785 break; 1786 default: 1787 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 1788 type); 1789 break; 1790 } 1791 1792 dev_kfree_skb_any(skb); 1793 } 1794 1795 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 1796 struct sk_buff_head *msdu_list, 1797 struct sk_buff *first, struct sk_buff *last, 1798 u8 l3pad_bytes, int msdu_len) 1799 { 1800 struct ath12k_base *ab = ar->ab; 1801 struct sk_buff *skb; 1802 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1803 int buf_first_hdr_len, buf_first_len; 1804 struct hal_rx_desc *ldesc; 1805 int space_extra, rem_len, buf_len; 1806 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 1807 1808 /* As the msdu is spread across multiple rx buffers, 1809 * find the offset to the start of msdu for computing 1810 * the length of the msdu in the first buffer. 1811 */ 1812 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1813 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1814 1815 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1816 skb_put(first, buf_first_hdr_len + msdu_len); 1817 skb_pull(first, buf_first_hdr_len); 1818 return 0; 1819 } 1820 1821 ldesc = (struct hal_rx_desc *)last->data; 1822 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 1823 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 1824 1825 /* MSDU spans over multiple buffers because the length of the MSDU 1826 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1827 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1828 */ 1829 skb_put(first, DP_RX_BUFFER_SIZE); 1830 skb_pull(first, buf_first_hdr_len); 1831 1832 /* When an MSDU spread over multiple buffers MSDU_END 1833 * tlvs are valid only in the last buffer. Copy those tlvs. 1834 */ 1835 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1836 1837 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1838 if (space_extra > 0 && 1839 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1840 /* Free up all buffers of the MSDU */ 1841 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1842 rxcb = ATH12K_SKB_RXCB(skb); 1843 if (!rxcb->is_continuation) { 1844 dev_kfree_skb_any(skb); 1845 break; 1846 } 1847 dev_kfree_skb_any(skb); 1848 } 1849 return -ENOMEM; 1850 } 1851 1852 rem_len = msdu_len - buf_first_len; 1853 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1854 rxcb = ATH12K_SKB_RXCB(skb); 1855 if (rxcb->is_continuation) 1856 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1857 else 1858 buf_len = rem_len; 1859 1860 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1861 WARN_ON_ONCE(1); 1862 dev_kfree_skb_any(skb); 1863 return -EINVAL; 1864 } 1865 1866 skb_put(skb, buf_len + hal_rx_desc_sz); 1867 skb_pull(skb, hal_rx_desc_sz); 1868 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1869 buf_len); 1870 dev_kfree_skb_any(skb); 1871 1872 rem_len -= buf_len; 1873 if (!rxcb->is_continuation) 1874 break; 1875 } 1876 1877 return 0; 1878 } 1879 1880 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1881 struct sk_buff *first) 1882 { 1883 struct sk_buff *skb; 1884 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1885 1886 if (!rxcb->is_continuation) 1887 return first; 1888 1889 skb_queue_walk(msdu_list, skb) { 1890 rxcb = ATH12K_SKB_RXCB(skb); 1891 if (!rxcb->is_continuation) 1892 return skb; 1893 } 1894 1895 return NULL; 1896 } 1897 1898 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu) 1899 { 1900 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1901 struct ath12k_base *ab = ar->ab; 1902 bool ip_csum_fail, l4_csum_fail; 1903 1904 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc); 1905 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc); 1906 1907 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1908 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1909 } 1910 1911 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, 1912 enum hal_encrypt_type enctype) 1913 { 1914 switch (enctype) { 1915 case HAL_ENCRYPT_TYPE_OPEN: 1916 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1917 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1918 return 0; 1919 case HAL_ENCRYPT_TYPE_CCMP_128: 1920 return IEEE80211_CCMP_MIC_LEN; 1921 case HAL_ENCRYPT_TYPE_CCMP_256: 1922 return IEEE80211_CCMP_256_MIC_LEN; 1923 case HAL_ENCRYPT_TYPE_GCMP_128: 1924 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1925 return IEEE80211_GCMP_MIC_LEN; 1926 case HAL_ENCRYPT_TYPE_WEP_40: 1927 case HAL_ENCRYPT_TYPE_WEP_104: 1928 case HAL_ENCRYPT_TYPE_WEP_128: 1929 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1930 case HAL_ENCRYPT_TYPE_WAPI: 1931 break; 1932 } 1933 1934 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1935 return 0; 1936 } 1937 1938 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 1939 enum hal_encrypt_type enctype) 1940 { 1941 switch (enctype) { 1942 case HAL_ENCRYPT_TYPE_OPEN: 1943 return 0; 1944 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1945 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1946 return IEEE80211_TKIP_IV_LEN; 1947 case HAL_ENCRYPT_TYPE_CCMP_128: 1948 return IEEE80211_CCMP_HDR_LEN; 1949 case HAL_ENCRYPT_TYPE_CCMP_256: 1950 return IEEE80211_CCMP_256_HDR_LEN; 1951 case HAL_ENCRYPT_TYPE_GCMP_128: 1952 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1953 return IEEE80211_GCMP_HDR_LEN; 1954 case HAL_ENCRYPT_TYPE_WEP_40: 1955 case HAL_ENCRYPT_TYPE_WEP_104: 1956 case HAL_ENCRYPT_TYPE_WEP_128: 1957 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1958 case HAL_ENCRYPT_TYPE_WAPI: 1959 break; 1960 } 1961 1962 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1963 return 0; 1964 } 1965 1966 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 1967 enum hal_encrypt_type enctype) 1968 { 1969 switch (enctype) { 1970 case HAL_ENCRYPT_TYPE_OPEN: 1971 case HAL_ENCRYPT_TYPE_CCMP_128: 1972 case HAL_ENCRYPT_TYPE_CCMP_256: 1973 case HAL_ENCRYPT_TYPE_GCMP_128: 1974 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1975 return 0; 1976 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1977 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1978 return IEEE80211_TKIP_ICV_LEN; 1979 case HAL_ENCRYPT_TYPE_WEP_40: 1980 case HAL_ENCRYPT_TYPE_WEP_104: 1981 case HAL_ENCRYPT_TYPE_WEP_128: 1982 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1983 case HAL_ENCRYPT_TYPE_WAPI: 1984 break; 1985 } 1986 1987 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1988 return 0; 1989 } 1990 1991 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 1992 struct sk_buff *msdu, 1993 enum hal_encrypt_type enctype, 1994 struct ieee80211_rx_status *status) 1995 { 1996 struct ath12k_base *ab = ar->ab; 1997 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1998 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1999 struct ieee80211_hdr *hdr; 2000 size_t hdr_len; 2001 u8 *crypto_hdr; 2002 u16 qos_ctl; 2003 2004 /* pull decapped header */ 2005 hdr = (struct ieee80211_hdr *)msdu->data; 2006 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2007 skb_pull(msdu, hdr_len); 2008 2009 /* Rebuild qos header */ 2010 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 2011 2012 /* Reset the order bit as the HT_Control header is stripped */ 2013 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2014 2015 qos_ctl = rxcb->tid; 2016 2017 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 2018 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2019 2020 /* TODO: Add other QoS ctl fields when required */ 2021 2022 /* copy decap header before overwriting for reuse below */ 2023 memcpy(decap_hdr, hdr, hdr_len); 2024 2025 /* Rebuild crypto header for mac80211 use */ 2026 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2027 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 2028 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 2029 rxcb->rx_desc, crypto_hdr, 2030 enctype); 2031 } 2032 2033 memcpy(skb_push(msdu, 2034 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2035 IEEE80211_QOS_CTL_LEN); 2036 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2037 } 2038 2039 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2040 enum hal_encrypt_type enctype, 2041 struct ieee80211_rx_status *status, 2042 bool decrypted) 2043 { 2044 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2045 struct ieee80211_hdr *hdr; 2046 size_t hdr_len; 2047 size_t crypto_len; 2048 2049 if (!rxcb->is_first_msdu || 2050 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2051 WARN_ON_ONCE(1); 2052 return; 2053 } 2054 2055 skb_trim(msdu, msdu->len - FCS_LEN); 2056 2057 if (!decrypted) 2058 return; 2059 2060 hdr = (void *)msdu->data; 2061 2062 /* Tail */ 2063 if (status->flag & RX_FLAG_IV_STRIPPED) { 2064 skb_trim(msdu, msdu->len - 2065 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2066 2067 skb_trim(msdu, msdu->len - 2068 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2069 } else { 2070 /* MIC */ 2071 if (status->flag & RX_FLAG_MIC_STRIPPED) 2072 skb_trim(msdu, msdu->len - 2073 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2074 2075 /* ICV */ 2076 if (status->flag & RX_FLAG_ICV_STRIPPED) 2077 skb_trim(msdu, msdu->len - 2078 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2079 } 2080 2081 /* MMIC */ 2082 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2083 !ieee80211_has_morefrags(hdr->frame_control) && 2084 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2085 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2086 2087 /* Head */ 2088 if (status->flag & RX_FLAG_IV_STRIPPED) { 2089 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2090 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2091 2092 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2093 skb_pull(msdu, crypto_len); 2094 } 2095 } 2096 2097 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2098 struct sk_buff *msdu, 2099 struct ath12k_skb_rxcb *rxcb, 2100 struct ieee80211_rx_status *status, 2101 enum hal_encrypt_type enctype) 2102 { 2103 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2104 struct ath12k_base *ab = ar->ab; 2105 size_t hdr_len, crypto_len; 2106 struct ieee80211_hdr *hdr; 2107 u16 qos_ctl; 2108 __le16 fc; 2109 u8 *crypto_hdr; 2110 2111 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2112 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2113 crypto_hdr = skb_push(msdu, crypto_len); 2114 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2115 } 2116 2117 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc)); 2118 hdr_len = ieee80211_hdrlen(fc); 2119 skb_push(msdu, hdr_len); 2120 hdr = (struct ieee80211_hdr *)msdu->data; 2121 hdr->frame_control = fc; 2122 2123 /* Get wifi header from rx_desc */ 2124 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr); 2125 2126 if (rxcb->is_mcbc) 2127 status->flag &= ~RX_FLAG_PN_VALIDATED; 2128 2129 /* Add QOS header */ 2130 if (ieee80211_is_data_qos(hdr->frame_control)) { 2131 qos_ctl = rxcb->tid; 2132 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc)) 2133 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2134 2135 /* TODO: Add other QoS ctl fields when required */ 2136 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN), 2137 &qos_ctl, IEEE80211_QOS_CTL_LEN); 2138 } 2139 } 2140 2141 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2142 struct sk_buff *msdu, 2143 enum hal_encrypt_type enctype, 2144 struct ieee80211_rx_status *status) 2145 { 2146 struct ieee80211_hdr *hdr; 2147 struct ethhdr *eth; 2148 u8 da[ETH_ALEN]; 2149 u8 sa[ETH_ALEN]; 2150 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2151 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2152 2153 eth = (struct ethhdr *)msdu->data; 2154 ether_addr_copy(da, eth->h_dest); 2155 ether_addr_copy(sa, eth->h_source); 2156 rfc.snap_type = eth->h_proto; 2157 skb_pull(msdu, sizeof(*eth)); 2158 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2159 sizeof(rfc)); 2160 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2161 2162 /* original 802.11 header has a different DA and in 2163 * case of 4addr it may also have different SA 2164 */ 2165 hdr = (struct ieee80211_hdr *)msdu->data; 2166 ether_addr_copy(ieee80211_get_DA(hdr), da); 2167 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2168 } 2169 2170 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2171 struct hal_rx_desc *rx_desc, 2172 enum hal_encrypt_type enctype, 2173 struct ieee80211_rx_status *status, 2174 bool decrypted) 2175 { 2176 struct ath12k_base *ab = ar->ab; 2177 u8 decap; 2178 struct ethhdr *ehdr; 2179 2180 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2181 2182 switch (decap) { 2183 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2184 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2185 break; 2186 case DP_RX_DECAP_TYPE_RAW: 2187 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2188 decrypted); 2189 break; 2190 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2191 ehdr = (struct ethhdr *)msdu->data; 2192 2193 /* mac80211 allows fast path only for authorized STA */ 2194 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2195 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2196 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2197 break; 2198 } 2199 2200 /* PN for mcast packets will be validated in mac80211; 2201 * remove eth header and add 802.11 header. 2202 */ 2203 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2204 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2205 break; 2206 case DP_RX_DECAP_TYPE_8023: 2207 /* TODO: Handle undecap for these formats */ 2208 break; 2209 } 2210 } 2211 2212 struct ath12k_peer * 2213 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu) 2214 { 2215 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2216 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2217 struct ath12k_peer *peer = NULL; 2218 2219 lockdep_assert_held(&ab->base_lock); 2220 2221 if (rxcb->peer_id) 2222 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2223 2224 if (peer) 2225 return peer; 2226 2227 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2228 return NULL; 2229 2230 peer = ath12k_peer_find_by_addr(ab, 2231 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, 2232 rx_desc)); 2233 return peer; 2234 } 2235 2236 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2237 struct sk_buff *msdu, 2238 struct hal_rx_desc *rx_desc, 2239 struct ieee80211_rx_status *rx_status) 2240 { 2241 bool fill_crypto_hdr; 2242 struct ath12k_base *ab = ar->ab; 2243 struct ath12k_skb_rxcb *rxcb; 2244 enum hal_encrypt_type enctype; 2245 bool is_decrypted = false; 2246 struct ieee80211_hdr *hdr; 2247 struct ath12k_peer *peer; 2248 u32 err_bitmap; 2249 2250 /* PN for multicast packets will be checked in mac80211 */ 2251 rxcb = ATH12K_SKB_RXCB(msdu); 2252 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc); 2253 rxcb->is_mcbc = fill_crypto_hdr; 2254 2255 if (rxcb->is_mcbc) 2256 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc); 2257 2258 spin_lock_bh(&ar->ab->base_lock); 2259 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 2260 if (peer) { 2261 if (rxcb->is_mcbc) 2262 enctype = peer->sec_type_grp; 2263 else 2264 enctype = peer->sec_type; 2265 } else { 2266 enctype = HAL_ENCRYPT_TYPE_OPEN; 2267 } 2268 spin_unlock_bh(&ar->ab->base_lock); 2269 2270 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2271 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2272 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2273 2274 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2275 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2276 RX_FLAG_MMIC_ERROR | 2277 RX_FLAG_DECRYPTED | 2278 RX_FLAG_IV_STRIPPED | 2279 RX_FLAG_MMIC_STRIPPED); 2280 2281 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2282 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2283 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2284 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2285 2286 if (is_decrypted) { 2287 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2288 2289 if (fill_crypto_hdr) 2290 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2291 RX_FLAG_ICV_STRIPPED; 2292 else 2293 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2294 RX_FLAG_PN_VALIDATED; 2295 } 2296 2297 ath12k_dp_rx_h_csum_offload(ar, msdu); 2298 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2299 enctype, rx_status, is_decrypted); 2300 2301 if (!is_decrypted || fill_crypto_hdr) 2302 return; 2303 2304 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) != 2305 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2306 hdr = (void *)msdu->data; 2307 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2308 } 2309 } 2310 2311 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2312 struct ieee80211_rx_status *rx_status) 2313 { 2314 struct ath12k_base *ab = ar->ab; 2315 struct ieee80211_supported_band *sband; 2316 enum rx_msdu_start_pkt_type pkt_type; 2317 u8 bw; 2318 u8 rate_mcs, nss; 2319 u8 sgi; 2320 bool is_cck; 2321 2322 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2323 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2324 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2325 nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2326 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2327 2328 switch (pkt_type) { 2329 case RX_MSDU_START_PKT_TYPE_11A: 2330 case RX_MSDU_START_PKT_TYPE_11B: 2331 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2332 sband = &ar->mac.sbands[rx_status->band]; 2333 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2334 is_cck); 2335 break; 2336 case RX_MSDU_START_PKT_TYPE_11N: 2337 rx_status->encoding = RX_ENC_HT; 2338 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2339 ath12k_warn(ar->ab, 2340 "Received with invalid mcs in HT mode %d\n", 2341 rate_mcs); 2342 break; 2343 } 2344 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2345 if (sgi) 2346 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2347 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2348 break; 2349 case RX_MSDU_START_PKT_TYPE_11AC: 2350 rx_status->encoding = RX_ENC_VHT; 2351 rx_status->rate_idx = rate_mcs; 2352 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2353 ath12k_warn(ar->ab, 2354 "Received with invalid mcs in VHT mode %d\n", 2355 rate_mcs); 2356 break; 2357 } 2358 rx_status->nss = nss; 2359 if (sgi) 2360 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2361 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2362 break; 2363 case RX_MSDU_START_PKT_TYPE_11AX: 2364 rx_status->rate_idx = rate_mcs; 2365 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2366 ath12k_warn(ar->ab, 2367 "Received with invalid mcs in HE mode %d\n", 2368 rate_mcs); 2369 break; 2370 } 2371 rx_status->encoding = RX_ENC_HE; 2372 rx_status->nss = nss; 2373 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2374 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2375 break; 2376 } 2377 } 2378 2379 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2380 struct ieee80211_rx_status *rx_status) 2381 { 2382 struct ath12k_base *ab = ar->ab; 2383 u8 channel_num; 2384 u32 center_freq, meta_data; 2385 struct ieee80211_channel *channel; 2386 2387 rx_status->freq = 0; 2388 rx_status->rate_idx = 0; 2389 rx_status->nss = 0; 2390 rx_status->encoding = RX_ENC_LEGACY; 2391 rx_status->bw = RATE_INFO_BW_20; 2392 rx_status->enc_flags = 0; 2393 2394 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2395 2396 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2397 channel_num = meta_data; 2398 center_freq = meta_data >> 16; 2399 2400 if (center_freq >= 5935 && center_freq <= 7105) { 2401 rx_status->band = NL80211_BAND_6GHZ; 2402 } else if (channel_num >= 1 && channel_num <= 14) { 2403 rx_status->band = NL80211_BAND_2GHZ; 2404 } else if (channel_num >= 36 && channel_num <= 173) { 2405 rx_status->band = NL80211_BAND_5GHZ; 2406 } else { 2407 spin_lock_bh(&ar->data_lock); 2408 channel = ar->rx_channel; 2409 if (channel) { 2410 rx_status->band = channel->band; 2411 channel_num = 2412 ieee80211_frequency_to_channel(channel->center_freq); 2413 } 2414 spin_unlock_bh(&ar->data_lock); 2415 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2416 rx_desc, sizeof(*rx_desc)); 2417 } 2418 2419 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2420 rx_status->band); 2421 2422 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status); 2423 } 2424 2425 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2426 struct sk_buff *msdu, 2427 struct ieee80211_rx_status *status) 2428 { 2429 struct ath12k_base *ab = ar->ab; 2430 static const struct ieee80211_radiotap_he known = { 2431 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2432 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2433 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2434 }; 2435 struct ieee80211_radiotap_he *he; 2436 struct ieee80211_rx_status *rx_status; 2437 struct ieee80211_sta *pubsta; 2438 struct ath12k_peer *peer; 2439 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2440 u8 decap = DP_RX_DECAP_TYPE_RAW; 2441 bool is_mcbc = rxcb->is_mcbc; 2442 bool is_eapol = rxcb->is_eapol; 2443 2444 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) && 2445 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2446 he = skb_push(msdu, sizeof(known)); 2447 memcpy(he, &known, sizeof(known)); 2448 status->flag |= RX_FLAG_RADIOTAP_HE; 2449 } 2450 2451 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2452 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc); 2453 2454 spin_lock_bh(&ab->base_lock); 2455 peer = ath12k_dp_rx_h_find_peer(ab, msdu); 2456 2457 pubsta = peer ? peer->sta : NULL; 2458 2459 spin_unlock_bh(&ab->base_lock); 2460 2461 ath12k_dbg(ab, ATH12K_DBG_DATA, 2462 "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2463 msdu, 2464 msdu->len, 2465 peer ? peer->addr : NULL, 2466 rxcb->tid, 2467 is_mcbc ? "mcast" : "ucast", 2468 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2469 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2470 (status->encoding == RX_ENC_HT) ? "ht" : "", 2471 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2472 (status->encoding == RX_ENC_HE) ? "he" : "", 2473 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2474 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2475 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2476 (status->bw == RATE_INFO_BW_320) ? "320" : "", 2477 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2478 status->rate_idx, 2479 status->nss, 2480 status->freq, 2481 status->band, status->flag, 2482 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2483 !!(status->flag & RX_FLAG_MMIC_ERROR), 2484 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2485 2486 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2487 msdu->data, msdu->len); 2488 2489 rx_status = IEEE80211_SKB_RXCB(msdu); 2490 *rx_status = *status; 2491 2492 /* TODO: trace rx packet */ 2493 2494 /* PN for multicast packets are not validate in HW, 2495 * so skip 802.3 rx path 2496 * Also, fast_rx expects the STA to be authorized, hence 2497 * eapol packets are sent in slow path. 2498 */ 2499 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2500 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2501 rx_status->flag |= RX_FLAG_8023; 2502 2503 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 2504 } 2505 2506 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2507 struct sk_buff *msdu, 2508 struct sk_buff_head *msdu_list, 2509 struct ieee80211_rx_status *rx_status) 2510 { 2511 struct ath12k_base *ab = ar->ab; 2512 struct hal_rx_desc *rx_desc, *lrx_desc; 2513 struct ath12k_skb_rxcb *rxcb; 2514 struct sk_buff *last_buf; 2515 u8 l3_pad_bytes; 2516 u16 msdu_len; 2517 int ret; 2518 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2519 2520 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2521 if (!last_buf) { 2522 ath12k_warn(ab, 2523 "No valid Rx buffer to access MSDU_END tlv\n"); 2524 ret = -EIO; 2525 goto free_out; 2526 } 2527 2528 rx_desc = (struct hal_rx_desc *)msdu->data; 2529 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2530 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2531 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2532 ret = -EIO; 2533 goto free_out; 2534 } 2535 2536 rxcb = ATH12K_SKB_RXCB(msdu); 2537 rxcb->rx_desc = rx_desc; 2538 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2539 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2540 2541 if (rxcb->is_frag) { 2542 skb_pull(msdu, hal_rx_desc_sz); 2543 } else if (!rxcb->is_continuation) { 2544 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2545 ret = -EINVAL; 2546 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2547 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2548 sizeof(*rx_desc)); 2549 goto free_out; 2550 } 2551 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2552 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2553 } else { 2554 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2555 msdu, last_buf, 2556 l3_pad_bytes, msdu_len); 2557 if (ret) { 2558 ath12k_warn(ab, 2559 "failed to coalesce msdu rx buffer%d\n", ret); 2560 goto free_out; 2561 } 2562 } 2563 2564 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2565 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2566 2567 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2568 2569 return 0; 2570 2571 free_out: 2572 return ret; 2573 } 2574 2575 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2576 struct napi_struct *napi, 2577 struct sk_buff_head *msdu_list, 2578 int ring_id) 2579 { 2580 struct ieee80211_rx_status rx_status = {0}; 2581 struct ath12k_skb_rxcb *rxcb; 2582 struct sk_buff *msdu; 2583 struct ath12k *ar; 2584 u8 mac_id, pdev_id; 2585 int ret; 2586 2587 if (skb_queue_empty(msdu_list)) 2588 return; 2589 2590 rcu_read_lock(); 2591 2592 while ((msdu = __skb_dequeue(msdu_list))) { 2593 rxcb = ATH12K_SKB_RXCB(msdu); 2594 mac_id = rxcb->mac_id; 2595 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 2596 ar = ab->pdevs[pdev_id].ar; 2597 if (!rcu_dereference(ab->pdevs_active[pdev_id])) { 2598 dev_kfree_skb_any(msdu); 2599 continue; 2600 } 2601 2602 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 2603 dev_kfree_skb_any(msdu); 2604 continue; 2605 } 2606 2607 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2608 if (ret) { 2609 ath12k_dbg(ab, ATH12K_DBG_DATA, 2610 "Unable to process msdu %d", ret); 2611 dev_kfree_skb_any(msdu); 2612 continue; 2613 } 2614 2615 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2616 } 2617 2618 rcu_read_unlock(); 2619 } 2620 2621 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2622 struct napi_struct *napi, int budget) 2623 { 2624 LIST_HEAD(rx_desc_used_list); 2625 struct ath12k_rx_desc_info *desc_info; 2626 struct ath12k_dp *dp = &ab->dp; 2627 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2628 struct hal_reo_dest_ring *desc; 2629 int num_buffs_reaped = 0; 2630 struct sk_buff_head msdu_list; 2631 struct ath12k_skb_rxcb *rxcb; 2632 int total_msdu_reaped = 0; 2633 struct hal_srng *srng; 2634 struct sk_buff *msdu; 2635 bool done = false; 2636 int mac_id; 2637 u64 desc_va; 2638 2639 __skb_queue_head_init(&msdu_list); 2640 2641 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2642 2643 spin_lock_bh(&srng->lock); 2644 2645 try_again: 2646 ath12k_hal_srng_access_begin(ab, srng); 2647 2648 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2649 enum hal_reo_dest_ring_push_reason push_reason; 2650 u32 cookie; 2651 2652 cookie = le32_get_bits(desc->buf_addr_info.info1, 2653 BUFFER_ADDR_INFO1_SW_COOKIE); 2654 2655 mac_id = le32_get_bits(desc->info0, 2656 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2657 2658 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2659 le32_to_cpu(desc->buf_va_lo)); 2660 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2661 2662 /* retry manual desc retrieval */ 2663 if (!desc_info) { 2664 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 2665 if (!desc_info) { 2666 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 2667 continue; 2668 } 2669 } 2670 2671 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 2672 ath12k_warn(ab, "Check HW CC implementation"); 2673 2674 msdu = desc_info->skb; 2675 desc_info->skb = NULL; 2676 2677 list_add_tail(&desc_info->list, &rx_desc_used_list); 2678 2679 rxcb = ATH12K_SKB_RXCB(msdu); 2680 dma_unmap_single(ab->dev, rxcb->paddr, 2681 msdu->len + skb_tailroom(msdu), 2682 DMA_FROM_DEVICE); 2683 2684 num_buffs_reaped++; 2685 2686 push_reason = le32_get_bits(desc->info0, 2687 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 2688 if (push_reason != 2689 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2690 dev_kfree_skb_any(msdu); 2691 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2692 continue; 2693 } 2694 2695 rxcb->is_first_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2696 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2697 rxcb->is_last_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2698 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2699 rxcb->is_continuation = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2700 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2701 rxcb->mac_id = mac_id; 2702 rxcb->peer_id = le32_get_bits(desc->rx_mpdu_info.peer_meta_data, 2703 RX_MPDU_DESC_META_DATA_PEER_ID); 2704 rxcb->tid = le32_get_bits(desc->rx_mpdu_info.info0, 2705 RX_MPDU_DESC_INFO0_TID); 2706 2707 __skb_queue_tail(&msdu_list, msdu); 2708 2709 if (!rxcb->is_continuation) { 2710 total_msdu_reaped++; 2711 done = true; 2712 } else { 2713 done = false; 2714 } 2715 2716 if (total_msdu_reaped >= budget) 2717 break; 2718 } 2719 2720 /* Hw might have updated the head pointer after we cached it. 2721 * In this case, even though there are entries in the ring we'll 2722 * get rx_desc NULL. Give the read another try with updated cached 2723 * head pointer so that we can reap complete MPDU in the current 2724 * rx processing. 2725 */ 2726 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 2727 ath12k_hal_srng_access_end(ab, srng); 2728 goto try_again; 2729 } 2730 2731 ath12k_hal_srng_access_end(ab, srng); 2732 2733 spin_unlock_bh(&srng->lock); 2734 2735 if (!total_msdu_reaped) 2736 goto exit; 2737 2738 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 2739 num_buffs_reaped); 2740 2741 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2742 ring_id); 2743 2744 exit: 2745 return total_msdu_reaped; 2746 } 2747 2748 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 2749 { 2750 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2751 2752 spin_lock_bh(&rx_tid->ab->base_lock); 2753 if (rx_tid->last_frag_no && 2754 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2755 spin_unlock_bh(&rx_tid->ab->base_lock); 2756 return; 2757 } 2758 ath12k_dp_rx_frags_cleanup(rx_tid, true); 2759 spin_unlock_bh(&rx_tid->ab->base_lock); 2760 } 2761 2762 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 2763 { 2764 struct ath12k_base *ab = ar->ab; 2765 struct crypto_shash *tfm; 2766 struct ath12k_peer *peer; 2767 struct ath12k_dp_rx_tid *rx_tid; 2768 int i; 2769 2770 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2771 if (IS_ERR(tfm)) 2772 return PTR_ERR(tfm); 2773 2774 spin_lock_bh(&ab->base_lock); 2775 2776 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 2777 if (!peer) { 2778 spin_unlock_bh(&ab->base_lock); 2779 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 2780 return -ENOENT; 2781 } 2782 2783 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 2784 rx_tid = &peer->rx_tid[i]; 2785 rx_tid->ab = ab; 2786 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 2787 skb_queue_head_init(&rx_tid->rx_frags); 2788 } 2789 2790 peer->tfm_mmic = tfm; 2791 peer->dp_setup_done = true; 2792 spin_unlock_bh(&ab->base_lock); 2793 2794 return 0; 2795 } 2796 2797 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 2798 struct ieee80211_hdr *hdr, u8 *data, 2799 size_t data_len, u8 *mic) 2800 { 2801 SHASH_DESC_ON_STACK(desc, tfm); 2802 u8 mic_hdr[16] = {0}; 2803 u8 tid = 0; 2804 int ret; 2805 2806 if (!tfm) 2807 return -EINVAL; 2808 2809 desc->tfm = tfm; 2810 2811 ret = crypto_shash_setkey(tfm, key, 8); 2812 if (ret) 2813 goto out; 2814 2815 ret = crypto_shash_init(desc); 2816 if (ret) 2817 goto out; 2818 2819 /* TKIP MIC header */ 2820 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 2821 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 2822 if (ieee80211_is_data_qos(hdr->frame_control)) 2823 tid = ieee80211_get_tid(hdr); 2824 mic_hdr[12] = tid; 2825 2826 ret = crypto_shash_update(desc, mic_hdr, 16); 2827 if (ret) 2828 goto out; 2829 ret = crypto_shash_update(desc, data, data_len); 2830 if (ret) 2831 goto out; 2832 ret = crypto_shash_final(desc, mic); 2833 out: 2834 shash_desc_zero(desc); 2835 return ret; 2836 } 2837 2838 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 2839 struct sk_buff *msdu) 2840 { 2841 struct ath12k_base *ab = ar->ab; 2842 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 2843 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 2844 struct ieee80211_key_conf *key_conf; 2845 struct ieee80211_hdr *hdr; 2846 u8 mic[IEEE80211_CCMP_MIC_LEN]; 2847 int head_len, tail_len, ret; 2848 size_t data_len; 2849 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2850 u8 *key, *data; 2851 u8 key_idx; 2852 2853 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 2854 return 0; 2855 2856 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2857 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2858 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 2859 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 2860 2861 if (!is_multicast_ether_addr(hdr->addr1)) 2862 key_idx = peer->ucast_keyidx; 2863 else 2864 key_idx = peer->mcast_keyidx; 2865 2866 key_conf = peer->keys[key_idx]; 2867 2868 data = msdu->data + head_len; 2869 data_len = msdu->len - head_len - tail_len; 2870 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 2871 2872 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 2873 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 2874 goto mic_fail; 2875 2876 return 0; 2877 2878 mic_fail: 2879 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 2880 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 2881 2882 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 2883 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 2884 skb_pull(msdu, hal_rx_desc_sz); 2885 2886 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 2887 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2888 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 2889 ieee80211_rx(ath12k_ar_to_hw(ar), msdu); 2890 return -EINVAL; 2891 } 2892 2893 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 2894 enum hal_encrypt_type enctype, u32 flags) 2895 { 2896 struct ieee80211_hdr *hdr; 2897 size_t hdr_len; 2898 size_t crypto_len; 2899 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2900 2901 if (!flags) 2902 return; 2903 2904 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2905 2906 if (flags & RX_FLAG_MIC_STRIPPED) 2907 skb_trim(msdu, msdu->len - 2908 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2909 2910 if (flags & RX_FLAG_ICV_STRIPPED) 2911 skb_trim(msdu, msdu->len - 2912 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2913 2914 if (flags & RX_FLAG_IV_STRIPPED) { 2915 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2916 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2917 2918 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 2919 msdu->data + hal_rx_desc_sz, hdr_len); 2920 skb_pull(msdu, crypto_len); 2921 } 2922 } 2923 2924 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 2925 struct ath12k_peer *peer, 2926 struct ath12k_dp_rx_tid *rx_tid, 2927 struct sk_buff **defrag_skb) 2928 { 2929 struct ath12k_base *ab = ar->ab; 2930 struct hal_rx_desc *rx_desc; 2931 struct sk_buff *skb, *first_frag, *last_frag; 2932 struct ieee80211_hdr *hdr; 2933 enum hal_encrypt_type enctype; 2934 bool is_decrypted = false; 2935 int msdu_len = 0; 2936 int extra_space; 2937 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2938 2939 first_frag = skb_peek(&rx_tid->rx_frags); 2940 last_frag = skb_peek_tail(&rx_tid->rx_frags); 2941 2942 skb_queue_walk(&rx_tid->rx_frags, skb) { 2943 flags = 0; 2944 rx_desc = (struct hal_rx_desc *)skb->data; 2945 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 2946 2947 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 2948 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 2949 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 2950 rx_desc); 2951 2952 if (is_decrypted) { 2953 if (skb != first_frag) 2954 flags |= RX_FLAG_IV_STRIPPED; 2955 if (skb != last_frag) 2956 flags |= RX_FLAG_ICV_STRIPPED | 2957 RX_FLAG_MIC_STRIPPED; 2958 } 2959 2960 /* RX fragments are always raw packets */ 2961 if (skb != last_frag) 2962 skb_trim(skb, skb->len - FCS_LEN); 2963 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 2964 2965 if (skb != first_frag) 2966 skb_pull(skb, hal_rx_desc_sz + 2967 ieee80211_hdrlen(hdr->frame_control)); 2968 msdu_len += skb->len; 2969 } 2970 2971 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 2972 if (extra_space > 0 && 2973 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 2974 return -ENOMEM; 2975 2976 __skb_unlink(first_frag, &rx_tid->rx_frags); 2977 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 2978 skb_put_data(first_frag, skb->data, skb->len); 2979 dev_kfree_skb_any(skb); 2980 } 2981 2982 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 2983 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 2984 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 2985 2986 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 2987 first_frag = NULL; 2988 2989 *defrag_skb = first_frag; 2990 return 0; 2991 } 2992 2993 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 2994 struct ath12k_dp_rx_tid *rx_tid, 2995 struct sk_buff *defrag_skb) 2996 { 2997 struct ath12k_base *ab = ar->ab; 2998 struct ath12k_dp *dp = &ab->dp; 2999 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3000 struct hal_reo_entrance_ring *reo_ent_ring; 3001 struct hal_reo_dest_ring *reo_dest_ring; 3002 struct dp_link_desc_bank *link_desc_banks; 3003 struct hal_rx_msdu_link *msdu_link; 3004 struct hal_rx_msdu_details *msdu0; 3005 struct hal_srng *srng; 3006 dma_addr_t link_paddr, buf_paddr; 3007 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 3008 u32 cookie, hal_rx_desc_sz, dest_ring_info0; 3009 int ret; 3010 struct ath12k_rx_desc_info *desc_info; 3011 u8 dst_ind; 3012 3013 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3014 link_desc_banks = dp->link_desc_banks; 3015 reo_dest_ring = rx_tid->dst_ring_desc; 3016 3017 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 3018 &link_paddr, &cookie); 3019 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 3020 3021 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3022 (link_paddr - link_desc_banks[desc_bank].paddr)); 3023 msdu0 = &msdu_link->msdu_link[0]; 3024 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 3025 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 3026 3027 memset(msdu0, 0, sizeof(*msdu0)); 3028 3029 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 3030 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 3031 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3032 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3033 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3034 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3035 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3036 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3037 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3038 3039 /* change msdu len in hal rx desc */ 3040 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3041 3042 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3043 defrag_skb->len + skb_tailroom(defrag_skb), 3044 DMA_FROM_DEVICE); 3045 if (dma_mapping_error(ab->dev, buf_paddr)) 3046 return -ENOMEM; 3047 3048 spin_lock_bh(&dp->rx_desc_lock); 3049 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3050 struct ath12k_rx_desc_info, 3051 list); 3052 if (!desc_info) { 3053 spin_unlock_bh(&dp->rx_desc_lock); 3054 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3055 ret = -ENOMEM; 3056 goto err_unmap_dma; 3057 } 3058 3059 desc_info->skb = defrag_skb; 3060 desc_info->in_use = true; 3061 3062 list_del(&desc_info->list); 3063 spin_unlock_bh(&dp->rx_desc_lock); 3064 3065 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3066 3067 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3068 desc_info->cookie, 3069 HAL_RX_BUF_RBM_SW3_BM); 3070 3071 /* Fill mpdu details into reo entrance ring */ 3072 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3073 3074 spin_lock_bh(&srng->lock); 3075 ath12k_hal_srng_access_begin(ab, srng); 3076 3077 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3078 if (!reo_ent_ring) { 3079 ath12k_hal_srng_access_end(ab, srng); 3080 spin_unlock_bh(&srng->lock); 3081 ret = -ENOSPC; 3082 goto err_free_desc; 3083 } 3084 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3085 3086 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3087 cookie, 3088 HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST); 3089 3090 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3091 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3092 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3093 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3094 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3095 3096 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3097 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3098 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3099 3100 /* Firmware expects physical address to be filled in queue_addr_lo in 3101 * the MLO scenario and in case of non MLO peer meta data needs to be 3102 * filled. 3103 * TODO: Need to handle for MLO scenario. 3104 */ 3105 reo_ent_ring->queue_addr_lo = reo_dest_ring->rx_mpdu_info.peer_meta_data; 3106 reo_ent_ring->info0 = le32_encode_bits(dst_ind, 3107 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3108 3109 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3110 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3111 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3112 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3113 reo_ent_ring->info2 = 3114 cpu_to_le32(u32_get_bits(dest_ring_info0, 3115 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3116 3117 ath12k_hal_srng_access_end(ab, srng); 3118 spin_unlock_bh(&srng->lock); 3119 3120 return 0; 3121 3122 err_free_desc: 3123 spin_lock_bh(&dp->rx_desc_lock); 3124 desc_info->in_use = false; 3125 desc_info->skb = NULL; 3126 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3127 spin_unlock_bh(&dp->rx_desc_lock); 3128 err_unmap_dma: 3129 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3130 DMA_FROM_DEVICE); 3131 return ret; 3132 } 3133 3134 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3135 struct sk_buff *a, struct sk_buff *b) 3136 { 3137 int frag1, frag2; 3138 3139 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3140 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3141 3142 return frag1 - frag2; 3143 } 3144 3145 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3146 struct sk_buff_head *frag_list, 3147 struct sk_buff *cur_frag) 3148 { 3149 struct sk_buff *skb; 3150 int cmp; 3151 3152 skb_queue_walk(frag_list, skb) { 3153 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3154 if (cmp < 0) 3155 continue; 3156 __skb_queue_before(frag_list, skb, cur_frag); 3157 return; 3158 } 3159 __skb_queue_tail(frag_list, cur_frag); 3160 } 3161 3162 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3163 { 3164 struct ieee80211_hdr *hdr; 3165 u64 pn = 0; 3166 u8 *ehdr; 3167 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3168 3169 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3170 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3171 3172 pn = ehdr[0]; 3173 pn |= (u64)ehdr[1] << 8; 3174 pn |= (u64)ehdr[4] << 16; 3175 pn |= (u64)ehdr[5] << 24; 3176 pn |= (u64)ehdr[6] << 32; 3177 pn |= (u64)ehdr[7] << 40; 3178 3179 return pn; 3180 } 3181 3182 static bool 3183 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3184 { 3185 struct ath12k_base *ab = ar->ab; 3186 enum hal_encrypt_type encrypt_type; 3187 struct sk_buff *first_frag, *skb; 3188 struct hal_rx_desc *desc; 3189 u64 last_pn; 3190 u64 cur_pn; 3191 3192 first_frag = skb_peek(&rx_tid->rx_frags); 3193 desc = (struct hal_rx_desc *)first_frag->data; 3194 3195 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3196 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3197 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3198 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3199 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3200 return true; 3201 3202 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3203 skb_queue_walk(&rx_tid->rx_frags, skb) { 3204 if (skb == first_frag) 3205 continue; 3206 3207 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3208 if (cur_pn != last_pn + 1) 3209 return false; 3210 last_pn = cur_pn; 3211 } 3212 return true; 3213 } 3214 3215 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3216 struct sk_buff *msdu, 3217 struct hal_reo_dest_ring *ring_desc) 3218 { 3219 struct ath12k_base *ab = ar->ab; 3220 struct hal_rx_desc *rx_desc; 3221 struct ath12k_peer *peer; 3222 struct ath12k_dp_rx_tid *rx_tid; 3223 struct sk_buff *defrag_skb = NULL; 3224 u32 peer_id; 3225 u16 seqno, frag_no; 3226 u8 tid; 3227 int ret = 0; 3228 bool more_frags; 3229 3230 rx_desc = (struct hal_rx_desc *)msdu->data; 3231 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3232 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3233 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3234 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3235 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3236 3237 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3238 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3239 tid > IEEE80211_NUM_TIDS) 3240 return -EINVAL; 3241 3242 /* received unfragmented packet in reo 3243 * exception ring, this shouldn't happen 3244 * as these packets typically come from 3245 * reo2sw srngs. 3246 */ 3247 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3248 return -EINVAL; 3249 3250 spin_lock_bh(&ab->base_lock); 3251 peer = ath12k_peer_find_by_id(ab, peer_id); 3252 if (!peer) { 3253 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3254 peer_id); 3255 ret = -ENOENT; 3256 goto out_unlock; 3257 } 3258 3259 if (!peer->dp_setup_done) { 3260 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3261 peer->addr, peer_id); 3262 ret = -ENOENT; 3263 goto out_unlock; 3264 } 3265 3266 rx_tid = &peer->rx_tid[tid]; 3267 3268 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3269 skb_queue_empty(&rx_tid->rx_frags)) { 3270 /* Flush stored fragments and start a new sequence */ 3271 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3272 rx_tid->cur_sn = seqno; 3273 } 3274 3275 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3276 /* Fragment already present */ 3277 ret = -EINVAL; 3278 goto out_unlock; 3279 } 3280 3281 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3282 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3283 else 3284 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3285 3286 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3287 if (!more_frags) 3288 rx_tid->last_frag_no = frag_no; 3289 3290 if (frag_no == 0) { 3291 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3292 sizeof(*rx_tid->dst_ring_desc), 3293 GFP_ATOMIC); 3294 if (!rx_tid->dst_ring_desc) { 3295 ret = -ENOMEM; 3296 goto out_unlock; 3297 } 3298 } else { 3299 ath12k_dp_rx_link_desc_return(ab, ring_desc, 3300 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3301 } 3302 3303 if (!rx_tid->last_frag_no || 3304 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3305 mod_timer(&rx_tid->frag_timer, jiffies + 3306 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3307 goto out_unlock; 3308 } 3309 3310 spin_unlock_bh(&ab->base_lock); 3311 del_timer_sync(&rx_tid->frag_timer); 3312 spin_lock_bh(&ab->base_lock); 3313 3314 peer = ath12k_peer_find_by_id(ab, peer_id); 3315 if (!peer) 3316 goto err_frags_cleanup; 3317 3318 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3319 goto err_frags_cleanup; 3320 3321 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3322 goto err_frags_cleanup; 3323 3324 if (!defrag_skb) 3325 goto err_frags_cleanup; 3326 3327 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3328 goto err_frags_cleanup; 3329 3330 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3331 goto out_unlock; 3332 3333 err_frags_cleanup: 3334 dev_kfree_skb_any(defrag_skb); 3335 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3336 out_unlock: 3337 spin_unlock_bh(&ab->base_lock); 3338 return ret; 3339 } 3340 3341 static int 3342 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3343 struct list_head *used_list, 3344 bool drop, u32 cookie) 3345 { 3346 struct ath12k_base *ab = ar->ab; 3347 struct sk_buff *msdu; 3348 struct ath12k_skb_rxcb *rxcb; 3349 struct hal_rx_desc *rx_desc; 3350 u16 msdu_len; 3351 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3352 struct ath12k_rx_desc_info *desc_info; 3353 u64 desc_va; 3354 3355 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3356 le32_to_cpu(desc->buf_va_lo)); 3357 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3358 3359 /* retry manual desc retrieval */ 3360 if (!desc_info) { 3361 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3362 if (!desc_info) { 3363 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 3364 return -EINVAL; 3365 } 3366 } 3367 3368 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3369 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3370 3371 msdu = desc_info->skb; 3372 desc_info->skb = NULL; 3373 3374 list_add_tail(&desc_info->list, used_list); 3375 3376 rxcb = ATH12K_SKB_RXCB(msdu); 3377 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3378 msdu->len + skb_tailroom(msdu), 3379 DMA_FROM_DEVICE); 3380 3381 if (drop) { 3382 dev_kfree_skb_any(msdu); 3383 return 0; 3384 } 3385 3386 rcu_read_lock(); 3387 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3388 dev_kfree_skb_any(msdu); 3389 goto exit; 3390 } 3391 3392 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3393 dev_kfree_skb_any(msdu); 3394 goto exit; 3395 } 3396 3397 rx_desc = (struct hal_rx_desc *)msdu->data; 3398 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3399 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3400 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3401 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3402 sizeof(*rx_desc)); 3403 dev_kfree_skb_any(msdu); 3404 goto exit; 3405 } 3406 3407 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3408 3409 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3410 dev_kfree_skb_any(msdu); 3411 ath12k_dp_rx_link_desc_return(ar->ab, desc, 3412 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3413 } 3414 exit: 3415 rcu_read_unlock(); 3416 return 0; 3417 } 3418 3419 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3420 int budget) 3421 { 3422 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3423 struct dp_link_desc_bank *link_desc_banks; 3424 enum hal_rx_buf_return_buf_manager rbm; 3425 struct hal_rx_msdu_link *link_desc_va; 3426 int tot_n_bufs_reaped, quota, ret, i; 3427 struct hal_reo_dest_ring *reo_desc; 3428 struct dp_rxdma_ring *rx_ring; 3429 struct dp_srng *reo_except; 3430 LIST_HEAD(rx_desc_used_list); 3431 u32 desc_bank, num_msdus; 3432 struct hal_srng *srng; 3433 struct ath12k_dp *dp; 3434 int mac_id; 3435 struct ath12k *ar; 3436 dma_addr_t paddr; 3437 bool is_frag; 3438 bool drop = false; 3439 int pdev_id; 3440 3441 tot_n_bufs_reaped = 0; 3442 quota = budget; 3443 3444 dp = &ab->dp; 3445 reo_except = &dp->reo_except_ring; 3446 link_desc_banks = dp->link_desc_banks; 3447 3448 srng = &ab->hal.srng_list[reo_except->ring_id]; 3449 3450 spin_lock_bh(&srng->lock); 3451 3452 ath12k_hal_srng_access_begin(ab, srng); 3453 3454 while (budget && 3455 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3456 ab->soc_stats.err_ring_pkts++; 3457 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3458 &desc_bank); 3459 if (ret) { 3460 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3461 ret); 3462 continue; 3463 } 3464 link_desc_va = link_desc_banks[desc_bank].vaddr + 3465 (paddr - link_desc_banks[desc_bank].paddr); 3466 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3467 &rbm); 3468 if (rbm != HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST && 3469 rbm != HAL_RX_BUF_RBM_SW3_BM && 3470 rbm != ab->hw_params->hal_params->rx_buf_rbm) { 3471 ab->soc_stats.invalid_rbm++; 3472 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3473 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3474 HAL_WBM_REL_BM_ACT_REL_MSDU); 3475 continue; 3476 } 3477 3478 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3479 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3480 3481 /* Process only rx fragments with one msdu per link desc below, and drop 3482 * msdu's indicated due to error reasons. 3483 */ 3484 if (!is_frag || num_msdus > 1) { 3485 drop = true; 3486 /* Return the link desc back to wbm idle list */ 3487 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3488 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3489 } 3490 3491 for (i = 0; i < num_msdus; i++) { 3492 mac_id = le32_get_bits(reo_desc->info0, 3493 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3494 3495 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3496 ar = ab->pdevs[pdev_id].ar; 3497 3498 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, 3499 &rx_desc_used_list, 3500 drop, 3501 msdu_cookies[i])) 3502 tot_n_bufs_reaped++; 3503 } 3504 3505 if (tot_n_bufs_reaped >= quota) { 3506 tot_n_bufs_reaped = quota; 3507 goto exit; 3508 } 3509 3510 budget = quota - tot_n_bufs_reaped; 3511 } 3512 3513 exit: 3514 ath12k_hal_srng_access_end(ab, srng); 3515 3516 spin_unlock_bh(&srng->lock); 3517 3518 rx_ring = &dp->rx_refill_buf_ring; 3519 3520 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3521 tot_n_bufs_reaped); 3522 3523 return tot_n_bufs_reaped; 3524 } 3525 3526 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3527 int msdu_len, 3528 struct sk_buff_head *msdu_list) 3529 { 3530 struct sk_buff *skb, *tmp; 3531 struct ath12k_skb_rxcb *rxcb; 3532 int n_buffs; 3533 3534 n_buffs = DIV_ROUND_UP(msdu_len, 3535 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz)); 3536 3537 skb_queue_walk_safe(msdu_list, skb, tmp) { 3538 rxcb = ATH12K_SKB_RXCB(skb); 3539 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3540 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3541 if (!n_buffs) 3542 break; 3543 __skb_unlink(skb, msdu_list); 3544 dev_kfree_skb_any(skb); 3545 n_buffs--; 3546 } 3547 } 3548 } 3549 3550 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 3551 struct ieee80211_rx_status *status, 3552 struct sk_buff_head *msdu_list) 3553 { 3554 struct ath12k_base *ab = ar->ab; 3555 u16 msdu_len; 3556 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3557 u8 l3pad_bytes; 3558 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3559 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3560 3561 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3562 3563 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3564 /* First buffer will be freed by the caller, so deduct it's length */ 3565 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3566 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3567 return -EINVAL; 3568 } 3569 3570 /* Even after cleaning up the sg buffers in the msdu list with above check 3571 * any msdu received with continuation flag needs to be dropped as invalid. 3572 * This protects against some random err frame with continuation flag. 3573 */ 3574 if (rxcb->is_continuation) 3575 return -EINVAL; 3576 3577 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 3578 ath12k_warn(ar->ab, 3579 "msdu_done bit not set in null_q_des processing\n"); 3580 __skb_queue_purge(msdu_list); 3581 return -EIO; 3582 } 3583 3584 /* Handle NULL queue descriptor violations arising out a missing 3585 * REO queue for a given peer or a given TID. This typically 3586 * may happen if a packet is received on a QOS enabled TID before the 3587 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3588 * it may also happen for MC/BC frames if they are not routed to the 3589 * non-QOS TID queue, in the absence of any other default TID queue. 3590 * This error can show up both in a REO destination or WBM release ring. 3591 */ 3592 3593 if (rxcb->is_frag) { 3594 skb_pull(msdu, hal_rx_desc_sz); 3595 } else { 3596 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3597 3598 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3599 return -EINVAL; 3600 3601 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3602 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3603 } 3604 ath12k_dp_rx_h_ppdu(ar, desc, status); 3605 3606 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status); 3607 3608 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc); 3609 3610 /* Please note that caller will having the access to msdu and completing 3611 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3612 */ 3613 3614 return 0; 3615 } 3616 3617 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 3618 struct ieee80211_rx_status *status, 3619 struct sk_buff_head *msdu_list) 3620 { 3621 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3622 bool drop = false; 3623 3624 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3625 3626 switch (rxcb->err_code) { 3627 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3628 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3629 drop = true; 3630 break; 3631 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3632 /* TODO: Do not drop PN failed packets in the driver; 3633 * instead, it is good to drop such packets in mac80211 3634 * after incrementing the replay counters. 3635 */ 3636 fallthrough; 3637 default: 3638 /* TODO: Review other errors and process them to mac80211 3639 * as appropriate. 3640 */ 3641 drop = true; 3642 break; 3643 } 3644 3645 return drop; 3646 } 3647 3648 static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 3649 struct ieee80211_rx_status *status) 3650 { 3651 struct ath12k_base *ab = ar->ab; 3652 u16 msdu_len; 3653 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3654 u8 l3pad_bytes; 3655 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3656 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3657 3658 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 3659 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 3660 3661 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3662 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3663 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3664 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3665 3666 ath12k_dp_rx_h_ppdu(ar, desc, status); 3667 3668 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3669 RX_FLAG_DECRYPTED); 3670 3671 ath12k_dp_rx_h_undecap(ar, msdu, desc, 3672 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3673 } 3674 3675 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 3676 struct ieee80211_rx_status *status) 3677 { 3678 struct ath12k_base *ab = ar->ab; 3679 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3680 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3681 bool drop = false; 3682 u32 err_bitmap; 3683 3684 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3685 3686 switch (rxcb->err_code) { 3687 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 3688 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3689 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 3690 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 3691 ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3692 break; 3693 } 3694 fallthrough; 3695 default: 3696 /* TODO: Review other rxdma error code to check if anything is 3697 * worth reporting to mac80211 3698 */ 3699 drop = true; 3700 break; 3701 } 3702 3703 return drop; 3704 } 3705 3706 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 3707 struct napi_struct *napi, 3708 struct sk_buff *msdu, 3709 struct sk_buff_head *msdu_list) 3710 { 3711 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3712 struct ieee80211_rx_status rxs = {0}; 3713 bool drop = true; 3714 3715 switch (rxcb->err_rel_src) { 3716 case HAL_WBM_REL_SRC_MODULE_REO: 3717 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3718 break; 3719 case HAL_WBM_REL_SRC_MODULE_RXDMA: 3720 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3721 break; 3722 default: 3723 /* msdu will get freed */ 3724 break; 3725 } 3726 3727 if (drop) { 3728 dev_kfree_skb_any(msdu); 3729 return; 3730 } 3731 3732 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 3733 } 3734 3735 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 3736 struct napi_struct *napi, int budget) 3737 { 3738 LIST_HEAD(rx_desc_used_list); 3739 struct ath12k *ar; 3740 struct ath12k_dp *dp = &ab->dp; 3741 struct dp_rxdma_ring *rx_ring; 3742 struct hal_rx_wbm_rel_info err_info; 3743 struct hal_srng *srng; 3744 struct sk_buff *msdu; 3745 struct sk_buff_head msdu_list; 3746 struct ath12k_skb_rxcb *rxcb; 3747 void *rx_desc; 3748 u8 mac_id; 3749 int num_buffs_reaped = 0; 3750 struct ath12k_rx_desc_info *desc_info; 3751 int ret, pdev_id; 3752 3753 __skb_queue_head_init(&msdu_list); 3754 3755 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3756 rx_ring = &dp->rx_refill_buf_ring; 3757 3758 spin_lock_bh(&srng->lock); 3759 3760 ath12k_hal_srng_access_begin(ab, srng); 3761 3762 while (budget) { 3763 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 3764 if (!rx_desc) 3765 break; 3766 3767 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3768 if (ret) { 3769 ath12k_warn(ab, 3770 "failed to parse rx error in wbm_rel ring desc %d\n", 3771 ret); 3772 continue; 3773 } 3774 3775 desc_info = err_info.rx_desc; 3776 3777 /* retry manual desc retrieval if hw cc is not done */ 3778 if (!desc_info) { 3779 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 3780 if (!desc_info) { 3781 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 3782 continue; 3783 } 3784 } 3785 3786 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3787 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 3788 3789 msdu = desc_info->skb; 3790 desc_info->skb = NULL; 3791 3792 list_add_tail(&desc_info->list, &rx_desc_used_list); 3793 3794 rxcb = ATH12K_SKB_RXCB(msdu); 3795 dma_unmap_single(ab->dev, rxcb->paddr, 3796 msdu->len + skb_tailroom(msdu), 3797 DMA_FROM_DEVICE); 3798 3799 num_buffs_reaped++; 3800 3801 if (!err_info.continuation) 3802 budget--; 3803 3804 if (err_info.push_reason != 3805 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3806 dev_kfree_skb_any(msdu); 3807 continue; 3808 } 3809 3810 rxcb->err_rel_src = err_info.err_rel_src; 3811 rxcb->err_code = err_info.err_code; 3812 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 3813 3814 __skb_queue_tail(&msdu_list, msdu); 3815 3816 rxcb->is_first_msdu = err_info.first_msdu; 3817 rxcb->is_last_msdu = err_info.last_msdu; 3818 rxcb->is_continuation = err_info.continuation; 3819 } 3820 3821 ath12k_hal_srng_access_end(ab, srng); 3822 3823 spin_unlock_bh(&srng->lock); 3824 3825 if (!num_buffs_reaped) 3826 goto done; 3827 3828 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3829 num_buffs_reaped); 3830 3831 rcu_read_lock(); 3832 while ((msdu = __skb_dequeue(&msdu_list))) { 3833 mac_id = ath12k_dp_rx_get_msdu_src_link(ab, 3834 (struct hal_rx_desc *)msdu->data); 3835 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3836 ar = ab->pdevs[pdev_id].ar; 3837 3838 if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) { 3839 dev_kfree_skb_any(msdu); 3840 continue; 3841 } 3842 3843 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3844 dev_kfree_skb_any(msdu); 3845 continue; 3846 } 3847 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); 3848 } 3849 rcu_read_unlock(); 3850 done: 3851 return num_buffs_reaped; 3852 } 3853 3854 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 3855 { 3856 struct ath12k_dp *dp = &ab->dp; 3857 struct hal_tlv_64_hdr *hdr; 3858 struct hal_srng *srng; 3859 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 3860 bool found = false; 3861 u16 tag; 3862 struct hal_reo_status reo_status; 3863 3864 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 3865 3866 memset(&reo_status, 0, sizeof(reo_status)); 3867 3868 spin_lock_bh(&srng->lock); 3869 3870 ath12k_hal_srng_access_begin(ab, srng); 3871 3872 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3873 tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 3874 3875 switch (tag) { 3876 case HAL_REO_GET_QUEUE_STATS_STATUS: 3877 ath12k_hal_reo_status_queue_stats(ab, hdr, 3878 &reo_status); 3879 break; 3880 case HAL_REO_FLUSH_QUEUE_STATUS: 3881 ath12k_hal_reo_flush_queue_status(ab, hdr, 3882 &reo_status); 3883 break; 3884 case HAL_REO_FLUSH_CACHE_STATUS: 3885 ath12k_hal_reo_flush_cache_status(ab, hdr, 3886 &reo_status); 3887 break; 3888 case HAL_REO_UNBLOCK_CACHE_STATUS: 3889 ath12k_hal_reo_unblk_cache_status(ab, hdr, 3890 &reo_status); 3891 break; 3892 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 3893 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 3894 &reo_status); 3895 break; 3896 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 3897 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 3898 &reo_status); 3899 break; 3900 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 3901 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 3902 &reo_status); 3903 break; 3904 default: 3905 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 3906 continue; 3907 } 3908 3909 spin_lock_bh(&dp->reo_cmd_lock); 3910 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 3911 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 3912 found = true; 3913 list_del(&cmd->list); 3914 break; 3915 } 3916 } 3917 spin_unlock_bh(&dp->reo_cmd_lock); 3918 3919 if (found) { 3920 cmd->handler(dp, (void *)&cmd->data, 3921 reo_status.uniform_hdr.cmd_status); 3922 kfree(cmd); 3923 } 3924 3925 found = false; 3926 } 3927 3928 ath12k_hal_srng_access_end(ab, srng); 3929 3930 spin_unlock_bh(&srng->lock); 3931 } 3932 3933 void ath12k_dp_rx_free(struct ath12k_base *ab) 3934 { 3935 struct ath12k_dp *dp = &ab->dp; 3936 int i; 3937 3938 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 3939 3940 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 3941 if (ab->hw_params->rx_mac_buf_ring) 3942 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 3943 } 3944 3945 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 3946 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 3947 3948 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 3949 ath12k_dp_srng_cleanup(ab, &dp->tx_mon_buf_ring.refill_buf_ring); 3950 3951 ath12k_dp_rxdma_buf_free(ab); 3952 } 3953 3954 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 3955 { 3956 struct ath12k *ar = ab->pdevs[mac_id].ar; 3957 3958 ath12k_dp_rx_pdev_srng_free(ar); 3959 } 3960 3961 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 3962 { 3963 struct ath12k_dp *dp = &ab->dp; 3964 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 3965 u32 ring_id; 3966 int ret; 3967 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3968 3969 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 3970 3971 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 3972 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 3973 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 3974 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 3975 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 3976 tlv_filter.offset_valid = true; 3977 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 3978 3979 tlv_filter.rx_mpdu_start_offset = 3980 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 3981 tlv_filter.rx_msdu_end_offset = 3982 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 3983 3984 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 3985 tlv_filter.rx_mpdu_start_wmask = 3986 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); 3987 tlv_filter.rx_msdu_end_wmask = 3988 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); 3989 ath12k_dbg(ab, ATH12K_DBG_DATA, 3990 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", 3991 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); 3992 } 3993 3994 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 3995 HAL_RXDMA_BUF, 3996 DP_RXDMA_REFILL_RING_SIZE, 3997 &tlv_filter); 3998 3999 return ret; 4000 } 4001 4002 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 4003 { 4004 struct ath12k_dp *dp = &ab->dp; 4005 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4006 u32 ring_id; 4007 int ret; 4008 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4009 int i; 4010 4011 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4012 4013 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4014 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4015 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4016 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4017 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4018 tlv_filter.offset_valid = true; 4019 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4020 4021 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4022 4023 tlv_filter.rx_mpdu_start_offset = 4024 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4025 tlv_filter.rx_msdu_end_offset = 4026 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4027 4028 /* TODO: Selectively subscribe to required qwords within msdu_end 4029 * and mpdu_start and setup the mask in below msg 4030 * and modify the rx_desc struct 4031 */ 4032 4033 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4034 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4035 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4036 HAL_RXDMA_BUF, 4037 DP_RXDMA_REFILL_RING_SIZE, 4038 &tlv_filter); 4039 } 4040 4041 return ret; 4042 } 4043 4044 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4045 { 4046 struct ath12k_dp *dp = &ab->dp; 4047 u32 ring_id; 4048 int i, ret; 4049 4050 /* TODO: Need to verify the HTT setup for QCN9224 */ 4051 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4052 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4053 if (ret) { 4054 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4055 ret); 4056 return ret; 4057 } 4058 4059 if (ab->hw_params->rx_mac_buf_ring) { 4060 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4061 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4062 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4063 i, HAL_RXDMA_BUF); 4064 if (ret) { 4065 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4066 i, ret); 4067 return ret; 4068 } 4069 } 4070 } 4071 4072 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4073 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4074 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4075 i, HAL_RXDMA_DST); 4076 if (ret) { 4077 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4078 i, ret); 4079 return ret; 4080 } 4081 } 4082 4083 if (ab->hw_params->rxdma1_enable) { 4084 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4085 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4086 0, HAL_RXDMA_MONITOR_BUF); 4087 if (ret) { 4088 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4089 ret); 4090 return ret; 4091 } 4092 4093 ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; 4094 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4095 0, HAL_TX_MONITOR_BUF); 4096 if (ret) { 4097 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4098 ret); 4099 return ret; 4100 } 4101 } 4102 4103 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4104 if (ret) { 4105 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4106 return ret; 4107 } 4108 4109 return 0; 4110 } 4111 4112 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4113 { 4114 struct ath12k_dp *dp = &ab->dp; 4115 int i, ret; 4116 4117 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4118 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4119 4120 idr_init(&dp->tx_mon_buf_ring.bufs_idr); 4121 spin_lock_init(&dp->tx_mon_buf_ring.idr_lock); 4122 4123 ret = ath12k_dp_srng_setup(ab, 4124 &dp->rx_refill_buf_ring.refill_buf_ring, 4125 HAL_RXDMA_BUF, 0, 0, 4126 DP_RXDMA_BUF_RING_SIZE); 4127 if (ret) { 4128 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4129 return ret; 4130 } 4131 4132 if (ab->hw_params->rx_mac_buf_ring) { 4133 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4134 ret = ath12k_dp_srng_setup(ab, 4135 &dp->rx_mac_buf_ring[i], 4136 HAL_RXDMA_BUF, 1, 4137 i, DP_RX_MAC_BUF_RING_SIZE); 4138 if (ret) { 4139 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4140 i); 4141 return ret; 4142 } 4143 } 4144 } 4145 4146 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4147 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4148 HAL_RXDMA_DST, 0, i, 4149 DP_RXDMA_ERR_DST_RING_SIZE); 4150 if (ret) { 4151 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4152 return ret; 4153 } 4154 } 4155 4156 if (ab->hw_params->rxdma1_enable) { 4157 ret = ath12k_dp_srng_setup(ab, 4158 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4159 HAL_RXDMA_MONITOR_BUF, 0, 0, 4160 DP_RXDMA_MONITOR_BUF_RING_SIZE); 4161 if (ret) { 4162 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4163 return ret; 4164 } 4165 4166 ret = ath12k_dp_srng_setup(ab, 4167 &dp->tx_mon_buf_ring.refill_buf_ring, 4168 HAL_TX_MONITOR_BUF, 0, 0, 4169 DP_TX_MONITOR_BUF_RING_SIZE); 4170 if (ret) { 4171 ath12k_warn(ab, "failed to setup DP_TX_MONITOR_BUF_RING_SIZE\n"); 4172 return ret; 4173 } 4174 } 4175 4176 ret = ath12k_dp_rxdma_buf_setup(ab); 4177 if (ret) { 4178 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4179 return ret; 4180 } 4181 4182 return 0; 4183 } 4184 4185 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4186 { 4187 struct ath12k *ar = ab->pdevs[mac_id].ar; 4188 struct ath12k_pdev_dp *dp = &ar->dp; 4189 u32 ring_id; 4190 int i; 4191 int ret; 4192 4193 if (!ab->hw_params->rxdma1_enable) 4194 goto out; 4195 4196 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4197 if (ret) { 4198 ath12k_warn(ab, "failed to setup rx srngs\n"); 4199 return ret; 4200 } 4201 4202 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4203 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4204 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4205 mac_id + i, 4206 HAL_RXDMA_MONITOR_DST); 4207 if (ret) { 4208 ath12k_warn(ab, 4209 "failed to configure rxdma_mon_dst_ring %d %d\n", 4210 i, ret); 4211 return ret; 4212 } 4213 4214 ring_id = dp->tx_mon_dst_ring[i].ring_id; 4215 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4216 mac_id + i, 4217 HAL_TX_MONITOR_DST); 4218 if (ret) { 4219 ath12k_warn(ab, 4220 "failed to configure tx_mon_dst_ring %d %d\n", 4221 i, ret); 4222 return ret; 4223 } 4224 } 4225 out: 4226 return 0; 4227 } 4228 4229 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4230 { 4231 struct ath12k_pdev_dp *dp = &ar->dp; 4232 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4233 4234 skb_queue_head_init(&pmon->rx_status_q); 4235 4236 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4237 4238 memset(&pmon->rx_mon_stats, 0, 4239 sizeof(pmon->rx_mon_stats)); 4240 return 0; 4241 } 4242 4243 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4244 { 4245 struct ath12k_pdev_dp *dp = &ar->dp; 4246 struct ath12k_mon_data *pmon = &dp->mon_data; 4247 int ret = 0; 4248 4249 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4250 if (ret) { 4251 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4252 return ret; 4253 } 4254 4255 /* if rxdma1_enable is false, no need to setup 4256 * rxdma_mon_desc_ring. 4257 */ 4258 if (!ar->ab->hw_params->rxdma1_enable) 4259 return 0; 4260 4261 pmon->mon_last_linkdesc_paddr = 0; 4262 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4263 spin_lock_init(&pmon->mon_lock); 4264 4265 return 0; 4266 } 4267 4268 int ath12k_dp_rx_pktlog_start(struct ath12k_base *ab) 4269 { 4270 /* start reap timer */ 4271 mod_timer(&ab->mon_reap_timer, 4272 jiffies + msecs_to_jiffies(ATH12K_MON_TIMER_INTERVAL)); 4273 4274 return 0; 4275 } 4276 4277 int ath12k_dp_rx_pktlog_stop(struct ath12k_base *ab, bool stop_timer) 4278 { 4279 int ret; 4280 4281 if (stop_timer) 4282 del_timer_sync(&ab->mon_reap_timer); 4283 4284 /* reap all the monitor related rings */ 4285 ret = ath12k_dp_purge_mon_ring(ab); 4286 if (ret) { 4287 ath12k_warn(ab, "failed to purge dp mon ring: %d\n", ret); 4288 return ret; 4289 } 4290 4291 return 0; 4292 } 4293