1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 #include "debugfs_htt_stats.h" 21 22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 23 24 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 25 struct hal_rx_desc *desc) 26 { 27 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) 28 return HAL_ENCRYPT_TYPE_OPEN; 29 30 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); 31 } 32 33 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 34 struct hal_rx_desc *desc) 35 { 36 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); 37 } 38 39 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 40 struct hal_rx_desc *desc) 41 { 42 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); 43 } 44 45 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 46 struct hal_rx_desc *desc) 47 { 48 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 49 } 50 51 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 52 struct hal_rx_desc *desc) 53 { 54 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); 55 } 56 57 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 58 struct sk_buff *skb) 59 { 60 struct ieee80211_hdr *hdr; 61 62 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 63 return ieee80211_has_morefrags(hdr->frame_control); 64 } 65 66 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 67 struct sk_buff *skb) 68 { 69 struct ieee80211_hdr *hdr; 70 71 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 72 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 73 } 74 75 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 76 struct hal_rx_desc *desc) 77 { 78 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc); 79 } 80 81 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 82 struct hal_rx_desc *desc) 83 { 84 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc); 85 } 86 87 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 88 struct hal_rx_desc *desc) 89 { 90 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc); 91 } 92 93 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 94 struct hal_rx_desc *desc) 95 { 96 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc); 97 } 98 99 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 100 struct hal_rx_desc *desc) 101 { 102 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc); 103 } 104 105 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 106 struct hal_rx_desc *desc) 107 { 108 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc); 109 } 110 111 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 112 struct hal_rx_desc *desc) 113 { 114 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc); 115 } 116 117 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 118 struct hal_rx_desc *desc) 119 { 120 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc); 121 } 122 123 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 124 struct hal_rx_desc *desc) 125 { 126 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc); 127 } 128 129 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 130 struct hal_rx_desc *desc) 131 { 132 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc); 133 } 134 135 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 136 struct hal_rx_desc *desc) 137 { 138 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc); 139 } 140 141 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 142 struct hal_rx_desc *desc) 143 { 144 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc); 145 } 146 147 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 148 struct hal_rx_desc *desc) 149 { 150 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc)); 151 } 152 153 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 154 struct hal_rx_desc *desc) 155 { 156 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc); 157 } 158 159 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 160 struct hal_rx_desc *desc) 161 { 162 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc); 163 } 164 165 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 166 struct hal_rx_desc *desc) 167 { 168 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc); 169 } 170 171 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 172 struct hal_rx_desc *desc) 173 { 174 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc); 175 } 176 177 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 178 struct hal_rx_desc *desc) 179 { 180 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc); 181 } 182 183 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 184 struct hal_rx_desc *fdesc, 185 struct hal_rx_desc *ldesc) 186 { 187 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 188 } 189 190 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 191 struct hal_rx_desc *desc, 192 u16 len) 193 { 194 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len); 195 } 196 197 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 198 struct hal_rx_desc *desc) 199 { 200 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 201 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc)); 202 } 203 204 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 205 struct hal_rx_desc *desc) 206 { 207 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc); 208 } 209 210 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 211 struct hal_rx_desc *desc) 212 { 213 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc); 214 } 215 216 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 217 struct hal_rx_desc *desc, 218 struct ieee80211_hdr *hdr) 219 { 220 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr); 221 } 222 223 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 224 struct hal_rx_desc *desc, 225 u8 *crypto_hdr, 226 enum hal_encrypt_type enctype) 227 { 228 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 229 } 230 231 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab, 232 struct hal_rx_desc *desc) 233 { 234 return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc); 235 } 236 237 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, 238 struct hal_rx_desc *desc) 239 { 240 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc); 241 } 242 243 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list) 244 { 245 struct sk_buff *skb; 246 247 while ((skb = __skb_dequeue(skb_list))) 248 dev_kfree_skb_any(skb); 249 } 250 251 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 252 struct list_head *head, 253 size_t count) 254 { 255 struct list_head *cur; 256 struct ath12k_rx_desc_info *rx_desc; 257 size_t nodes = 0; 258 259 if (!count) { 260 INIT_LIST_HEAD(list); 261 goto out; 262 } 263 264 list_for_each(cur, head) { 265 if (!count) 266 break; 267 268 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 269 rx_desc->in_use = true; 270 271 count--; 272 nodes++; 273 } 274 275 list_cut_before(list, head, cur); 276 out: 277 return nodes; 278 } 279 280 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 281 struct list_head *used_list) 282 { 283 struct ath12k_rx_desc_info *rx_desc, *safe; 284 285 /* Reset the use flag */ 286 list_for_each_entry_safe(rx_desc, safe, used_list, list) 287 rx_desc->in_use = false; 288 289 spin_lock_bh(&dp->rx_desc_lock); 290 list_splice_tail(used_list, &dp->rx_desc_free_list); 291 spin_unlock_bh(&dp->rx_desc_lock); 292 } 293 294 /* Returns number of Rx buffers replenished */ 295 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, 296 struct dp_rxdma_ring *rx_ring, 297 struct list_head *used_list, 298 int req_entries) 299 { 300 struct ath12k_buffer_addr *desc; 301 struct hal_srng *srng; 302 struct sk_buff *skb; 303 int num_free; 304 int num_remain; 305 u32 cookie; 306 dma_addr_t paddr; 307 struct ath12k_dp *dp = &ab->dp; 308 struct ath12k_rx_desc_info *rx_desc; 309 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; 310 311 req_entries = min(req_entries, rx_ring->bufs_max); 312 313 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 314 315 spin_lock_bh(&srng->lock); 316 317 ath12k_hal_srng_access_begin(ab, srng); 318 319 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 320 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 321 req_entries = num_free; 322 323 req_entries = min(num_free, req_entries); 324 num_remain = req_entries; 325 326 if (!num_remain) 327 goto out; 328 329 /* Get the descriptor from free list */ 330 if (list_empty(used_list)) { 331 spin_lock_bh(&dp->rx_desc_lock); 332 req_entries = ath12k_dp_list_cut_nodes(used_list, 333 &dp->rx_desc_free_list, 334 num_remain); 335 spin_unlock_bh(&dp->rx_desc_lock); 336 num_remain = req_entries; 337 } 338 339 while (num_remain > 0) { 340 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 341 DP_RX_BUFFER_ALIGN_SIZE); 342 if (!skb) 343 break; 344 345 if (!IS_ALIGNED((unsigned long)skb->data, 346 DP_RX_BUFFER_ALIGN_SIZE)) { 347 skb_pull(skb, 348 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 349 skb->data); 350 } 351 352 paddr = dma_map_single(ab->dev, skb->data, 353 skb->len + skb_tailroom(skb), 354 DMA_FROM_DEVICE); 355 if (dma_mapping_error(ab->dev, paddr)) 356 goto fail_free_skb; 357 358 rx_desc = list_first_entry_or_null(used_list, 359 struct ath12k_rx_desc_info, 360 list); 361 if (!rx_desc) 362 goto fail_dma_unmap; 363 364 rx_desc->skb = skb; 365 cookie = rx_desc->cookie; 366 367 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 368 if (!desc) 369 goto fail_dma_unmap; 370 371 list_del(&rx_desc->list); 372 ATH12K_SKB_RXCB(skb)->paddr = paddr; 373 374 num_remain--; 375 376 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 377 } 378 379 goto out; 380 381 fail_dma_unmap: 382 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 383 DMA_FROM_DEVICE); 384 fail_free_skb: 385 dev_kfree_skb_any(skb); 386 out: 387 ath12k_hal_srng_access_end(ab, srng); 388 389 if (!list_empty(used_list)) 390 ath12k_dp_rx_enqueue_free(dp, used_list); 391 392 spin_unlock_bh(&srng->lock); 393 394 return req_entries - num_remain; 395 } 396 397 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 398 struct dp_rxdma_mon_ring *rx_ring) 399 { 400 struct sk_buff *skb; 401 int buf_id; 402 403 spin_lock_bh(&rx_ring->idr_lock); 404 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 405 idr_remove(&rx_ring->bufs_idr, buf_id); 406 /* TODO: Understand where internal driver does this dma_unmap 407 * of rxdma_buffer. 408 */ 409 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 410 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 411 dev_kfree_skb_any(skb); 412 } 413 414 idr_destroy(&rx_ring->bufs_idr); 415 spin_unlock_bh(&rx_ring->idr_lock); 416 417 return 0; 418 } 419 420 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 421 { 422 struct ath12k_dp *dp = &ab->dp; 423 424 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 425 426 return 0; 427 } 428 429 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 430 struct dp_rxdma_mon_ring *rx_ring, 431 u32 ringtype) 432 { 433 int num_entries; 434 435 num_entries = rx_ring->refill_buf_ring.size / 436 ath12k_hal_srng_get_entrysize(ab, ringtype); 437 438 rx_ring->bufs_max = num_entries; 439 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 440 441 return 0; 442 } 443 444 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 445 struct dp_rxdma_ring *rx_ring) 446 { 447 LIST_HEAD(list); 448 449 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 450 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 451 452 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 453 454 return 0; 455 } 456 457 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 458 { 459 struct ath12k_dp *dp = &ab->dp; 460 int ret; 461 462 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 463 if (ret) { 464 ath12k_warn(ab, 465 "failed to setup HAL_RXDMA_BUF\n"); 466 return ret; 467 } 468 469 if (ab->hw_params->rxdma1_enable) { 470 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 471 &dp->rxdma_mon_buf_ring, 472 HAL_RXDMA_MONITOR_BUF); 473 if (ret) { 474 ath12k_warn(ab, 475 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 476 return ret; 477 } 478 } 479 480 return 0; 481 } 482 483 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 484 { 485 struct ath12k_pdev_dp *dp = &ar->dp; 486 struct ath12k_base *ab = ar->ab; 487 int i; 488 489 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 490 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 491 } 492 493 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 494 { 495 struct ath12k_dp *dp = &ab->dp; 496 int i; 497 498 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 499 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 500 } 501 502 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 503 { 504 struct ath12k_dp *dp = &ab->dp; 505 int ret; 506 int i; 507 508 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 509 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 510 HAL_REO_DST, i, 0, 511 DP_REO_DST_RING_SIZE); 512 if (ret) { 513 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 514 goto err_reo_cleanup; 515 } 516 } 517 518 return 0; 519 520 err_reo_cleanup: 521 ath12k_dp_rx_pdev_reo_cleanup(ab); 522 523 return ret; 524 } 525 526 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 527 { 528 struct ath12k_pdev_dp *dp = &ar->dp; 529 struct ath12k_base *ab = ar->ab; 530 int i; 531 int ret; 532 u32 mac_id = dp->mac_id; 533 534 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 535 ret = ath12k_dp_srng_setup(ar->ab, 536 &dp->rxdma_mon_dst_ring[i], 537 HAL_RXDMA_MONITOR_DST, 538 0, mac_id + i, 539 DP_RXDMA_MONITOR_DST_RING_SIZE); 540 if (ret) { 541 ath12k_warn(ar->ab, 542 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 543 return ret; 544 } 545 } 546 547 return 0; 548 } 549 550 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 551 { 552 struct ath12k_dp *dp = &ab->dp; 553 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 554 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 555 556 spin_lock_bh(&dp->reo_cmd_lock); 557 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 558 list_del(&cmd->list); 559 dma_unmap_single(ab->dev, cmd->data.paddr, 560 cmd->data.size, DMA_BIDIRECTIONAL); 561 kfree(cmd->data.vaddr); 562 kfree(cmd); 563 } 564 565 list_for_each_entry_safe(cmd_cache, tmp_cache, 566 &dp->reo_cmd_cache_flush_list, list) { 567 list_del(&cmd_cache->list); 568 dp->reo_cmd_cache_flush_count--; 569 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 570 cmd_cache->data.size, DMA_BIDIRECTIONAL); 571 kfree(cmd_cache->data.vaddr); 572 kfree(cmd_cache); 573 } 574 spin_unlock_bh(&dp->reo_cmd_lock); 575 } 576 577 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 578 enum hal_reo_cmd_status status) 579 { 580 struct ath12k_dp_rx_tid *rx_tid = ctx; 581 582 if (status != HAL_REO_CMD_SUCCESS) 583 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 584 rx_tid->tid, status); 585 586 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 587 DMA_BIDIRECTIONAL); 588 kfree(rx_tid->vaddr); 589 rx_tid->vaddr = NULL; 590 } 591 592 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 593 enum hal_reo_cmd_type type, 594 struct ath12k_hal_reo_cmd *cmd, 595 void (*cb)(struct ath12k_dp *dp, void *ctx, 596 enum hal_reo_cmd_status status)) 597 { 598 struct ath12k_dp *dp = &ab->dp; 599 struct ath12k_dp_rx_reo_cmd *dp_cmd; 600 struct hal_srng *cmd_ring; 601 int cmd_num; 602 603 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 604 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 605 606 /* cmd_num should start from 1, during failure return the error code */ 607 if (cmd_num < 0) 608 return cmd_num; 609 610 /* reo cmd ring descriptors has cmd_num starting from 1 */ 611 if (cmd_num == 0) 612 return -EINVAL; 613 614 if (!cb) 615 return 0; 616 617 /* Can this be optimized so that we keep the pending command list only 618 * for tid delete command to free up the resource on the command status 619 * indication? 620 */ 621 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 622 623 if (!dp_cmd) 624 return -ENOMEM; 625 626 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 627 dp_cmd->cmd_num = cmd_num; 628 dp_cmd->handler = cb; 629 630 spin_lock_bh(&dp->reo_cmd_lock); 631 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 632 spin_unlock_bh(&dp->reo_cmd_lock); 633 634 return 0; 635 } 636 637 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 638 struct ath12k_dp_rx_tid *rx_tid) 639 { 640 struct ath12k_hal_reo_cmd cmd = {0}; 641 unsigned long tot_desc_sz, desc_sz; 642 int ret; 643 644 tot_desc_sz = rx_tid->size; 645 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 646 647 while (tot_desc_sz > desc_sz) { 648 tot_desc_sz -= desc_sz; 649 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 650 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 651 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 652 HAL_REO_CMD_FLUSH_CACHE, &cmd, 653 NULL); 654 if (ret) 655 ath12k_warn(ab, 656 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 657 rx_tid->tid, ret); 658 } 659 660 memset(&cmd, 0, sizeof(cmd)); 661 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 662 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 663 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 664 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 665 HAL_REO_CMD_FLUSH_CACHE, 666 &cmd, ath12k_dp_reo_cmd_free); 667 if (ret) { 668 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 669 rx_tid->tid, ret); 670 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 671 DMA_BIDIRECTIONAL); 672 kfree(rx_tid->vaddr); 673 rx_tid->vaddr = NULL; 674 } 675 } 676 677 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 678 enum hal_reo_cmd_status status) 679 { 680 struct ath12k_base *ab = dp->ab; 681 struct ath12k_dp_rx_tid *rx_tid = ctx; 682 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 683 684 if (status == HAL_REO_CMD_DRAIN) { 685 goto free_desc; 686 } else if (status != HAL_REO_CMD_SUCCESS) { 687 /* Shouldn't happen! Cleanup in case of other failure? */ 688 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 689 rx_tid->tid, status); 690 return; 691 } 692 693 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 694 if (!elem) 695 goto free_desc; 696 697 elem->ts = jiffies; 698 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 699 700 spin_lock_bh(&dp->reo_cmd_lock); 701 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 702 dp->reo_cmd_cache_flush_count++; 703 704 /* Flush and invalidate aged REO desc from HW cache */ 705 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 706 list) { 707 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 708 time_after(jiffies, elem->ts + 709 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 710 list_del(&elem->list); 711 dp->reo_cmd_cache_flush_count--; 712 713 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 714 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 715 * is used in only two contexts, one is in this function called 716 * from napi and the other in ath12k_dp_free during core destroy. 717 * Before dp_free, the irqs would be disabled and would wait to 718 * synchronize. Hence there wouldn’t be any race against add or 719 * delete to this list. Hence unlock-lock is safe here. 720 */ 721 spin_unlock_bh(&dp->reo_cmd_lock); 722 723 ath12k_dp_reo_cache_flush(ab, &elem->data); 724 kfree(elem); 725 spin_lock_bh(&dp->reo_cmd_lock); 726 } 727 } 728 spin_unlock_bh(&dp->reo_cmd_lock); 729 730 return; 731 free_desc: 732 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 733 DMA_BIDIRECTIONAL); 734 kfree(rx_tid->vaddr); 735 rx_tid->vaddr = NULL; 736 } 737 738 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 739 dma_addr_t paddr) 740 { 741 struct ath12k_reo_queue_ref *qref; 742 struct ath12k_dp *dp = &ab->dp; 743 bool ml_peer = false; 744 745 if (!ab->hw_params->reoq_lut_support) 746 return; 747 748 if (peer_id & ATH12K_PEER_ML_ID_VALID) { 749 peer_id &= ~ATH12K_PEER_ML_ID_VALID; 750 ml_peer = true; 751 } 752 753 if (ml_peer) 754 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 755 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 756 else 757 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 758 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 759 760 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 761 BUFFER_ADDR_INFO0_ADDR); 762 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 763 BUFFER_ADDR_INFO1_ADDR) | 764 u32_encode_bits(tid, DP_REO_QREF_NUM); 765 } 766 767 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 768 { 769 struct ath12k_reo_queue_ref *qref; 770 struct ath12k_dp *dp = &ab->dp; 771 bool ml_peer = false; 772 773 if (!ab->hw_params->reoq_lut_support) 774 return; 775 776 if (peer_id & ATH12K_PEER_ML_ID_VALID) { 777 peer_id &= ~ATH12K_PEER_ML_ID_VALID; 778 ml_peer = true; 779 } 780 781 if (ml_peer) 782 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 783 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 784 else 785 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 786 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 787 788 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 789 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 790 u32_encode_bits(tid, DP_REO_QREF_NUM); 791 } 792 793 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 794 struct ath12k_peer *peer, u8 tid) 795 { 796 struct ath12k_hal_reo_cmd cmd = {0}; 797 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 798 int ret; 799 800 if (!rx_tid->active) 801 return; 802 803 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 804 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 805 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 806 cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 807 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 808 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 809 ath12k_dp_rx_tid_del_func); 810 if (ret) { 811 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 812 tid, ret); 813 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 814 DMA_BIDIRECTIONAL); 815 kfree(rx_tid->vaddr); 816 rx_tid->vaddr = NULL; 817 } 818 819 if (peer->mlo) 820 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->ml_id, tid); 821 else 822 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 823 824 rx_tid->active = false; 825 } 826 827 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted 828 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind 829 * that. 830 */ 831 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 832 struct hal_reo_dest_ring *ring, 833 enum hal_wbm_rel_bm_act action) 834 { 835 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring; 836 struct hal_wbm_release_ring *desc; 837 struct ath12k_dp *dp = &ab->dp; 838 struct hal_srng *srng; 839 int ret = 0; 840 841 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 842 843 spin_lock_bh(&srng->lock); 844 845 ath12k_hal_srng_access_begin(ab, srng); 846 847 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 848 if (!desc) { 849 ret = -ENOBUFS; 850 goto exit; 851 } 852 853 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action); 854 855 exit: 856 ath12k_hal_srng_access_end(ab, srng); 857 858 spin_unlock_bh(&srng->lock); 859 860 return ret; 861 } 862 863 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 864 bool rel_link_desc) 865 { 866 struct ath12k_base *ab = rx_tid->ab; 867 868 lockdep_assert_held(&ab->base_lock); 869 870 if (rx_tid->dst_ring_desc) { 871 if (rel_link_desc) 872 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc, 873 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 874 kfree(rx_tid->dst_ring_desc); 875 rx_tid->dst_ring_desc = NULL; 876 } 877 878 rx_tid->cur_sn = 0; 879 rx_tid->last_frag_no = 0; 880 rx_tid->rx_frag_bitmap = 0; 881 __skb_queue_purge(&rx_tid->rx_frags); 882 } 883 884 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 885 { 886 struct ath12k_dp_rx_tid *rx_tid; 887 int i; 888 889 lockdep_assert_held(&ar->ab->base_lock); 890 891 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 892 rx_tid = &peer->rx_tid[i]; 893 894 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 895 ath12k_dp_rx_frags_cleanup(rx_tid, true); 896 897 spin_unlock_bh(&ar->ab->base_lock); 898 del_timer_sync(&rx_tid->frag_timer); 899 spin_lock_bh(&ar->ab->base_lock); 900 } 901 } 902 903 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 904 struct ath12k_peer *peer, 905 struct ath12k_dp_rx_tid *rx_tid, 906 u32 ba_win_sz, u16 ssn, 907 bool update_ssn) 908 { 909 struct ath12k_hal_reo_cmd cmd = {0}; 910 int ret; 911 912 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 913 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 914 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 915 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 916 cmd.ba_window_size = ba_win_sz; 917 918 if (update_ssn) { 919 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 920 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 921 } 922 923 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 924 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 925 NULL); 926 if (ret) { 927 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 928 rx_tid->tid, ret); 929 return ret; 930 } 931 932 rx_tid->ba_win_sz = ba_win_sz; 933 934 return 0; 935 } 936 937 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 938 u8 tid, u32 ba_win_sz, u16 ssn, 939 enum hal_pn_type pn_type) 940 { 941 struct ath12k_base *ab = ar->ab; 942 struct ath12k_dp *dp = &ab->dp; 943 struct hal_rx_reo_queue *addr_aligned; 944 struct ath12k_peer *peer; 945 struct ath12k_dp_rx_tid *rx_tid; 946 u32 hw_desc_sz; 947 void *vaddr; 948 dma_addr_t paddr; 949 int ret; 950 951 spin_lock_bh(&ab->base_lock); 952 953 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 954 if (!peer) { 955 spin_unlock_bh(&ab->base_lock); 956 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 957 return -ENOENT; 958 } 959 960 if (!peer->primary_link) { 961 spin_unlock_bh(&ab->base_lock); 962 return 0; 963 } 964 965 if (ab->hw_params->reoq_lut_support && 966 (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) { 967 spin_unlock_bh(&ab->base_lock); 968 ath12k_warn(ab, "reo qref table is not setup\n"); 969 return -EINVAL; 970 } 971 972 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 973 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 974 peer->peer_id, tid); 975 spin_unlock_bh(&ab->base_lock); 976 return -EINVAL; 977 } 978 979 rx_tid = &peer->rx_tid[tid]; 980 /* Update the tid queue if it is already setup */ 981 if (rx_tid->active) { 982 paddr = rx_tid->paddr; 983 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 984 ba_win_sz, ssn, true); 985 spin_unlock_bh(&ab->base_lock); 986 if (ret) { 987 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 988 return ret; 989 } 990 991 if (!ab->hw_params->reoq_lut_support) { 992 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 993 peer_mac, 994 paddr, tid, 1, 995 ba_win_sz); 996 if (ret) { 997 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 998 tid, ret); 999 return ret; 1000 } 1001 } 1002 1003 return 0; 1004 } 1005 1006 rx_tid->tid = tid; 1007 1008 rx_tid->ba_win_sz = ba_win_sz; 1009 1010 /* TODO: Optimize the memory allocation for qos tid based on 1011 * the actual BA window size in REO tid update path. 1012 */ 1013 if (tid == HAL_DESC_REO_NON_QOS_TID) 1014 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 1015 else 1016 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1017 1018 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1019 if (!vaddr) { 1020 spin_unlock_bh(&ab->base_lock); 1021 return -ENOMEM; 1022 } 1023 1024 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1025 1026 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1027 ssn, pn_type); 1028 1029 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1030 DMA_BIDIRECTIONAL); 1031 1032 ret = dma_mapping_error(ab->dev, paddr); 1033 if (ret) { 1034 spin_unlock_bh(&ab->base_lock); 1035 goto err_mem_free; 1036 } 1037 1038 rx_tid->vaddr = vaddr; 1039 rx_tid->paddr = paddr; 1040 rx_tid->size = hw_desc_sz; 1041 rx_tid->active = true; 1042 1043 if (ab->hw_params->reoq_lut_support) { 1044 /* Update the REO queue LUT at the corresponding peer id 1045 * and tid with qaddr. 1046 */ 1047 if (peer->mlo) 1048 ath12k_peer_rx_tid_qref_setup(ab, peer->ml_id, tid, paddr); 1049 else 1050 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr); 1051 1052 spin_unlock_bh(&ab->base_lock); 1053 } else { 1054 spin_unlock_bh(&ab->base_lock); 1055 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1056 paddr, tid, 1, ba_win_sz); 1057 } 1058 1059 return ret; 1060 1061 err_mem_free: 1062 kfree(vaddr); 1063 1064 return ret; 1065 } 1066 1067 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1068 struct ieee80211_ampdu_params *params, 1069 u8 link_id) 1070 { 1071 struct ath12k_base *ab = ar->ab; 1072 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 1073 struct ath12k_link_sta *arsta; 1074 int vdev_id; 1075 int ret; 1076 1077 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 1078 1079 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 1080 ahsta->link[link_id]); 1081 if (!arsta) 1082 return -ENOLINK; 1083 1084 vdev_id = arsta->arvif->vdev_id; 1085 1086 ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id, 1087 params->tid, params->buf_size, 1088 params->ssn, arsta->ahsta->pn_type); 1089 if (ret) 1090 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1091 1092 return ret; 1093 } 1094 1095 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1096 struct ieee80211_ampdu_params *params, 1097 u8 link_id) 1098 { 1099 struct ath12k_base *ab = ar->ab; 1100 struct ath12k_peer *peer; 1101 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 1102 struct ath12k_link_sta *arsta; 1103 int vdev_id; 1104 bool active; 1105 int ret; 1106 1107 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 1108 1109 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 1110 ahsta->link[link_id]); 1111 if (!arsta) 1112 return -ENOLINK; 1113 1114 vdev_id = arsta->arvif->vdev_id; 1115 1116 spin_lock_bh(&ab->base_lock); 1117 1118 peer = ath12k_peer_find(ab, vdev_id, arsta->addr); 1119 if (!peer) { 1120 spin_unlock_bh(&ab->base_lock); 1121 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1122 return -ENOENT; 1123 } 1124 1125 active = peer->rx_tid[params->tid].active; 1126 1127 if (!active) { 1128 spin_unlock_bh(&ab->base_lock); 1129 return 0; 1130 } 1131 1132 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1133 spin_unlock_bh(&ab->base_lock); 1134 if (ret) { 1135 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1136 params->tid, ret); 1137 return ret; 1138 } 1139 1140 return ret; 1141 } 1142 1143 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, 1144 const u8 *peer_addr, 1145 enum set_key_cmd key_cmd, 1146 struct ieee80211_key_conf *key) 1147 { 1148 struct ath12k *ar = arvif->ar; 1149 struct ath12k_base *ab = ar->ab; 1150 struct ath12k_hal_reo_cmd cmd = {0}; 1151 struct ath12k_peer *peer; 1152 struct ath12k_dp_rx_tid *rx_tid; 1153 u8 tid; 1154 int ret = 0; 1155 1156 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1157 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1158 * for now. 1159 */ 1160 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1161 return 0; 1162 1163 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1164 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1165 HAL_REO_CMD_UPD0_PN_SIZE | 1166 HAL_REO_CMD_UPD0_PN_VALID | 1167 HAL_REO_CMD_UPD0_PN_CHECK | 1168 HAL_REO_CMD_UPD0_SVLD; 1169 1170 switch (key->cipher) { 1171 case WLAN_CIPHER_SUITE_TKIP: 1172 case WLAN_CIPHER_SUITE_CCMP: 1173 case WLAN_CIPHER_SUITE_CCMP_256: 1174 case WLAN_CIPHER_SUITE_GCMP: 1175 case WLAN_CIPHER_SUITE_GCMP_256: 1176 if (key_cmd == SET_KEY) { 1177 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1178 cmd.pn_size = 48; 1179 } 1180 break; 1181 default: 1182 break; 1183 } 1184 1185 spin_lock_bh(&ab->base_lock); 1186 1187 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1188 if (!peer) { 1189 spin_unlock_bh(&ab->base_lock); 1190 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1191 peer_addr); 1192 return -ENOENT; 1193 } 1194 1195 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1196 rx_tid = &peer->rx_tid[tid]; 1197 if (!rx_tid->active) 1198 continue; 1199 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1200 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1201 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1202 HAL_REO_CMD_UPDATE_RX_QUEUE, 1203 &cmd, NULL); 1204 if (ret) { 1205 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1206 tid, peer_addr, ret); 1207 break; 1208 } 1209 } 1210 1211 spin_unlock_bh(&ab->base_lock); 1212 1213 return ret; 1214 } 1215 1216 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1217 u16 peer_id) 1218 { 1219 int i; 1220 1221 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1222 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1223 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1224 return i; 1225 } else { 1226 return i; 1227 } 1228 } 1229 1230 return -EINVAL; 1231 } 1232 1233 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1234 u16 tag, u16 len, const void *ptr, 1235 void *data) 1236 { 1237 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1238 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1239 const struct htt_ppdu_stats_user_rate *user_rate; 1240 struct htt_ppdu_stats_info *ppdu_info; 1241 struct htt_ppdu_user_stats *user_stats; 1242 int cur_user; 1243 u16 peer_id; 1244 1245 ppdu_info = data; 1246 1247 switch (tag) { 1248 case HTT_PPDU_STATS_TAG_COMMON: 1249 if (len < sizeof(struct htt_ppdu_stats_common)) { 1250 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1251 len, tag); 1252 return -EINVAL; 1253 } 1254 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1255 sizeof(struct htt_ppdu_stats_common)); 1256 break; 1257 case HTT_PPDU_STATS_TAG_USR_RATE: 1258 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1259 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1260 len, tag); 1261 return -EINVAL; 1262 } 1263 user_rate = ptr; 1264 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1265 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1266 peer_id); 1267 if (cur_user < 0) 1268 return -EINVAL; 1269 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1270 user_stats->peer_id = peer_id; 1271 user_stats->is_valid_peer_id = true; 1272 memcpy(&user_stats->rate, ptr, 1273 sizeof(struct htt_ppdu_stats_user_rate)); 1274 user_stats->tlv_flags |= BIT(tag); 1275 break; 1276 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1277 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1278 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1279 len, tag); 1280 return -EINVAL; 1281 } 1282 1283 cmplt_cmn = ptr; 1284 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1285 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1286 peer_id); 1287 if (cur_user < 0) 1288 return -EINVAL; 1289 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1290 user_stats->peer_id = peer_id; 1291 user_stats->is_valid_peer_id = true; 1292 memcpy(&user_stats->cmpltn_cmn, ptr, 1293 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1294 user_stats->tlv_flags |= BIT(tag); 1295 break; 1296 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1297 if (len < 1298 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1299 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1300 len, tag); 1301 return -EINVAL; 1302 } 1303 1304 ba_status = ptr; 1305 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1306 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1307 peer_id); 1308 if (cur_user < 0) 1309 return -EINVAL; 1310 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1311 user_stats->peer_id = peer_id; 1312 user_stats->is_valid_peer_id = true; 1313 memcpy(&user_stats->ack_ba, ptr, 1314 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1315 user_stats->tlv_flags |= BIT(tag); 1316 break; 1317 } 1318 return 0; 1319 } 1320 1321 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1322 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1323 const void *ptr, void *data), 1324 void *data) 1325 { 1326 const struct htt_tlv *tlv; 1327 const void *begin = ptr; 1328 u16 tlv_tag, tlv_len; 1329 int ret = -EINVAL; 1330 1331 while (len > 0) { 1332 if (len < sizeof(*tlv)) { 1333 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1334 ptr - begin, len, sizeof(*tlv)); 1335 return -EINVAL; 1336 } 1337 tlv = (struct htt_tlv *)ptr; 1338 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1339 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1340 ptr += sizeof(*tlv); 1341 len -= sizeof(*tlv); 1342 1343 if (tlv_len > len) { 1344 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1345 tlv_tag, ptr - begin, len, tlv_len); 1346 return -EINVAL; 1347 } 1348 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1349 if (ret == -ENOMEM) 1350 return ret; 1351 1352 ptr += tlv_len; 1353 len -= tlv_len; 1354 } 1355 return 0; 1356 } 1357 1358 static void 1359 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1360 struct htt_ppdu_stats *ppdu_stats, u8 user) 1361 { 1362 struct ath12k_base *ab = ar->ab; 1363 struct ath12k_peer *peer; 1364 struct ieee80211_sta *sta; 1365 struct ath12k_sta *ahsta; 1366 struct ath12k_link_sta *arsta; 1367 struct htt_ppdu_stats_user_rate *user_rate; 1368 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1369 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1370 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1371 int ret; 1372 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1373 u32 v, succ_bytes = 0; 1374 u16 tones, rate = 0, succ_pkts = 0; 1375 u32 tx_duration = 0; 1376 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1377 bool is_ampdu = false; 1378 1379 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1380 return; 1381 1382 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1383 is_ampdu = 1384 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1385 1386 if (usr_stats->tlv_flags & 1387 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1388 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1389 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1390 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1391 tid = le32_get_bits(usr_stats->ack_ba.info, 1392 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1393 } 1394 1395 if (common->fes_duration_us) 1396 tx_duration = le32_to_cpu(common->fes_duration_us); 1397 1398 user_rate = &usr_stats->rate; 1399 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1400 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1401 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1402 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1403 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1404 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1405 1406 /* Note: If host configured fixed rates and in some other special 1407 * cases, the broadcast/management frames are sent in different rates. 1408 * Firmware rate's control to be skipped for this? 1409 */ 1410 1411 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1412 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1413 return; 1414 } 1415 1416 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1417 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1418 return; 1419 } 1420 1421 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1422 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1423 mcs, nss); 1424 return; 1425 } 1426 1427 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1428 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1429 flags, 1430 &rate_idx, 1431 &rate); 1432 if (ret < 0) 1433 return; 1434 } 1435 1436 rcu_read_lock(); 1437 spin_lock_bh(&ab->base_lock); 1438 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1439 1440 if (!peer || !peer->sta) { 1441 spin_unlock_bh(&ab->base_lock); 1442 rcu_read_unlock(); 1443 return; 1444 } 1445 1446 sta = peer->sta; 1447 ahsta = ath12k_sta_to_ahsta(sta); 1448 arsta = &ahsta->deflink; 1449 1450 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1451 1452 switch (flags) { 1453 case WMI_RATE_PREAMBLE_OFDM: 1454 arsta->txrate.legacy = rate; 1455 break; 1456 case WMI_RATE_PREAMBLE_CCK: 1457 arsta->txrate.legacy = rate; 1458 break; 1459 case WMI_RATE_PREAMBLE_HT: 1460 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1461 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1462 if (sgi) 1463 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1464 break; 1465 case WMI_RATE_PREAMBLE_VHT: 1466 arsta->txrate.mcs = mcs; 1467 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1468 if (sgi) 1469 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1470 break; 1471 case WMI_RATE_PREAMBLE_HE: 1472 arsta->txrate.mcs = mcs; 1473 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1474 arsta->txrate.he_dcm = dcm; 1475 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1476 tones = le16_to_cpu(user_rate->ru_end) - 1477 le16_to_cpu(user_rate->ru_start) + 1; 1478 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1479 arsta->txrate.he_ru_alloc = v; 1480 break; 1481 } 1482 1483 arsta->txrate.nss = nss; 1484 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1485 arsta->tx_duration += tx_duration; 1486 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1487 1488 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1489 * So skip peer stats update for mgmt packets. 1490 */ 1491 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1492 memset(peer_stats, 0, sizeof(*peer_stats)); 1493 peer_stats->succ_pkts = succ_pkts; 1494 peer_stats->succ_bytes = succ_bytes; 1495 peer_stats->is_ampdu = is_ampdu; 1496 peer_stats->duration = tx_duration; 1497 peer_stats->ba_fails = 1498 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1499 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1500 } 1501 1502 spin_unlock_bh(&ab->base_lock); 1503 rcu_read_unlock(); 1504 } 1505 1506 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1507 struct htt_ppdu_stats *ppdu_stats) 1508 { 1509 u8 user; 1510 1511 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1512 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1513 } 1514 1515 static 1516 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1517 u32 ppdu_id) 1518 { 1519 struct htt_ppdu_stats_info *ppdu_info; 1520 1521 lockdep_assert_held(&ar->data_lock); 1522 if (!list_empty(&ar->ppdu_stats_info)) { 1523 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1524 if (ppdu_info->ppdu_id == ppdu_id) 1525 return ppdu_info; 1526 } 1527 1528 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1529 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1530 typeof(*ppdu_info), list); 1531 list_del(&ppdu_info->list); 1532 ar->ppdu_stat_list_depth--; 1533 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1534 kfree(ppdu_info); 1535 } 1536 } 1537 1538 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1539 if (!ppdu_info) 1540 return NULL; 1541 1542 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1543 ar->ppdu_stat_list_depth++; 1544 1545 return ppdu_info; 1546 } 1547 1548 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1549 struct htt_ppdu_user_stats *usr_stats) 1550 { 1551 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1552 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1553 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1554 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1555 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1556 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1557 peer->ppdu_stats_delayba.resp_rate_flags = 1558 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1559 1560 peer->delayba_flag = true; 1561 } 1562 1563 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1564 struct htt_ppdu_user_stats *usr_stats) 1565 { 1566 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1567 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1568 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1569 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1570 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1571 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1572 usr_stats->rate.resp_rate_flags = 1573 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1574 1575 peer->delayba_flag = false; 1576 } 1577 1578 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1579 struct sk_buff *skb) 1580 { 1581 struct ath12k_htt_ppdu_stats_msg *msg; 1582 struct htt_ppdu_stats_info *ppdu_info; 1583 struct ath12k_peer *peer = NULL; 1584 struct htt_ppdu_user_stats *usr_stats = NULL; 1585 u32 peer_id = 0; 1586 struct ath12k *ar; 1587 int ret, i; 1588 u8 pdev_id; 1589 u32 ppdu_id, len; 1590 1591 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1592 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1593 if (len > (skb->len - struct_size(msg, data, 0))) { 1594 ath12k_warn(ab, 1595 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1596 len, skb->len); 1597 return -EINVAL; 1598 } 1599 1600 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1601 ppdu_id = le32_to_cpu(msg->ppdu_id); 1602 1603 rcu_read_lock(); 1604 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1605 if (!ar) { 1606 ret = -EINVAL; 1607 goto exit; 1608 } 1609 1610 spin_lock_bh(&ar->data_lock); 1611 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1612 if (!ppdu_info) { 1613 spin_unlock_bh(&ar->data_lock); 1614 ret = -EINVAL; 1615 goto exit; 1616 } 1617 1618 ppdu_info->ppdu_id = ppdu_id; 1619 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1620 ath12k_htt_tlv_ppdu_stats_parse, 1621 (void *)ppdu_info); 1622 if (ret) { 1623 spin_unlock_bh(&ar->data_lock); 1624 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1625 goto exit; 1626 } 1627 1628 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1629 spin_unlock_bh(&ar->data_lock); 1630 ath12k_warn(ab, 1631 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1632 ppdu_info->ppdu_stats.common.num_users, 1633 HTT_PPDU_STATS_MAX_USERS); 1634 ret = -EINVAL; 1635 goto exit; 1636 } 1637 1638 /* back up data rate tlv for all peers */ 1639 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1640 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1641 ppdu_info->delay_ba) { 1642 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1643 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1644 spin_lock_bh(&ab->base_lock); 1645 peer = ath12k_peer_find_by_id(ab, peer_id); 1646 if (!peer) { 1647 spin_unlock_bh(&ab->base_lock); 1648 continue; 1649 } 1650 1651 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1652 if (usr_stats->delay_ba) 1653 ath12k_copy_to_delay_stats(peer, usr_stats); 1654 spin_unlock_bh(&ab->base_lock); 1655 } 1656 } 1657 1658 /* restore all peers' data rate tlv to mu-bar tlv */ 1659 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1660 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1661 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1662 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1663 spin_lock_bh(&ab->base_lock); 1664 peer = ath12k_peer_find_by_id(ab, peer_id); 1665 if (!peer) { 1666 spin_unlock_bh(&ab->base_lock); 1667 continue; 1668 } 1669 1670 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1671 if (peer->delayba_flag) 1672 ath12k_copy_to_bar(peer, usr_stats); 1673 spin_unlock_bh(&ab->base_lock); 1674 } 1675 } 1676 1677 spin_unlock_bh(&ar->data_lock); 1678 1679 exit: 1680 rcu_read_unlock(); 1681 1682 return ret; 1683 } 1684 1685 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1686 struct sk_buff *skb) 1687 { 1688 struct ath12k_htt_mlo_offset_msg *msg; 1689 struct ath12k_pdev *pdev; 1690 struct ath12k *ar; 1691 u8 pdev_id; 1692 1693 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1694 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1695 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1696 1697 rcu_read_lock(); 1698 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1699 if (!ar) { 1700 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id); 1701 goto exit; 1702 } 1703 1704 spin_lock_bh(&ar->data_lock); 1705 pdev = ar->pdev; 1706 1707 pdev->timestamp.info = __le32_to_cpu(msg->info); 1708 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1709 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1710 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1711 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1712 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1713 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1714 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1715 1716 spin_unlock_bh(&ar->data_lock); 1717 exit: 1718 rcu_read_unlock(); 1719 } 1720 1721 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1722 struct sk_buff *skb) 1723 { 1724 struct ath12k_dp *dp = &ab->dp; 1725 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1726 enum htt_t2h_msg_type type; 1727 u16 peer_id; 1728 u8 vdev_id; 1729 u8 mac_addr[ETH_ALEN]; 1730 u16 peer_mac_h16; 1731 u16 ast_hash = 0; 1732 u16 hw_peer_id; 1733 1734 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1735 1736 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1737 1738 switch (type) { 1739 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1740 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1741 HTT_T2H_VERSION_CONF_MAJOR); 1742 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1743 HTT_T2H_VERSION_CONF_MINOR); 1744 complete(&dp->htt_tgt_version_received); 1745 break; 1746 /* TODO: remove unused peer map versions after testing */ 1747 case HTT_T2H_MSG_TYPE_PEER_MAP: 1748 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1749 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1750 peer_id = le32_get_bits(resp->peer_map_ev.info, 1751 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1752 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1753 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1754 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1755 peer_mac_h16, mac_addr); 1756 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1757 break; 1758 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1759 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1760 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1761 peer_id = le32_get_bits(resp->peer_map_ev.info, 1762 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1763 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1764 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1765 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1766 peer_mac_h16, mac_addr); 1767 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1768 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1769 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1770 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1771 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1772 hw_peer_id); 1773 break; 1774 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1775 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1776 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1777 peer_id = le32_get_bits(resp->peer_map_ev.info, 1778 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1779 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1780 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1781 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1782 peer_mac_h16, mac_addr); 1783 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1784 peer_id); 1785 break; 1786 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1787 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1788 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1789 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1790 ath12k_peer_unmap_event(ab, peer_id); 1791 break; 1792 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1793 ath12k_htt_pull_ppdu_stats(ab, skb); 1794 break; 1795 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1796 ath12k_debugfs_htt_ext_stats_handler(ab, skb); 1797 break; 1798 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 1799 ath12k_htt_mlo_offset_event_handler(ab, skb); 1800 break; 1801 default: 1802 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 1803 type); 1804 break; 1805 } 1806 1807 dev_kfree_skb_any(skb); 1808 } 1809 1810 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 1811 struct sk_buff_head *msdu_list, 1812 struct sk_buff *first, struct sk_buff *last, 1813 u8 l3pad_bytes, int msdu_len) 1814 { 1815 struct ath12k_base *ab = ar->ab; 1816 struct sk_buff *skb; 1817 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1818 int buf_first_hdr_len, buf_first_len; 1819 struct hal_rx_desc *ldesc; 1820 int space_extra, rem_len, buf_len; 1821 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 1822 1823 /* As the msdu is spread across multiple rx buffers, 1824 * find the offset to the start of msdu for computing 1825 * the length of the msdu in the first buffer. 1826 */ 1827 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1828 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1829 1830 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1831 skb_put(first, buf_first_hdr_len + msdu_len); 1832 skb_pull(first, buf_first_hdr_len); 1833 return 0; 1834 } 1835 1836 ldesc = (struct hal_rx_desc *)last->data; 1837 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 1838 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 1839 1840 /* MSDU spans over multiple buffers because the length of the MSDU 1841 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1842 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1843 */ 1844 skb_put(first, DP_RX_BUFFER_SIZE); 1845 skb_pull(first, buf_first_hdr_len); 1846 1847 /* When an MSDU spread over multiple buffers MSDU_END 1848 * tlvs are valid only in the last buffer. Copy those tlvs. 1849 */ 1850 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1851 1852 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1853 if (space_extra > 0 && 1854 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1855 /* Free up all buffers of the MSDU */ 1856 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1857 rxcb = ATH12K_SKB_RXCB(skb); 1858 if (!rxcb->is_continuation) { 1859 dev_kfree_skb_any(skb); 1860 break; 1861 } 1862 dev_kfree_skb_any(skb); 1863 } 1864 return -ENOMEM; 1865 } 1866 1867 rem_len = msdu_len - buf_first_len; 1868 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1869 rxcb = ATH12K_SKB_RXCB(skb); 1870 if (rxcb->is_continuation) 1871 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1872 else 1873 buf_len = rem_len; 1874 1875 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1876 WARN_ON_ONCE(1); 1877 dev_kfree_skb_any(skb); 1878 return -EINVAL; 1879 } 1880 1881 skb_put(skb, buf_len + hal_rx_desc_sz); 1882 skb_pull(skb, hal_rx_desc_sz); 1883 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1884 buf_len); 1885 dev_kfree_skb_any(skb); 1886 1887 rem_len -= buf_len; 1888 if (!rxcb->is_continuation) 1889 break; 1890 } 1891 1892 return 0; 1893 } 1894 1895 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1896 struct sk_buff *first) 1897 { 1898 struct sk_buff *skb; 1899 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1900 1901 if (!rxcb->is_continuation) 1902 return first; 1903 1904 skb_queue_walk(msdu_list, skb) { 1905 rxcb = ATH12K_SKB_RXCB(skb); 1906 if (!rxcb->is_continuation) 1907 return skb; 1908 } 1909 1910 return NULL; 1911 } 1912 1913 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu) 1914 { 1915 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1916 struct ath12k_base *ab = ar->ab; 1917 bool ip_csum_fail, l4_csum_fail; 1918 1919 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc); 1920 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc); 1921 1922 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1923 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1924 } 1925 1926 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, 1927 enum hal_encrypt_type enctype) 1928 { 1929 switch (enctype) { 1930 case HAL_ENCRYPT_TYPE_OPEN: 1931 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1932 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1933 return 0; 1934 case HAL_ENCRYPT_TYPE_CCMP_128: 1935 return IEEE80211_CCMP_MIC_LEN; 1936 case HAL_ENCRYPT_TYPE_CCMP_256: 1937 return IEEE80211_CCMP_256_MIC_LEN; 1938 case HAL_ENCRYPT_TYPE_GCMP_128: 1939 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1940 return IEEE80211_GCMP_MIC_LEN; 1941 case HAL_ENCRYPT_TYPE_WEP_40: 1942 case HAL_ENCRYPT_TYPE_WEP_104: 1943 case HAL_ENCRYPT_TYPE_WEP_128: 1944 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1945 case HAL_ENCRYPT_TYPE_WAPI: 1946 break; 1947 } 1948 1949 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1950 return 0; 1951 } 1952 1953 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 1954 enum hal_encrypt_type enctype) 1955 { 1956 switch (enctype) { 1957 case HAL_ENCRYPT_TYPE_OPEN: 1958 return 0; 1959 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1960 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1961 return IEEE80211_TKIP_IV_LEN; 1962 case HAL_ENCRYPT_TYPE_CCMP_128: 1963 return IEEE80211_CCMP_HDR_LEN; 1964 case HAL_ENCRYPT_TYPE_CCMP_256: 1965 return IEEE80211_CCMP_256_HDR_LEN; 1966 case HAL_ENCRYPT_TYPE_GCMP_128: 1967 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1968 return IEEE80211_GCMP_HDR_LEN; 1969 case HAL_ENCRYPT_TYPE_WEP_40: 1970 case HAL_ENCRYPT_TYPE_WEP_104: 1971 case HAL_ENCRYPT_TYPE_WEP_128: 1972 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1973 case HAL_ENCRYPT_TYPE_WAPI: 1974 break; 1975 } 1976 1977 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1978 return 0; 1979 } 1980 1981 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 1982 enum hal_encrypt_type enctype) 1983 { 1984 switch (enctype) { 1985 case HAL_ENCRYPT_TYPE_OPEN: 1986 case HAL_ENCRYPT_TYPE_CCMP_128: 1987 case HAL_ENCRYPT_TYPE_CCMP_256: 1988 case HAL_ENCRYPT_TYPE_GCMP_128: 1989 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1990 return 0; 1991 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1992 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1993 return IEEE80211_TKIP_ICV_LEN; 1994 case HAL_ENCRYPT_TYPE_WEP_40: 1995 case HAL_ENCRYPT_TYPE_WEP_104: 1996 case HAL_ENCRYPT_TYPE_WEP_128: 1997 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1998 case HAL_ENCRYPT_TYPE_WAPI: 1999 break; 2000 } 2001 2002 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 2003 return 0; 2004 } 2005 2006 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 2007 struct sk_buff *msdu, 2008 enum hal_encrypt_type enctype, 2009 struct ieee80211_rx_status *status) 2010 { 2011 struct ath12k_base *ab = ar->ab; 2012 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2013 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 2014 struct ieee80211_hdr *hdr; 2015 size_t hdr_len; 2016 u8 *crypto_hdr; 2017 u16 qos_ctl; 2018 2019 /* pull decapped header */ 2020 hdr = (struct ieee80211_hdr *)msdu->data; 2021 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2022 skb_pull(msdu, hdr_len); 2023 2024 /* Rebuild qos header */ 2025 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 2026 2027 /* Reset the order bit as the HT_Control header is stripped */ 2028 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2029 2030 qos_ctl = rxcb->tid; 2031 2032 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 2033 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2034 2035 /* TODO: Add other QoS ctl fields when required */ 2036 2037 /* copy decap header before overwriting for reuse below */ 2038 memcpy(decap_hdr, hdr, hdr_len); 2039 2040 /* Rebuild crypto header for mac80211 use */ 2041 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2042 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 2043 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 2044 rxcb->rx_desc, crypto_hdr, 2045 enctype); 2046 } 2047 2048 memcpy(skb_push(msdu, 2049 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2050 IEEE80211_QOS_CTL_LEN); 2051 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2052 } 2053 2054 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2055 enum hal_encrypt_type enctype, 2056 struct ieee80211_rx_status *status, 2057 bool decrypted) 2058 { 2059 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2060 struct ieee80211_hdr *hdr; 2061 size_t hdr_len; 2062 size_t crypto_len; 2063 2064 if (!rxcb->is_first_msdu || 2065 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2066 WARN_ON_ONCE(1); 2067 return; 2068 } 2069 2070 skb_trim(msdu, msdu->len - FCS_LEN); 2071 2072 if (!decrypted) 2073 return; 2074 2075 hdr = (void *)msdu->data; 2076 2077 /* Tail */ 2078 if (status->flag & RX_FLAG_IV_STRIPPED) { 2079 skb_trim(msdu, msdu->len - 2080 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2081 2082 skb_trim(msdu, msdu->len - 2083 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2084 } else { 2085 /* MIC */ 2086 if (status->flag & RX_FLAG_MIC_STRIPPED) 2087 skb_trim(msdu, msdu->len - 2088 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2089 2090 /* ICV */ 2091 if (status->flag & RX_FLAG_ICV_STRIPPED) 2092 skb_trim(msdu, msdu->len - 2093 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2094 } 2095 2096 /* MMIC */ 2097 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2098 !ieee80211_has_morefrags(hdr->frame_control) && 2099 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2100 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2101 2102 /* Head */ 2103 if (status->flag & RX_FLAG_IV_STRIPPED) { 2104 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2105 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2106 2107 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2108 skb_pull(msdu, crypto_len); 2109 } 2110 } 2111 2112 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2113 struct sk_buff *msdu, 2114 struct ath12k_skb_rxcb *rxcb, 2115 struct ieee80211_rx_status *status, 2116 enum hal_encrypt_type enctype) 2117 { 2118 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2119 struct ath12k_base *ab = ar->ab; 2120 size_t hdr_len, crypto_len; 2121 struct ieee80211_hdr *hdr; 2122 u16 qos_ctl; 2123 __le16 fc; 2124 u8 *crypto_hdr; 2125 2126 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2127 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2128 crypto_hdr = skb_push(msdu, crypto_len); 2129 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2130 } 2131 2132 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc)); 2133 hdr_len = ieee80211_hdrlen(fc); 2134 skb_push(msdu, hdr_len); 2135 hdr = (struct ieee80211_hdr *)msdu->data; 2136 hdr->frame_control = fc; 2137 2138 /* Get wifi header from rx_desc */ 2139 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr); 2140 2141 if (rxcb->is_mcbc) 2142 status->flag &= ~RX_FLAG_PN_VALIDATED; 2143 2144 /* Add QOS header */ 2145 if (ieee80211_is_data_qos(hdr->frame_control)) { 2146 qos_ctl = rxcb->tid; 2147 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc)) 2148 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2149 2150 /* TODO: Add other QoS ctl fields when required */ 2151 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN), 2152 &qos_ctl, IEEE80211_QOS_CTL_LEN); 2153 } 2154 } 2155 2156 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2157 struct sk_buff *msdu, 2158 enum hal_encrypt_type enctype, 2159 struct ieee80211_rx_status *status) 2160 { 2161 struct ieee80211_hdr *hdr; 2162 struct ethhdr *eth; 2163 u8 da[ETH_ALEN]; 2164 u8 sa[ETH_ALEN]; 2165 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2166 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2167 2168 eth = (struct ethhdr *)msdu->data; 2169 ether_addr_copy(da, eth->h_dest); 2170 ether_addr_copy(sa, eth->h_source); 2171 rfc.snap_type = eth->h_proto; 2172 skb_pull(msdu, sizeof(*eth)); 2173 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2174 sizeof(rfc)); 2175 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2176 2177 /* original 802.11 header has a different DA and in 2178 * case of 4addr it may also have different SA 2179 */ 2180 hdr = (struct ieee80211_hdr *)msdu->data; 2181 ether_addr_copy(ieee80211_get_DA(hdr), da); 2182 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2183 } 2184 2185 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2186 struct hal_rx_desc *rx_desc, 2187 enum hal_encrypt_type enctype, 2188 struct ieee80211_rx_status *status, 2189 bool decrypted) 2190 { 2191 struct ath12k_base *ab = ar->ab; 2192 u8 decap; 2193 struct ethhdr *ehdr; 2194 2195 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2196 2197 switch (decap) { 2198 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2199 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2200 break; 2201 case DP_RX_DECAP_TYPE_RAW: 2202 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2203 decrypted); 2204 break; 2205 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2206 ehdr = (struct ethhdr *)msdu->data; 2207 2208 /* mac80211 allows fast path only for authorized STA */ 2209 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2210 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2211 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2212 break; 2213 } 2214 2215 /* PN for mcast packets will be validated in mac80211; 2216 * remove eth header and add 802.11 header. 2217 */ 2218 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2219 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2220 break; 2221 case DP_RX_DECAP_TYPE_8023: 2222 /* TODO: Handle undecap for these formats */ 2223 break; 2224 } 2225 } 2226 2227 struct ath12k_peer * 2228 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu) 2229 { 2230 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2231 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2232 struct ath12k_peer *peer = NULL; 2233 2234 lockdep_assert_held(&ab->base_lock); 2235 2236 if (rxcb->peer_id) 2237 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2238 2239 if (peer) 2240 return peer; 2241 2242 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2243 return NULL; 2244 2245 peer = ath12k_peer_find_by_addr(ab, 2246 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, 2247 rx_desc)); 2248 return peer; 2249 } 2250 2251 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2252 struct sk_buff *msdu, 2253 struct hal_rx_desc *rx_desc, 2254 struct ieee80211_rx_status *rx_status) 2255 { 2256 bool fill_crypto_hdr; 2257 struct ath12k_base *ab = ar->ab; 2258 struct ath12k_skb_rxcb *rxcb; 2259 enum hal_encrypt_type enctype; 2260 bool is_decrypted = false; 2261 struct ieee80211_hdr *hdr; 2262 struct ath12k_peer *peer; 2263 u32 err_bitmap; 2264 2265 /* PN for multicast packets will be checked in mac80211 */ 2266 rxcb = ATH12K_SKB_RXCB(msdu); 2267 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc); 2268 rxcb->is_mcbc = fill_crypto_hdr; 2269 2270 if (rxcb->is_mcbc) 2271 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc); 2272 2273 spin_lock_bh(&ar->ab->base_lock); 2274 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 2275 if (peer) { 2276 if (rxcb->is_mcbc) 2277 enctype = peer->sec_type_grp; 2278 else 2279 enctype = peer->sec_type; 2280 } else { 2281 enctype = HAL_ENCRYPT_TYPE_OPEN; 2282 } 2283 spin_unlock_bh(&ar->ab->base_lock); 2284 2285 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2286 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2287 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2288 2289 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2290 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2291 RX_FLAG_MMIC_ERROR | 2292 RX_FLAG_DECRYPTED | 2293 RX_FLAG_IV_STRIPPED | 2294 RX_FLAG_MMIC_STRIPPED); 2295 2296 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2297 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2298 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2299 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2300 2301 if (is_decrypted) { 2302 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2303 2304 if (fill_crypto_hdr) 2305 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2306 RX_FLAG_ICV_STRIPPED; 2307 else 2308 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2309 RX_FLAG_PN_VALIDATED; 2310 } 2311 2312 ath12k_dp_rx_h_csum_offload(ar, msdu); 2313 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2314 enctype, rx_status, is_decrypted); 2315 2316 if (!is_decrypted || fill_crypto_hdr) 2317 return; 2318 2319 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) != 2320 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2321 hdr = (void *)msdu->data; 2322 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2323 } 2324 } 2325 2326 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2327 struct ieee80211_rx_status *rx_status) 2328 { 2329 struct ath12k_base *ab = ar->ab; 2330 struct ieee80211_supported_band *sband; 2331 enum rx_msdu_start_pkt_type pkt_type; 2332 u8 bw; 2333 u8 rate_mcs, nss; 2334 u8 sgi; 2335 bool is_cck; 2336 2337 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2338 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2339 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2340 nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2341 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2342 2343 switch (pkt_type) { 2344 case RX_MSDU_START_PKT_TYPE_11A: 2345 case RX_MSDU_START_PKT_TYPE_11B: 2346 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2347 sband = &ar->mac.sbands[rx_status->band]; 2348 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2349 is_cck); 2350 break; 2351 case RX_MSDU_START_PKT_TYPE_11N: 2352 rx_status->encoding = RX_ENC_HT; 2353 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2354 ath12k_warn(ar->ab, 2355 "Received with invalid mcs in HT mode %d\n", 2356 rate_mcs); 2357 break; 2358 } 2359 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2360 if (sgi) 2361 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2362 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2363 break; 2364 case RX_MSDU_START_PKT_TYPE_11AC: 2365 rx_status->encoding = RX_ENC_VHT; 2366 rx_status->rate_idx = rate_mcs; 2367 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2368 ath12k_warn(ar->ab, 2369 "Received with invalid mcs in VHT mode %d\n", 2370 rate_mcs); 2371 break; 2372 } 2373 rx_status->nss = nss; 2374 if (sgi) 2375 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2376 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2377 break; 2378 case RX_MSDU_START_PKT_TYPE_11AX: 2379 rx_status->rate_idx = rate_mcs; 2380 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2381 ath12k_warn(ar->ab, 2382 "Received with invalid mcs in HE mode %d\n", 2383 rate_mcs); 2384 break; 2385 } 2386 rx_status->encoding = RX_ENC_HE; 2387 rx_status->nss = nss; 2388 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2389 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2390 break; 2391 } 2392 } 2393 2394 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2395 struct ieee80211_rx_status *rx_status) 2396 { 2397 struct ath12k_base *ab = ar->ab; 2398 u8 channel_num; 2399 u32 center_freq, meta_data; 2400 struct ieee80211_channel *channel; 2401 2402 rx_status->freq = 0; 2403 rx_status->rate_idx = 0; 2404 rx_status->nss = 0; 2405 rx_status->encoding = RX_ENC_LEGACY; 2406 rx_status->bw = RATE_INFO_BW_20; 2407 rx_status->enc_flags = 0; 2408 2409 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2410 2411 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2412 channel_num = meta_data; 2413 center_freq = meta_data >> 16; 2414 2415 if (center_freq >= ATH12K_MIN_6G_FREQ && 2416 center_freq <= ATH12K_MAX_6G_FREQ) { 2417 rx_status->band = NL80211_BAND_6GHZ; 2418 rx_status->freq = center_freq; 2419 } else if (channel_num >= 1 && channel_num <= 14) { 2420 rx_status->band = NL80211_BAND_2GHZ; 2421 } else if (channel_num >= 36 && channel_num <= 173) { 2422 rx_status->band = NL80211_BAND_5GHZ; 2423 } else { 2424 spin_lock_bh(&ar->data_lock); 2425 channel = ar->rx_channel; 2426 if (channel) { 2427 rx_status->band = channel->band; 2428 channel_num = 2429 ieee80211_frequency_to_channel(channel->center_freq); 2430 } 2431 spin_unlock_bh(&ar->data_lock); 2432 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2433 rx_desc, sizeof(*rx_desc)); 2434 } 2435 2436 if (rx_status->band != NL80211_BAND_6GHZ) 2437 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2438 rx_status->band); 2439 2440 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status); 2441 } 2442 2443 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2444 struct sk_buff *msdu, 2445 struct ieee80211_rx_status *status) 2446 { 2447 struct ath12k_base *ab = ar->ab; 2448 static const struct ieee80211_radiotap_he known = { 2449 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2450 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2451 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2452 }; 2453 struct ieee80211_radiotap_he *he; 2454 struct ieee80211_rx_status *rx_status; 2455 struct ieee80211_sta *pubsta; 2456 struct ath12k_peer *peer; 2457 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2458 u8 decap = DP_RX_DECAP_TYPE_RAW; 2459 bool is_mcbc = rxcb->is_mcbc; 2460 bool is_eapol = rxcb->is_eapol; 2461 2462 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) && 2463 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2464 he = skb_push(msdu, sizeof(known)); 2465 memcpy(he, &known, sizeof(known)); 2466 status->flag |= RX_FLAG_RADIOTAP_HE; 2467 } 2468 2469 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2470 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc); 2471 2472 spin_lock_bh(&ab->base_lock); 2473 peer = ath12k_dp_rx_h_find_peer(ab, msdu); 2474 2475 pubsta = peer ? peer->sta : NULL; 2476 2477 spin_unlock_bh(&ab->base_lock); 2478 2479 ath12k_dbg(ab, ATH12K_DBG_DATA, 2480 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2481 msdu, 2482 msdu->len, 2483 peer ? peer->addr : NULL, 2484 rxcb->tid, 2485 is_mcbc ? "mcast" : "ucast", 2486 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2487 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2488 (status->encoding == RX_ENC_HT) ? "ht" : "", 2489 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2490 (status->encoding == RX_ENC_HE) ? "he" : "", 2491 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2492 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2493 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2494 (status->bw == RATE_INFO_BW_320) ? "320" : "", 2495 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2496 status->rate_idx, 2497 status->nss, 2498 status->freq, 2499 status->band, status->flag, 2500 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2501 !!(status->flag & RX_FLAG_MMIC_ERROR), 2502 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2503 2504 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2505 msdu->data, msdu->len); 2506 2507 rx_status = IEEE80211_SKB_RXCB(msdu); 2508 *rx_status = *status; 2509 2510 /* TODO: trace rx packet */ 2511 2512 /* PN for multicast packets are not validate in HW, 2513 * so skip 802.3 rx path 2514 * Also, fast_rx expects the STA to be authorized, hence 2515 * eapol packets are sent in slow path. 2516 */ 2517 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2518 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2519 rx_status->flag |= RX_FLAG_8023; 2520 2521 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 2522 } 2523 2524 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2525 struct sk_buff *msdu, 2526 struct sk_buff_head *msdu_list, 2527 struct ieee80211_rx_status *rx_status) 2528 { 2529 struct ath12k_base *ab = ar->ab; 2530 struct hal_rx_desc *rx_desc, *lrx_desc; 2531 struct ath12k_skb_rxcb *rxcb; 2532 struct sk_buff *last_buf; 2533 u8 l3_pad_bytes; 2534 u16 msdu_len; 2535 int ret; 2536 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2537 2538 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2539 if (!last_buf) { 2540 ath12k_warn(ab, 2541 "No valid Rx buffer to access MSDU_END tlv\n"); 2542 ret = -EIO; 2543 goto free_out; 2544 } 2545 2546 rx_desc = (struct hal_rx_desc *)msdu->data; 2547 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2548 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2549 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2550 ret = -EIO; 2551 goto free_out; 2552 } 2553 2554 rxcb = ATH12K_SKB_RXCB(msdu); 2555 rxcb->rx_desc = rx_desc; 2556 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2557 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2558 2559 if (rxcb->is_frag) { 2560 skb_pull(msdu, hal_rx_desc_sz); 2561 } else if (!rxcb->is_continuation) { 2562 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2563 ret = -EINVAL; 2564 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2565 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2566 sizeof(*rx_desc)); 2567 goto free_out; 2568 } 2569 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2570 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2571 } else { 2572 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2573 msdu, last_buf, 2574 l3_pad_bytes, msdu_len); 2575 if (ret) { 2576 ath12k_warn(ab, 2577 "failed to coalesce msdu rx buffer%d\n", ret); 2578 goto free_out; 2579 } 2580 } 2581 2582 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2583 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2584 2585 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2586 2587 return 0; 2588 2589 free_out: 2590 return ret; 2591 } 2592 2593 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2594 struct napi_struct *napi, 2595 struct sk_buff_head *msdu_list, 2596 int ring_id) 2597 { 2598 struct ieee80211_rx_status rx_status = {0}; 2599 struct ath12k_skb_rxcb *rxcb; 2600 struct sk_buff *msdu; 2601 struct ath12k *ar; 2602 u8 mac_id, pdev_id; 2603 int ret; 2604 2605 if (skb_queue_empty(msdu_list)) 2606 return; 2607 2608 rcu_read_lock(); 2609 2610 while ((msdu = __skb_dequeue(msdu_list))) { 2611 rxcb = ATH12K_SKB_RXCB(msdu); 2612 mac_id = rxcb->mac_id; 2613 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 2614 ar = ab->pdevs[pdev_id].ar; 2615 if (!rcu_dereference(ab->pdevs_active[pdev_id])) { 2616 dev_kfree_skb_any(msdu); 2617 continue; 2618 } 2619 2620 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 2621 dev_kfree_skb_any(msdu); 2622 continue; 2623 } 2624 2625 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2626 if (ret) { 2627 ath12k_dbg(ab, ATH12K_DBG_DATA, 2628 "Unable to process msdu %d", ret); 2629 dev_kfree_skb_any(msdu); 2630 continue; 2631 } 2632 2633 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2634 } 2635 2636 rcu_read_unlock(); 2637 } 2638 2639 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab, 2640 enum ath12k_peer_metadata_version ver, 2641 __le32 peer_metadata) 2642 { 2643 switch (ver) { 2644 default: 2645 ath12k_warn(ab, "Unknown peer metadata version: %d", ver); 2646 fallthrough; 2647 case ATH12K_PEER_METADATA_V0: 2648 return le32_get_bits(peer_metadata, 2649 RX_MPDU_DESC_META_DATA_V0_PEER_ID); 2650 case ATH12K_PEER_METADATA_V1: 2651 return le32_get_bits(peer_metadata, 2652 RX_MPDU_DESC_META_DATA_V1_PEER_ID); 2653 case ATH12K_PEER_METADATA_V1A: 2654 return le32_get_bits(peer_metadata, 2655 RX_MPDU_DESC_META_DATA_V1A_PEER_ID); 2656 case ATH12K_PEER_METADATA_V1B: 2657 return le32_get_bits(peer_metadata, 2658 RX_MPDU_DESC_META_DATA_V1B_PEER_ID); 2659 } 2660 } 2661 2662 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2663 struct napi_struct *napi, int budget) 2664 { 2665 LIST_HEAD(rx_desc_used_list); 2666 struct ath12k_rx_desc_info *desc_info; 2667 struct ath12k_dp *dp = &ab->dp; 2668 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2669 struct hal_reo_dest_ring *desc; 2670 int num_buffs_reaped = 0; 2671 struct sk_buff_head msdu_list; 2672 struct ath12k_skb_rxcb *rxcb; 2673 int total_msdu_reaped = 0; 2674 struct hal_srng *srng; 2675 struct sk_buff *msdu; 2676 bool done = false; 2677 int mac_id; 2678 u64 desc_va; 2679 2680 __skb_queue_head_init(&msdu_list); 2681 2682 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2683 2684 spin_lock_bh(&srng->lock); 2685 2686 try_again: 2687 ath12k_hal_srng_access_begin(ab, srng); 2688 2689 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2690 struct rx_mpdu_desc *mpdu_info; 2691 struct rx_msdu_desc *msdu_info; 2692 enum hal_reo_dest_ring_push_reason push_reason; 2693 u32 cookie; 2694 2695 cookie = le32_get_bits(desc->buf_addr_info.info1, 2696 BUFFER_ADDR_INFO1_SW_COOKIE); 2697 2698 mac_id = le32_get_bits(desc->info0, 2699 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2700 2701 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2702 le32_to_cpu(desc->buf_va_lo)); 2703 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2704 2705 /* retry manual desc retrieval */ 2706 if (!desc_info) { 2707 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 2708 if (!desc_info) { 2709 ath12k_warn(ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n", 2710 cookie); 2711 continue; 2712 } 2713 } 2714 2715 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 2716 ath12k_warn(ab, "Check HW CC implementation"); 2717 2718 msdu = desc_info->skb; 2719 desc_info->skb = NULL; 2720 2721 list_add_tail(&desc_info->list, &rx_desc_used_list); 2722 2723 rxcb = ATH12K_SKB_RXCB(msdu); 2724 dma_unmap_single(ab->dev, rxcb->paddr, 2725 msdu->len + skb_tailroom(msdu), 2726 DMA_FROM_DEVICE); 2727 2728 num_buffs_reaped++; 2729 2730 push_reason = le32_get_bits(desc->info0, 2731 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 2732 if (push_reason != 2733 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2734 dev_kfree_skb_any(msdu); 2735 ab->soc_stats.hal_reo_error[ring_id]++; 2736 continue; 2737 } 2738 2739 msdu_info = &desc->rx_msdu_info; 2740 mpdu_info = &desc->rx_mpdu_info; 2741 2742 rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) & 2743 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2744 rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) & 2745 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2746 rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) & 2747 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2748 rxcb->mac_id = mac_id; 2749 rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver, 2750 mpdu_info->peer_meta_data); 2751 rxcb->tid = le32_get_bits(mpdu_info->info0, 2752 RX_MPDU_DESC_INFO0_TID); 2753 2754 __skb_queue_tail(&msdu_list, msdu); 2755 2756 if (!rxcb->is_continuation) { 2757 total_msdu_reaped++; 2758 done = true; 2759 } else { 2760 done = false; 2761 } 2762 2763 if (total_msdu_reaped >= budget) 2764 break; 2765 } 2766 2767 /* Hw might have updated the head pointer after we cached it. 2768 * In this case, even though there are entries in the ring we'll 2769 * get rx_desc NULL. Give the read another try with updated cached 2770 * head pointer so that we can reap complete MPDU in the current 2771 * rx processing. 2772 */ 2773 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 2774 ath12k_hal_srng_access_end(ab, srng); 2775 goto try_again; 2776 } 2777 2778 ath12k_hal_srng_access_end(ab, srng); 2779 2780 spin_unlock_bh(&srng->lock); 2781 2782 if (!total_msdu_reaped) 2783 goto exit; 2784 2785 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 2786 num_buffs_reaped); 2787 2788 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2789 ring_id); 2790 2791 exit: 2792 return total_msdu_reaped; 2793 } 2794 2795 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 2796 { 2797 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2798 2799 spin_lock_bh(&rx_tid->ab->base_lock); 2800 if (rx_tid->last_frag_no && 2801 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2802 spin_unlock_bh(&rx_tid->ab->base_lock); 2803 return; 2804 } 2805 ath12k_dp_rx_frags_cleanup(rx_tid, true); 2806 spin_unlock_bh(&rx_tid->ab->base_lock); 2807 } 2808 2809 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 2810 { 2811 struct ath12k_base *ab = ar->ab; 2812 struct crypto_shash *tfm; 2813 struct ath12k_peer *peer; 2814 struct ath12k_dp_rx_tid *rx_tid; 2815 int i; 2816 2817 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2818 if (IS_ERR(tfm)) 2819 return PTR_ERR(tfm); 2820 2821 spin_lock_bh(&ab->base_lock); 2822 2823 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 2824 if (!peer) { 2825 spin_unlock_bh(&ab->base_lock); 2826 crypto_free_shash(tfm); 2827 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 2828 return -ENOENT; 2829 } 2830 2831 if (!peer->primary_link) { 2832 spin_unlock_bh(&ab->base_lock); 2833 return 0; 2834 } 2835 2836 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 2837 rx_tid = &peer->rx_tid[i]; 2838 rx_tid->ab = ab; 2839 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 2840 skb_queue_head_init(&rx_tid->rx_frags); 2841 } 2842 2843 peer->tfm_mmic = tfm; 2844 peer->dp_setup_done = true; 2845 spin_unlock_bh(&ab->base_lock); 2846 2847 return 0; 2848 } 2849 2850 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 2851 struct ieee80211_hdr *hdr, u8 *data, 2852 size_t data_len, u8 *mic) 2853 { 2854 SHASH_DESC_ON_STACK(desc, tfm); 2855 u8 mic_hdr[16] = {0}; 2856 u8 tid = 0; 2857 int ret; 2858 2859 if (!tfm) 2860 return -EINVAL; 2861 2862 desc->tfm = tfm; 2863 2864 ret = crypto_shash_setkey(tfm, key, 8); 2865 if (ret) 2866 goto out; 2867 2868 ret = crypto_shash_init(desc); 2869 if (ret) 2870 goto out; 2871 2872 /* TKIP MIC header */ 2873 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 2874 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 2875 if (ieee80211_is_data_qos(hdr->frame_control)) 2876 tid = ieee80211_get_tid(hdr); 2877 mic_hdr[12] = tid; 2878 2879 ret = crypto_shash_update(desc, mic_hdr, 16); 2880 if (ret) 2881 goto out; 2882 ret = crypto_shash_update(desc, data, data_len); 2883 if (ret) 2884 goto out; 2885 ret = crypto_shash_final(desc, mic); 2886 out: 2887 shash_desc_zero(desc); 2888 return ret; 2889 } 2890 2891 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 2892 struct sk_buff *msdu) 2893 { 2894 struct ath12k_base *ab = ar->ab; 2895 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 2896 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 2897 struct ieee80211_key_conf *key_conf; 2898 struct ieee80211_hdr *hdr; 2899 u8 mic[IEEE80211_CCMP_MIC_LEN]; 2900 int head_len, tail_len, ret; 2901 size_t data_len; 2902 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2903 u8 *key, *data; 2904 u8 key_idx; 2905 2906 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 2907 return 0; 2908 2909 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2910 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2911 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 2912 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 2913 2914 if (!is_multicast_ether_addr(hdr->addr1)) 2915 key_idx = peer->ucast_keyidx; 2916 else 2917 key_idx = peer->mcast_keyidx; 2918 2919 key_conf = peer->keys[key_idx]; 2920 2921 data = msdu->data + head_len; 2922 data_len = msdu->len - head_len - tail_len; 2923 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 2924 2925 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 2926 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 2927 goto mic_fail; 2928 2929 return 0; 2930 2931 mic_fail: 2932 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 2933 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 2934 2935 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 2936 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 2937 skb_pull(msdu, hal_rx_desc_sz); 2938 2939 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 2940 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2941 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 2942 ieee80211_rx(ath12k_ar_to_hw(ar), msdu); 2943 return -EINVAL; 2944 } 2945 2946 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 2947 enum hal_encrypt_type enctype, u32 flags) 2948 { 2949 struct ieee80211_hdr *hdr; 2950 size_t hdr_len; 2951 size_t crypto_len; 2952 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2953 2954 if (!flags) 2955 return; 2956 2957 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2958 2959 if (flags & RX_FLAG_MIC_STRIPPED) 2960 skb_trim(msdu, msdu->len - 2961 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2962 2963 if (flags & RX_FLAG_ICV_STRIPPED) 2964 skb_trim(msdu, msdu->len - 2965 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2966 2967 if (flags & RX_FLAG_IV_STRIPPED) { 2968 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2969 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2970 2971 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 2972 msdu->data + hal_rx_desc_sz, hdr_len); 2973 skb_pull(msdu, crypto_len); 2974 } 2975 } 2976 2977 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 2978 struct ath12k_peer *peer, 2979 struct ath12k_dp_rx_tid *rx_tid, 2980 struct sk_buff **defrag_skb) 2981 { 2982 struct ath12k_base *ab = ar->ab; 2983 struct hal_rx_desc *rx_desc; 2984 struct sk_buff *skb, *first_frag, *last_frag; 2985 struct ieee80211_hdr *hdr; 2986 enum hal_encrypt_type enctype; 2987 bool is_decrypted = false; 2988 int msdu_len = 0; 2989 int extra_space; 2990 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2991 2992 first_frag = skb_peek(&rx_tid->rx_frags); 2993 last_frag = skb_peek_tail(&rx_tid->rx_frags); 2994 2995 skb_queue_walk(&rx_tid->rx_frags, skb) { 2996 flags = 0; 2997 rx_desc = (struct hal_rx_desc *)skb->data; 2998 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 2999 3000 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 3001 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 3002 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 3003 rx_desc); 3004 3005 if (is_decrypted) { 3006 if (skb != first_frag) 3007 flags |= RX_FLAG_IV_STRIPPED; 3008 if (skb != last_frag) 3009 flags |= RX_FLAG_ICV_STRIPPED | 3010 RX_FLAG_MIC_STRIPPED; 3011 } 3012 3013 /* RX fragments are always raw packets */ 3014 if (skb != last_frag) 3015 skb_trim(skb, skb->len - FCS_LEN); 3016 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3017 3018 if (skb != first_frag) 3019 skb_pull(skb, hal_rx_desc_sz + 3020 ieee80211_hdrlen(hdr->frame_control)); 3021 msdu_len += skb->len; 3022 } 3023 3024 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3025 if (extra_space > 0 && 3026 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3027 return -ENOMEM; 3028 3029 __skb_unlink(first_frag, &rx_tid->rx_frags); 3030 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3031 skb_put_data(first_frag, skb->data, skb->len); 3032 dev_kfree_skb_any(skb); 3033 } 3034 3035 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3036 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3037 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 3038 3039 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3040 first_frag = NULL; 3041 3042 *defrag_skb = first_frag; 3043 return 0; 3044 } 3045 3046 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 3047 struct ath12k_dp_rx_tid *rx_tid, 3048 struct sk_buff *defrag_skb) 3049 { 3050 struct ath12k_base *ab = ar->ab; 3051 struct ath12k_dp *dp = &ab->dp; 3052 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3053 struct hal_reo_entrance_ring *reo_ent_ring; 3054 struct hal_reo_dest_ring *reo_dest_ring; 3055 struct dp_link_desc_bank *link_desc_banks; 3056 struct hal_rx_msdu_link *msdu_link; 3057 struct hal_rx_msdu_details *msdu0; 3058 struct hal_srng *srng; 3059 dma_addr_t link_paddr, buf_paddr; 3060 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 3061 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi; 3062 int ret; 3063 struct ath12k_rx_desc_info *desc_info; 3064 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm; 3065 u8 dst_ind; 3066 3067 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3068 link_desc_banks = dp->link_desc_banks; 3069 reo_dest_ring = rx_tid->dst_ring_desc; 3070 3071 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 3072 &link_paddr, &cookie); 3073 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 3074 3075 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3076 (link_paddr - link_desc_banks[desc_bank].paddr)); 3077 msdu0 = &msdu_link->msdu_link[0]; 3078 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 3079 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 3080 3081 memset(msdu0, 0, sizeof(*msdu0)); 3082 3083 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 3084 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 3085 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3086 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3087 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3088 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3089 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3090 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3091 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3092 3093 /* change msdu len in hal rx desc */ 3094 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3095 3096 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3097 defrag_skb->len + skb_tailroom(defrag_skb), 3098 DMA_TO_DEVICE); 3099 if (dma_mapping_error(ab->dev, buf_paddr)) 3100 return -ENOMEM; 3101 3102 spin_lock_bh(&dp->rx_desc_lock); 3103 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3104 struct ath12k_rx_desc_info, 3105 list); 3106 if (!desc_info) { 3107 spin_unlock_bh(&dp->rx_desc_lock); 3108 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3109 ret = -ENOMEM; 3110 goto err_unmap_dma; 3111 } 3112 3113 desc_info->skb = defrag_skb; 3114 desc_info->in_use = true; 3115 3116 list_del(&desc_info->list); 3117 spin_unlock_bh(&dp->rx_desc_lock); 3118 3119 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3120 3121 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3122 desc_info->cookie, 3123 HAL_RX_BUF_RBM_SW3_BM); 3124 3125 /* Fill mpdu details into reo entrance ring */ 3126 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3127 3128 spin_lock_bh(&srng->lock); 3129 ath12k_hal_srng_access_begin(ab, srng); 3130 3131 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3132 if (!reo_ent_ring) { 3133 ath12k_hal_srng_access_end(ab, srng); 3134 spin_unlock_bh(&srng->lock); 3135 ret = -ENOSPC; 3136 goto err_free_desc; 3137 } 3138 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3139 3140 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3141 cookie, 3142 idle_link_rbm); 3143 3144 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3145 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3146 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3147 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3148 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3149 3150 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3151 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3152 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3153 3154 reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr)); 3155 queue_addr_hi = upper_32_bits(rx_tid->paddr); 3156 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi, 3157 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) | 3158 le32_encode_bits(dst_ind, 3159 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3160 3161 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3162 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3163 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3164 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3165 reo_ent_ring->info2 = 3166 cpu_to_le32(u32_get_bits(dest_ring_info0, 3167 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3168 3169 ath12k_hal_srng_access_end(ab, srng); 3170 spin_unlock_bh(&srng->lock); 3171 3172 return 0; 3173 3174 err_free_desc: 3175 spin_lock_bh(&dp->rx_desc_lock); 3176 desc_info->in_use = false; 3177 desc_info->skb = NULL; 3178 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3179 spin_unlock_bh(&dp->rx_desc_lock); 3180 err_unmap_dma: 3181 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3182 DMA_TO_DEVICE); 3183 return ret; 3184 } 3185 3186 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3187 struct sk_buff *a, struct sk_buff *b) 3188 { 3189 int frag1, frag2; 3190 3191 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3192 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3193 3194 return frag1 - frag2; 3195 } 3196 3197 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3198 struct sk_buff_head *frag_list, 3199 struct sk_buff *cur_frag) 3200 { 3201 struct sk_buff *skb; 3202 int cmp; 3203 3204 skb_queue_walk(frag_list, skb) { 3205 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3206 if (cmp < 0) 3207 continue; 3208 __skb_queue_before(frag_list, skb, cur_frag); 3209 return; 3210 } 3211 __skb_queue_tail(frag_list, cur_frag); 3212 } 3213 3214 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3215 { 3216 struct ieee80211_hdr *hdr; 3217 u64 pn = 0; 3218 u8 *ehdr; 3219 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3220 3221 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3222 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3223 3224 pn = ehdr[0]; 3225 pn |= (u64)ehdr[1] << 8; 3226 pn |= (u64)ehdr[4] << 16; 3227 pn |= (u64)ehdr[5] << 24; 3228 pn |= (u64)ehdr[6] << 32; 3229 pn |= (u64)ehdr[7] << 40; 3230 3231 return pn; 3232 } 3233 3234 static bool 3235 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3236 { 3237 struct ath12k_base *ab = ar->ab; 3238 enum hal_encrypt_type encrypt_type; 3239 struct sk_buff *first_frag, *skb; 3240 struct hal_rx_desc *desc; 3241 u64 last_pn; 3242 u64 cur_pn; 3243 3244 first_frag = skb_peek(&rx_tid->rx_frags); 3245 desc = (struct hal_rx_desc *)first_frag->data; 3246 3247 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3248 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3249 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3250 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3251 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3252 return true; 3253 3254 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3255 skb_queue_walk(&rx_tid->rx_frags, skb) { 3256 if (skb == first_frag) 3257 continue; 3258 3259 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3260 if (cur_pn != last_pn + 1) 3261 return false; 3262 last_pn = cur_pn; 3263 } 3264 return true; 3265 } 3266 3267 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3268 struct sk_buff *msdu, 3269 struct hal_reo_dest_ring *ring_desc) 3270 { 3271 struct ath12k_base *ab = ar->ab; 3272 struct hal_rx_desc *rx_desc; 3273 struct ath12k_peer *peer; 3274 struct ath12k_dp_rx_tid *rx_tid; 3275 struct sk_buff *defrag_skb = NULL; 3276 u32 peer_id; 3277 u16 seqno, frag_no; 3278 u8 tid; 3279 int ret = 0; 3280 bool more_frags; 3281 3282 rx_desc = (struct hal_rx_desc *)msdu->data; 3283 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3284 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3285 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3286 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3287 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3288 3289 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3290 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3291 tid > IEEE80211_NUM_TIDS) 3292 return -EINVAL; 3293 3294 /* received unfragmented packet in reo 3295 * exception ring, this shouldn't happen 3296 * as these packets typically come from 3297 * reo2sw srngs. 3298 */ 3299 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3300 return -EINVAL; 3301 3302 spin_lock_bh(&ab->base_lock); 3303 peer = ath12k_peer_find_by_id(ab, peer_id); 3304 if (!peer) { 3305 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3306 peer_id); 3307 ret = -ENOENT; 3308 goto out_unlock; 3309 } 3310 3311 if (!peer->dp_setup_done) { 3312 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3313 peer->addr, peer_id); 3314 ret = -ENOENT; 3315 goto out_unlock; 3316 } 3317 3318 rx_tid = &peer->rx_tid[tid]; 3319 3320 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3321 skb_queue_empty(&rx_tid->rx_frags)) { 3322 /* Flush stored fragments and start a new sequence */ 3323 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3324 rx_tid->cur_sn = seqno; 3325 } 3326 3327 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3328 /* Fragment already present */ 3329 ret = -EINVAL; 3330 goto out_unlock; 3331 } 3332 3333 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3334 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3335 else 3336 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3337 3338 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3339 if (!more_frags) 3340 rx_tid->last_frag_no = frag_no; 3341 3342 if (frag_no == 0) { 3343 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3344 sizeof(*rx_tid->dst_ring_desc), 3345 GFP_ATOMIC); 3346 if (!rx_tid->dst_ring_desc) { 3347 ret = -ENOMEM; 3348 goto out_unlock; 3349 } 3350 } else { 3351 ath12k_dp_rx_link_desc_return(ab, ring_desc, 3352 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3353 } 3354 3355 if (!rx_tid->last_frag_no || 3356 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3357 mod_timer(&rx_tid->frag_timer, jiffies + 3358 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3359 goto out_unlock; 3360 } 3361 3362 spin_unlock_bh(&ab->base_lock); 3363 del_timer_sync(&rx_tid->frag_timer); 3364 spin_lock_bh(&ab->base_lock); 3365 3366 peer = ath12k_peer_find_by_id(ab, peer_id); 3367 if (!peer) 3368 goto err_frags_cleanup; 3369 3370 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3371 goto err_frags_cleanup; 3372 3373 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3374 goto err_frags_cleanup; 3375 3376 if (!defrag_skb) 3377 goto err_frags_cleanup; 3378 3379 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3380 goto err_frags_cleanup; 3381 3382 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3383 goto out_unlock; 3384 3385 err_frags_cleanup: 3386 dev_kfree_skb_any(defrag_skb); 3387 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3388 out_unlock: 3389 spin_unlock_bh(&ab->base_lock); 3390 return ret; 3391 } 3392 3393 static int 3394 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3395 struct list_head *used_list, 3396 bool drop, u32 cookie) 3397 { 3398 struct ath12k_base *ab = ar->ab; 3399 struct sk_buff *msdu; 3400 struct ath12k_skb_rxcb *rxcb; 3401 struct hal_rx_desc *rx_desc; 3402 u16 msdu_len; 3403 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3404 struct ath12k_rx_desc_info *desc_info; 3405 u64 desc_va; 3406 3407 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3408 le32_to_cpu(desc->buf_va_lo)); 3409 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3410 3411 /* retry manual desc retrieval */ 3412 if (!desc_info) { 3413 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3414 if (!desc_info) { 3415 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n", 3416 cookie); 3417 return -EINVAL; 3418 } 3419 } 3420 3421 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3422 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3423 3424 msdu = desc_info->skb; 3425 desc_info->skb = NULL; 3426 3427 list_add_tail(&desc_info->list, used_list); 3428 3429 rxcb = ATH12K_SKB_RXCB(msdu); 3430 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3431 msdu->len + skb_tailroom(msdu), 3432 DMA_FROM_DEVICE); 3433 3434 if (drop) { 3435 dev_kfree_skb_any(msdu); 3436 return 0; 3437 } 3438 3439 rcu_read_lock(); 3440 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3441 dev_kfree_skb_any(msdu); 3442 goto exit; 3443 } 3444 3445 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3446 dev_kfree_skb_any(msdu); 3447 goto exit; 3448 } 3449 3450 rx_desc = (struct hal_rx_desc *)msdu->data; 3451 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3452 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3453 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3454 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3455 sizeof(*rx_desc)); 3456 dev_kfree_skb_any(msdu); 3457 goto exit; 3458 } 3459 3460 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3461 3462 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3463 dev_kfree_skb_any(msdu); 3464 ath12k_dp_rx_link_desc_return(ar->ab, desc, 3465 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3466 } 3467 exit: 3468 rcu_read_unlock(); 3469 return 0; 3470 } 3471 3472 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3473 int budget) 3474 { 3475 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3476 struct dp_link_desc_bank *link_desc_banks; 3477 enum hal_rx_buf_return_buf_manager rbm; 3478 struct hal_rx_msdu_link *link_desc_va; 3479 int tot_n_bufs_reaped, quota, ret, i; 3480 struct hal_reo_dest_ring *reo_desc; 3481 struct dp_rxdma_ring *rx_ring; 3482 struct dp_srng *reo_except; 3483 LIST_HEAD(rx_desc_used_list); 3484 u32 desc_bank, num_msdus; 3485 struct hal_srng *srng; 3486 struct ath12k_dp *dp; 3487 int mac_id; 3488 struct ath12k *ar; 3489 dma_addr_t paddr; 3490 bool is_frag; 3491 bool drop; 3492 int pdev_id; 3493 3494 tot_n_bufs_reaped = 0; 3495 quota = budget; 3496 3497 dp = &ab->dp; 3498 reo_except = &dp->reo_except_ring; 3499 link_desc_banks = dp->link_desc_banks; 3500 3501 srng = &ab->hal.srng_list[reo_except->ring_id]; 3502 3503 spin_lock_bh(&srng->lock); 3504 3505 ath12k_hal_srng_access_begin(ab, srng); 3506 3507 while (budget && 3508 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3509 drop = false; 3510 ab->soc_stats.err_ring_pkts++; 3511 3512 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3513 &desc_bank); 3514 if (ret) { 3515 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3516 ret); 3517 continue; 3518 } 3519 link_desc_va = link_desc_banks[desc_bank].vaddr + 3520 (paddr - link_desc_banks[desc_bank].paddr); 3521 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3522 &rbm); 3523 if (rbm != dp->idle_link_rbm && 3524 rbm != HAL_RX_BUF_RBM_SW3_BM && 3525 rbm != ab->hw_params->hal_params->rx_buf_rbm) { 3526 ab->soc_stats.invalid_rbm++; 3527 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3528 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3529 HAL_WBM_REL_BM_ACT_REL_MSDU); 3530 continue; 3531 } 3532 3533 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3534 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3535 3536 /* Process only rx fragments with one msdu per link desc below, and drop 3537 * msdu's indicated due to error reasons. 3538 */ 3539 if (!is_frag || num_msdus > 1) { 3540 drop = true; 3541 /* Return the link desc back to wbm idle list */ 3542 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3543 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3544 } 3545 3546 for (i = 0; i < num_msdus; i++) { 3547 mac_id = le32_get_bits(reo_desc->info0, 3548 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3549 3550 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3551 ar = ab->pdevs[pdev_id].ar; 3552 3553 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, 3554 &rx_desc_used_list, 3555 drop, 3556 msdu_cookies[i])) 3557 tot_n_bufs_reaped++; 3558 } 3559 3560 if (tot_n_bufs_reaped >= quota) { 3561 tot_n_bufs_reaped = quota; 3562 goto exit; 3563 } 3564 3565 budget = quota - tot_n_bufs_reaped; 3566 } 3567 3568 exit: 3569 ath12k_hal_srng_access_end(ab, srng); 3570 3571 spin_unlock_bh(&srng->lock); 3572 3573 rx_ring = &dp->rx_refill_buf_ring; 3574 3575 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3576 tot_n_bufs_reaped); 3577 3578 return tot_n_bufs_reaped; 3579 } 3580 3581 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3582 int msdu_len, 3583 struct sk_buff_head *msdu_list) 3584 { 3585 struct sk_buff *skb, *tmp; 3586 struct ath12k_skb_rxcb *rxcb; 3587 int n_buffs; 3588 3589 n_buffs = DIV_ROUND_UP(msdu_len, 3590 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz)); 3591 3592 skb_queue_walk_safe(msdu_list, skb, tmp) { 3593 rxcb = ATH12K_SKB_RXCB(skb); 3594 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3595 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3596 if (!n_buffs) 3597 break; 3598 __skb_unlink(skb, msdu_list); 3599 dev_kfree_skb_any(skb); 3600 n_buffs--; 3601 } 3602 } 3603 } 3604 3605 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 3606 struct ieee80211_rx_status *status, 3607 struct sk_buff_head *msdu_list) 3608 { 3609 struct ath12k_base *ab = ar->ab; 3610 u16 msdu_len; 3611 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3612 u8 l3pad_bytes; 3613 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3614 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3615 3616 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3617 3618 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3619 /* First buffer will be freed by the caller, so deduct it's length */ 3620 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3621 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3622 return -EINVAL; 3623 } 3624 3625 /* Even after cleaning up the sg buffers in the msdu list with above check 3626 * any msdu received with continuation flag needs to be dropped as invalid. 3627 * This protects against some random err frame with continuation flag. 3628 */ 3629 if (rxcb->is_continuation) 3630 return -EINVAL; 3631 3632 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 3633 ath12k_warn(ar->ab, 3634 "msdu_done bit not set in null_q_des processing\n"); 3635 __skb_queue_purge(msdu_list); 3636 return -EIO; 3637 } 3638 3639 /* Handle NULL queue descriptor violations arising out a missing 3640 * REO queue for a given peer or a given TID. This typically 3641 * may happen if a packet is received on a QOS enabled TID before the 3642 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3643 * it may also happen for MC/BC frames if they are not routed to the 3644 * non-QOS TID queue, in the absence of any other default TID queue. 3645 * This error can show up both in a REO destination or WBM release ring. 3646 */ 3647 3648 if (rxcb->is_frag) { 3649 skb_pull(msdu, hal_rx_desc_sz); 3650 } else { 3651 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3652 3653 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3654 return -EINVAL; 3655 3656 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3657 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3658 } 3659 ath12k_dp_rx_h_ppdu(ar, desc, status); 3660 3661 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status); 3662 3663 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc); 3664 3665 /* Please note that caller will having the access to msdu and completing 3666 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3667 */ 3668 3669 return 0; 3670 } 3671 3672 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 3673 struct ieee80211_rx_status *status, 3674 struct sk_buff_head *msdu_list) 3675 { 3676 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3677 bool drop = false; 3678 3679 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3680 3681 switch (rxcb->err_code) { 3682 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3683 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3684 drop = true; 3685 break; 3686 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3687 /* TODO: Do not drop PN failed packets in the driver; 3688 * instead, it is good to drop such packets in mac80211 3689 * after incrementing the replay counters. 3690 */ 3691 fallthrough; 3692 default: 3693 /* TODO: Review other errors and process them to mac80211 3694 * as appropriate. 3695 */ 3696 drop = true; 3697 break; 3698 } 3699 3700 return drop; 3701 } 3702 3703 static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 3704 struct ieee80211_rx_status *status) 3705 { 3706 struct ath12k_base *ab = ar->ab; 3707 u16 msdu_len; 3708 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3709 u8 l3pad_bytes; 3710 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3711 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3712 3713 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 3714 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 3715 3716 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3717 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3718 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3719 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3720 3721 ath12k_dp_rx_h_ppdu(ar, desc, status); 3722 3723 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3724 RX_FLAG_DECRYPTED); 3725 3726 ath12k_dp_rx_h_undecap(ar, msdu, desc, 3727 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3728 } 3729 3730 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 3731 struct ieee80211_rx_status *status) 3732 { 3733 struct ath12k_base *ab = ar->ab; 3734 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3735 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3736 bool drop = false; 3737 u32 err_bitmap; 3738 3739 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3740 3741 switch (rxcb->err_code) { 3742 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 3743 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3744 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 3745 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 3746 ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3747 break; 3748 } 3749 fallthrough; 3750 default: 3751 /* TODO: Review other rxdma error code to check if anything is 3752 * worth reporting to mac80211 3753 */ 3754 drop = true; 3755 break; 3756 } 3757 3758 return drop; 3759 } 3760 3761 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 3762 struct napi_struct *napi, 3763 struct sk_buff *msdu, 3764 struct sk_buff_head *msdu_list) 3765 { 3766 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3767 struct ieee80211_rx_status rxs = {0}; 3768 bool drop = true; 3769 3770 switch (rxcb->err_rel_src) { 3771 case HAL_WBM_REL_SRC_MODULE_REO: 3772 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3773 break; 3774 case HAL_WBM_REL_SRC_MODULE_RXDMA: 3775 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3776 break; 3777 default: 3778 /* msdu will get freed */ 3779 break; 3780 } 3781 3782 if (drop) { 3783 dev_kfree_skb_any(msdu); 3784 return; 3785 } 3786 3787 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 3788 } 3789 3790 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 3791 struct napi_struct *napi, int budget) 3792 { 3793 LIST_HEAD(rx_desc_used_list); 3794 struct ath12k *ar; 3795 struct ath12k_dp *dp = &ab->dp; 3796 struct dp_rxdma_ring *rx_ring; 3797 struct hal_rx_wbm_rel_info err_info; 3798 struct hal_srng *srng; 3799 struct sk_buff *msdu; 3800 struct sk_buff_head msdu_list, scatter_msdu_list; 3801 struct ath12k_skb_rxcb *rxcb; 3802 void *rx_desc; 3803 u8 mac_id; 3804 int num_buffs_reaped = 0; 3805 struct ath12k_rx_desc_info *desc_info; 3806 int ret, pdev_id; 3807 struct hal_rx_desc *msdu_data; 3808 3809 __skb_queue_head_init(&msdu_list); 3810 __skb_queue_head_init(&scatter_msdu_list); 3811 3812 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3813 rx_ring = &dp->rx_refill_buf_ring; 3814 spin_lock_bh(&srng->lock); 3815 3816 ath12k_hal_srng_access_begin(ab, srng); 3817 3818 while (budget) { 3819 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 3820 if (!rx_desc) 3821 break; 3822 3823 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3824 if (ret) { 3825 ath12k_warn(ab, 3826 "failed to parse rx error in wbm_rel ring desc %d\n", 3827 ret); 3828 continue; 3829 } 3830 3831 desc_info = err_info.rx_desc; 3832 3833 /* retry manual desc retrieval if hw cc is not done */ 3834 if (!desc_info) { 3835 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 3836 if (!desc_info) { 3837 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n", 3838 err_info.cookie); 3839 continue; 3840 } 3841 } 3842 3843 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3844 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 3845 3846 msdu = desc_info->skb; 3847 desc_info->skb = NULL; 3848 3849 list_add_tail(&desc_info->list, &rx_desc_used_list); 3850 3851 rxcb = ATH12K_SKB_RXCB(msdu); 3852 dma_unmap_single(ab->dev, rxcb->paddr, 3853 msdu->len + skb_tailroom(msdu), 3854 DMA_FROM_DEVICE); 3855 3856 num_buffs_reaped++; 3857 3858 if (!err_info.continuation) 3859 budget--; 3860 3861 if (err_info.push_reason != 3862 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3863 dev_kfree_skb_any(msdu); 3864 continue; 3865 } 3866 3867 msdu_data = (struct hal_rx_desc *)msdu->data; 3868 rxcb->err_rel_src = err_info.err_rel_src; 3869 rxcb->err_code = err_info.err_code; 3870 rxcb->is_first_msdu = err_info.first_msdu; 3871 rxcb->is_last_msdu = err_info.last_msdu; 3872 rxcb->is_continuation = err_info.continuation; 3873 rxcb->rx_desc = msdu_data; 3874 3875 if (err_info.continuation) { 3876 __skb_queue_tail(&scatter_msdu_list, msdu); 3877 continue; 3878 } 3879 3880 mac_id = ath12k_dp_rx_get_msdu_src_link(ab, 3881 msdu_data); 3882 if (mac_id >= MAX_RADIOS) { 3883 dev_kfree_skb_any(msdu); 3884 3885 /* In any case continuation bit is set 3886 * in the previous record, cleanup scatter_msdu_list 3887 */ 3888 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 3889 continue; 3890 } 3891 3892 if (!skb_queue_empty(&scatter_msdu_list)) { 3893 struct sk_buff *msdu; 3894 3895 skb_queue_walk(&scatter_msdu_list, msdu) { 3896 rxcb = ATH12K_SKB_RXCB(msdu); 3897 rxcb->mac_id = mac_id; 3898 } 3899 3900 skb_queue_splice_tail_init(&scatter_msdu_list, 3901 &msdu_list); 3902 } 3903 3904 rxcb = ATH12K_SKB_RXCB(msdu); 3905 rxcb->mac_id = mac_id; 3906 __skb_queue_tail(&msdu_list, msdu); 3907 } 3908 3909 /* In any case continuation bit is set in the 3910 * last record, cleanup scatter_msdu_list 3911 */ 3912 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 3913 3914 ath12k_hal_srng_access_end(ab, srng); 3915 3916 spin_unlock_bh(&srng->lock); 3917 3918 if (!num_buffs_reaped) 3919 goto done; 3920 3921 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3922 num_buffs_reaped); 3923 3924 rcu_read_lock(); 3925 while ((msdu = __skb_dequeue(&msdu_list))) { 3926 rxcb = ATH12K_SKB_RXCB(msdu); 3927 mac_id = rxcb->mac_id; 3928 3929 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3930 ar = ab->pdevs[pdev_id].ar; 3931 3932 if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) { 3933 dev_kfree_skb_any(msdu); 3934 continue; 3935 } 3936 3937 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3938 dev_kfree_skb_any(msdu); 3939 continue; 3940 } 3941 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); 3942 } 3943 rcu_read_unlock(); 3944 done: 3945 return num_buffs_reaped; 3946 } 3947 3948 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 3949 { 3950 struct ath12k_dp *dp = &ab->dp; 3951 struct hal_tlv_64_hdr *hdr; 3952 struct hal_srng *srng; 3953 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 3954 bool found = false; 3955 u16 tag; 3956 struct hal_reo_status reo_status; 3957 3958 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 3959 3960 memset(&reo_status, 0, sizeof(reo_status)); 3961 3962 spin_lock_bh(&srng->lock); 3963 3964 ath12k_hal_srng_access_begin(ab, srng); 3965 3966 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3967 tag = le64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 3968 3969 switch (tag) { 3970 case HAL_REO_GET_QUEUE_STATS_STATUS: 3971 ath12k_hal_reo_status_queue_stats(ab, hdr, 3972 &reo_status); 3973 break; 3974 case HAL_REO_FLUSH_QUEUE_STATUS: 3975 ath12k_hal_reo_flush_queue_status(ab, hdr, 3976 &reo_status); 3977 break; 3978 case HAL_REO_FLUSH_CACHE_STATUS: 3979 ath12k_hal_reo_flush_cache_status(ab, hdr, 3980 &reo_status); 3981 break; 3982 case HAL_REO_UNBLOCK_CACHE_STATUS: 3983 ath12k_hal_reo_unblk_cache_status(ab, hdr, 3984 &reo_status); 3985 break; 3986 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 3987 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 3988 &reo_status); 3989 break; 3990 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 3991 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 3992 &reo_status); 3993 break; 3994 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 3995 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 3996 &reo_status); 3997 break; 3998 default: 3999 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 4000 continue; 4001 } 4002 4003 spin_lock_bh(&dp->reo_cmd_lock); 4004 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4005 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4006 found = true; 4007 list_del(&cmd->list); 4008 break; 4009 } 4010 } 4011 spin_unlock_bh(&dp->reo_cmd_lock); 4012 4013 if (found) { 4014 cmd->handler(dp, (void *)&cmd->data, 4015 reo_status.uniform_hdr.cmd_status); 4016 kfree(cmd); 4017 } 4018 4019 found = false; 4020 } 4021 4022 ath12k_hal_srng_access_end(ab, srng); 4023 4024 spin_unlock_bh(&srng->lock); 4025 } 4026 4027 void ath12k_dp_rx_free(struct ath12k_base *ab) 4028 { 4029 struct ath12k_dp *dp = &ab->dp; 4030 int i; 4031 4032 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 4033 4034 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4035 if (ab->hw_params->rx_mac_buf_ring) 4036 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 4037 } 4038 4039 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 4040 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 4041 4042 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 4043 4044 ath12k_dp_rxdma_buf_free(ab); 4045 } 4046 4047 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 4048 { 4049 struct ath12k *ar = ab->pdevs[mac_id].ar; 4050 4051 ath12k_dp_rx_pdev_srng_free(ar); 4052 } 4053 4054 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 4055 { 4056 struct ath12k_dp *dp = &ab->dp; 4057 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4058 u32 ring_id; 4059 int ret; 4060 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4061 4062 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4063 4064 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4065 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4066 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4067 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4068 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4069 tlv_filter.offset_valid = true; 4070 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4071 4072 tlv_filter.rx_mpdu_start_offset = 4073 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4074 tlv_filter.rx_msdu_end_offset = 4075 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4076 4077 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 4078 tlv_filter.rx_mpdu_start_wmask = 4079 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); 4080 tlv_filter.rx_msdu_end_wmask = 4081 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); 4082 ath12k_dbg(ab, ATH12K_DBG_DATA, 4083 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", 4084 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); 4085 } 4086 4087 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 4088 HAL_RXDMA_BUF, 4089 DP_RXDMA_REFILL_RING_SIZE, 4090 &tlv_filter); 4091 4092 return ret; 4093 } 4094 4095 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 4096 { 4097 struct ath12k_dp *dp = &ab->dp; 4098 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4099 u32 ring_id; 4100 int ret = 0; 4101 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4102 int i; 4103 4104 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4105 4106 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4107 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4108 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4109 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4110 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4111 tlv_filter.offset_valid = true; 4112 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4113 4114 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4115 4116 tlv_filter.rx_mpdu_start_offset = 4117 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4118 tlv_filter.rx_msdu_end_offset = 4119 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4120 4121 /* TODO: Selectively subscribe to required qwords within msdu_end 4122 * and mpdu_start and setup the mask in below msg 4123 * and modify the rx_desc struct 4124 */ 4125 4126 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4127 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4128 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4129 HAL_RXDMA_BUF, 4130 DP_RXDMA_REFILL_RING_SIZE, 4131 &tlv_filter); 4132 } 4133 4134 return ret; 4135 } 4136 4137 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4138 { 4139 struct ath12k_dp *dp = &ab->dp; 4140 u32 ring_id; 4141 int i, ret; 4142 4143 /* TODO: Need to verify the HTT setup for QCN9224 */ 4144 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4145 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4146 if (ret) { 4147 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4148 ret); 4149 return ret; 4150 } 4151 4152 if (ab->hw_params->rx_mac_buf_ring) { 4153 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4154 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4155 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4156 i, HAL_RXDMA_BUF); 4157 if (ret) { 4158 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4159 i, ret); 4160 return ret; 4161 } 4162 } 4163 } 4164 4165 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4166 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4167 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4168 i, HAL_RXDMA_DST); 4169 if (ret) { 4170 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4171 i, ret); 4172 return ret; 4173 } 4174 } 4175 4176 if (ab->hw_params->rxdma1_enable) { 4177 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4178 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4179 0, HAL_RXDMA_MONITOR_BUF); 4180 if (ret) { 4181 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4182 ret); 4183 return ret; 4184 } 4185 } 4186 4187 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4188 if (ret) { 4189 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4190 return ret; 4191 } 4192 4193 return 0; 4194 } 4195 4196 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4197 { 4198 struct ath12k_dp *dp = &ab->dp; 4199 int i, ret; 4200 4201 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4202 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4203 4204 ret = ath12k_dp_srng_setup(ab, 4205 &dp->rx_refill_buf_ring.refill_buf_ring, 4206 HAL_RXDMA_BUF, 0, 0, 4207 DP_RXDMA_BUF_RING_SIZE); 4208 if (ret) { 4209 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4210 return ret; 4211 } 4212 4213 if (ab->hw_params->rx_mac_buf_ring) { 4214 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4215 ret = ath12k_dp_srng_setup(ab, 4216 &dp->rx_mac_buf_ring[i], 4217 HAL_RXDMA_BUF, 1, 4218 i, DP_RX_MAC_BUF_RING_SIZE); 4219 if (ret) { 4220 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4221 i); 4222 return ret; 4223 } 4224 } 4225 } 4226 4227 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4228 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4229 HAL_RXDMA_DST, 0, i, 4230 DP_RXDMA_ERR_DST_RING_SIZE); 4231 if (ret) { 4232 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4233 return ret; 4234 } 4235 } 4236 4237 if (ab->hw_params->rxdma1_enable) { 4238 ret = ath12k_dp_srng_setup(ab, 4239 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4240 HAL_RXDMA_MONITOR_BUF, 0, 0, 4241 DP_RXDMA_MONITOR_BUF_RING_SIZE); 4242 if (ret) { 4243 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4244 return ret; 4245 } 4246 } 4247 4248 ret = ath12k_dp_rxdma_buf_setup(ab); 4249 if (ret) { 4250 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4251 return ret; 4252 } 4253 4254 return 0; 4255 } 4256 4257 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4258 { 4259 struct ath12k *ar = ab->pdevs[mac_id].ar; 4260 struct ath12k_pdev_dp *dp = &ar->dp; 4261 u32 ring_id; 4262 int i; 4263 int ret; 4264 4265 if (!ab->hw_params->rxdma1_enable) 4266 goto out; 4267 4268 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4269 if (ret) { 4270 ath12k_warn(ab, "failed to setup rx srngs\n"); 4271 return ret; 4272 } 4273 4274 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4275 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4276 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4277 mac_id + i, 4278 HAL_RXDMA_MONITOR_DST); 4279 if (ret) { 4280 ath12k_warn(ab, 4281 "failed to configure rxdma_mon_dst_ring %d %d\n", 4282 i, ret); 4283 return ret; 4284 } 4285 } 4286 out: 4287 return 0; 4288 } 4289 4290 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4291 { 4292 struct ath12k_pdev_dp *dp = &ar->dp; 4293 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4294 4295 skb_queue_head_init(&pmon->rx_status_q); 4296 4297 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4298 4299 memset(&pmon->rx_mon_stats, 0, 4300 sizeof(pmon->rx_mon_stats)); 4301 return 0; 4302 } 4303 4304 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4305 { 4306 struct ath12k_pdev_dp *dp = &ar->dp; 4307 struct ath12k_mon_data *pmon = &dp->mon_data; 4308 int ret = 0; 4309 4310 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4311 if (ret) { 4312 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4313 return ret; 4314 } 4315 4316 /* if rxdma1_enable is false, no need to setup 4317 * rxdma_mon_desc_ring. 4318 */ 4319 if (!ar->ab->hw_params->rxdma1_enable) 4320 return 0; 4321 4322 pmon->mon_last_linkdesc_paddr = 0; 4323 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4324 spin_lock_init(&pmon->mon_lock); 4325 4326 return 0; 4327 } 4328