1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/fips.h> 8 #include <linux/ieee80211.h> 9 #include <linux/kernel.h> 10 #include <linux/skbuff.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hw.h" 14 #include "dp_rx.h" 15 #include "dp_tx.h" 16 #include "peer.h" 17 #include "dp_mon.h" 18 #include "debugfs_htt_stats.h" 19 20 #define ATH12K_2GHZ_MIN_CHAN_NUM 1 21 #define ATH12K_2GHZ_MAX_CHAN_NUM 14 22 #define ATH12K_5GHZ_MIN_CHAN_NUM 36 23 #define ATH12K_5GHZ_MAX_CHAN_NUM 177 24 25 static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 26 struct ath12k_dp_rx_tid_rxq *rx_tid); 27 28 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 29 struct list_head *head, 30 size_t count) 31 { 32 struct list_head *cur; 33 struct ath12k_rx_desc_info *rx_desc; 34 size_t nodes = 0; 35 36 if (!count) { 37 INIT_LIST_HEAD(list); 38 goto out; 39 } 40 41 list_for_each(cur, head) { 42 if (!count) 43 break; 44 45 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 46 rx_desc->in_use = true; 47 48 count--; 49 nodes++; 50 } 51 52 list_cut_before(list, head, cur); 53 out: 54 return nodes; 55 } 56 57 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 58 struct list_head *used_list) 59 { 60 struct ath12k_rx_desc_info *rx_desc, *safe; 61 62 /* Reset the use flag */ 63 list_for_each_entry_safe(rx_desc, safe, used_list, list) 64 rx_desc->in_use = false; 65 66 spin_lock_bh(&dp->rx_desc_lock); 67 list_splice_tail(used_list, &dp->rx_desc_free_list); 68 spin_unlock_bh(&dp->rx_desc_lock); 69 } 70 71 /* Returns number of Rx buffers replenished */ 72 int ath12k_dp_rx_bufs_replenish(struct ath12k_dp *dp, 73 struct dp_rxdma_ring *rx_ring, 74 struct list_head *used_list, 75 int req_entries) 76 { 77 struct ath12k_base *ab = dp->ab; 78 struct ath12k_buffer_addr *desc; 79 struct hal_srng *srng; 80 struct sk_buff *skb; 81 int num_free; 82 int num_remain; 83 u32 cookie; 84 dma_addr_t paddr; 85 struct ath12k_rx_desc_info *rx_desc; 86 enum hal_rx_buf_return_buf_manager mgr = dp->hal->hal_params->rx_buf_rbm; 87 88 req_entries = min(req_entries, rx_ring->bufs_max); 89 90 srng = &dp->hal->srng_list[rx_ring->refill_buf_ring.ring_id]; 91 92 spin_lock_bh(&srng->lock); 93 94 ath12k_hal_srng_access_begin(ab, srng); 95 96 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 97 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 98 req_entries = num_free; 99 100 req_entries = min(num_free, req_entries); 101 num_remain = req_entries; 102 103 if (!num_remain) 104 goto out; 105 106 /* Get the descriptor from free list */ 107 if (list_empty(used_list)) { 108 spin_lock_bh(&dp->rx_desc_lock); 109 req_entries = ath12k_dp_list_cut_nodes(used_list, 110 &dp->rx_desc_free_list, 111 num_remain); 112 spin_unlock_bh(&dp->rx_desc_lock); 113 num_remain = req_entries; 114 } 115 116 while (num_remain > 0) { 117 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 118 DP_RX_BUFFER_ALIGN_SIZE); 119 if (!skb) 120 break; 121 122 if (!IS_ALIGNED((unsigned long)skb->data, 123 DP_RX_BUFFER_ALIGN_SIZE)) { 124 skb_pull(skb, 125 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 126 skb->data); 127 } 128 129 paddr = dma_map_single(dp->dev, skb->data, 130 skb->len + skb_tailroom(skb), 131 DMA_FROM_DEVICE); 132 if (dma_mapping_error(dp->dev, paddr)) 133 goto fail_free_skb; 134 135 rx_desc = list_first_entry_or_null(used_list, 136 struct ath12k_rx_desc_info, 137 list); 138 if (!rx_desc) 139 goto fail_dma_unmap; 140 141 rx_desc->skb = skb; 142 cookie = rx_desc->cookie; 143 144 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 145 if (!desc) 146 goto fail_dma_unmap; 147 148 list_del(&rx_desc->list); 149 ATH12K_SKB_RXCB(skb)->paddr = paddr; 150 151 num_remain--; 152 153 ath12k_hal_rx_buf_addr_info_set(dp->hal, desc, paddr, cookie, 154 mgr); 155 } 156 157 goto out; 158 159 fail_dma_unmap: 160 dma_unmap_single(dp->dev, paddr, skb->len + skb_tailroom(skb), 161 DMA_FROM_DEVICE); 162 fail_free_skb: 163 dev_kfree_skb_any(skb); 164 out: 165 ath12k_hal_srng_access_end(ab, srng); 166 167 if (!list_empty(used_list)) 168 ath12k_dp_rx_enqueue_free(dp, used_list); 169 170 spin_unlock_bh(&srng->lock); 171 172 return req_entries - num_remain; 173 } 174 EXPORT_SYMBOL(ath12k_dp_rx_bufs_replenish); 175 176 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 177 struct dp_rxdma_mon_ring *rx_ring) 178 { 179 struct sk_buff *skb; 180 int buf_id; 181 182 spin_lock_bh(&rx_ring->idr_lock); 183 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 184 idr_remove(&rx_ring->bufs_idr, buf_id); 185 /* TODO: Understand where internal driver does this dma_unmap 186 * of rxdma_buffer. 187 */ 188 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 189 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 190 dev_kfree_skb_any(skb); 191 } 192 193 idr_destroy(&rx_ring->bufs_idr); 194 spin_unlock_bh(&rx_ring->idr_lock); 195 196 return 0; 197 } 198 199 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 200 { 201 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 202 int i; 203 204 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 205 206 if (ab->hw_params->rxdma1_enable) 207 return 0; 208 209 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 210 ath12k_dp_rxdma_mon_buf_ring_free(ab, 211 &dp->rx_mon_status_refill_ring[i]); 212 213 return 0; 214 } 215 216 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 217 struct dp_rxdma_mon_ring *rx_ring, 218 u32 ringtype) 219 { 220 int num_entries; 221 222 num_entries = rx_ring->refill_buf_ring.size / 223 ath12k_hal_srng_get_entrysize(ab, ringtype); 224 225 rx_ring->bufs_max = num_entries; 226 227 if (ringtype == HAL_RXDMA_MONITOR_STATUS) 228 ath12k_dp_mon_status_bufs_replenish(ab, rx_ring, 229 num_entries); 230 else 231 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 232 233 return 0; 234 } 235 236 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 237 struct dp_rxdma_ring *rx_ring) 238 { 239 LIST_HEAD(list); 240 241 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 242 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 243 244 ath12k_dp_rx_bufs_replenish(ath12k_ab_to_dp(ab), rx_ring, &list, 0); 245 246 return 0; 247 } 248 249 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 250 { 251 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 252 struct dp_rxdma_mon_ring *mon_ring; 253 int ret, i; 254 255 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 256 if (ret) { 257 ath12k_warn(ab, 258 "failed to setup HAL_RXDMA_BUF\n"); 259 return ret; 260 } 261 262 if (ab->hw_params->rxdma1_enable) { 263 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 264 &dp->rxdma_mon_buf_ring, 265 HAL_RXDMA_MONITOR_BUF); 266 if (ret) 267 ath12k_warn(ab, 268 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 269 return ret; 270 } 271 272 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 273 mon_ring = &dp->rx_mon_status_refill_ring[i]; 274 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, mon_ring, 275 HAL_RXDMA_MONITOR_STATUS); 276 if (ret) { 277 ath12k_warn(ab, 278 "failed to setup HAL_RXDMA_MONITOR_STATUS\n"); 279 return ret; 280 } 281 } 282 283 return 0; 284 } 285 286 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 287 { 288 struct ath12k_pdev_dp *dp = &ar->dp; 289 struct ath12k_base *ab = ar->ab; 290 int i; 291 292 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 293 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 294 } 295 296 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 297 { 298 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 299 int i; 300 301 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 302 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 303 } 304 305 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 306 { 307 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 308 int ret; 309 int i; 310 311 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 312 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 313 HAL_REO_DST, i, 0, 314 DP_REO_DST_RING_SIZE); 315 if (ret) { 316 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 317 goto err_reo_cleanup; 318 } 319 } 320 321 return 0; 322 323 err_reo_cleanup: 324 ath12k_dp_rx_pdev_reo_cleanup(ab); 325 326 return ret; 327 } 328 329 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 330 { 331 struct ath12k_pdev_dp *dp = &ar->dp; 332 struct ath12k_base *ab = ar->ab; 333 int i; 334 int ret; 335 u32 mac_id = dp->mac_id; 336 337 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 338 ret = ath12k_dp_srng_setup(ar->ab, 339 &dp->rxdma_mon_dst_ring[i], 340 HAL_RXDMA_MONITOR_DST, 341 0, mac_id + i, 342 DP_RXDMA_MONITOR_DST_RING_SIZE(ab)); 343 if (ret) { 344 ath12k_warn(ar->ab, 345 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 346 return ret; 347 } 348 } 349 350 return 0; 351 } 352 353 void ath12k_dp_init_rx_tid_rxq(struct ath12k_dp_rx_tid_rxq *rx_tid_rxq, 354 struct ath12k_dp_rx_tid *rx_tid, 355 bool active) 356 { 357 rx_tid_rxq->tid = rx_tid->tid; 358 rx_tid_rxq->active = active; 359 rx_tid_rxq->qbuf = rx_tid->qbuf; 360 } 361 EXPORT_SYMBOL(ath12k_dp_init_rx_tid_rxq); 362 363 static void ath12k_dp_rx_tid_cleanup(struct ath12k_base *ab, 364 struct ath12k_reoq_buf *tid_qbuf) 365 { 366 if (tid_qbuf->vaddr) { 367 dma_unmap_single(ab->dev, tid_qbuf->paddr_aligned, 368 tid_qbuf->size, DMA_BIDIRECTIONAL); 369 kfree(tid_qbuf->vaddr); 370 tid_qbuf->vaddr = NULL; 371 } 372 } 373 374 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 375 { 376 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 377 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 378 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 379 struct dp_reo_update_rx_queue_elem *cmd_queue, *tmp_queue; 380 381 spin_lock_bh(&dp->reo_rxq_flush_lock); 382 list_for_each_entry_safe(cmd_queue, tmp_queue, &dp->reo_cmd_update_rx_queue_list, 383 list) { 384 list_del(&cmd_queue->list); 385 ath12k_dp_rx_tid_cleanup(ab, &cmd_queue->rx_tid.qbuf); 386 kfree(cmd_queue); 387 } 388 list_for_each_entry_safe(cmd_cache, tmp_cache, 389 &dp->reo_cmd_cache_flush_list, list) { 390 list_del(&cmd_cache->list); 391 dp->reo_cmd_cache_flush_count--; 392 ath12k_dp_rx_tid_cleanup(ab, &cmd_cache->data.qbuf); 393 kfree(cmd_cache); 394 } 395 spin_unlock_bh(&dp->reo_rxq_flush_lock); 396 397 spin_lock_bh(&dp->reo_cmd_lock); 398 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 399 list_del(&cmd->list); 400 ath12k_dp_rx_tid_cleanup(ab, &cmd->data.qbuf); 401 kfree(cmd); 402 } 403 spin_unlock_bh(&dp->reo_cmd_lock); 404 } 405 406 void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 407 enum hal_reo_cmd_status status) 408 { 409 struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 410 411 if (status != HAL_REO_CMD_SUCCESS) 412 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 413 rx_tid->tid, status); 414 415 ath12k_dp_rx_tid_cleanup(dp->ab, &rx_tid->qbuf); 416 } 417 EXPORT_SYMBOL(ath12k_dp_reo_cmd_free); 418 419 void ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(struct ath12k_dp *dp) 420 { 421 struct ath12k_base *ab = dp->ab; 422 struct dp_reo_update_rx_queue_elem *elem, *tmp; 423 424 spin_lock_bh(&dp->reo_rxq_flush_lock); 425 426 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_update_rx_queue_list, list) { 427 if (elem->rx_tid.active) 428 continue; 429 430 if (ath12k_dp_rx_tid_delete_handler(ab, &elem->rx_tid)) 431 break; 432 433 ath12k_dp_arch_peer_rx_tid_qref_reset(dp, 434 elem->is_ml_peer ? 435 elem->ml_peer_id : elem->peer_id, 436 elem->rx_tid.tid); 437 438 if (ab->hw_params->reoq_lut_support) 439 ath12k_hal_reo_shared_qaddr_cache_clear(ab); 440 441 list_del(&elem->list); 442 kfree(elem); 443 } 444 445 spin_unlock_bh(&dp->reo_rxq_flush_lock); 446 } 447 EXPORT_SYMBOL(ath12k_dp_rx_process_reo_cmd_update_rx_queue_list); 448 449 void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 450 enum hal_reo_cmd_status status) 451 { 452 struct ath12k_base *ab = dp->ab; 453 struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 454 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 455 456 if (status == HAL_REO_CMD_DRAIN) { 457 goto free_desc; 458 } else if (status != HAL_REO_CMD_SUCCESS) { 459 /* Shouldn't happen! Cleanup in case of other failure? */ 460 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 461 rx_tid->tid, status); 462 return; 463 } 464 465 /* Retry the HAL_REO_CMD_UPDATE_RX_QUEUE command for entries 466 * in the pending queue list marked TID as inactive 467 */ 468 spin_lock_bh(&dp->dp_lock); 469 ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(dp); 470 spin_unlock_bh(&dp->dp_lock); 471 472 elem = kzalloc_obj(*elem, GFP_ATOMIC); 473 if (!elem) 474 goto free_desc; 475 476 elem->ts = jiffies; 477 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 478 479 spin_lock_bh(&dp->reo_rxq_flush_lock); 480 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 481 dp->reo_cmd_cache_flush_count++; 482 483 /* Flush and invalidate aged REO desc from HW cache */ 484 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 485 list) { 486 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 487 time_after(jiffies, elem->ts + 488 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 489 /* The reo_cmd_cache_flush_list is used in only two contexts, 490 * one is in this function called from napi and the 491 * other in ath12k_dp_free during core destroy. 492 * If cache command sent is success, delete the element in 493 * the cache list. ath12k_dp_rx_reo_cmd_list_cleanup 494 * will be called during core destroy. 495 */ 496 497 if (ath12k_dp_arch_reo_cache_flush(dp, &elem->data)) 498 break; 499 500 list_del(&elem->list); 501 dp->reo_cmd_cache_flush_count--; 502 503 kfree(elem); 504 } 505 } 506 spin_unlock_bh(&dp->reo_rxq_flush_lock); 507 508 return; 509 free_desc: 510 ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 511 } 512 EXPORT_SYMBOL(ath12k_dp_rx_tid_del_func); 513 514 static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 515 struct ath12k_dp_rx_tid_rxq *rx_tid) 516 { 517 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 518 519 return ath12k_dp_arch_rx_tid_delete_handler(dp, rx_tid); 520 } 521 522 void ath12k_dp_mark_tid_as_inactive(struct ath12k_dp *dp, int peer_id, u8 tid) 523 { 524 struct dp_reo_update_rx_queue_elem *elem; 525 struct ath12k_dp_rx_tid_rxq *rx_tid; 526 527 spin_lock_bh(&dp->reo_rxq_flush_lock); 528 list_for_each_entry(elem, &dp->reo_cmd_update_rx_queue_list, list) { 529 if (elem->peer_id == peer_id) { 530 rx_tid = &elem->rx_tid; 531 if (rx_tid->tid == tid) { 532 rx_tid->active = false; 533 break; 534 } 535 } 536 } 537 spin_unlock_bh(&dp->reo_rxq_flush_lock); 538 } 539 EXPORT_SYMBOL(ath12k_dp_mark_tid_as_inactive); 540 541 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_dp_link_peer *peer) 542 { 543 struct ath12k_dp_rx_tid *rx_tid; 544 int i; 545 struct ath12k_base *ab = ar->ab; 546 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 547 548 lockdep_assert_held(&dp->dp_lock); 549 550 if (!peer->primary_link) 551 return; 552 553 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 554 rx_tid = &peer->dp_peer->rx_tid[i]; 555 556 ath12k_dp_arch_rx_peer_tid_delete(dp, peer, i); 557 ath12k_dp_arch_rx_frags_cleanup(dp, rx_tid, true); 558 559 spin_unlock_bh(&dp->dp_lock); 560 timer_delete_sync(&rx_tid->frag_timer); 561 spin_lock_bh(&dp->dp_lock); 562 } 563 } 564 565 static int ath12k_dp_prepare_reo_update_elem(struct ath12k_dp *dp, 566 struct ath12k_dp_link_peer *peer, 567 struct ath12k_dp_rx_tid *rx_tid) 568 { 569 struct dp_reo_update_rx_queue_elem *elem; 570 571 lockdep_assert_held(&dp->dp_lock); 572 573 if (!peer->primary_link) 574 return 0; 575 576 elem = kzalloc_obj(*elem, GFP_ATOMIC); 577 if (!elem) 578 return -ENOMEM; 579 580 elem->peer_id = peer->peer_id; 581 elem->is_ml_peer = peer->mlo; 582 elem->ml_peer_id = peer->ml_id; 583 584 ath12k_dp_init_rx_tid_rxq(&elem->rx_tid, rx_tid, 585 (peer->rx_tid_active_bitmask & (1 << rx_tid->tid))); 586 587 spin_lock_bh(&dp->reo_rxq_flush_lock); 588 list_add_tail(&elem->list, &dp->reo_cmd_update_rx_queue_list); 589 spin_unlock_bh(&dp->reo_rxq_flush_lock); 590 591 return 0; 592 } 593 594 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 595 u8 tid, u32 ba_win_sz, u16 ssn, 596 enum hal_pn_type pn_type) 597 { 598 struct ath12k_base *ab = ar->ab; 599 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 600 struct ath12k_dp_link_peer *peer; 601 struct ath12k_dp_rx_tid *rx_tid; 602 dma_addr_t paddr_aligned; 603 int ret; 604 605 spin_lock_bh(&dp->dp_lock); 606 607 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, peer_mac); 608 if (!peer || !peer->dp_peer) { 609 spin_unlock_bh(&dp->dp_lock); 610 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 611 return -ENOENT; 612 } 613 614 if (ab->hw_params->dp_primary_link_only && 615 !peer->primary_link) { 616 spin_unlock_bh(&dp->dp_lock); 617 return 0; 618 } 619 620 if (ab->hw_params->reoq_lut_support && 621 (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) { 622 spin_unlock_bh(&dp->dp_lock); 623 ath12k_warn(ab, "reo qref table is not setup\n"); 624 return -EINVAL; 625 } 626 627 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 628 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 629 peer->peer_id, tid); 630 spin_unlock_bh(&dp->dp_lock); 631 return -EINVAL; 632 } 633 634 rx_tid = &peer->dp_peer->rx_tid[tid]; 635 /* Update the tid queue if it is already setup */ 636 if (peer->rx_tid_active_bitmask & (1 << tid)) { 637 ret = ath12k_dp_arch_peer_rx_tid_reo_update(dp, peer, rx_tid, 638 ba_win_sz, ssn, true); 639 spin_unlock_bh(&dp->dp_lock); 640 if (ret) { 641 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 642 return ret; 643 } 644 645 if (!ab->hw_params->reoq_lut_support) { 646 paddr_aligned = rx_tid->qbuf.paddr_aligned; 647 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 648 peer_mac, 649 paddr_aligned, tid, 650 1, ba_win_sz); 651 if (ret) { 652 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 653 tid, ret); 654 return ret; 655 } 656 } 657 658 return 0; 659 } 660 661 rx_tid->tid = tid; 662 663 rx_tid->ba_win_sz = ba_win_sz; 664 665 ret = ath12k_dp_arch_rx_assign_reoq(dp, peer->dp_peer, rx_tid, ssn, pn_type); 666 if (ret) { 667 spin_unlock_bh(&dp->dp_lock); 668 ath12k_warn(ab, "failed to assign reoq buf for rx tid %u\n", tid); 669 return ret; 670 } 671 672 peer->rx_tid_active_bitmask |= (1 << tid); 673 674 /* Pre-allocate the update_rxq_list for the corresponding tid 675 * This will be used during the tid delete. The reason we are not 676 * allocating during tid delete is that, if any alloc fail in update_rxq_list 677 * we may not be able to delete the tid vaddr/paddr and may lead to leak 678 */ 679 ret = ath12k_dp_prepare_reo_update_elem(dp, peer, rx_tid); 680 if (ret) { 681 ath12k_warn(ab, "failed to alloc update_rxq_list for rx tid %u\n", tid); 682 ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 683 spin_unlock_bh(&dp->dp_lock); 684 return ret; 685 } 686 687 paddr_aligned = rx_tid->qbuf.paddr_aligned; 688 if (ab->hw_params->reoq_lut_support) { 689 /* Update the REO queue LUT at the corresponding peer id 690 * and tid with qaddr. 691 */ 692 if (peer->mlo) 693 ath12k_dp_arch_peer_rx_tid_qref_setup(dp, peer->ml_id, tid, 694 paddr_aligned); 695 else 696 ath12k_dp_arch_peer_rx_tid_qref_setup(dp, peer->peer_id, tid, 697 paddr_aligned); 698 699 spin_unlock_bh(&dp->dp_lock); 700 } else { 701 spin_unlock_bh(&dp->dp_lock); 702 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 703 paddr_aligned, tid, 1, 704 ba_win_sz); 705 } 706 707 return ret; 708 } 709 710 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 711 struct ieee80211_ampdu_params *params, 712 u8 link_id) 713 { 714 struct ath12k_base *ab = ar->ab; 715 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 716 struct ath12k_link_sta *arsta; 717 int vdev_id; 718 int ret; 719 720 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 721 722 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 723 ahsta->link[link_id]); 724 if (!arsta) 725 return -ENOLINK; 726 727 vdev_id = arsta->arvif->vdev_id; 728 729 ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id, 730 params->tid, params->buf_size, 731 params->ssn, arsta->ahsta->pn_type); 732 if (ret) 733 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 734 735 return ret; 736 } 737 738 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 739 struct ieee80211_ampdu_params *params, 740 u8 link_id) 741 { 742 struct ath12k_base *ab = ar->ab; 743 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 744 struct ath12k_dp_link_peer *peer; 745 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 746 struct ath12k_dp_rx_tid *rx_tid; 747 struct ath12k_link_sta *arsta; 748 int vdev_id; 749 bool active; 750 int ret; 751 752 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 753 754 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 755 ahsta->link[link_id]); 756 if (!arsta) 757 return -ENOLINK; 758 759 vdev_id = arsta->arvif->vdev_id; 760 761 spin_lock_bh(&dp->dp_lock); 762 763 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, arsta->addr); 764 if (!peer || !peer->dp_peer) { 765 spin_unlock_bh(&dp->dp_lock); 766 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 767 return -ENOENT; 768 } 769 770 if (ab->hw_params->dp_primary_link_only && 771 !peer->primary_link) { 772 spin_unlock_bh(&dp->dp_lock); 773 return 0; 774 } 775 776 active = peer->rx_tid_active_bitmask & (1 << params->tid); 777 if (!active) { 778 spin_unlock_bh(&dp->dp_lock); 779 return 0; 780 } 781 782 rx_tid = &peer->dp_peer->rx_tid[params->tid]; 783 ret = ath12k_dp_arch_peer_rx_tid_reo_update(dp, peer, rx_tid, 784 1, 0, false); 785 spin_unlock_bh(&dp->dp_lock); 786 if (ret) { 787 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 788 params->tid, ret); 789 return ret; 790 } 791 792 return ret; 793 } 794 795 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, 796 const u8 *peer_addr, 797 enum set_key_cmd key_cmd, 798 struct ieee80211_key_conf *key) 799 { 800 struct ath12k *ar = arvif->ar; 801 struct ath12k_base *ab = ar->ab; 802 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 803 struct ath12k_hal_reo_cmd cmd = {}; 804 struct ath12k_dp_link_peer *peer; 805 struct ath12k_dp_rx_tid *rx_tid; 806 struct ath12k_dp_rx_tid_rxq rx_tid_rxq; 807 u8 tid; 808 int ret = 0; 809 810 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 811 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 812 * for now. 813 */ 814 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 815 return 0; 816 817 spin_lock_bh(&dp->dp_lock); 818 819 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, arvif->vdev_id, 820 peer_addr); 821 if (!peer || !peer->dp_peer) { 822 spin_unlock_bh(&dp->dp_lock); 823 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 824 peer_addr); 825 return -ENOENT; 826 } 827 828 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 829 if (!(peer->rx_tid_active_bitmask & (1 << tid))) 830 continue; 831 832 rx_tid = &peer->dp_peer->rx_tid[tid]; 833 ath12k_dp_init_rx_tid_rxq(&rx_tid_rxq, rx_tid, 834 (peer->rx_tid_active_bitmask & (1 << tid))); 835 ath12k_dp_arch_setup_pn_check_reo_cmd(dp, &cmd, rx_tid, key->cipher, 836 key_cmd); 837 ret = ath12k_dp_arch_reo_cmd_send(dp, &rx_tid_rxq, 838 HAL_REO_CMD_UPDATE_RX_QUEUE, 839 &cmd, NULL); 840 if (ret) { 841 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 842 tid, peer_addr, ret); 843 break; 844 } 845 } 846 847 spin_unlock_bh(&dp->dp_lock); 848 849 return ret; 850 } 851 EXPORT_SYMBOL(ath12k_dp_rx_get_msdu_last_buf); 852 853 struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 854 struct sk_buff *first) 855 { 856 struct sk_buff *skb; 857 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 858 859 if (!rxcb->is_continuation) 860 return first; 861 862 skb_queue_walk(msdu_list, skb) { 863 rxcb = ATH12K_SKB_RXCB(skb); 864 if (!rxcb->is_continuation) 865 return skb; 866 } 867 868 return NULL; 869 } 870 871 int ath12k_dp_rx_crypto_mic_len(struct ath12k_dp *dp, enum hal_encrypt_type enctype) 872 { 873 switch (enctype) { 874 case HAL_ENCRYPT_TYPE_OPEN: 875 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 876 case HAL_ENCRYPT_TYPE_TKIP_MIC: 877 return 0; 878 case HAL_ENCRYPT_TYPE_CCMP_128: 879 return IEEE80211_CCMP_MIC_LEN; 880 case HAL_ENCRYPT_TYPE_CCMP_256: 881 return IEEE80211_CCMP_256_MIC_LEN; 882 case HAL_ENCRYPT_TYPE_GCMP_128: 883 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 884 return IEEE80211_GCMP_MIC_LEN; 885 case HAL_ENCRYPT_TYPE_WEP_40: 886 case HAL_ENCRYPT_TYPE_WEP_104: 887 case HAL_ENCRYPT_TYPE_WEP_128: 888 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 889 case HAL_ENCRYPT_TYPE_WAPI: 890 break; 891 } 892 893 ath12k_warn(dp->ab, "unsupported encryption type %d for mic len\n", enctype); 894 return 0; 895 } 896 897 static int ath12k_dp_rx_crypto_param_len(struct ath12k_pdev_dp *dp_pdev, 898 enum hal_encrypt_type enctype) 899 { 900 switch (enctype) { 901 case HAL_ENCRYPT_TYPE_OPEN: 902 return 0; 903 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 904 case HAL_ENCRYPT_TYPE_TKIP_MIC: 905 return IEEE80211_TKIP_IV_LEN; 906 case HAL_ENCRYPT_TYPE_CCMP_128: 907 return IEEE80211_CCMP_HDR_LEN; 908 case HAL_ENCRYPT_TYPE_CCMP_256: 909 return IEEE80211_CCMP_256_HDR_LEN; 910 case HAL_ENCRYPT_TYPE_GCMP_128: 911 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 912 return IEEE80211_GCMP_HDR_LEN; 913 case HAL_ENCRYPT_TYPE_WEP_40: 914 case HAL_ENCRYPT_TYPE_WEP_104: 915 case HAL_ENCRYPT_TYPE_WEP_128: 916 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 917 case HAL_ENCRYPT_TYPE_WAPI: 918 break; 919 } 920 921 ath12k_warn(dp_pdev->dp->ab, "unsupported encryption type %d\n", enctype); 922 return 0; 923 } 924 925 static int ath12k_dp_rx_crypto_icv_len(struct ath12k_pdev_dp *dp_pdev, 926 enum hal_encrypt_type enctype) 927 { 928 switch (enctype) { 929 case HAL_ENCRYPT_TYPE_OPEN: 930 case HAL_ENCRYPT_TYPE_CCMP_128: 931 case HAL_ENCRYPT_TYPE_CCMP_256: 932 case HAL_ENCRYPT_TYPE_GCMP_128: 933 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 934 return 0; 935 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 936 case HAL_ENCRYPT_TYPE_TKIP_MIC: 937 return IEEE80211_TKIP_ICV_LEN; 938 case HAL_ENCRYPT_TYPE_WEP_40: 939 case HAL_ENCRYPT_TYPE_WEP_104: 940 case HAL_ENCRYPT_TYPE_WEP_128: 941 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 942 case HAL_ENCRYPT_TYPE_WAPI: 943 break; 944 } 945 946 ath12k_warn(dp_pdev->dp->ab, "unsupported encryption type %d\n", enctype); 947 return 0; 948 } 949 950 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k_pdev_dp *dp_pdev, 951 struct sk_buff *msdu, 952 enum hal_encrypt_type enctype, 953 struct hal_rx_desc_data *rx_info) 954 { 955 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 956 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 957 struct ieee80211_hdr *hdr; 958 size_t hdr_len; 959 u8 *crypto_hdr; 960 u16 qos_ctl; 961 962 /* pull decapped header */ 963 hdr = (struct ieee80211_hdr *)msdu->data; 964 hdr_len = ieee80211_hdrlen(hdr->frame_control); 965 skb_pull(msdu, hdr_len); 966 967 /* Rebuild qos header */ 968 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 969 970 /* Reset the order bit as the HT_Control header is stripped */ 971 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 972 973 qos_ctl = rxcb->tid; 974 975 if (rx_info->mesh_ctrl_present) 976 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 977 978 /* TODO: Add other QoS ctl fields when required */ 979 980 /* copy decap header before overwriting for reuse below */ 981 memcpy(decap_hdr, hdr, hdr_len); 982 983 /* Rebuild crypto header for mac80211 use */ 984 if (!(rx_info->rx_status->flag & RX_FLAG_IV_STRIPPED)) { 985 crypto_hdr = skb_push(msdu, 986 ath12k_dp_rx_crypto_param_len(dp_pdev, enctype)); 987 ath12k_dp_rx_desc_get_crypto_header(dp_pdev->dp->hal, 988 rxcb->rx_desc, crypto_hdr, 989 enctype); 990 } 991 992 memcpy(skb_push(msdu, 993 IEEE80211_QOS_CTL_LEN), &qos_ctl, 994 IEEE80211_QOS_CTL_LEN); 995 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 996 } 997 998 static void ath12k_dp_rx_h_undecap_raw(struct ath12k_pdev_dp *dp_pdev, 999 struct sk_buff *msdu, 1000 enum hal_encrypt_type enctype, 1001 struct ieee80211_rx_status *status, 1002 bool decrypted) 1003 { 1004 struct ath12k_dp *dp = dp_pdev->dp; 1005 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1006 struct ieee80211_hdr *hdr; 1007 size_t hdr_len; 1008 size_t crypto_len; 1009 1010 if (!rxcb->is_first_msdu || 1011 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 1012 WARN_ON_ONCE(1); 1013 return; 1014 } 1015 1016 skb_trim(msdu, msdu->len - FCS_LEN); 1017 1018 if (!decrypted) 1019 return; 1020 1021 hdr = (void *)msdu->data; 1022 1023 /* Tail */ 1024 if (status->flag & RX_FLAG_IV_STRIPPED) { 1025 skb_trim(msdu, msdu->len - 1026 ath12k_dp_rx_crypto_mic_len(dp, enctype)); 1027 1028 skb_trim(msdu, msdu->len - 1029 ath12k_dp_rx_crypto_icv_len(dp_pdev, enctype)); 1030 } else { 1031 /* MIC */ 1032 if (status->flag & RX_FLAG_MIC_STRIPPED) 1033 skb_trim(msdu, msdu->len - 1034 ath12k_dp_rx_crypto_mic_len(dp, enctype)); 1035 1036 /* ICV */ 1037 if (status->flag & RX_FLAG_ICV_STRIPPED) 1038 skb_trim(msdu, msdu->len - 1039 ath12k_dp_rx_crypto_icv_len(dp_pdev, enctype)); 1040 } 1041 1042 /* MMIC */ 1043 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 1044 !ieee80211_has_morefrags(hdr->frame_control) && 1045 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 1046 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 1047 1048 /* Head */ 1049 if (status->flag & RX_FLAG_IV_STRIPPED) { 1050 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1051 crypto_len = ath12k_dp_rx_crypto_param_len(dp_pdev, enctype); 1052 1053 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 1054 skb_pull(msdu, crypto_len); 1055 } 1056 } 1057 1058 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k_pdev_dp *dp_pdev, 1059 struct sk_buff *msdu, 1060 struct ath12k_skb_rxcb *rxcb, 1061 enum hal_encrypt_type enctype, 1062 struct hal_rx_desc_data *rx_info) 1063 { 1064 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 1065 struct ath12k_dp *dp = dp_pdev->dp; 1066 struct ath12k_hal *hal = dp->hal; 1067 size_t hdr_len, crypto_len; 1068 struct ieee80211_hdr hdr; 1069 __le16 qos_ctl; 1070 u8 *crypto_hdr; 1071 1072 ath12k_dp_rx_desc_get_dot11_hdr(hal, rx_desc, &hdr); 1073 hdr_len = ieee80211_hdrlen(hdr.frame_control); 1074 1075 if (!(rx_info->rx_status->flag & RX_FLAG_IV_STRIPPED)) { 1076 crypto_len = ath12k_dp_rx_crypto_param_len(dp_pdev, enctype); 1077 crypto_hdr = skb_push(msdu, crypto_len); 1078 ath12k_dp_rx_desc_get_crypto_header(dp->hal, rx_desc, crypto_hdr, 1079 enctype); 1080 } 1081 1082 skb_push(msdu, hdr_len); 1083 memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr))); 1084 1085 if (rxcb->is_mcbc) 1086 rx_info->rx_status->flag &= ~RX_FLAG_PN_VALIDATED; 1087 1088 /* Add QOS header */ 1089 if (ieee80211_is_data_qos(hdr.frame_control)) { 1090 struct ieee80211_hdr *qos_ptr = (struct ieee80211_hdr *)msdu->data; 1091 1092 qos_ctl = cpu_to_le16(rxcb->tid & IEEE80211_QOS_CTL_TID_MASK); 1093 if (rx_info->mesh_ctrl_present) 1094 qos_ctl |= cpu_to_le16(IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT); 1095 1096 memcpy(ieee80211_get_qos_ctl(qos_ptr), &qos_ctl, IEEE80211_QOS_CTL_LEN); 1097 } 1098 } 1099 1100 static void ath12k_dp_rx_h_undecap_eth(struct ath12k_pdev_dp *dp_pdev, 1101 struct sk_buff *msdu, 1102 enum hal_encrypt_type enctype, 1103 struct hal_rx_desc_data *rx_info, 1104 enum ath12k_dp_rx_decap_type decap_type) 1105 { 1106 struct ieee80211_hdr *hdr; 1107 struct ethhdr *eth; 1108 u8 da[ETH_ALEN]; 1109 u8 sa[ETH_ALEN]; 1110 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1111 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 1112 struct ath12k_dp_rx_rfc1042_hdr *llc; 1113 1114 eth = (struct ethhdr *)msdu->data; 1115 ether_addr_copy(da, eth->h_dest); 1116 ether_addr_copy(sa, eth->h_source); 1117 if (decap_type == DP_RX_DECAP_TYPE_8023) { 1118 /* 1119 * For 802.3 frames, eth->h_proto carries a length field, not 1120 * an EtherType. The actual EtherType is in the LLC/SNAP header 1121 * that follows the Ethernet header. 1122 */ 1123 llc = (struct ath12k_dp_rx_rfc1042_hdr *)(msdu->data + sizeof(*eth)); 1124 rfc.snap_type = llc->snap_type; 1125 skb_pull(msdu, sizeof(*eth) + sizeof(*llc)); 1126 } else { 1127 rfc.snap_type = eth->h_proto; 1128 skb_pull(msdu, sizeof(*eth)); 1129 } 1130 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 1131 sizeof(rfc)); 1132 ath12k_get_dot11_hdr_from_rx_desc(dp_pdev, msdu, rxcb, enctype, rx_info); 1133 1134 /* original 802.11 header has a different DA and in 1135 * case of 4addr it may also have different SA 1136 */ 1137 hdr = (struct ieee80211_hdr *)msdu->data; 1138 ether_addr_copy(ieee80211_get_DA(hdr), da); 1139 ether_addr_copy(ieee80211_get_SA(hdr), sa); 1140 } 1141 1142 void ath12k_dp_rx_h_undecap(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *msdu, 1143 enum hal_encrypt_type enctype, 1144 bool decrypted, 1145 struct hal_rx_desc_data *rx_info, 1146 struct ath12k_dp_peer *peer) 1147 { 1148 enum ath12k_dp_rx_decap_type decap_type = rx_info->decap_type; 1149 struct ethhdr *ehdr; 1150 1151 switch (decap_type) { 1152 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 1153 ath12k_dp_rx_h_undecap_nwifi(dp_pdev, msdu, enctype, rx_info); 1154 break; 1155 case DP_RX_DECAP_TYPE_RAW: 1156 ath12k_dp_rx_h_undecap_raw(dp_pdev, msdu, enctype, rx_info->rx_status, 1157 decrypted); 1158 break; 1159 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 1160 ehdr = (struct ethhdr *)msdu->data; 1161 1162 /* mac80211 allows fast path only for authorized STA */ 1163 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 1164 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 1165 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1166 decap_type); 1167 break; 1168 } 1169 1170 if (peer && !peer->use_4addr && 1171 rx_info->is_from_ds && rx_info->is_to_ds) { 1172 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1173 decap_type); 1174 break; 1175 } 1176 1177 /* PN for mcast packets will be validated in mac80211; 1178 * remove eth header and add 802.11 header. 1179 */ 1180 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) { 1181 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1182 decap_type); 1183 break; 1184 } 1185 1186 rx_info->rx_status->flag |= RX_FLAG_8023; 1187 break; 1188 case DP_RX_DECAP_TYPE_8023: 1189 /* 1190 * Note that ethernet decap format indicates that the decapped 1191 * packet is either Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC). 1192 */ 1193 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) { 1194 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1195 decap_type); 1196 break; 1197 } 1198 rx_info->rx_status->flag |= RX_FLAG_8023; 1199 } 1200 } 1201 EXPORT_SYMBOL(ath12k_dp_rx_h_undecap); 1202 1203 struct ath12k_dp_link_peer * 1204 ath12k_dp_rx_h_find_link_peer(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *msdu, 1205 struct hal_rx_desc_data *rx_info) 1206 { 1207 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1208 struct ath12k_dp_link_peer *peer = NULL; 1209 struct ath12k_dp *dp = dp_pdev->dp; 1210 1211 lockdep_assert_held(&dp->dp_lock); 1212 1213 peer = ath12k_dp_link_peer_find_by_peerid(dp_pdev, rxcb->peer_id); 1214 1215 if (peer) 1216 return peer; 1217 1218 if (rx_info->addr2_present) 1219 peer = ath12k_dp_link_peer_find_by_addr(dp, rx_info->addr2); 1220 1221 return peer; 1222 } 1223 1224 static void ath12k_dp_rx_h_rate(struct ath12k_pdev_dp *dp_pdev, 1225 struct hal_rx_desc_data *rx_info) 1226 { 1227 struct ath12k_dp *dp = dp_pdev->dp; 1228 struct ieee80211_supported_band *sband; 1229 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 1230 enum rx_msdu_start_pkt_type pkt_type = rx_info->pkt_type; 1231 u8 bw = rx_info->bw, sgi = rx_info->sgi; 1232 u8 rate_mcs = rx_info->rate_mcs, nss = rx_info->nss; 1233 bool is_cck; 1234 struct ath12k *ar; 1235 1236 switch (pkt_type) { 1237 case RX_MSDU_START_PKT_TYPE_11A: 1238 case RX_MSDU_START_PKT_TYPE_11B: 1239 ar = ath12k_pdev_dp_to_ar(dp_pdev); 1240 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 1241 sband = &ar->mac.sbands[rx_status->band]; 1242 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 1243 is_cck); 1244 break; 1245 case RX_MSDU_START_PKT_TYPE_11N: 1246 rx_status->encoding = RX_ENC_HT; 1247 if (rate_mcs > ATH12K_HT_MCS_MAX) { 1248 ath12k_warn(dp->ab, 1249 "Received with invalid mcs in HT mode %d\n", 1250 rate_mcs); 1251 break; 1252 } 1253 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 1254 if (sgi) 1255 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1256 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1257 break; 1258 case RX_MSDU_START_PKT_TYPE_11AC: 1259 rx_status->encoding = RX_ENC_VHT; 1260 rx_status->rate_idx = rate_mcs; 1261 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 1262 ath12k_warn(dp->ab, 1263 "Received with invalid mcs in VHT mode %d\n", 1264 rate_mcs); 1265 break; 1266 } 1267 rx_status->nss = nss; 1268 if (sgi) 1269 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1270 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1271 break; 1272 case RX_MSDU_START_PKT_TYPE_11AX: 1273 rx_status->rate_idx = rate_mcs; 1274 if (rate_mcs > ATH12K_HE_MCS_MAX) { 1275 ath12k_warn(dp->ab, 1276 "Received with invalid mcs in HE mode %d\n", 1277 rate_mcs); 1278 break; 1279 } 1280 rx_status->encoding = RX_ENC_HE; 1281 rx_status->nss = nss; 1282 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1283 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1284 break; 1285 case RX_MSDU_START_PKT_TYPE_11BE: 1286 rx_status->rate_idx = rate_mcs; 1287 1288 if (rate_mcs > ATH12K_EHT_MCS_MAX) { 1289 ath12k_warn(dp->ab, 1290 "Received with invalid mcs in EHT mode %d\n", 1291 rate_mcs); 1292 break; 1293 } 1294 1295 rx_status->encoding = RX_ENC_EHT; 1296 rx_status->nss = nss; 1297 rx_status->eht.gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi); 1298 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1299 break; 1300 default: 1301 break; 1302 } 1303 } 1304 1305 void ath12k_dp_rx_h_ppdu(struct ath12k_pdev_dp *dp_pdev, 1306 struct hal_rx_desc_data *rx_info) 1307 { 1308 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 1309 u8 channel_num; 1310 u32 center_freq, meta_data; 1311 struct ieee80211_channel *channel; 1312 1313 rx_status->freq = 0; 1314 rx_status->rate_idx = 0; 1315 rx_status->nss = 0; 1316 rx_status->encoding = RX_ENC_LEGACY; 1317 rx_status->bw = RATE_INFO_BW_20; 1318 rx_status->enc_flags = 0; 1319 1320 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 1321 1322 meta_data = rx_info->phy_meta_data; 1323 channel_num = meta_data; 1324 center_freq = meta_data >> 16; 1325 1326 rx_status->band = NUM_NL80211_BANDS; 1327 1328 if (center_freq >= ATH12K_MIN_6GHZ_FREQ && 1329 center_freq <= ATH12K_MAX_6GHZ_FREQ) { 1330 rx_status->band = NL80211_BAND_6GHZ; 1331 rx_status->freq = center_freq; 1332 } else if (channel_num >= ATH12K_2GHZ_MIN_CHAN_NUM && 1333 channel_num <= ATH12K_2GHZ_MAX_CHAN_NUM) { 1334 rx_status->band = NL80211_BAND_2GHZ; 1335 } else if (channel_num >= ATH12K_5GHZ_MIN_CHAN_NUM && 1336 channel_num <= ATH12K_5GHZ_MAX_CHAN_NUM) { 1337 rx_status->band = NL80211_BAND_5GHZ; 1338 } 1339 1340 if (unlikely(rx_status->band == NUM_NL80211_BANDS || 1341 !ath12k_pdev_dp_to_hw(dp_pdev)->wiphy->bands[rx_status->band])) { 1342 struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); 1343 1344 ath12k_warn(ar->ab, "sband is NULL for status band %d channel_num %d center_freq %d pdev_id %d\n", 1345 rx_status->band, channel_num, center_freq, ar->pdev_idx); 1346 1347 spin_lock_bh(&ar->data_lock); 1348 channel = ar->rx_channel; 1349 if (channel) { 1350 rx_status->band = channel->band; 1351 channel_num = 1352 ieee80211_frequency_to_channel(channel->center_freq); 1353 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 1354 rx_status->band); 1355 } else { 1356 ath12k_err(ar->ab, "unable to determine channel, band for rx packet"); 1357 } 1358 spin_unlock_bh(&ar->data_lock); 1359 goto h_rate; 1360 } 1361 1362 if (rx_status->band != NL80211_BAND_6GHZ) 1363 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 1364 rx_status->band); 1365 1366 h_rate: 1367 ath12k_dp_rx_h_rate(dp_pdev, rx_info); 1368 } 1369 EXPORT_SYMBOL(ath12k_dp_rx_h_ppdu); 1370 1371 void ath12k_dp_rx_deliver_msdu(struct ath12k_pdev_dp *dp_pdev, struct napi_struct *napi, 1372 struct sk_buff *msdu, 1373 struct hal_rx_desc_data *rx_info) 1374 { 1375 struct ath12k_dp *dp = dp_pdev->dp; 1376 struct ieee80211_rx_status *rx_status; 1377 struct ieee80211_sta *pubsta; 1378 struct ath12k_dp_peer *peer; 1379 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1380 struct ieee80211_rx_status *status = rx_info->rx_status; 1381 bool is_mcbc = rxcb->is_mcbc; 1382 1383 peer = ath12k_dp_peer_find_by_peerid(dp_pdev, rxcb->peer_id); 1384 1385 pubsta = peer ? peer->sta : NULL; 1386 1387 status->link_valid = 0; 1388 if (pubsta && pubsta->valid_links) 1389 ath12k_hw_set_rx_link_id(dp->hw_params, peer, rxcb, status); 1390 1391 ath12k_dbg(dp->ab, ATH12K_DBG_DATA, 1392 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 1393 msdu, 1394 msdu->len, 1395 peer ? peer->addr : NULL, 1396 rxcb->tid, 1397 is_mcbc ? "mcast" : "ucast", 1398 rx_info->seq_no, 1399 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 1400 (status->encoding == RX_ENC_HT) ? "ht" : "", 1401 (status->encoding == RX_ENC_VHT) ? "vht" : "", 1402 (status->encoding == RX_ENC_HE) ? "he" : "", 1403 (status->encoding == RX_ENC_EHT) ? "eht" : "", 1404 (status->bw == RATE_INFO_BW_40) ? "40" : "", 1405 (status->bw == RATE_INFO_BW_80) ? "80" : "", 1406 (status->bw == RATE_INFO_BW_160) ? "160" : "", 1407 (status->bw == RATE_INFO_BW_320) ? "320" : "", 1408 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 1409 status->rate_idx, 1410 status->nss, 1411 status->freq, 1412 status->band, status->flag, 1413 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 1414 !!(status->flag & RX_FLAG_MMIC_ERROR), 1415 !!(status->flag & RX_FLAG_AMSDU_MORE)); 1416 1417 ath12k_dbg_dump(dp->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 1418 msdu->data, msdu->len); 1419 1420 rx_status = IEEE80211_SKB_RXCB(msdu); 1421 *rx_status = *status; 1422 1423 /* TODO: trace rx packet */ 1424 1425 ieee80211_rx_napi(ath12k_pdev_dp_to_hw(dp_pdev), pubsta, msdu, napi); 1426 } 1427 EXPORT_SYMBOL(ath12k_dp_rx_deliver_msdu); 1428 1429 bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_dp *dp, 1430 struct sk_buff *msdu, 1431 struct hal_rx_desc_data *rx_info) 1432 { 1433 struct ieee80211_hdr *hdr; 1434 u32 hdr_len; 1435 1436 if (rx_info->decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI) 1437 return true; 1438 1439 hdr = (struct ieee80211_hdr *)msdu->data; 1440 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1441 1442 if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN))) 1443 return true; 1444 1445 dp->device_stats.invalid_rbm++; 1446 WARN_ON_ONCE(1); 1447 return false; 1448 } 1449 EXPORT_SYMBOL(ath12k_dp_rx_check_nwifi_hdr_len_valid); 1450 1451 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 1452 { 1453 struct ath12k_dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer, 1454 frag_timer); 1455 1456 spin_lock_bh(&rx_tid->dp->dp_lock); 1457 if (rx_tid->last_frag_no && 1458 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 1459 spin_unlock_bh(&rx_tid->dp->dp_lock); 1460 return; 1461 } 1462 ath12k_dp_arch_rx_frags_cleanup(rx_tid->dp, rx_tid, true); 1463 spin_unlock_bh(&rx_tid->dp->dp_lock); 1464 } 1465 1466 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 1467 { 1468 struct ath12k_base *ab = ar->ab; 1469 struct ath12k_dp_link_peer *peer; 1470 struct ath12k_dp_rx_tid *rx_tid; 1471 int i; 1472 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1473 1474 if (fips_enabled) { 1475 ath12k_warn(ab, "This driver is disabled due to FIPS\n"); 1476 return -ENOENT; 1477 } 1478 1479 spin_lock_bh(&dp->dp_lock); 1480 1481 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, peer_mac); 1482 if (!peer || !peer->dp_peer) { 1483 spin_unlock_bh(&dp->dp_lock); 1484 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 1485 return -ENOENT; 1486 } 1487 1488 if (!peer->primary_link) { 1489 spin_unlock_bh(&dp->dp_lock); 1490 return 0; 1491 } 1492 1493 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 1494 rx_tid = &peer->dp_peer->rx_tid[i]; 1495 rx_tid->dp = dp; 1496 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 1497 skb_queue_head_init(&rx_tid->rx_frags); 1498 } 1499 1500 peer->dp_peer->dp_setup_done = true; 1501 spin_unlock_bh(&dp->dp_lock); 1502 1503 return 0; 1504 } 1505 1506 void ath12k_dp_rx_h_undecap_frag(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *msdu, 1507 enum hal_encrypt_type enctype, u32 flags) 1508 { 1509 struct ath12k_dp *dp = dp_pdev->dp; 1510 struct ieee80211_hdr *hdr; 1511 size_t hdr_len; 1512 size_t crypto_len; 1513 u32 hal_rx_desc_sz = dp->ab->hal.hal_desc_sz; 1514 1515 if (!flags) 1516 return; 1517 1518 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 1519 1520 if (flags & RX_FLAG_MIC_STRIPPED) 1521 skb_trim(msdu, msdu->len - 1522 ath12k_dp_rx_crypto_mic_len(dp, enctype)); 1523 1524 if (flags & RX_FLAG_ICV_STRIPPED) 1525 skb_trim(msdu, msdu->len - 1526 ath12k_dp_rx_crypto_icv_len(dp_pdev, enctype)); 1527 1528 if (flags & RX_FLAG_IV_STRIPPED) { 1529 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1530 crypto_len = ath12k_dp_rx_crypto_param_len(dp_pdev, enctype); 1531 1532 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 1533 msdu->data + hal_rx_desc_sz, hdr_len); 1534 skb_pull(msdu, crypto_len); 1535 } 1536 } 1537 EXPORT_SYMBOL(ath12k_dp_rx_h_undecap_frag); 1538 1539 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_hal *hal, 1540 struct sk_buff *a, struct sk_buff *b) 1541 { 1542 int frag1, frag2; 1543 1544 frag1 = ath12k_dp_rx_h_frag_no(hal, a); 1545 frag2 = ath12k_dp_rx_h_frag_no(hal, b); 1546 1547 return frag1 - frag2; 1548 } 1549 1550 void ath12k_dp_rx_h_sort_frags(struct ath12k_hal *hal, 1551 struct sk_buff_head *frag_list, 1552 struct sk_buff *cur_frag) 1553 { 1554 struct sk_buff *skb; 1555 int cmp; 1556 1557 skb_queue_walk(frag_list, skb) { 1558 cmp = ath12k_dp_rx_h_cmp_frags(hal, skb, cur_frag); 1559 if (cmp < 0) 1560 continue; 1561 __skb_queue_before(frag_list, skb, cur_frag); 1562 return; 1563 } 1564 __skb_queue_tail(frag_list, cur_frag); 1565 } 1566 EXPORT_SYMBOL(ath12k_dp_rx_h_sort_frags); 1567 1568 u64 ath12k_dp_rx_h_get_pn(struct ath12k_dp *dp, struct sk_buff *skb) 1569 { 1570 struct ieee80211_hdr *hdr; 1571 u64 pn = 0; 1572 u8 *ehdr; 1573 u32 hal_rx_desc_sz = dp->ab->hal.hal_desc_sz; 1574 1575 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 1576 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 1577 1578 pn = ehdr[0]; 1579 pn |= (u64)ehdr[1] << 8; 1580 pn |= (u64)ehdr[4] << 16; 1581 pn |= (u64)ehdr[5] << 24; 1582 pn |= (u64)ehdr[6] << 32; 1583 pn |= (u64)ehdr[7] << 40; 1584 1585 return pn; 1586 } 1587 EXPORT_SYMBOL(ath12k_dp_rx_h_get_pn); 1588 1589 void ath12k_dp_rx_free(struct ath12k_base *ab) 1590 { 1591 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1592 struct dp_srng *srng; 1593 int i; 1594 1595 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 1596 1597 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1598 if (ab->hw_params->rx_mac_buf_ring) 1599 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 1600 if (!ab->hw_params->rxdma1_enable) { 1601 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 1602 ath12k_dp_srng_cleanup(ab, srng); 1603 } 1604 } 1605 1606 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 1607 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 1608 1609 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 1610 1611 ath12k_dp_rxdma_buf_free(ab); 1612 } 1613 1614 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 1615 { 1616 struct ath12k *ar = ab->pdevs[mac_id].ar; 1617 1618 ath12k_dp_rx_pdev_srng_free(ar); 1619 } 1620 1621 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 1622 { 1623 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1624 u32 ring_id; 1625 int i, ret; 1626 1627 /* TODO: Need to verify the HTT setup for QCN9224 */ 1628 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 1629 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 1630 if (ret) { 1631 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 1632 ret); 1633 return ret; 1634 } 1635 1636 if (ab->hw_params->rx_mac_buf_ring) { 1637 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1638 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1639 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1640 i, HAL_RXDMA_BUF); 1641 if (ret) { 1642 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 1643 i, ret); 1644 return ret; 1645 } 1646 } 1647 } 1648 1649 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 1650 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 1651 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1652 i, HAL_RXDMA_DST); 1653 if (ret) { 1654 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 1655 i, ret); 1656 return ret; 1657 } 1658 } 1659 1660 if (ab->hw_params->rxdma1_enable) { 1661 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1662 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1663 0, HAL_RXDMA_MONITOR_BUF); 1664 if (ret) { 1665 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 1666 ret); 1667 return ret; 1668 } 1669 } else { 1670 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1671 ring_id = 1672 dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1673 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, i, 1674 HAL_RXDMA_MONITOR_STATUS); 1675 if (ret) { 1676 ath12k_warn(ab, 1677 "failed to configure mon_status_refill_ring%d %d\n", 1678 i, ret); 1679 return ret; 1680 } 1681 } 1682 } 1683 1684 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 1685 if (ret) { 1686 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 1687 return ret; 1688 } 1689 1690 return 0; 1691 } 1692 1693 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 1694 { 1695 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1696 struct dp_srng *srng; 1697 int i, ret; 1698 1699 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 1700 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 1701 1702 ret = ath12k_dp_srng_setup(ab, 1703 &dp->rx_refill_buf_ring.refill_buf_ring, 1704 HAL_RXDMA_BUF, 0, 0, 1705 DP_RXDMA_BUF_RING_SIZE); 1706 if (ret) { 1707 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 1708 return ret; 1709 } 1710 1711 if (ab->hw_params->rx_mac_buf_ring) { 1712 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1713 ret = ath12k_dp_srng_setup(ab, 1714 &dp->rx_mac_buf_ring[i], 1715 HAL_RXDMA_BUF, 1, 1716 i, DP_RX_MAC_BUF_RING_SIZE); 1717 if (ret) { 1718 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 1719 i); 1720 return ret; 1721 } 1722 } 1723 } 1724 1725 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 1726 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 1727 HAL_RXDMA_DST, 0, i, 1728 DP_RXDMA_ERR_DST_RING_SIZE); 1729 if (ret) { 1730 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 1731 return ret; 1732 } 1733 } 1734 1735 if (ab->hw_params->rxdma1_enable) { 1736 ret = ath12k_dp_srng_setup(ab, 1737 &dp->rxdma_mon_buf_ring.refill_buf_ring, 1738 HAL_RXDMA_MONITOR_BUF, 0, 0, 1739 DP_RXDMA_MONITOR_BUF_RING_SIZE(ab)); 1740 if (ret) { 1741 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 1742 return ret; 1743 } 1744 } else { 1745 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1746 idr_init(&dp->rx_mon_status_refill_ring[i].bufs_idr); 1747 spin_lock_init(&dp->rx_mon_status_refill_ring[i].idr_lock); 1748 } 1749 1750 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1751 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 1752 ret = ath12k_dp_srng_setup(ab, srng, 1753 HAL_RXDMA_MONITOR_STATUS, 0, i, 1754 DP_RXDMA_MON_STATUS_RING_SIZE); 1755 if (ret) { 1756 ath12k_warn(ab, "failed to setup mon status ring %d\n", 1757 i); 1758 return ret; 1759 } 1760 } 1761 } 1762 1763 ret = ath12k_dp_rxdma_buf_setup(ab); 1764 if (ret) { 1765 ath12k_warn(ab, "failed to setup rxdma ring\n"); 1766 return ret; 1767 } 1768 1769 return 0; 1770 } 1771 1772 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 1773 { 1774 struct ath12k *ar = ab->pdevs[mac_id].ar; 1775 struct ath12k_pdev_dp *dp = &ar->dp; 1776 u32 ring_id; 1777 int i; 1778 int ret; 1779 1780 if (!ab->hw_params->rxdma1_enable) 1781 goto out; 1782 1783 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 1784 if (ret) { 1785 ath12k_warn(ab, "failed to setup rx srngs\n"); 1786 return ret; 1787 } 1788 1789 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1790 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 1791 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1792 mac_id + i, 1793 HAL_RXDMA_MONITOR_DST); 1794 if (ret) { 1795 ath12k_warn(ab, 1796 "failed to configure rxdma_mon_dst_ring %d %d\n", 1797 i, ret); 1798 return ret; 1799 } 1800 } 1801 out: 1802 return 0; 1803 } 1804 1805 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 1806 { 1807 struct ath12k_pdev_dp *dp = &ar->dp; 1808 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 1809 1810 skb_queue_head_init(&pmon->rx_status_q); 1811 1812 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 1813 1814 memset(&pmon->rx_mon_stats, 0, 1815 sizeof(pmon->rx_mon_stats)); 1816 return 0; 1817 } 1818 1819 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 1820 { 1821 struct ath12k_pdev_dp *dp = &ar->dp; 1822 struct ath12k_mon_data *pmon = &dp->mon_data; 1823 int ret = 0; 1824 1825 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 1826 if (ret) { 1827 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 1828 return ret; 1829 } 1830 1831 pmon->mon_last_linkdesc_paddr = 0; 1832 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 1833 spin_lock_init(&pmon->mon_lock); 1834 1835 if (!ar->ab->hw_params->rxdma1_enable) 1836 return 0; 1837 1838 INIT_LIST_HEAD(&pmon->dp_rx_mon_mpdu_list); 1839 pmon->mon_mpdu = NULL; 1840 1841 return 0; 1842 } 1843