1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 #include "debugfs_htt_stats.h" 21 22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 23 24 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 25 struct hal_rx_desc *desc) 26 { 27 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) 28 return HAL_ENCRYPT_TYPE_OPEN; 29 30 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); 31 } 32 33 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 34 struct hal_rx_desc *desc) 35 { 36 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); 37 } 38 39 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 40 struct hal_rx_desc *desc) 41 { 42 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); 43 } 44 45 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 46 struct hal_rx_desc *desc) 47 { 48 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 49 } 50 51 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 52 struct hal_rx_desc *desc) 53 { 54 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); 55 } 56 57 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 58 struct sk_buff *skb) 59 { 60 struct ieee80211_hdr *hdr; 61 62 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 63 return ieee80211_has_morefrags(hdr->frame_control); 64 } 65 66 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 67 struct sk_buff *skb) 68 { 69 struct ieee80211_hdr *hdr; 70 71 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 72 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 73 } 74 75 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 76 struct hal_rx_desc *desc) 77 { 78 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc); 79 } 80 81 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 82 struct hal_rx_desc *desc) 83 { 84 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc); 85 } 86 87 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 88 struct hal_rx_desc *desc) 89 { 90 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc); 91 } 92 93 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 94 struct hal_rx_desc *desc) 95 { 96 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc); 97 } 98 99 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 100 struct hal_rx_desc *desc) 101 { 102 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc); 103 } 104 105 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 106 struct hal_rx_desc *desc) 107 { 108 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc); 109 } 110 111 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 112 struct hal_rx_desc *desc) 113 { 114 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc); 115 } 116 117 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 118 struct hal_rx_desc *desc) 119 { 120 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc); 121 } 122 123 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 124 struct hal_rx_desc *desc) 125 { 126 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc); 127 } 128 129 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 130 struct hal_rx_desc *desc) 131 { 132 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc); 133 } 134 135 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 136 struct hal_rx_desc *desc) 137 { 138 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc); 139 } 140 141 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 142 struct hal_rx_desc *desc) 143 { 144 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc); 145 } 146 147 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 148 struct hal_rx_desc *desc) 149 { 150 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc)); 151 } 152 153 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 154 struct hal_rx_desc *desc) 155 { 156 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc); 157 } 158 159 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 160 struct hal_rx_desc *desc) 161 { 162 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc); 163 } 164 165 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 166 struct hal_rx_desc *desc) 167 { 168 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc); 169 } 170 171 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 172 struct hal_rx_desc *desc) 173 { 174 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc); 175 } 176 177 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 178 struct hal_rx_desc *desc) 179 { 180 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc); 181 } 182 183 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 184 struct hal_rx_desc *fdesc, 185 struct hal_rx_desc *ldesc) 186 { 187 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 188 } 189 190 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 191 struct hal_rx_desc *desc, 192 u16 len) 193 { 194 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len); 195 } 196 197 u32 ath12k_dp_rxdesc_get_ppduid(struct ath12k_base *ab, 198 struct hal_rx_desc *rx_desc) 199 { 200 return ab->hal_rx_ops->rx_desc_get_mpdu_ppdu_id(rx_desc); 201 } 202 203 bool ath12k_dp_rxdesc_mpdu_valid(struct ath12k_base *ab, 204 struct hal_rx_desc *rx_desc) 205 { 206 u32 tlv_tag; 207 208 tlv_tag = ab->hal_rx_ops->rx_desc_get_mpdu_start_tag(rx_desc); 209 210 return tlv_tag == HAL_RX_MPDU_START; 211 } 212 213 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 214 struct hal_rx_desc *desc) 215 { 216 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 217 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc)); 218 } 219 220 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 221 struct hal_rx_desc *desc) 222 { 223 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc); 224 } 225 226 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 227 struct hal_rx_desc *desc) 228 { 229 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc); 230 } 231 232 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 233 struct hal_rx_desc *desc, 234 struct ieee80211_hdr *hdr) 235 { 236 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr); 237 } 238 239 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 240 struct hal_rx_desc *desc, 241 u8 *crypto_hdr, 242 enum hal_encrypt_type enctype) 243 { 244 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 245 } 246 247 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, 248 struct hal_rx_desc *desc) 249 { 250 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc); 251 } 252 253 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list) 254 { 255 struct sk_buff *skb; 256 257 while ((skb = __skb_dequeue(skb_list))) 258 dev_kfree_skb_any(skb); 259 } 260 261 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 262 struct list_head *head, 263 size_t count) 264 { 265 struct list_head *cur; 266 struct ath12k_rx_desc_info *rx_desc; 267 size_t nodes = 0; 268 269 if (!count) { 270 INIT_LIST_HEAD(list); 271 goto out; 272 } 273 274 list_for_each(cur, head) { 275 if (!count) 276 break; 277 278 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 279 rx_desc->in_use = true; 280 281 count--; 282 nodes++; 283 } 284 285 list_cut_before(list, head, cur); 286 out: 287 return nodes; 288 } 289 290 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 291 struct list_head *used_list) 292 { 293 struct ath12k_rx_desc_info *rx_desc, *safe; 294 295 /* Reset the use flag */ 296 list_for_each_entry_safe(rx_desc, safe, used_list, list) 297 rx_desc->in_use = false; 298 299 spin_lock_bh(&dp->rx_desc_lock); 300 list_splice_tail(used_list, &dp->rx_desc_free_list); 301 spin_unlock_bh(&dp->rx_desc_lock); 302 } 303 304 /* Returns number of Rx buffers replenished */ 305 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, 306 struct dp_rxdma_ring *rx_ring, 307 struct list_head *used_list, 308 int req_entries) 309 { 310 struct ath12k_buffer_addr *desc; 311 struct hal_srng *srng; 312 struct sk_buff *skb; 313 int num_free; 314 int num_remain; 315 u32 cookie; 316 dma_addr_t paddr; 317 struct ath12k_dp *dp = &ab->dp; 318 struct ath12k_rx_desc_info *rx_desc; 319 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; 320 321 req_entries = min(req_entries, rx_ring->bufs_max); 322 323 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 324 325 spin_lock_bh(&srng->lock); 326 327 ath12k_hal_srng_access_begin(ab, srng); 328 329 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 330 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 331 req_entries = num_free; 332 333 req_entries = min(num_free, req_entries); 334 num_remain = req_entries; 335 336 if (!num_remain) 337 goto out; 338 339 /* Get the descriptor from free list */ 340 if (list_empty(used_list)) { 341 spin_lock_bh(&dp->rx_desc_lock); 342 req_entries = ath12k_dp_list_cut_nodes(used_list, 343 &dp->rx_desc_free_list, 344 num_remain); 345 spin_unlock_bh(&dp->rx_desc_lock); 346 num_remain = req_entries; 347 } 348 349 while (num_remain > 0) { 350 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 351 DP_RX_BUFFER_ALIGN_SIZE); 352 if (!skb) 353 break; 354 355 if (!IS_ALIGNED((unsigned long)skb->data, 356 DP_RX_BUFFER_ALIGN_SIZE)) { 357 skb_pull(skb, 358 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 359 skb->data); 360 } 361 362 paddr = dma_map_single(ab->dev, skb->data, 363 skb->len + skb_tailroom(skb), 364 DMA_FROM_DEVICE); 365 if (dma_mapping_error(ab->dev, paddr)) 366 goto fail_free_skb; 367 368 rx_desc = list_first_entry_or_null(used_list, 369 struct ath12k_rx_desc_info, 370 list); 371 if (!rx_desc) 372 goto fail_dma_unmap; 373 374 rx_desc->skb = skb; 375 cookie = rx_desc->cookie; 376 377 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 378 if (!desc) 379 goto fail_dma_unmap; 380 381 list_del(&rx_desc->list); 382 ATH12K_SKB_RXCB(skb)->paddr = paddr; 383 384 num_remain--; 385 386 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 387 } 388 389 goto out; 390 391 fail_dma_unmap: 392 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 393 DMA_FROM_DEVICE); 394 fail_free_skb: 395 dev_kfree_skb_any(skb); 396 out: 397 ath12k_hal_srng_access_end(ab, srng); 398 399 if (!list_empty(used_list)) 400 ath12k_dp_rx_enqueue_free(dp, used_list); 401 402 spin_unlock_bh(&srng->lock); 403 404 return req_entries - num_remain; 405 } 406 407 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 408 struct dp_rxdma_mon_ring *rx_ring) 409 { 410 struct sk_buff *skb; 411 int buf_id; 412 413 spin_lock_bh(&rx_ring->idr_lock); 414 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 415 idr_remove(&rx_ring->bufs_idr, buf_id); 416 /* TODO: Understand where internal driver does this dma_unmap 417 * of rxdma_buffer. 418 */ 419 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 420 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 421 dev_kfree_skb_any(skb); 422 } 423 424 idr_destroy(&rx_ring->bufs_idr); 425 spin_unlock_bh(&rx_ring->idr_lock); 426 427 return 0; 428 } 429 430 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 431 { 432 struct ath12k_dp *dp = &ab->dp; 433 int i; 434 435 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 436 437 if (ab->hw_params->rxdma1_enable) 438 return 0; 439 440 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 441 ath12k_dp_rxdma_mon_buf_ring_free(ab, 442 &dp->rx_mon_status_refill_ring[i]); 443 444 return 0; 445 } 446 447 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 448 struct dp_rxdma_mon_ring *rx_ring, 449 u32 ringtype) 450 { 451 int num_entries; 452 453 num_entries = rx_ring->refill_buf_ring.size / 454 ath12k_hal_srng_get_entrysize(ab, ringtype); 455 456 rx_ring->bufs_max = num_entries; 457 458 if (ringtype == HAL_RXDMA_MONITOR_STATUS) 459 ath12k_dp_mon_status_bufs_replenish(ab, rx_ring, 460 num_entries); 461 else 462 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 463 464 return 0; 465 } 466 467 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 468 struct dp_rxdma_ring *rx_ring) 469 { 470 LIST_HEAD(list); 471 472 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 473 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 474 475 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 476 477 return 0; 478 } 479 480 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 481 { 482 struct ath12k_dp *dp = &ab->dp; 483 struct dp_rxdma_mon_ring *mon_ring; 484 int ret, i; 485 486 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 487 if (ret) { 488 ath12k_warn(ab, 489 "failed to setup HAL_RXDMA_BUF\n"); 490 return ret; 491 } 492 493 if (ab->hw_params->rxdma1_enable) { 494 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 495 &dp->rxdma_mon_buf_ring, 496 HAL_RXDMA_MONITOR_BUF); 497 if (ret) 498 ath12k_warn(ab, 499 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 500 return ret; 501 } 502 503 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 504 mon_ring = &dp->rx_mon_status_refill_ring[i]; 505 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, mon_ring, 506 HAL_RXDMA_MONITOR_STATUS); 507 if (ret) { 508 ath12k_warn(ab, 509 "failed to setup HAL_RXDMA_MONITOR_STATUS\n"); 510 return ret; 511 } 512 } 513 514 return 0; 515 } 516 517 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 518 { 519 struct ath12k_pdev_dp *dp = &ar->dp; 520 struct ath12k_base *ab = ar->ab; 521 int i; 522 523 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 524 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 525 } 526 527 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 528 { 529 struct ath12k_dp *dp = &ab->dp; 530 int i; 531 532 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 533 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 534 } 535 536 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 537 { 538 struct ath12k_dp *dp = &ab->dp; 539 int ret; 540 int i; 541 542 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 543 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 544 HAL_REO_DST, i, 0, 545 DP_REO_DST_RING_SIZE); 546 if (ret) { 547 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 548 goto err_reo_cleanup; 549 } 550 } 551 552 return 0; 553 554 err_reo_cleanup: 555 ath12k_dp_rx_pdev_reo_cleanup(ab); 556 557 return ret; 558 } 559 560 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 561 { 562 struct ath12k_pdev_dp *dp = &ar->dp; 563 struct ath12k_base *ab = ar->ab; 564 int i; 565 int ret; 566 u32 mac_id = dp->mac_id; 567 568 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 569 ret = ath12k_dp_srng_setup(ar->ab, 570 &dp->rxdma_mon_dst_ring[i], 571 HAL_RXDMA_MONITOR_DST, 572 0, mac_id + i, 573 DP_RXDMA_MONITOR_DST_RING_SIZE); 574 if (ret) { 575 ath12k_warn(ar->ab, 576 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 577 return ret; 578 } 579 } 580 581 return 0; 582 } 583 584 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 585 { 586 struct ath12k_dp *dp = &ab->dp; 587 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 588 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 589 590 spin_lock_bh(&dp->reo_cmd_lock); 591 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 592 list_del(&cmd->list); 593 dma_unmap_single(ab->dev, cmd->data.qbuf.paddr_aligned, 594 cmd->data.qbuf.size, DMA_BIDIRECTIONAL); 595 kfree(cmd->data.qbuf.vaddr); 596 kfree(cmd); 597 } 598 599 list_for_each_entry_safe(cmd_cache, tmp_cache, 600 &dp->reo_cmd_cache_flush_list, list) { 601 list_del(&cmd_cache->list); 602 dp->reo_cmd_cache_flush_count--; 603 dma_unmap_single(ab->dev, cmd_cache->data.qbuf.paddr_aligned, 604 cmd_cache->data.qbuf.size, DMA_BIDIRECTIONAL); 605 kfree(cmd_cache->data.qbuf.vaddr); 606 kfree(cmd_cache); 607 } 608 spin_unlock_bh(&dp->reo_cmd_lock); 609 } 610 611 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 612 enum hal_reo_cmd_status status) 613 { 614 struct ath12k_dp_rx_tid *rx_tid = ctx; 615 616 if (status != HAL_REO_CMD_SUCCESS) 617 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 618 rx_tid->tid, status); 619 620 dma_unmap_single(dp->ab->dev, rx_tid->qbuf.paddr_aligned, rx_tid->qbuf.size, 621 DMA_BIDIRECTIONAL); 622 kfree(rx_tid->qbuf.vaddr); 623 rx_tid->qbuf.vaddr = NULL; 624 } 625 626 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 627 enum hal_reo_cmd_type type, 628 struct ath12k_hal_reo_cmd *cmd, 629 void (*cb)(struct ath12k_dp *dp, void *ctx, 630 enum hal_reo_cmd_status status)) 631 { 632 struct ath12k_dp *dp = &ab->dp; 633 struct ath12k_dp_rx_reo_cmd *dp_cmd; 634 struct hal_srng *cmd_ring; 635 int cmd_num; 636 637 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 638 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 639 640 /* cmd_num should start from 1, during failure return the error code */ 641 if (cmd_num < 0) 642 return cmd_num; 643 644 /* reo cmd ring descriptors has cmd_num starting from 1 */ 645 if (cmd_num == 0) 646 return -EINVAL; 647 648 if (!cb) 649 return 0; 650 651 /* Can this be optimized so that we keep the pending command list only 652 * for tid delete command to free up the resource on the command status 653 * indication? 654 */ 655 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 656 657 if (!dp_cmd) 658 return -ENOMEM; 659 660 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 661 dp_cmd->cmd_num = cmd_num; 662 dp_cmd->handler = cb; 663 664 spin_lock_bh(&dp->reo_cmd_lock); 665 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 666 spin_unlock_bh(&dp->reo_cmd_lock); 667 668 return 0; 669 } 670 671 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 672 struct ath12k_dp_rx_tid *rx_tid) 673 { 674 struct ath12k_hal_reo_cmd cmd = {0}; 675 unsigned long tot_desc_sz, desc_sz; 676 int ret; 677 678 tot_desc_sz = rx_tid->qbuf.size; 679 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 680 681 while (tot_desc_sz > desc_sz) { 682 tot_desc_sz -= desc_sz; 683 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned + tot_desc_sz); 684 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 685 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 686 HAL_REO_CMD_FLUSH_CACHE, &cmd, 687 NULL); 688 if (ret) 689 ath12k_warn(ab, 690 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 691 rx_tid->tid, ret); 692 } 693 694 memset(&cmd, 0, sizeof(cmd)); 695 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 696 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 697 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 698 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 699 HAL_REO_CMD_FLUSH_CACHE, 700 &cmd, ath12k_dp_reo_cmd_free); 701 if (ret) { 702 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 703 rx_tid->tid, ret); 704 dma_unmap_single(ab->dev, rx_tid->qbuf.paddr_aligned, rx_tid->qbuf.size, 705 DMA_BIDIRECTIONAL); 706 kfree(rx_tid->qbuf.vaddr); 707 rx_tid->qbuf.vaddr = NULL; 708 } 709 } 710 711 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 712 enum hal_reo_cmd_status status) 713 { 714 struct ath12k_base *ab = dp->ab; 715 struct ath12k_dp_rx_tid *rx_tid = ctx; 716 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 717 718 if (status == HAL_REO_CMD_DRAIN) { 719 goto free_desc; 720 } else if (status != HAL_REO_CMD_SUCCESS) { 721 /* Shouldn't happen! Cleanup in case of other failure? */ 722 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 723 rx_tid->tid, status); 724 return; 725 } 726 727 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 728 if (!elem) 729 goto free_desc; 730 731 elem->ts = jiffies; 732 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 733 734 spin_lock_bh(&dp->reo_cmd_lock); 735 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 736 dp->reo_cmd_cache_flush_count++; 737 738 /* Flush and invalidate aged REO desc from HW cache */ 739 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 740 list) { 741 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 742 time_after(jiffies, elem->ts + 743 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 744 list_del(&elem->list); 745 dp->reo_cmd_cache_flush_count--; 746 747 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 748 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 749 * is used in only two contexts, one is in this function called 750 * from napi and the other in ath12k_dp_free during core destroy. 751 * Before dp_free, the irqs would be disabled and would wait to 752 * synchronize. Hence there wouldn’t be any race against add or 753 * delete to this list. Hence unlock-lock is safe here. 754 */ 755 spin_unlock_bh(&dp->reo_cmd_lock); 756 757 ath12k_dp_reo_cache_flush(ab, &elem->data); 758 kfree(elem); 759 spin_lock_bh(&dp->reo_cmd_lock); 760 } 761 } 762 spin_unlock_bh(&dp->reo_cmd_lock); 763 764 return; 765 free_desc: 766 dma_unmap_single(ab->dev, rx_tid->qbuf.paddr_aligned, rx_tid->qbuf.size, 767 DMA_BIDIRECTIONAL); 768 kfree(rx_tid->qbuf.vaddr); 769 rx_tid->qbuf.vaddr = NULL; 770 } 771 772 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 773 dma_addr_t paddr) 774 { 775 struct ath12k_reo_queue_ref *qref; 776 struct ath12k_dp *dp = &ab->dp; 777 bool ml_peer = false; 778 779 if (!ab->hw_params->reoq_lut_support) 780 return; 781 782 if (peer_id & ATH12K_PEER_ML_ID_VALID) { 783 peer_id &= ~ATH12K_PEER_ML_ID_VALID; 784 ml_peer = true; 785 } 786 787 if (ml_peer) 788 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 789 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 790 else 791 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 792 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 793 794 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 795 BUFFER_ADDR_INFO0_ADDR); 796 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 797 BUFFER_ADDR_INFO1_ADDR) | 798 u32_encode_bits(tid, DP_REO_QREF_NUM); 799 ath12k_hal_reo_shared_qaddr_cache_clear(ab); 800 } 801 802 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 803 { 804 struct ath12k_reo_queue_ref *qref; 805 struct ath12k_dp *dp = &ab->dp; 806 bool ml_peer = false; 807 808 if (!ab->hw_params->reoq_lut_support) 809 return; 810 811 if (peer_id & ATH12K_PEER_ML_ID_VALID) { 812 peer_id &= ~ATH12K_PEER_ML_ID_VALID; 813 ml_peer = true; 814 } 815 816 if (ml_peer) 817 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 818 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 819 else 820 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 821 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 822 823 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 824 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 825 u32_encode_bits(tid, DP_REO_QREF_NUM); 826 } 827 828 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 829 struct ath12k_peer *peer, u8 tid) 830 { 831 struct ath12k_hal_reo_cmd cmd = {0}; 832 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 833 int ret; 834 835 if (!rx_tid->active) 836 return; 837 838 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 839 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 840 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 841 cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 842 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 843 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 844 ath12k_dp_rx_tid_del_func); 845 if (ret) { 846 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 847 tid, ret); 848 dma_unmap_single(ar->ab->dev, rx_tid->qbuf.paddr_aligned, 849 rx_tid->qbuf.size, DMA_BIDIRECTIONAL); 850 kfree(rx_tid->qbuf.vaddr); 851 rx_tid->qbuf.vaddr = NULL; 852 } 853 854 if (peer->mlo) 855 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->ml_id, tid); 856 else 857 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 858 859 rx_tid->active = false; 860 } 861 862 int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 863 struct ath12k_buffer_addr *buf_addr_info, 864 enum hal_wbm_rel_bm_act action) 865 { 866 struct hal_wbm_release_ring *desc; 867 struct ath12k_dp *dp = &ab->dp; 868 struct hal_srng *srng; 869 int ret = 0; 870 871 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 872 873 spin_lock_bh(&srng->lock); 874 875 ath12k_hal_srng_access_begin(ab, srng); 876 877 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 878 if (!desc) { 879 ret = -ENOBUFS; 880 goto exit; 881 } 882 883 ath12k_hal_rx_msdu_link_desc_set(ab, desc, buf_addr_info, action); 884 885 exit: 886 ath12k_hal_srng_access_end(ab, srng); 887 888 spin_unlock_bh(&srng->lock); 889 890 return ret; 891 } 892 893 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 894 bool rel_link_desc) 895 { 896 struct ath12k_buffer_addr *buf_addr_info; 897 struct ath12k_base *ab = rx_tid->ab; 898 899 lockdep_assert_held(&ab->base_lock); 900 901 if (rx_tid->dst_ring_desc) { 902 if (rel_link_desc) { 903 buf_addr_info = &rx_tid->dst_ring_desc->buf_addr_info; 904 ath12k_dp_rx_link_desc_return(ab, buf_addr_info, 905 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 906 } 907 kfree(rx_tid->dst_ring_desc); 908 rx_tid->dst_ring_desc = NULL; 909 } 910 911 rx_tid->cur_sn = 0; 912 rx_tid->last_frag_no = 0; 913 rx_tid->rx_frag_bitmap = 0; 914 __skb_queue_purge(&rx_tid->rx_frags); 915 } 916 917 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 918 { 919 struct ath12k_dp_rx_tid *rx_tid; 920 int i; 921 922 lockdep_assert_held(&ar->ab->base_lock); 923 924 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 925 rx_tid = &peer->rx_tid[i]; 926 927 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 928 ath12k_dp_rx_frags_cleanup(rx_tid, true); 929 930 spin_unlock_bh(&ar->ab->base_lock); 931 timer_delete_sync(&rx_tid->frag_timer); 932 spin_lock_bh(&ar->ab->base_lock); 933 } 934 } 935 936 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 937 struct ath12k_peer *peer, 938 struct ath12k_dp_rx_tid *rx_tid, 939 u32 ba_win_sz, u16 ssn, 940 bool update_ssn) 941 { 942 struct ath12k_hal_reo_cmd cmd = {0}; 943 int ret; 944 945 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 946 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 947 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 948 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 949 cmd.ba_window_size = ba_win_sz; 950 951 if (update_ssn) { 952 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 953 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 954 } 955 956 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 957 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 958 NULL); 959 if (ret) { 960 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 961 rx_tid->tid, ret); 962 return ret; 963 } 964 965 rx_tid->ba_win_sz = ba_win_sz; 966 967 return 0; 968 } 969 970 static int ath12k_dp_rx_assign_reoq(struct ath12k_base *ab, 971 struct ath12k_sta *ahsta, 972 struct ath12k_dp_rx_tid *rx_tid, 973 u16 ssn, enum hal_pn_type pn_type) 974 { 975 u32 ba_win_sz = rx_tid->ba_win_sz; 976 struct ath12k_reoq_buf *buf; 977 void *vaddr, *vaddr_aligned; 978 dma_addr_t paddr_aligned; 979 u8 tid = rx_tid->tid; 980 u32 hw_desc_sz; 981 int ret; 982 983 buf = &ahsta->reoq_bufs[tid]; 984 if (!buf->vaddr) { 985 /* TODO: Optimize the memory allocation for qos tid based on 986 * the actual BA window size in REO tid update path. 987 */ 988 if (tid == HAL_DESC_REO_NON_QOS_TID) 989 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 990 else 991 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 992 993 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 994 if (!vaddr) 995 return -ENOMEM; 996 997 vaddr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 998 999 ath12k_hal_reo_qdesc_setup(vaddr_aligned, tid, ba_win_sz, 1000 ssn, pn_type); 1001 1002 paddr_aligned = dma_map_single(ab->dev, vaddr_aligned, hw_desc_sz, 1003 DMA_BIDIRECTIONAL); 1004 ret = dma_mapping_error(ab->dev, paddr_aligned); 1005 if (ret) { 1006 kfree(vaddr); 1007 return ret; 1008 } 1009 1010 buf->vaddr = vaddr; 1011 buf->paddr_aligned = paddr_aligned; 1012 buf->size = hw_desc_sz; 1013 } 1014 1015 rx_tid->qbuf = *buf; 1016 rx_tid->active = true; 1017 1018 return 0; 1019 } 1020 1021 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 1022 u8 tid, u32 ba_win_sz, u16 ssn, 1023 enum hal_pn_type pn_type) 1024 { 1025 struct ath12k_base *ab = ar->ab; 1026 struct ath12k_dp *dp = &ab->dp; 1027 struct ath12k_peer *peer; 1028 struct ath12k_sta *ahsta; 1029 struct ath12k_dp_rx_tid *rx_tid; 1030 dma_addr_t paddr_aligned; 1031 int ret; 1032 1033 spin_lock_bh(&ab->base_lock); 1034 1035 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 1036 if (!peer) { 1037 spin_unlock_bh(&ab->base_lock); 1038 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 1039 return -ENOENT; 1040 } 1041 1042 if (ab->hw_params->dp_primary_link_only && 1043 !peer->primary_link) { 1044 spin_unlock_bh(&ab->base_lock); 1045 return 0; 1046 } 1047 1048 if (ab->hw_params->reoq_lut_support && 1049 (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) { 1050 spin_unlock_bh(&ab->base_lock); 1051 ath12k_warn(ab, "reo qref table is not setup\n"); 1052 return -EINVAL; 1053 } 1054 1055 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 1056 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 1057 peer->peer_id, tid); 1058 spin_unlock_bh(&ab->base_lock); 1059 return -EINVAL; 1060 } 1061 1062 rx_tid = &peer->rx_tid[tid]; 1063 paddr_aligned = rx_tid->qbuf.paddr_aligned; 1064 /* Update the tid queue if it is already setup */ 1065 if (rx_tid->active) { 1066 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1067 ba_win_sz, ssn, true); 1068 spin_unlock_bh(&ab->base_lock); 1069 if (ret) { 1070 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 1071 return ret; 1072 } 1073 1074 if (!ab->hw_params->reoq_lut_support) { 1075 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1076 peer_mac, 1077 paddr_aligned, tid, 1078 1, ba_win_sz); 1079 if (ret) { 1080 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 1081 tid, ret); 1082 return ret; 1083 } 1084 } 1085 1086 return 0; 1087 } 1088 1089 rx_tid->tid = tid; 1090 1091 rx_tid->ba_win_sz = ba_win_sz; 1092 1093 ahsta = ath12k_sta_to_ahsta(peer->sta); 1094 ret = ath12k_dp_rx_assign_reoq(ab, ahsta, rx_tid, ssn, pn_type); 1095 if (ret) { 1096 spin_unlock_bh(&ab->base_lock); 1097 ath12k_warn(ab, "failed to assign reoq buf for rx tid %u\n", tid); 1098 return ret; 1099 } 1100 1101 if (ab->hw_params->reoq_lut_support) { 1102 /* Update the REO queue LUT at the corresponding peer id 1103 * and tid with qaddr. 1104 */ 1105 if (peer->mlo) 1106 ath12k_peer_rx_tid_qref_setup(ab, peer->ml_id, tid, 1107 paddr_aligned); 1108 else 1109 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, 1110 paddr_aligned); 1111 1112 spin_unlock_bh(&ab->base_lock); 1113 } else { 1114 spin_unlock_bh(&ab->base_lock); 1115 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1116 paddr_aligned, tid, 1, 1117 ba_win_sz); 1118 } 1119 1120 return ret; 1121 } 1122 1123 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1124 struct ieee80211_ampdu_params *params, 1125 u8 link_id) 1126 { 1127 struct ath12k_base *ab = ar->ab; 1128 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 1129 struct ath12k_link_sta *arsta; 1130 int vdev_id; 1131 int ret; 1132 1133 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 1134 1135 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 1136 ahsta->link[link_id]); 1137 if (!arsta) 1138 return -ENOLINK; 1139 1140 vdev_id = arsta->arvif->vdev_id; 1141 1142 ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id, 1143 params->tid, params->buf_size, 1144 params->ssn, arsta->ahsta->pn_type); 1145 if (ret) 1146 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1147 1148 return ret; 1149 } 1150 1151 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1152 struct ieee80211_ampdu_params *params, 1153 u8 link_id) 1154 { 1155 struct ath12k_base *ab = ar->ab; 1156 struct ath12k_peer *peer; 1157 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 1158 struct ath12k_link_sta *arsta; 1159 int vdev_id; 1160 bool active; 1161 int ret; 1162 1163 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 1164 1165 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 1166 ahsta->link[link_id]); 1167 if (!arsta) 1168 return -ENOLINK; 1169 1170 vdev_id = arsta->arvif->vdev_id; 1171 1172 spin_lock_bh(&ab->base_lock); 1173 1174 peer = ath12k_peer_find(ab, vdev_id, arsta->addr); 1175 if (!peer) { 1176 spin_unlock_bh(&ab->base_lock); 1177 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1178 return -ENOENT; 1179 } 1180 1181 active = peer->rx_tid[params->tid].active; 1182 1183 if (!active) { 1184 spin_unlock_bh(&ab->base_lock); 1185 return 0; 1186 } 1187 1188 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1189 spin_unlock_bh(&ab->base_lock); 1190 if (ret) { 1191 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1192 params->tid, ret); 1193 return ret; 1194 } 1195 1196 return ret; 1197 } 1198 1199 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, 1200 const u8 *peer_addr, 1201 enum set_key_cmd key_cmd, 1202 struct ieee80211_key_conf *key) 1203 { 1204 struct ath12k *ar = arvif->ar; 1205 struct ath12k_base *ab = ar->ab; 1206 struct ath12k_hal_reo_cmd cmd = {0}; 1207 struct ath12k_peer *peer; 1208 struct ath12k_dp_rx_tid *rx_tid; 1209 u8 tid; 1210 int ret = 0; 1211 1212 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1213 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1214 * for now. 1215 */ 1216 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1217 return 0; 1218 1219 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1220 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1221 HAL_REO_CMD_UPD0_PN_SIZE | 1222 HAL_REO_CMD_UPD0_PN_VALID | 1223 HAL_REO_CMD_UPD0_PN_CHECK | 1224 HAL_REO_CMD_UPD0_SVLD; 1225 1226 switch (key->cipher) { 1227 case WLAN_CIPHER_SUITE_TKIP: 1228 case WLAN_CIPHER_SUITE_CCMP: 1229 case WLAN_CIPHER_SUITE_CCMP_256: 1230 case WLAN_CIPHER_SUITE_GCMP: 1231 case WLAN_CIPHER_SUITE_GCMP_256: 1232 if (key_cmd == SET_KEY) { 1233 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1234 cmd.pn_size = 48; 1235 } 1236 break; 1237 default: 1238 break; 1239 } 1240 1241 spin_lock_bh(&ab->base_lock); 1242 1243 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1244 if (!peer) { 1245 spin_unlock_bh(&ab->base_lock); 1246 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1247 peer_addr); 1248 return -ENOENT; 1249 } 1250 1251 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1252 rx_tid = &peer->rx_tid[tid]; 1253 if (!rx_tid->active) 1254 continue; 1255 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 1256 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 1257 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1258 HAL_REO_CMD_UPDATE_RX_QUEUE, 1259 &cmd, NULL); 1260 if (ret) { 1261 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1262 tid, peer_addr, ret); 1263 break; 1264 } 1265 } 1266 1267 spin_unlock_bh(&ab->base_lock); 1268 1269 return ret; 1270 } 1271 1272 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1273 u16 peer_id) 1274 { 1275 int i; 1276 1277 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1278 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1279 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1280 return i; 1281 } else { 1282 return i; 1283 } 1284 } 1285 1286 return -EINVAL; 1287 } 1288 1289 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1290 u16 tag, u16 len, const void *ptr, 1291 void *data) 1292 { 1293 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1294 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1295 const struct htt_ppdu_stats_user_rate *user_rate; 1296 struct htt_ppdu_stats_info *ppdu_info; 1297 struct htt_ppdu_user_stats *user_stats; 1298 int cur_user; 1299 u16 peer_id; 1300 1301 ppdu_info = data; 1302 1303 switch (tag) { 1304 case HTT_PPDU_STATS_TAG_COMMON: 1305 if (len < sizeof(struct htt_ppdu_stats_common)) { 1306 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1307 len, tag); 1308 return -EINVAL; 1309 } 1310 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1311 sizeof(struct htt_ppdu_stats_common)); 1312 break; 1313 case HTT_PPDU_STATS_TAG_USR_RATE: 1314 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1315 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1316 len, tag); 1317 return -EINVAL; 1318 } 1319 user_rate = ptr; 1320 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1321 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1322 peer_id); 1323 if (cur_user < 0) 1324 return -EINVAL; 1325 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1326 user_stats->peer_id = peer_id; 1327 user_stats->is_valid_peer_id = true; 1328 memcpy(&user_stats->rate, ptr, 1329 sizeof(struct htt_ppdu_stats_user_rate)); 1330 user_stats->tlv_flags |= BIT(tag); 1331 break; 1332 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1333 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1334 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1335 len, tag); 1336 return -EINVAL; 1337 } 1338 1339 cmplt_cmn = ptr; 1340 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1341 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1342 peer_id); 1343 if (cur_user < 0) 1344 return -EINVAL; 1345 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1346 user_stats->peer_id = peer_id; 1347 user_stats->is_valid_peer_id = true; 1348 memcpy(&user_stats->cmpltn_cmn, ptr, 1349 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1350 user_stats->tlv_flags |= BIT(tag); 1351 break; 1352 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1353 if (len < 1354 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1355 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1356 len, tag); 1357 return -EINVAL; 1358 } 1359 1360 ba_status = ptr; 1361 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1362 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1363 peer_id); 1364 if (cur_user < 0) 1365 return -EINVAL; 1366 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1367 user_stats->peer_id = peer_id; 1368 user_stats->is_valid_peer_id = true; 1369 memcpy(&user_stats->ack_ba, ptr, 1370 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1371 user_stats->tlv_flags |= BIT(tag); 1372 break; 1373 } 1374 return 0; 1375 } 1376 1377 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1378 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1379 const void *ptr, void *data), 1380 void *data) 1381 { 1382 const struct htt_tlv *tlv; 1383 const void *begin = ptr; 1384 u16 tlv_tag, tlv_len; 1385 int ret = -EINVAL; 1386 1387 while (len > 0) { 1388 if (len < sizeof(*tlv)) { 1389 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1390 ptr - begin, len, sizeof(*tlv)); 1391 return -EINVAL; 1392 } 1393 tlv = (struct htt_tlv *)ptr; 1394 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1395 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1396 ptr += sizeof(*tlv); 1397 len -= sizeof(*tlv); 1398 1399 if (tlv_len > len) { 1400 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1401 tlv_tag, ptr - begin, len, tlv_len); 1402 return -EINVAL; 1403 } 1404 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1405 if (ret == -ENOMEM) 1406 return ret; 1407 1408 ptr += tlv_len; 1409 len -= tlv_len; 1410 } 1411 return 0; 1412 } 1413 1414 static void 1415 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1416 struct htt_ppdu_stats *ppdu_stats, u8 user) 1417 { 1418 struct ath12k_base *ab = ar->ab; 1419 struct ath12k_peer *peer; 1420 struct ath12k_link_sta *arsta; 1421 struct htt_ppdu_stats_user_rate *user_rate; 1422 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1423 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1424 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1425 int ret; 1426 u8 flags, mcs, nss, bw, sgi, dcm, ppdu_type, rate_idx = 0; 1427 u32 v, succ_bytes = 0; 1428 u16 tones, rate = 0, succ_pkts = 0; 1429 u32 tx_duration = 0; 1430 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1431 u16 tx_retry_failed = 0, tx_retry_count = 0; 1432 bool is_ampdu = false, is_ofdma; 1433 1434 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1435 return; 1436 1437 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) { 1438 is_ampdu = 1439 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1440 tx_retry_failed = 1441 __le16_to_cpu(usr_stats->cmpltn_cmn.mpdu_tried) - 1442 __le16_to_cpu(usr_stats->cmpltn_cmn.mpdu_success); 1443 tx_retry_count = 1444 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1445 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1446 } 1447 1448 if (usr_stats->tlv_flags & 1449 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1450 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1451 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1452 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1453 tid = le32_get_bits(usr_stats->ack_ba.info, 1454 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1455 } 1456 1457 if (common->fes_duration_us) 1458 tx_duration = le32_to_cpu(common->fes_duration_us); 1459 1460 user_rate = &usr_stats->rate; 1461 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1462 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1463 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1464 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1465 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1466 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1467 1468 ppdu_type = HTT_USR_RATE_PPDU_TYPE(user_rate->info1); 1469 is_ofdma = (ppdu_type == HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA) || 1470 (ppdu_type == HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA); 1471 1472 /* Note: If host configured fixed rates and in some other special 1473 * cases, the broadcast/management frames are sent in different rates. 1474 * Firmware rate's control to be skipped for this? 1475 */ 1476 1477 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1478 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1479 return; 1480 } 1481 1482 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1483 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1484 return; 1485 } 1486 1487 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1488 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1489 mcs, nss); 1490 return; 1491 } 1492 1493 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1494 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1495 flags, 1496 &rate_idx, 1497 &rate); 1498 if (ret < 0) 1499 return; 1500 } 1501 1502 rcu_read_lock(); 1503 spin_lock_bh(&ab->base_lock); 1504 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1505 1506 if (!peer || !peer->sta) { 1507 spin_unlock_bh(&ab->base_lock); 1508 rcu_read_unlock(); 1509 return; 1510 } 1511 1512 arsta = ath12k_peer_get_link_sta(ab, peer); 1513 if (!arsta) { 1514 spin_unlock_bh(&ab->base_lock); 1515 rcu_read_unlock(); 1516 return; 1517 } 1518 1519 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1520 1521 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1522 1523 switch (flags) { 1524 case WMI_RATE_PREAMBLE_OFDM: 1525 arsta->txrate.legacy = rate; 1526 break; 1527 case WMI_RATE_PREAMBLE_CCK: 1528 arsta->txrate.legacy = rate; 1529 break; 1530 case WMI_RATE_PREAMBLE_HT: 1531 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1532 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1533 if (sgi) 1534 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1535 break; 1536 case WMI_RATE_PREAMBLE_VHT: 1537 arsta->txrate.mcs = mcs; 1538 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1539 if (sgi) 1540 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1541 break; 1542 case WMI_RATE_PREAMBLE_HE: 1543 arsta->txrate.mcs = mcs; 1544 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1545 arsta->txrate.he_dcm = dcm; 1546 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1547 tones = le16_to_cpu(user_rate->ru_end) - 1548 le16_to_cpu(user_rate->ru_start) + 1; 1549 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1550 arsta->txrate.he_ru_alloc = v; 1551 if (is_ofdma) 1552 arsta->txrate.bw = RATE_INFO_BW_HE_RU; 1553 break; 1554 case WMI_RATE_PREAMBLE_EHT: 1555 arsta->txrate.mcs = mcs; 1556 arsta->txrate.flags = RATE_INFO_FLAGS_EHT_MCS; 1557 arsta->txrate.he_dcm = dcm; 1558 arsta->txrate.eht_gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi); 1559 tones = le16_to_cpu(user_rate->ru_end) - 1560 le16_to_cpu(user_rate->ru_start) + 1; 1561 v = ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(tones); 1562 arsta->txrate.eht_ru_alloc = v; 1563 if (is_ofdma) 1564 arsta->txrate.bw = RATE_INFO_BW_EHT_RU; 1565 break; 1566 } 1567 1568 arsta->tx_retry_failed += tx_retry_failed; 1569 arsta->tx_retry_count += tx_retry_count; 1570 arsta->txrate.nss = nss; 1571 arsta->tx_duration += tx_duration; 1572 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1573 1574 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1575 * So skip peer stats update for mgmt packets. 1576 */ 1577 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1578 memset(peer_stats, 0, sizeof(*peer_stats)); 1579 peer_stats->succ_pkts = succ_pkts; 1580 peer_stats->succ_bytes = succ_bytes; 1581 peer_stats->is_ampdu = is_ampdu; 1582 peer_stats->duration = tx_duration; 1583 peer_stats->ba_fails = 1584 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1585 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1586 } 1587 1588 spin_unlock_bh(&ab->base_lock); 1589 rcu_read_unlock(); 1590 } 1591 1592 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1593 struct htt_ppdu_stats *ppdu_stats) 1594 { 1595 u8 user; 1596 1597 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1598 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1599 } 1600 1601 static 1602 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1603 u32 ppdu_id) 1604 { 1605 struct htt_ppdu_stats_info *ppdu_info; 1606 1607 lockdep_assert_held(&ar->data_lock); 1608 if (!list_empty(&ar->ppdu_stats_info)) { 1609 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1610 if (ppdu_info->ppdu_id == ppdu_id) 1611 return ppdu_info; 1612 } 1613 1614 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1615 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1616 typeof(*ppdu_info), list); 1617 list_del(&ppdu_info->list); 1618 ar->ppdu_stat_list_depth--; 1619 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1620 kfree(ppdu_info); 1621 } 1622 } 1623 1624 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1625 if (!ppdu_info) 1626 return NULL; 1627 1628 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1629 ar->ppdu_stat_list_depth++; 1630 1631 return ppdu_info; 1632 } 1633 1634 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1635 struct htt_ppdu_user_stats *usr_stats) 1636 { 1637 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1638 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1639 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1640 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1641 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1642 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1643 peer->ppdu_stats_delayba.resp_rate_flags = 1644 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1645 1646 peer->delayba_flag = true; 1647 } 1648 1649 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1650 struct htt_ppdu_user_stats *usr_stats) 1651 { 1652 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1653 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1654 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1655 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1656 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1657 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1658 usr_stats->rate.resp_rate_flags = 1659 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1660 1661 peer->delayba_flag = false; 1662 } 1663 1664 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1665 struct sk_buff *skb) 1666 { 1667 struct ath12k_htt_ppdu_stats_msg *msg; 1668 struct htt_ppdu_stats_info *ppdu_info; 1669 struct ath12k_peer *peer = NULL; 1670 struct htt_ppdu_user_stats *usr_stats = NULL; 1671 u32 peer_id = 0; 1672 struct ath12k *ar; 1673 int ret, i; 1674 u8 pdev_id; 1675 u32 ppdu_id, len; 1676 1677 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1678 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1679 if (len > (skb->len - struct_size(msg, data, 0))) { 1680 ath12k_warn(ab, 1681 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1682 len, skb->len); 1683 return -EINVAL; 1684 } 1685 1686 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1687 ppdu_id = le32_to_cpu(msg->ppdu_id); 1688 1689 rcu_read_lock(); 1690 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1691 if (!ar) { 1692 ret = -EINVAL; 1693 goto exit; 1694 } 1695 1696 spin_lock_bh(&ar->data_lock); 1697 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1698 if (!ppdu_info) { 1699 spin_unlock_bh(&ar->data_lock); 1700 ret = -EINVAL; 1701 goto exit; 1702 } 1703 1704 ppdu_info->ppdu_id = ppdu_id; 1705 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1706 ath12k_htt_tlv_ppdu_stats_parse, 1707 (void *)ppdu_info); 1708 if (ret) { 1709 spin_unlock_bh(&ar->data_lock); 1710 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1711 goto exit; 1712 } 1713 1714 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1715 spin_unlock_bh(&ar->data_lock); 1716 ath12k_warn(ab, 1717 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1718 ppdu_info->ppdu_stats.common.num_users, 1719 HTT_PPDU_STATS_MAX_USERS); 1720 ret = -EINVAL; 1721 goto exit; 1722 } 1723 1724 /* back up data rate tlv for all peers */ 1725 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1726 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1727 ppdu_info->delay_ba) { 1728 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1729 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1730 spin_lock_bh(&ab->base_lock); 1731 peer = ath12k_peer_find_by_id(ab, peer_id); 1732 if (!peer) { 1733 spin_unlock_bh(&ab->base_lock); 1734 continue; 1735 } 1736 1737 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1738 if (usr_stats->delay_ba) 1739 ath12k_copy_to_delay_stats(peer, usr_stats); 1740 spin_unlock_bh(&ab->base_lock); 1741 } 1742 } 1743 1744 /* restore all peers' data rate tlv to mu-bar tlv */ 1745 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1746 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1747 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1748 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1749 spin_lock_bh(&ab->base_lock); 1750 peer = ath12k_peer_find_by_id(ab, peer_id); 1751 if (!peer) { 1752 spin_unlock_bh(&ab->base_lock); 1753 continue; 1754 } 1755 1756 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1757 if (peer->delayba_flag) 1758 ath12k_copy_to_bar(peer, usr_stats); 1759 spin_unlock_bh(&ab->base_lock); 1760 } 1761 } 1762 1763 spin_unlock_bh(&ar->data_lock); 1764 1765 exit: 1766 rcu_read_unlock(); 1767 1768 return ret; 1769 } 1770 1771 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1772 struct sk_buff *skb) 1773 { 1774 struct ath12k_htt_mlo_offset_msg *msg; 1775 struct ath12k_pdev *pdev; 1776 struct ath12k *ar; 1777 u8 pdev_id; 1778 1779 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1780 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1781 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1782 1783 rcu_read_lock(); 1784 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1785 if (!ar) { 1786 /* It is possible that the ar is not yet active (started). 1787 * The above function will only look for the active pdev 1788 * and hence %NULL return is possible. Just silently 1789 * discard this message 1790 */ 1791 goto exit; 1792 } 1793 1794 spin_lock_bh(&ar->data_lock); 1795 pdev = ar->pdev; 1796 1797 pdev->timestamp.info = __le32_to_cpu(msg->info); 1798 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1799 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1800 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1801 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1802 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1803 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1804 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1805 1806 spin_unlock_bh(&ar->data_lock); 1807 exit: 1808 rcu_read_unlock(); 1809 } 1810 1811 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1812 struct sk_buff *skb) 1813 { 1814 struct ath12k_dp *dp = &ab->dp; 1815 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1816 enum htt_t2h_msg_type type; 1817 u16 peer_id; 1818 u8 vdev_id; 1819 u8 mac_addr[ETH_ALEN]; 1820 u16 peer_mac_h16; 1821 u16 ast_hash = 0; 1822 u16 hw_peer_id; 1823 1824 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1825 1826 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1827 1828 switch (type) { 1829 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1830 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1831 HTT_T2H_VERSION_CONF_MAJOR); 1832 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1833 HTT_T2H_VERSION_CONF_MINOR); 1834 complete(&dp->htt_tgt_version_received); 1835 break; 1836 /* TODO: remove unused peer map versions after testing */ 1837 case HTT_T2H_MSG_TYPE_PEER_MAP: 1838 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1839 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1840 peer_id = le32_get_bits(resp->peer_map_ev.info, 1841 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1842 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1843 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1844 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1845 peer_mac_h16, mac_addr); 1846 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1847 break; 1848 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1849 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1850 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1851 peer_id = le32_get_bits(resp->peer_map_ev.info, 1852 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1853 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1854 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1855 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1856 peer_mac_h16, mac_addr); 1857 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1858 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1859 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1860 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1861 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1862 hw_peer_id); 1863 break; 1864 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1865 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1866 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1867 peer_id = le32_get_bits(resp->peer_map_ev.info, 1868 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1869 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1870 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1871 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1872 peer_mac_h16, mac_addr); 1873 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1874 HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL); 1875 hw_peer_id = le32_get_bits(resp->peer_map_ev.info2, 1876 HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID); 1877 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1878 hw_peer_id); 1879 break; 1880 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1881 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1882 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1883 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1884 ath12k_peer_unmap_event(ab, peer_id); 1885 break; 1886 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1887 ath12k_htt_pull_ppdu_stats(ab, skb); 1888 break; 1889 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1890 ath12k_debugfs_htt_ext_stats_handler(ab, skb); 1891 break; 1892 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 1893 ath12k_htt_mlo_offset_event_handler(ab, skb); 1894 break; 1895 default: 1896 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 1897 type); 1898 break; 1899 } 1900 1901 dev_kfree_skb_any(skb); 1902 } 1903 1904 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 1905 struct sk_buff_head *msdu_list, 1906 struct sk_buff *first, struct sk_buff *last, 1907 u8 l3pad_bytes, int msdu_len) 1908 { 1909 struct ath12k_base *ab = ar->ab; 1910 struct sk_buff *skb; 1911 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1912 int buf_first_hdr_len, buf_first_len; 1913 struct hal_rx_desc *ldesc; 1914 int space_extra, rem_len, buf_len; 1915 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 1916 bool is_continuation; 1917 1918 /* As the msdu is spread across multiple rx buffers, 1919 * find the offset to the start of msdu for computing 1920 * the length of the msdu in the first buffer. 1921 */ 1922 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1923 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1924 1925 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1926 skb_put(first, buf_first_hdr_len + msdu_len); 1927 skb_pull(first, buf_first_hdr_len); 1928 return 0; 1929 } 1930 1931 ldesc = (struct hal_rx_desc *)last->data; 1932 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 1933 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 1934 1935 /* MSDU spans over multiple buffers because the length of the MSDU 1936 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1937 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1938 */ 1939 skb_put(first, DP_RX_BUFFER_SIZE); 1940 skb_pull(first, buf_first_hdr_len); 1941 1942 /* When an MSDU spread over multiple buffers MSDU_END 1943 * tlvs are valid only in the last buffer. Copy those tlvs. 1944 */ 1945 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1946 1947 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1948 if (space_extra > 0 && 1949 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1950 /* Free up all buffers of the MSDU */ 1951 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1952 rxcb = ATH12K_SKB_RXCB(skb); 1953 if (!rxcb->is_continuation) { 1954 dev_kfree_skb_any(skb); 1955 break; 1956 } 1957 dev_kfree_skb_any(skb); 1958 } 1959 return -ENOMEM; 1960 } 1961 1962 rem_len = msdu_len - buf_first_len; 1963 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1964 rxcb = ATH12K_SKB_RXCB(skb); 1965 is_continuation = rxcb->is_continuation; 1966 if (is_continuation) 1967 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1968 else 1969 buf_len = rem_len; 1970 1971 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1972 WARN_ON_ONCE(1); 1973 dev_kfree_skb_any(skb); 1974 return -EINVAL; 1975 } 1976 1977 skb_put(skb, buf_len + hal_rx_desc_sz); 1978 skb_pull(skb, hal_rx_desc_sz); 1979 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1980 buf_len); 1981 dev_kfree_skb_any(skb); 1982 1983 rem_len -= buf_len; 1984 if (!is_continuation) 1985 break; 1986 } 1987 1988 return 0; 1989 } 1990 1991 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1992 struct sk_buff *first) 1993 { 1994 struct sk_buff *skb; 1995 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1996 1997 if (!rxcb->is_continuation) 1998 return first; 1999 2000 skb_queue_walk(msdu_list, skb) { 2001 rxcb = ATH12K_SKB_RXCB(skb); 2002 if (!rxcb->is_continuation) 2003 return skb; 2004 } 2005 2006 return NULL; 2007 } 2008 2009 static void ath12k_dp_rx_h_csum_offload(struct sk_buff *msdu, 2010 struct ath12k_dp_rx_info *rx_info) 2011 { 2012 msdu->ip_summed = (rx_info->ip_csum_fail || rx_info->l4_csum_fail) ? 2013 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 2014 } 2015 2016 int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, enum hal_encrypt_type enctype) 2017 { 2018 switch (enctype) { 2019 case HAL_ENCRYPT_TYPE_OPEN: 2020 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 2021 case HAL_ENCRYPT_TYPE_TKIP_MIC: 2022 return 0; 2023 case HAL_ENCRYPT_TYPE_CCMP_128: 2024 return IEEE80211_CCMP_MIC_LEN; 2025 case HAL_ENCRYPT_TYPE_CCMP_256: 2026 return IEEE80211_CCMP_256_MIC_LEN; 2027 case HAL_ENCRYPT_TYPE_GCMP_128: 2028 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 2029 return IEEE80211_GCMP_MIC_LEN; 2030 case HAL_ENCRYPT_TYPE_WEP_40: 2031 case HAL_ENCRYPT_TYPE_WEP_104: 2032 case HAL_ENCRYPT_TYPE_WEP_128: 2033 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 2034 case HAL_ENCRYPT_TYPE_WAPI: 2035 break; 2036 } 2037 2038 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 2039 return 0; 2040 } 2041 2042 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 2043 enum hal_encrypt_type enctype) 2044 { 2045 switch (enctype) { 2046 case HAL_ENCRYPT_TYPE_OPEN: 2047 return 0; 2048 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 2049 case HAL_ENCRYPT_TYPE_TKIP_MIC: 2050 return IEEE80211_TKIP_IV_LEN; 2051 case HAL_ENCRYPT_TYPE_CCMP_128: 2052 return IEEE80211_CCMP_HDR_LEN; 2053 case HAL_ENCRYPT_TYPE_CCMP_256: 2054 return IEEE80211_CCMP_256_HDR_LEN; 2055 case HAL_ENCRYPT_TYPE_GCMP_128: 2056 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 2057 return IEEE80211_GCMP_HDR_LEN; 2058 case HAL_ENCRYPT_TYPE_WEP_40: 2059 case HAL_ENCRYPT_TYPE_WEP_104: 2060 case HAL_ENCRYPT_TYPE_WEP_128: 2061 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 2062 case HAL_ENCRYPT_TYPE_WAPI: 2063 break; 2064 } 2065 2066 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 2067 return 0; 2068 } 2069 2070 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 2071 enum hal_encrypt_type enctype) 2072 { 2073 switch (enctype) { 2074 case HAL_ENCRYPT_TYPE_OPEN: 2075 case HAL_ENCRYPT_TYPE_CCMP_128: 2076 case HAL_ENCRYPT_TYPE_CCMP_256: 2077 case HAL_ENCRYPT_TYPE_GCMP_128: 2078 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 2079 return 0; 2080 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 2081 case HAL_ENCRYPT_TYPE_TKIP_MIC: 2082 return IEEE80211_TKIP_ICV_LEN; 2083 case HAL_ENCRYPT_TYPE_WEP_40: 2084 case HAL_ENCRYPT_TYPE_WEP_104: 2085 case HAL_ENCRYPT_TYPE_WEP_128: 2086 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 2087 case HAL_ENCRYPT_TYPE_WAPI: 2088 break; 2089 } 2090 2091 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 2092 return 0; 2093 } 2094 2095 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 2096 struct sk_buff *msdu, 2097 enum hal_encrypt_type enctype, 2098 struct ieee80211_rx_status *status) 2099 { 2100 struct ath12k_base *ab = ar->ab; 2101 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2102 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 2103 struct ieee80211_hdr *hdr; 2104 size_t hdr_len; 2105 u8 *crypto_hdr; 2106 u16 qos_ctl; 2107 2108 /* pull decapped header */ 2109 hdr = (struct ieee80211_hdr *)msdu->data; 2110 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2111 skb_pull(msdu, hdr_len); 2112 2113 /* Rebuild qos header */ 2114 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 2115 2116 /* Reset the order bit as the HT_Control header is stripped */ 2117 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2118 2119 qos_ctl = rxcb->tid; 2120 2121 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 2122 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2123 2124 /* TODO: Add other QoS ctl fields when required */ 2125 2126 /* copy decap header before overwriting for reuse below */ 2127 memcpy(decap_hdr, hdr, hdr_len); 2128 2129 /* Rebuild crypto header for mac80211 use */ 2130 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2131 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 2132 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 2133 rxcb->rx_desc, crypto_hdr, 2134 enctype); 2135 } 2136 2137 memcpy(skb_push(msdu, 2138 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2139 IEEE80211_QOS_CTL_LEN); 2140 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2141 } 2142 2143 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2144 enum hal_encrypt_type enctype, 2145 struct ieee80211_rx_status *status, 2146 bool decrypted) 2147 { 2148 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2149 struct ieee80211_hdr *hdr; 2150 size_t hdr_len; 2151 size_t crypto_len; 2152 2153 if (!rxcb->is_first_msdu || 2154 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2155 WARN_ON_ONCE(1); 2156 return; 2157 } 2158 2159 skb_trim(msdu, msdu->len - FCS_LEN); 2160 2161 if (!decrypted) 2162 return; 2163 2164 hdr = (void *)msdu->data; 2165 2166 /* Tail */ 2167 if (status->flag & RX_FLAG_IV_STRIPPED) { 2168 skb_trim(msdu, msdu->len - 2169 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2170 2171 skb_trim(msdu, msdu->len - 2172 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2173 } else { 2174 /* MIC */ 2175 if (status->flag & RX_FLAG_MIC_STRIPPED) 2176 skb_trim(msdu, msdu->len - 2177 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2178 2179 /* ICV */ 2180 if (status->flag & RX_FLAG_ICV_STRIPPED) 2181 skb_trim(msdu, msdu->len - 2182 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2183 } 2184 2185 /* MMIC */ 2186 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2187 !ieee80211_has_morefrags(hdr->frame_control) && 2188 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2189 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2190 2191 /* Head */ 2192 if (status->flag & RX_FLAG_IV_STRIPPED) { 2193 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2194 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2195 2196 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2197 skb_pull(msdu, crypto_len); 2198 } 2199 } 2200 2201 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2202 struct sk_buff *msdu, 2203 struct ath12k_skb_rxcb *rxcb, 2204 struct ieee80211_rx_status *status, 2205 enum hal_encrypt_type enctype) 2206 { 2207 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2208 struct ath12k_base *ab = ar->ab; 2209 size_t hdr_len, crypto_len; 2210 struct ieee80211_hdr hdr; 2211 __le16 qos_ctl; 2212 u8 *crypto_hdr, mesh_ctrl; 2213 2214 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, &hdr); 2215 hdr_len = ieee80211_hdrlen(hdr.frame_control); 2216 mesh_ctrl = ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc); 2217 2218 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2219 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2220 crypto_hdr = skb_push(msdu, crypto_len); 2221 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2222 } 2223 2224 skb_push(msdu, hdr_len); 2225 memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr))); 2226 2227 if (rxcb->is_mcbc) 2228 status->flag &= ~RX_FLAG_PN_VALIDATED; 2229 2230 /* Add QOS header */ 2231 if (ieee80211_is_data_qos(hdr.frame_control)) { 2232 struct ieee80211_hdr *qos_ptr = (struct ieee80211_hdr *)msdu->data; 2233 2234 qos_ctl = cpu_to_le16(rxcb->tid & IEEE80211_QOS_CTL_TID_MASK); 2235 if (mesh_ctrl) 2236 qos_ctl |= cpu_to_le16(IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT); 2237 2238 memcpy(ieee80211_get_qos_ctl(qos_ptr), &qos_ctl, IEEE80211_QOS_CTL_LEN); 2239 } 2240 } 2241 2242 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2243 struct sk_buff *msdu, 2244 enum hal_encrypt_type enctype, 2245 struct ieee80211_rx_status *status) 2246 { 2247 struct ieee80211_hdr *hdr; 2248 struct ethhdr *eth; 2249 u8 da[ETH_ALEN]; 2250 u8 sa[ETH_ALEN]; 2251 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2252 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2253 2254 eth = (struct ethhdr *)msdu->data; 2255 ether_addr_copy(da, eth->h_dest); 2256 ether_addr_copy(sa, eth->h_source); 2257 rfc.snap_type = eth->h_proto; 2258 skb_pull(msdu, sizeof(*eth)); 2259 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2260 sizeof(rfc)); 2261 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2262 2263 /* original 802.11 header has a different DA and in 2264 * case of 4addr it may also have different SA 2265 */ 2266 hdr = (struct ieee80211_hdr *)msdu->data; 2267 ether_addr_copy(ieee80211_get_DA(hdr), da); 2268 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2269 } 2270 2271 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2272 struct hal_rx_desc *rx_desc, 2273 enum hal_encrypt_type enctype, 2274 struct ieee80211_rx_status *status, 2275 bool decrypted) 2276 { 2277 struct ath12k_base *ab = ar->ab; 2278 u8 decap; 2279 struct ethhdr *ehdr; 2280 2281 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2282 2283 switch (decap) { 2284 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2285 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2286 break; 2287 case DP_RX_DECAP_TYPE_RAW: 2288 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2289 decrypted); 2290 break; 2291 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2292 ehdr = (struct ethhdr *)msdu->data; 2293 2294 /* mac80211 allows fast path only for authorized STA */ 2295 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2296 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2297 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2298 break; 2299 } 2300 2301 /* PN for mcast packets will be validated in mac80211; 2302 * remove eth header and add 802.11 header. 2303 */ 2304 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2305 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2306 break; 2307 case DP_RX_DECAP_TYPE_8023: 2308 /* TODO: Handle undecap for these formats */ 2309 break; 2310 } 2311 } 2312 2313 struct ath12k_peer * 2314 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu, 2315 struct ath12k_dp_rx_info *rx_info) 2316 { 2317 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2318 struct ath12k_peer *peer = NULL; 2319 2320 lockdep_assert_held(&ab->base_lock); 2321 2322 if (rxcb->peer_id) 2323 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2324 2325 if (peer) 2326 return peer; 2327 2328 if (rx_info->addr2_present) 2329 peer = ath12k_peer_find_by_addr(ab, rx_info->addr2); 2330 2331 return peer; 2332 } 2333 2334 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2335 struct sk_buff *msdu, 2336 struct hal_rx_desc *rx_desc, 2337 struct ath12k_dp_rx_info *rx_info) 2338 { 2339 struct ath12k_base *ab = ar->ab; 2340 struct ath12k_skb_rxcb *rxcb; 2341 enum hal_encrypt_type enctype; 2342 bool is_decrypted = false; 2343 struct ieee80211_hdr *hdr; 2344 struct ath12k_peer *peer; 2345 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 2346 u32 err_bitmap; 2347 2348 /* PN for multicast packets will be checked in mac80211 */ 2349 rxcb = ATH12K_SKB_RXCB(msdu); 2350 rxcb->is_mcbc = rx_info->is_mcbc; 2351 2352 if (rxcb->is_mcbc) 2353 rxcb->peer_id = rx_info->peer_id; 2354 2355 spin_lock_bh(&ar->ab->base_lock); 2356 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu, rx_info); 2357 if (peer) { 2358 /* resetting mcbc bit because mcbc packets are unicast 2359 * packets only for AP as STA sends unicast packets. 2360 */ 2361 rxcb->is_mcbc = rxcb->is_mcbc && !peer->ucast_ra_only; 2362 2363 if (rxcb->is_mcbc) 2364 enctype = peer->sec_type_grp; 2365 else 2366 enctype = peer->sec_type; 2367 } else { 2368 enctype = HAL_ENCRYPT_TYPE_OPEN; 2369 } 2370 spin_unlock_bh(&ar->ab->base_lock); 2371 2372 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2373 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2374 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2375 2376 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2377 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2378 RX_FLAG_MMIC_ERROR | 2379 RX_FLAG_DECRYPTED | 2380 RX_FLAG_IV_STRIPPED | 2381 RX_FLAG_MMIC_STRIPPED); 2382 2383 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2384 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2385 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2386 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2387 2388 if (is_decrypted) { 2389 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2390 2391 if (rx_info->is_mcbc) 2392 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2393 RX_FLAG_ICV_STRIPPED; 2394 else 2395 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2396 RX_FLAG_PN_VALIDATED; 2397 } 2398 2399 ath12k_dp_rx_h_csum_offload(msdu, rx_info); 2400 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2401 enctype, rx_status, is_decrypted); 2402 2403 if (!is_decrypted || rx_info->is_mcbc) 2404 return; 2405 2406 if (rx_info->decap_type != DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2407 hdr = (void *)msdu->data; 2408 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2409 } 2410 } 2411 2412 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info) 2413 { 2414 struct ieee80211_supported_band *sband; 2415 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 2416 enum rx_msdu_start_pkt_type pkt_type = rx_info->pkt_type; 2417 u8 bw = rx_info->bw, sgi = rx_info->sgi; 2418 u8 rate_mcs = rx_info->rate_mcs, nss = rx_info->nss; 2419 bool is_cck; 2420 2421 switch (pkt_type) { 2422 case RX_MSDU_START_PKT_TYPE_11A: 2423 case RX_MSDU_START_PKT_TYPE_11B: 2424 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2425 sband = &ar->mac.sbands[rx_status->band]; 2426 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2427 is_cck); 2428 break; 2429 case RX_MSDU_START_PKT_TYPE_11N: 2430 rx_status->encoding = RX_ENC_HT; 2431 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2432 ath12k_warn(ar->ab, 2433 "Received with invalid mcs in HT mode %d\n", 2434 rate_mcs); 2435 break; 2436 } 2437 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2438 if (sgi) 2439 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2440 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2441 break; 2442 case RX_MSDU_START_PKT_TYPE_11AC: 2443 rx_status->encoding = RX_ENC_VHT; 2444 rx_status->rate_idx = rate_mcs; 2445 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2446 ath12k_warn(ar->ab, 2447 "Received with invalid mcs in VHT mode %d\n", 2448 rate_mcs); 2449 break; 2450 } 2451 rx_status->nss = nss; 2452 if (sgi) 2453 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2454 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2455 break; 2456 case RX_MSDU_START_PKT_TYPE_11AX: 2457 rx_status->rate_idx = rate_mcs; 2458 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2459 ath12k_warn(ar->ab, 2460 "Received with invalid mcs in HE mode %d\n", 2461 rate_mcs); 2462 break; 2463 } 2464 rx_status->encoding = RX_ENC_HE; 2465 rx_status->nss = nss; 2466 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2467 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2468 break; 2469 case RX_MSDU_START_PKT_TYPE_11BE: 2470 rx_status->rate_idx = rate_mcs; 2471 2472 if (rate_mcs > ATH12K_EHT_MCS_MAX) { 2473 ath12k_warn(ar->ab, 2474 "Received with invalid mcs in EHT mode %d\n", 2475 rate_mcs); 2476 break; 2477 } 2478 2479 rx_status->encoding = RX_ENC_EHT; 2480 rx_status->nss = nss; 2481 rx_status->eht.gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi); 2482 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2483 break; 2484 default: 2485 break; 2486 } 2487 } 2488 2489 void ath12k_dp_rx_h_fetch_info(struct ath12k_base *ab, struct hal_rx_desc *rx_desc, 2490 struct ath12k_dp_rx_info *rx_info) 2491 { 2492 rx_info->ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rx_desc); 2493 rx_info->l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rx_desc); 2494 rx_info->is_mcbc = ath12k_dp_rx_h_is_da_mcbc(ab, rx_desc); 2495 rx_info->decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2496 rx_info->pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2497 rx_info->sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2498 rx_info->rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2499 rx_info->bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2500 rx_info->nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2501 rx_info->tid = ath12k_dp_rx_h_tid(ab, rx_desc); 2502 rx_info->peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 2503 rx_info->phy_meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2504 2505 if (ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)) { 2506 ether_addr_copy(rx_info->addr2, 2507 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, rx_desc)); 2508 rx_info->addr2_present = true; 2509 } 2510 2511 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2512 rx_desc, sizeof(*rx_desc)); 2513 } 2514 2515 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info) 2516 { 2517 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 2518 u8 channel_num; 2519 u32 center_freq, meta_data; 2520 struct ieee80211_channel *channel; 2521 2522 rx_status->freq = 0; 2523 rx_status->rate_idx = 0; 2524 rx_status->nss = 0; 2525 rx_status->encoding = RX_ENC_LEGACY; 2526 rx_status->bw = RATE_INFO_BW_20; 2527 rx_status->enc_flags = 0; 2528 2529 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2530 2531 meta_data = rx_info->phy_meta_data; 2532 channel_num = meta_data; 2533 center_freq = meta_data >> 16; 2534 2535 if (center_freq >= ATH12K_MIN_6GHZ_FREQ && 2536 center_freq <= ATH12K_MAX_6GHZ_FREQ) { 2537 rx_status->band = NL80211_BAND_6GHZ; 2538 rx_status->freq = center_freq; 2539 } else if (channel_num >= 1 && channel_num <= 14) { 2540 rx_status->band = NL80211_BAND_2GHZ; 2541 } else if (channel_num >= 36 && channel_num <= 173) { 2542 rx_status->band = NL80211_BAND_5GHZ; 2543 } else { 2544 spin_lock_bh(&ar->data_lock); 2545 channel = ar->rx_channel; 2546 if (channel) { 2547 rx_status->band = channel->band; 2548 channel_num = 2549 ieee80211_frequency_to_channel(channel->center_freq); 2550 } 2551 spin_unlock_bh(&ar->data_lock); 2552 } 2553 2554 if (rx_status->band != NL80211_BAND_6GHZ) 2555 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2556 rx_status->band); 2557 2558 ath12k_dp_rx_h_rate(ar, rx_info); 2559 } 2560 2561 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2562 struct sk_buff *msdu, 2563 struct ath12k_dp_rx_info *rx_info) 2564 { 2565 struct ath12k_base *ab = ar->ab; 2566 struct ieee80211_rx_status *rx_status; 2567 struct ieee80211_sta *pubsta; 2568 struct ath12k_peer *peer; 2569 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2570 struct ieee80211_rx_status *status = rx_info->rx_status; 2571 u8 decap = rx_info->decap_type; 2572 bool is_mcbc = rxcb->is_mcbc; 2573 bool is_eapol = rxcb->is_eapol; 2574 2575 spin_lock_bh(&ab->base_lock); 2576 peer = ath12k_dp_rx_h_find_peer(ab, msdu, rx_info); 2577 2578 pubsta = peer ? peer->sta : NULL; 2579 2580 if (pubsta && pubsta->valid_links) { 2581 status->link_valid = 1; 2582 status->link_id = peer->link_id; 2583 } 2584 2585 spin_unlock_bh(&ab->base_lock); 2586 2587 ath12k_dbg(ab, ATH12K_DBG_DATA, 2588 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2589 msdu, 2590 msdu->len, 2591 peer ? peer->addr : NULL, 2592 rxcb->tid, 2593 is_mcbc ? "mcast" : "ucast", 2594 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2595 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2596 (status->encoding == RX_ENC_HT) ? "ht" : "", 2597 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2598 (status->encoding == RX_ENC_HE) ? "he" : "", 2599 (status->encoding == RX_ENC_EHT) ? "eht" : "", 2600 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2601 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2602 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2603 (status->bw == RATE_INFO_BW_320) ? "320" : "", 2604 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2605 status->rate_idx, 2606 status->nss, 2607 status->freq, 2608 status->band, status->flag, 2609 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2610 !!(status->flag & RX_FLAG_MMIC_ERROR), 2611 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2612 2613 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2614 msdu->data, msdu->len); 2615 2616 rx_status = IEEE80211_SKB_RXCB(msdu); 2617 *rx_status = *status; 2618 2619 /* TODO: trace rx packet */ 2620 2621 /* PN for multicast packets are not validate in HW, 2622 * so skip 802.3 rx path 2623 * Also, fast_rx expects the STA to be authorized, hence 2624 * eapol packets are sent in slow path. 2625 */ 2626 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2627 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2628 rx_status->flag |= RX_FLAG_8023; 2629 2630 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 2631 } 2632 2633 static bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base *ab, 2634 struct hal_rx_desc *rx_desc, 2635 struct sk_buff *msdu) 2636 { 2637 struct ieee80211_hdr *hdr; 2638 u8 decap_type; 2639 u32 hdr_len; 2640 2641 decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2642 if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI) 2643 return true; 2644 2645 hdr = (struct ieee80211_hdr *)msdu->data; 2646 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2647 2648 if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN))) 2649 return true; 2650 2651 ab->device_stats.invalid_rbm++; 2652 WARN_ON_ONCE(1); 2653 return false; 2654 } 2655 2656 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2657 struct sk_buff *msdu, 2658 struct sk_buff_head *msdu_list, 2659 struct ath12k_dp_rx_info *rx_info) 2660 { 2661 struct ath12k_base *ab = ar->ab; 2662 struct hal_rx_desc *rx_desc, *lrx_desc; 2663 struct ath12k_skb_rxcb *rxcb; 2664 struct sk_buff *last_buf; 2665 u8 l3_pad_bytes; 2666 u16 msdu_len; 2667 int ret; 2668 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2669 2670 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2671 if (!last_buf) { 2672 ath12k_warn(ab, 2673 "No valid Rx buffer to access MSDU_END tlv\n"); 2674 ret = -EIO; 2675 goto free_out; 2676 } 2677 2678 rx_desc = (struct hal_rx_desc *)msdu->data; 2679 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2680 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2681 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2682 ret = -EIO; 2683 goto free_out; 2684 } 2685 2686 rxcb = ATH12K_SKB_RXCB(msdu); 2687 rxcb->rx_desc = rx_desc; 2688 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2689 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2690 2691 if (rxcb->is_frag) { 2692 skb_pull(msdu, hal_rx_desc_sz); 2693 } else if (!rxcb->is_continuation) { 2694 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2695 ret = -EINVAL; 2696 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2697 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2698 sizeof(*rx_desc)); 2699 goto free_out; 2700 } 2701 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2702 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2703 } else { 2704 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2705 msdu, last_buf, 2706 l3_pad_bytes, msdu_len); 2707 if (ret) { 2708 ath12k_warn(ab, 2709 "failed to coalesce msdu rx buffer%d\n", ret); 2710 goto free_out; 2711 } 2712 } 2713 2714 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) { 2715 ret = -EINVAL; 2716 goto free_out; 2717 } 2718 2719 ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); 2720 ath12k_dp_rx_h_ppdu(ar, rx_info); 2721 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_info); 2722 2723 rx_info->rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2724 2725 return 0; 2726 2727 free_out: 2728 return ret; 2729 } 2730 2731 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2732 struct napi_struct *napi, 2733 struct sk_buff_head *msdu_list, 2734 int ring_id) 2735 { 2736 struct ath12k_hw_group *ag = ab->ag; 2737 struct ieee80211_rx_status rx_status = {0}; 2738 struct ath12k_skb_rxcb *rxcb; 2739 struct sk_buff *msdu; 2740 struct ath12k *ar; 2741 struct ath12k_hw_link *hw_links = ag->hw_links; 2742 struct ath12k_base *partner_ab; 2743 struct ath12k_dp_rx_info rx_info; 2744 u8 hw_link_id, pdev_id; 2745 int ret; 2746 2747 if (skb_queue_empty(msdu_list)) 2748 return; 2749 2750 rx_info.addr2_present = false; 2751 rx_info.rx_status = &rx_status; 2752 2753 rcu_read_lock(); 2754 2755 while ((msdu = __skb_dequeue(msdu_list))) { 2756 rxcb = ATH12K_SKB_RXCB(msdu); 2757 hw_link_id = rxcb->hw_link_id; 2758 partner_ab = ath12k_ag_to_ab(ag, 2759 hw_links[hw_link_id].device_id); 2760 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params, 2761 hw_links[hw_link_id].pdev_idx); 2762 ar = partner_ab->pdevs[pdev_id].ar; 2763 if (!rcu_dereference(partner_ab->pdevs_active[pdev_id])) { 2764 dev_kfree_skb_any(msdu); 2765 continue; 2766 } 2767 2768 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) { 2769 dev_kfree_skb_any(msdu); 2770 continue; 2771 } 2772 2773 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_info); 2774 if (ret) { 2775 ath12k_dbg(ab, ATH12K_DBG_DATA, 2776 "Unable to process msdu %d", ret); 2777 dev_kfree_skb_any(msdu); 2778 continue; 2779 } 2780 2781 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_info); 2782 } 2783 2784 rcu_read_unlock(); 2785 } 2786 2787 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab, 2788 enum ath12k_peer_metadata_version ver, 2789 __le32 peer_metadata) 2790 { 2791 switch (ver) { 2792 default: 2793 ath12k_warn(ab, "Unknown peer metadata version: %d", ver); 2794 fallthrough; 2795 case ATH12K_PEER_METADATA_V0: 2796 return le32_get_bits(peer_metadata, 2797 RX_MPDU_DESC_META_DATA_V0_PEER_ID); 2798 case ATH12K_PEER_METADATA_V1: 2799 return le32_get_bits(peer_metadata, 2800 RX_MPDU_DESC_META_DATA_V1_PEER_ID); 2801 case ATH12K_PEER_METADATA_V1A: 2802 return le32_get_bits(peer_metadata, 2803 RX_MPDU_DESC_META_DATA_V1A_PEER_ID); 2804 case ATH12K_PEER_METADATA_V1B: 2805 return le32_get_bits(peer_metadata, 2806 RX_MPDU_DESC_META_DATA_V1B_PEER_ID); 2807 } 2808 } 2809 2810 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2811 struct napi_struct *napi, int budget) 2812 { 2813 struct ath12k_hw_group *ag = ab->ag; 2814 struct list_head rx_desc_used_list[ATH12K_MAX_DEVICES]; 2815 struct ath12k_hw_link *hw_links = ag->hw_links; 2816 int num_buffs_reaped[ATH12K_MAX_DEVICES] = {}; 2817 struct ath12k_rx_desc_info *desc_info; 2818 struct ath12k_dp *dp = &ab->dp; 2819 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2820 struct hal_reo_dest_ring *desc; 2821 struct ath12k_base *partner_ab; 2822 struct sk_buff_head msdu_list; 2823 struct ath12k_skb_rxcb *rxcb; 2824 int total_msdu_reaped = 0; 2825 u8 hw_link_id, device_id; 2826 struct hal_srng *srng; 2827 struct sk_buff *msdu; 2828 bool done = false; 2829 u64 desc_va; 2830 2831 __skb_queue_head_init(&msdu_list); 2832 2833 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) 2834 INIT_LIST_HEAD(&rx_desc_used_list[device_id]); 2835 2836 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2837 2838 spin_lock_bh(&srng->lock); 2839 2840 try_again: 2841 ath12k_hal_srng_access_begin(ab, srng); 2842 2843 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2844 struct rx_mpdu_desc *mpdu_info; 2845 struct rx_msdu_desc *msdu_info; 2846 enum hal_reo_dest_ring_push_reason push_reason; 2847 u32 cookie; 2848 2849 cookie = le32_get_bits(desc->buf_addr_info.info1, 2850 BUFFER_ADDR_INFO1_SW_COOKIE); 2851 2852 hw_link_id = le32_get_bits(desc->info0, 2853 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2854 2855 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2856 le32_to_cpu(desc->buf_va_lo)); 2857 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2858 2859 device_id = hw_links[hw_link_id].device_id; 2860 partner_ab = ath12k_ag_to_ab(ag, device_id); 2861 if (unlikely(!partner_ab)) { 2862 if (desc_info->skb) { 2863 dev_kfree_skb_any(desc_info->skb); 2864 desc_info->skb = NULL; 2865 } 2866 2867 continue; 2868 } 2869 2870 /* retry manual desc retrieval */ 2871 if (!desc_info) { 2872 desc_info = ath12k_dp_get_rx_desc(partner_ab, cookie); 2873 if (!desc_info) { 2874 ath12k_warn(partner_ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n", 2875 cookie); 2876 continue; 2877 } 2878 } 2879 2880 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 2881 ath12k_warn(ab, "Check HW CC implementation"); 2882 2883 msdu = desc_info->skb; 2884 desc_info->skb = NULL; 2885 2886 list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]); 2887 2888 rxcb = ATH12K_SKB_RXCB(msdu); 2889 dma_unmap_single(partner_ab->dev, rxcb->paddr, 2890 msdu->len + skb_tailroom(msdu), 2891 DMA_FROM_DEVICE); 2892 2893 num_buffs_reaped[device_id]++; 2894 ab->device_stats.reo_rx[ring_id][ab->device_id]++; 2895 2896 push_reason = le32_get_bits(desc->info0, 2897 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 2898 if (push_reason != 2899 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2900 dev_kfree_skb_any(msdu); 2901 ab->device_stats.hal_reo_error[ring_id]++; 2902 continue; 2903 } 2904 2905 msdu_info = &desc->rx_msdu_info; 2906 mpdu_info = &desc->rx_mpdu_info; 2907 2908 rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) & 2909 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2910 rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) & 2911 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2912 rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) & 2913 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2914 rxcb->hw_link_id = hw_link_id; 2915 rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver, 2916 mpdu_info->peer_meta_data); 2917 rxcb->tid = le32_get_bits(mpdu_info->info0, 2918 RX_MPDU_DESC_INFO0_TID); 2919 2920 __skb_queue_tail(&msdu_list, msdu); 2921 2922 if (!rxcb->is_continuation) { 2923 total_msdu_reaped++; 2924 done = true; 2925 } else { 2926 done = false; 2927 } 2928 2929 if (total_msdu_reaped >= budget) 2930 break; 2931 } 2932 2933 /* Hw might have updated the head pointer after we cached it. 2934 * In this case, even though there are entries in the ring we'll 2935 * get rx_desc NULL. Give the read another try with updated cached 2936 * head pointer so that we can reap complete MPDU in the current 2937 * rx processing. 2938 */ 2939 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 2940 ath12k_hal_srng_access_end(ab, srng); 2941 goto try_again; 2942 } 2943 2944 ath12k_hal_srng_access_end(ab, srng); 2945 2946 spin_unlock_bh(&srng->lock); 2947 2948 if (!total_msdu_reaped) 2949 goto exit; 2950 2951 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) { 2952 if (!num_buffs_reaped[device_id]) 2953 continue; 2954 2955 partner_ab = ath12k_ag_to_ab(ag, device_id); 2956 rx_ring = &partner_ab->dp.rx_refill_buf_ring; 2957 2958 ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring, 2959 &rx_desc_used_list[device_id], 2960 num_buffs_reaped[device_id]); 2961 } 2962 2963 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2964 ring_id); 2965 2966 exit: 2967 return total_msdu_reaped; 2968 } 2969 2970 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 2971 { 2972 struct ath12k_dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer, 2973 frag_timer); 2974 2975 spin_lock_bh(&rx_tid->ab->base_lock); 2976 if (rx_tid->last_frag_no && 2977 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2978 spin_unlock_bh(&rx_tid->ab->base_lock); 2979 return; 2980 } 2981 ath12k_dp_rx_frags_cleanup(rx_tid, true); 2982 spin_unlock_bh(&rx_tid->ab->base_lock); 2983 } 2984 2985 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 2986 { 2987 struct ath12k_base *ab = ar->ab; 2988 struct crypto_shash *tfm; 2989 struct ath12k_peer *peer; 2990 struct ath12k_dp_rx_tid *rx_tid; 2991 int i; 2992 2993 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2994 if (IS_ERR(tfm)) 2995 return PTR_ERR(tfm); 2996 2997 spin_lock_bh(&ab->base_lock); 2998 2999 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 3000 if (!peer) { 3001 spin_unlock_bh(&ab->base_lock); 3002 crypto_free_shash(tfm); 3003 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 3004 return -ENOENT; 3005 } 3006 3007 if (!peer->primary_link) { 3008 spin_unlock_bh(&ab->base_lock); 3009 crypto_free_shash(tfm); 3010 return 0; 3011 } 3012 3013 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3014 rx_tid = &peer->rx_tid[i]; 3015 rx_tid->ab = ab; 3016 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 3017 skb_queue_head_init(&rx_tid->rx_frags); 3018 } 3019 3020 peer->tfm_mmic = tfm; 3021 peer->dp_setup_done = true; 3022 spin_unlock_bh(&ab->base_lock); 3023 3024 return 0; 3025 } 3026 3027 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3028 struct ieee80211_hdr *hdr, u8 *data, 3029 size_t data_len, u8 *mic) 3030 { 3031 SHASH_DESC_ON_STACK(desc, tfm); 3032 u8 mic_hdr[16] = {0}; 3033 u8 tid = 0; 3034 int ret; 3035 3036 if (!tfm) 3037 return -EINVAL; 3038 3039 desc->tfm = tfm; 3040 3041 ret = crypto_shash_setkey(tfm, key, 8); 3042 if (ret) 3043 goto out; 3044 3045 ret = crypto_shash_init(desc); 3046 if (ret) 3047 goto out; 3048 3049 /* TKIP MIC header */ 3050 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3051 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3052 if (ieee80211_is_data_qos(hdr->frame_control)) 3053 tid = ieee80211_get_tid(hdr); 3054 mic_hdr[12] = tid; 3055 3056 ret = crypto_shash_update(desc, mic_hdr, 16); 3057 if (ret) 3058 goto out; 3059 ret = crypto_shash_update(desc, data, data_len); 3060 if (ret) 3061 goto out; 3062 ret = crypto_shash_final(desc, mic); 3063 out: 3064 shash_desc_zero(desc); 3065 return ret; 3066 } 3067 3068 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 3069 struct sk_buff *msdu) 3070 { 3071 struct ath12k_base *ab = ar->ab; 3072 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3073 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3074 struct ieee80211_key_conf *key_conf; 3075 struct ieee80211_hdr *hdr; 3076 struct ath12k_dp_rx_info rx_info; 3077 u8 mic[IEEE80211_CCMP_MIC_LEN]; 3078 int head_len, tail_len, ret; 3079 size_t data_len; 3080 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3081 u8 *key, *data; 3082 u8 key_idx; 3083 3084 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 3085 return 0; 3086 3087 rx_info.addr2_present = false; 3088 rx_info.rx_status = rxs; 3089 3090 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3091 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3092 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 3093 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3094 3095 if (!is_multicast_ether_addr(hdr->addr1)) 3096 key_idx = peer->ucast_keyidx; 3097 else 3098 key_idx = peer->mcast_keyidx; 3099 3100 key_conf = peer->keys[key_idx]; 3101 3102 data = msdu->data + head_len; 3103 data_len = msdu->len - head_len - tail_len; 3104 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3105 3106 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3107 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3108 goto mic_fail; 3109 3110 return 0; 3111 3112 mic_fail: 3113 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 3114 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 3115 3116 ath12k_dp_rx_h_fetch_info(ab, rx_desc, &rx_info); 3117 3118 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3119 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3120 skb_pull(msdu, hal_rx_desc_sz); 3121 3122 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) 3123 return -EINVAL; 3124 3125 ath12k_dp_rx_h_ppdu(ar, &rx_info); 3126 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 3127 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3128 ieee80211_rx(ath12k_ar_to_hw(ar), msdu); 3129 return -EINVAL; 3130 } 3131 3132 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 3133 enum hal_encrypt_type enctype, u32 flags) 3134 { 3135 struct ieee80211_hdr *hdr; 3136 size_t hdr_len; 3137 size_t crypto_len; 3138 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3139 3140 if (!flags) 3141 return; 3142 3143 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3144 3145 if (flags & RX_FLAG_MIC_STRIPPED) 3146 skb_trim(msdu, msdu->len - 3147 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 3148 3149 if (flags & RX_FLAG_ICV_STRIPPED) 3150 skb_trim(msdu, msdu->len - 3151 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 3152 3153 if (flags & RX_FLAG_IV_STRIPPED) { 3154 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3155 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 3156 3157 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 3158 msdu->data + hal_rx_desc_sz, hdr_len); 3159 skb_pull(msdu, crypto_len); 3160 } 3161 } 3162 3163 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 3164 struct ath12k_peer *peer, 3165 struct ath12k_dp_rx_tid *rx_tid, 3166 struct sk_buff **defrag_skb) 3167 { 3168 struct ath12k_base *ab = ar->ab; 3169 struct hal_rx_desc *rx_desc; 3170 struct sk_buff *skb, *first_frag, *last_frag; 3171 struct ieee80211_hdr *hdr; 3172 enum hal_encrypt_type enctype; 3173 bool is_decrypted = false; 3174 int msdu_len = 0; 3175 int extra_space; 3176 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3177 3178 first_frag = skb_peek(&rx_tid->rx_frags); 3179 last_frag = skb_peek_tail(&rx_tid->rx_frags); 3180 3181 skb_queue_walk(&rx_tid->rx_frags, skb) { 3182 flags = 0; 3183 rx_desc = (struct hal_rx_desc *)skb->data; 3184 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3185 3186 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 3187 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 3188 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 3189 rx_desc); 3190 3191 if (is_decrypted) { 3192 if (skb != first_frag) 3193 flags |= RX_FLAG_IV_STRIPPED; 3194 if (skb != last_frag) 3195 flags |= RX_FLAG_ICV_STRIPPED | 3196 RX_FLAG_MIC_STRIPPED; 3197 } 3198 3199 /* RX fragments are always raw packets */ 3200 if (skb != last_frag) 3201 skb_trim(skb, skb->len - FCS_LEN); 3202 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3203 3204 if (skb != first_frag) 3205 skb_pull(skb, hal_rx_desc_sz + 3206 ieee80211_hdrlen(hdr->frame_control)); 3207 msdu_len += skb->len; 3208 } 3209 3210 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3211 if (extra_space > 0 && 3212 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3213 return -ENOMEM; 3214 3215 __skb_unlink(first_frag, &rx_tid->rx_frags); 3216 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3217 skb_put_data(first_frag, skb->data, skb->len); 3218 dev_kfree_skb_any(skb); 3219 } 3220 3221 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3222 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3223 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 3224 3225 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3226 first_frag = NULL; 3227 3228 *defrag_skb = first_frag; 3229 return 0; 3230 } 3231 3232 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 3233 struct ath12k_dp_rx_tid *rx_tid, 3234 struct sk_buff *defrag_skb) 3235 { 3236 struct ath12k_base *ab = ar->ab; 3237 struct ath12k_dp *dp = &ab->dp; 3238 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3239 struct hal_reo_entrance_ring *reo_ent_ring; 3240 struct hal_reo_dest_ring *reo_dest_ring; 3241 struct dp_link_desc_bank *link_desc_banks; 3242 struct hal_rx_msdu_link *msdu_link; 3243 struct hal_rx_msdu_details *msdu0; 3244 struct hal_srng *srng; 3245 dma_addr_t link_paddr, buf_paddr; 3246 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 3247 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi; 3248 int ret; 3249 struct ath12k_rx_desc_info *desc_info; 3250 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm; 3251 u8 dst_ind; 3252 3253 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3254 link_desc_banks = dp->link_desc_banks; 3255 reo_dest_ring = rx_tid->dst_ring_desc; 3256 3257 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 3258 &link_paddr, &cookie); 3259 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 3260 3261 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3262 (link_paddr - link_desc_banks[desc_bank].paddr)); 3263 msdu0 = &msdu_link->msdu_link[0]; 3264 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 3265 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 3266 3267 memset(msdu0, 0, sizeof(*msdu0)); 3268 3269 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 3270 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 3271 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3272 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3273 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3274 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3275 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3276 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3277 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3278 3279 /* change msdu len in hal rx desc */ 3280 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3281 3282 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3283 defrag_skb->len + skb_tailroom(defrag_skb), 3284 DMA_TO_DEVICE); 3285 if (dma_mapping_error(ab->dev, buf_paddr)) 3286 return -ENOMEM; 3287 3288 spin_lock_bh(&dp->rx_desc_lock); 3289 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3290 struct ath12k_rx_desc_info, 3291 list); 3292 if (!desc_info) { 3293 spin_unlock_bh(&dp->rx_desc_lock); 3294 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3295 ret = -ENOMEM; 3296 goto err_unmap_dma; 3297 } 3298 3299 desc_info->skb = defrag_skb; 3300 desc_info->in_use = true; 3301 3302 list_del(&desc_info->list); 3303 spin_unlock_bh(&dp->rx_desc_lock); 3304 3305 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3306 3307 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3308 desc_info->cookie, 3309 HAL_RX_BUF_RBM_SW3_BM); 3310 3311 /* Fill mpdu details into reo entrance ring */ 3312 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3313 3314 spin_lock_bh(&srng->lock); 3315 ath12k_hal_srng_access_begin(ab, srng); 3316 3317 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3318 if (!reo_ent_ring) { 3319 ath12k_hal_srng_access_end(ab, srng); 3320 spin_unlock_bh(&srng->lock); 3321 ret = -ENOSPC; 3322 goto err_free_desc; 3323 } 3324 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3325 3326 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3327 cookie, 3328 idle_link_rbm); 3329 3330 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3331 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3332 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3333 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3334 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3335 3336 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3337 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3338 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3339 3340 if (ab->hw_params->reoq_lut_support) { 3341 reo_ent_ring->queue_addr_lo = reo_dest_ring->rx_mpdu_info.peer_meta_data; 3342 queue_addr_hi = 0; 3343 } else { 3344 reo_ent_ring->queue_addr_lo = 3345 cpu_to_le32(lower_32_bits(rx_tid->qbuf.paddr_aligned)); 3346 queue_addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 3347 } 3348 3349 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi, 3350 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) | 3351 le32_encode_bits(dst_ind, 3352 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3353 3354 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3355 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3356 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3357 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3358 reo_ent_ring->info2 = 3359 cpu_to_le32(u32_get_bits(dest_ring_info0, 3360 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3361 3362 ath12k_hal_srng_access_end(ab, srng); 3363 spin_unlock_bh(&srng->lock); 3364 3365 return 0; 3366 3367 err_free_desc: 3368 spin_lock_bh(&dp->rx_desc_lock); 3369 desc_info->in_use = false; 3370 desc_info->skb = NULL; 3371 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3372 spin_unlock_bh(&dp->rx_desc_lock); 3373 err_unmap_dma: 3374 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3375 DMA_TO_DEVICE); 3376 return ret; 3377 } 3378 3379 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3380 struct sk_buff *a, struct sk_buff *b) 3381 { 3382 int frag1, frag2; 3383 3384 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3385 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3386 3387 return frag1 - frag2; 3388 } 3389 3390 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3391 struct sk_buff_head *frag_list, 3392 struct sk_buff *cur_frag) 3393 { 3394 struct sk_buff *skb; 3395 int cmp; 3396 3397 skb_queue_walk(frag_list, skb) { 3398 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3399 if (cmp < 0) 3400 continue; 3401 __skb_queue_before(frag_list, skb, cur_frag); 3402 return; 3403 } 3404 __skb_queue_tail(frag_list, cur_frag); 3405 } 3406 3407 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3408 { 3409 struct ieee80211_hdr *hdr; 3410 u64 pn = 0; 3411 u8 *ehdr; 3412 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3413 3414 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3415 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3416 3417 pn = ehdr[0]; 3418 pn |= (u64)ehdr[1] << 8; 3419 pn |= (u64)ehdr[4] << 16; 3420 pn |= (u64)ehdr[5] << 24; 3421 pn |= (u64)ehdr[6] << 32; 3422 pn |= (u64)ehdr[7] << 40; 3423 3424 return pn; 3425 } 3426 3427 static bool 3428 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3429 { 3430 struct ath12k_base *ab = ar->ab; 3431 enum hal_encrypt_type encrypt_type; 3432 struct sk_buff *first_frag, *skb; 3433 struct hal_rx_desc *desc; 3434 u64 last_pn; 3435 u64 cur_pn; 3436 3437 first_frag = skb_peek(&rx_tid->rx_frags); 3438 desc = (struct hal_rx_desc *)first_frag->data; 3439 3440 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3441 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3442 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3443 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3444 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3445 return true; 3446 3447 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3448 skb_queue_walk(&rx_tid->rx_frags, skb) { 3449 if (skb == first_frag) 3450 continue; 3451 3452 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3453 if (cur_pn != last_pn + 1) 3454 return false; 3455 last_pn = cur_pn; 3456 } 3457 return true; 3458 } 3459 3460 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3461 struct sk_buff *msdu, 3462 struct hal_reo_dest_ring *ring_desc) 3463 { 3464 struct ath12k_base *ab = ar->ab; 3465 struct hal_rx_desc *rx_desc; 3466 struct ath12k_peer *peer; 3467 struct ath12k_dp_rx_tid *rx_tid; 3468 struct sk_buff *defrag_skb = NULL; 3469 u32 peer_id; 3470 u16 seqno, frag_no; 3471 u8 tid; 3472 int ret = 0; 3473 bool more_frags; 3474 3475 rx_desc = (struct hal_rx_desc *)msdu->data; 3476 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3477 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3478 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3479 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3480 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3481 3482 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3483 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3484 tid > IEEE80211_NUM_TIDS) 3485 return -EINVAL; 3486 3487 /* received unfragmented packet in reo 3488 * exception ring, this shouldn't happen 3489 * as these packets typically come from 3490 * reo2sw srngs. 3491 */ 3492 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3493 return -EINVAL; 3494 3495 spin_lock_bh(&ab->base_lock); 3496 peer = ath12k_peer_find_by_id(ab, peer_id); 3497 if (!peer) { 3498 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3499 peer_id); 3500 ret = -ENOENT; 3501 goto out_unlock; 3502 } 3503 3504 if (!peer->dp_setup_done) { 3505 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3506 peer->addr, peer_id); 3507 ret = -ENOENT; 3508 goto out_unlock; 3509 } 3510 3511 rx_tid = &peer->rx_tid[tid]; 3512 3513 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3514 skb_queue_empty(&rx_tid->rx_frags)) { 3515 /* Flush stored fragments and start a new sequence */ 3516 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3517 rx_tid->cur_sn = seqno; 3518 } 3519 3520 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3521 /* Fragment already present */ 3522 ret = -EINVAL; 3523 goto out_unlock; 3524 } 3525 3526 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3527 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3528 else 3529 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3530 3531 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3532 if (!more_frags) 3533 rx_tid->last_frag_no = frag_no; 3534 3535 if (frag_no == 0) { 3536 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3537 sizeof(*rx_tid->dst_ring_desc), 3538 GFP_ATOMIC); 3539 if (!rx_tid->dst_ring_desc) { 3540 ret = -ENOMEM; 3541 goto out_unlock; 3542 } 3543 } else { 3544 ath12k_dp_rx_link_desc_return(ab, &ring_desc->buf_addr_info, 3545 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3546 } 3547 3548 if (!rx_tid->last_frag_no || 3549 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3550 mod_timer(&rx_tid->frag_timer, jiffies + 3551 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3552 goto out_unlock; 3553 } 3554 3555 spin_unlock_bh(&ab->base_lock); 3556 timer_delete_sync(&rx_tid->frag_timer); 3557 spin_lock_bh(&ab->base_lock); 3558 3559 peer = ath12k_peer_find_by_id(ab, peer_id); 3560 if (!peer) 3561 goto err_frags_cleanup; 3562 3563 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3564 goto err_frags_cleanup; 3565 3566 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3567 goto err_frags_cleanup; 3568 3569 if (!defrag_skb) 3570 goto err_frags_cleanup; 3571 3572 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3573 goto err_frags_cleanup; 3574 3575 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3576 goto out_unlock; 3577 3578 err_frags_cleanup: 3579 dev_kfree_skb_any(defrag_skb); 3580 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3581 out_unlock: 3582 spin_unlock_bh(&ab->base_lock); 3583 return ret; 3584 } 3585 3586 static int 3587 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3588 struct list_head *used_list, 3589 bool drop, u32 cookie) 3590 { 3591 struct ath12k_base *ab = ar->ab; 3592 struct sk_buff *msdu; 3593 struct ath12k_skb_rxcb *rxcb; 3594 struct hal_rx_desc *rx_desc; 3595 u16 msdu_len; 3596 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3597 struct ath12k_rx_desc_info *desc_info; 3598 u64 desc_va; 3599 3600 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3601 le32_to_cpu(desc->buf_va_lo)); 3602 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3603 3604 /* retry manual desc retrieval */ 3605 if (!desc_info) { 3606 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3607 if (!desc_info) { 3608 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n", 3609 cookie); 3610 return -EINVAL; 3611 } 3612 } 3613 3614 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3615 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3616 3617 msdu = desc_info->skb; 3618 desc_info->skb = NULL; 3619 3620 list_add_tail(&desc_info->list, used_list); 3621 3622 rxcb = ATH12K_SKB_RXCB(msdu); 3623 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3624 msdu->len + skb_tailroom(msdu), 3625 DMA_FROM_DEVICE); 3626 3627 if (drop) { 3628 dev_kfree_skb_any(msdu); 3629 return 0; 3630 } 3631 3632 rcu_read_lock(); 3633 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3634 dev_kfree_skb_any(msdu); 3635 goto exit; 3636 } 3637 3638 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) { 3639 dev_kfree_skb_any(msdu); 3640 goto exit; 3641 } 3642 3643 rx_desc = (struct hal_rx_desc *)msdu->data; 3644 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3645 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3646 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3647 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3648 sizeof(*rx_desc)); 3649 dev_kfree_skb_any(msdu); 3650 goto exit; 3651 } 3652 3653 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3654 3655 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3656 dev_kfree_skb_any(msdu); 3657 ath12k_dp_rx_link_desc_return(ar->ab, &desc->buf_addr_info, 3658 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3659 } 3660 exit: 3661 rcu_read_unlock(); 3662 return 0; 3663 } 3664 3665 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3666 int budget) 3667 { 3668 struct ath12k_hw_group *ag = ab->ag; 3669 struct list_head rx_desc_used_list[ATH12K_MAX_DEVICES]; 3670 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3671 int num_buffs_reaped[ATH12K_MAX_DEVICES] = {}; 3672 struct dp_link_desc_bank *link_desc_banks; 3673 enum hal_rx_buf_return_buf_manager rbm; 3674 struct hal_rx_msdu_link *link_desc_va; 3675 int tot_n_bufs_reaped, quota, ret, i; 3676 struct hal_reo_dest_ring *reo_desc; 3677 struct dp_rxdma_ring *rx_ring; 3678 struct dp_srng *reo_except; 3679 struct ath12k_hw_link *hw_links = ag->hw_links; 3680 struct ath12k_base *partner_ab; 3681 u8 hw_link_id, device_id; 3682 u32 desc_bank, num_msdus; 3683 struct hal_srng *srng; 3684 struct ath12k *ar; 3685 dma_addr_t paddr; 3686 bool is_frag; 3687 bool drop; 3688 int pdev_id; 3689 3690 tot_n_bufs_reaped = 0; 3691 quota = budget; 3692 3693 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) 3694 INIT_LIST_HEAD(&rx_desc_used_list[device_id]); 3695 3696 reo_except = &ab->dp.reo_except_ring; 3697 3698 srng = &ab->hal.srng_list[reo_except->ring_id]; 3699 3700 spin_lock_bh(&srng->lock); 3701 3702 ath12k_hal_srng_access_begin(ab, srng); 3703 3704 while (budget && 3705 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3706 drop = false; 3707 ab->device_stats.err_ring_pkts++; 3708 3709 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3710 &desc_bank); 3711 if (ret) { 3712 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3713 ret); 3714 continue; 3715 } 3716 3717 hw_link_id = le32_get_bits(reo_desc->info0, 3718 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3719 device_id = hw_links[hw_link_id].device_id; 3720 partner_ab = ath12k_ag_to_ab(ag, device_id); 3721 3722 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params, 3723 hw_links[hw_link_id].pdev_idx); 3724 ar = partner_ab->pdevs[pdev_id].ar; 3725 3726 link_desc_banks = partner_ab->dp.link_desc_banks; 3727 link_desc_va = link_desc_banks[desc_bank].vaddr + 3728 (paddr - link_desc_banks[desc_bank].paddr); 3729 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3730 &rbm); 3731 if (rbm != partner_ab->dp.idle_link_rbm && 3732 rbm != HAL_RX_BUF_RBM_SW3_BM && 3733 rbm != partner_ab->hw_params->hal_params->rx_buf_rbm) { 3734 ab->device_stats.invalid_rbm++; 3735 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3736 ath12k_dp_rx_link_desc_return(partner_ab, 3737 &reo_desc->buf_addr_info, 3738 HAL_WBM_REL_BM_ACT_REL_MSDU); 3739 continue; 3740 } 3741 3742 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3743 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3744 3745 /* Process only rx fragments with one msdu per link desc below, and drop 3746 * msdu's indicated due to error reasons. 3747 * Dynamic fragmentation not supported in Multi-link client, so drop the 3748 * partner device buffers. 3749 */ 3750 if (!is_frag || num_msdus > 1 || 3751 partner_ab->device_id != ab->device_id) { 3752 drop = true; 3753 3754 /* Return the link desc back to wbm idle list */ 3755 ath12k_dp_rx_link_desc_return(partner_ab, 3756 &reo_desc->buf_addr_info, 3757 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3758 } 3759 3760 for (i = 0; i < num_msdus; i++) { 3761 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, 3762 &rx_desc_used_list[device_id], 3763 drop, 3764 msdu_cookies[i])) { 3765 num_buffs_reaped[device_id]++; 3766 tot_n_bufs_reaped++; 3767 } 3768 } 3769 3770 if (tot_n_bufs_reaped >= quota) { 3771 tot_n_bufs_reaped = quota; 3772 goto exit; 3773 } 3774 3775 budget = quota - tot_n_bufs_reaped; 3776 } 3777 3778 exit: 3779 ath12k_hal_srng_access_end(ab, srng); 3780 3781 spin_unlock_bh(&srng->lock); 3782 3783 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) { 3784 if (!num_buffs_reaped[device_id]) 3785 continue; 3786 3787 partner_ab = ath12k_ag_to_ab(ag, device_id); 3788 rx_ring = &partner_ab->dp.rx_refill_buf_ring; 3789 3790 ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring, 3791 &rx_desc_used_list[device_id], 3792 num_buffs_reaped[device_id]); 3793 } 3794 3795 return tot_n_bufs_reaped; 3796 } 3797 3798 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3799 int msdu_len, 3800 struct sk_buff_head *msdu_list) 3801 { 3802 struct sk_buff *skb, *tmp; 3803 struct ath12k_skb_rxcb *rxcb; 3804 int n_buffs; 3805 3806 n_buffs = DIV_ROUND_UP(msdu_len, 3807 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz)); 3808 3809 skb_queue_walk_safe(msdu_list, skb, tmp) { 3810 rxcb = ATH12K_SKB_RXCB(skb); 3811 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3812 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3813 if (!n_buffs) 3814 break; 3815 __skb_unlink(skb, msdu_list); 3816 dev_kfree_skb_any(skb); 3817 n_buffs--; 3818 } 3819 } 3820 } 3821 3822 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 3823 struct ath12k_dp_rx_info *rx_info, 3824 struct sk_buff_head *msdu_list) 3825 { 3826 struct ath12k_base *ab = ar->ab; 3827 u16 msdu_len; 3828 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3829 u8 l3pad_bytes; 3830 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3831 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3832 3833 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3834 3835 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3836 /* First buffer will be freed by the caller, so deduct it's length */ 3837 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3838 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3839 return -EINVAL; 3840 } 3841 3842 /* Even after cleaning up the sg buffers in the msdu list with above check 3843 * any msdu received with continuation flag needs to be dropped as invalid. 3844 * This protects against some random err frame with continuation flag. 3845 */ 3846 if (rxcb->is_continuation) 3847 return -EINVAL; 3848 3849 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 3850 ath12k_warn(ar->ab, 3851 "msdu_done bit not set in null_q_des processing\n"); 3852 __skb_queue_purge(msdu_list); 3853 return -EIO; 3854 } 3855 3856 /* Handle NULL queue descriptor violations arising out a missing 3857 * REO queue for a given peer or a given TID. This typically 3858 * may happen if a packet is received on a QOS enabled TID before the 3859 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3860 * it may also happen for MC/BC frames if they are not routed to the 3861 * non-QOS TID queue, in the absence of any other default TID queue. 3862 * This error can show up both in a REO destination or WBM release ring. 3863 */ 3864 3865 if (rxcb->is_frag) { 3866 skb_pull(msdu, hal_rx_desc_sz); 3867 } else { 3868 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3869 3870 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3871 return -EINVAL; 3872 3873 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3874 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3875 } 3876 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu))) 3877 return -EINVAL; 3878 3879 ath12k_dp_rx_h_fetch_info(ab, desc, rx_info); 3880 ath12k_dp_rx_h_ppdu(ar, rx_info); 3881 ath12k_dp_rx_h_mpdu(ar, msdu, desc, rx_info); 3882 3883 rxcb->tid = rx_info->tid; 3884 3885 /* Please note that caller will having the access to msdu and completing 3886 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3887 */ 3888 3889 return 0; 3890 } 3891 3892 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 3893 struct ath12k_dp_rx_info *rx_info, 3894 struct sk_buff_head *msdu_list) 3895 { 3896 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3897 bool drop = false; 3898 3899 ar->ab->device_stats.reo_error[rxcb->err_code]++; 3900 3901 switch (rxcb->err_code) { 3902 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3903 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, rx_info, msdu_list)) 3904 drop = true; 3905 break; 3906 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3907 /* TODO: Do not drop PN failed packets in the driver; 3908 * instead, it is good to drop such packets in mac80211 3909 * after incrementing the replay counters. 3910 */ 3911 fallthrough; 3912 default: 3913 /* TODO: Review other errors and process them to mac80211 3914 * as appropriate. 3915 */ 3916 drop = true; 3917 break; 3918 } 3919 3920 return drop; 3921 } 3922 3923 static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 3924 struct ath12k_dp_rx_info *rx_info) 3925 { 3926 struct ath12k_base *ab = ar->ab; 3927 u16 msdu_len; 3928 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3929 u8 l3pad_bytes; 3930 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3931 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3932 3933 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 3934 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 3935 3936 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3937 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3938 3939 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) { 3940 ath12k_dbg(ab, ATH12K_DBG_DATA, 3941 "invalid msdu len in tkip mic err %u\n", msdu_len); 3942 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", desc, 3943 sizeof(*desc)); 3944 return true; 3945 } 3946 3947 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3948 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3949 3950 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu))) 3951 return true; 3952 3953 ath12k_dp_rx_h_ppdu(ar, rx_info); 3954 3955 rx_info->rx_status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3956 RX_FLAG_DECRYPTED); 3957 3958 ath12k_dp_rx_h_undecap(ar, msdu, desc, 3959 HAL_ENCRYPT_TYPE_TKIP_MIC, rx_info->rx_status, false); 3960 return false; 3961 } 3962 3963 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 3964 struct ath12k_dp_rx_info *rx_info) 3965 { 3966 struct ath12k_base *ab = ar->ab; 3967 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3968 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3969 bool drop = false; 3970 u32 err_bitmap; 3971 3972 ar->ab->device_stats.rxdma_error[rxcb->err_code]++; 3973 3974 switch (rxcb->err_code) { 3975 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 3976 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3977 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 3978 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 3979 ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); 3980 drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, rx_info); 3981 break; 3982 } 3983 fallthrough; 3984 default: 3985 /* TODO: Review other rxdma error code to check if anything is 3986 * worth reporting to mac80211 3987 */ 3988 drop = true; 3989 break; 3990 } 3991 3992 return drop; 3993 } 3994 3995 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 3996 struct napi_struct *napi, 3997 struct sk_buff *msdu, 3998 struct sk_buff_head *msdu_list) 3999 { 4000 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 4001 struct ieee80211_rx_status rxs = {0}; 4002 struct ath12k_dp_rx_info rx_info; 4003 bool drop = true; 4004 4005 rx_info.addr2_present = false; 4006 rx_info.rx_status = &rxs; 4007 4008 switch (rxcb->err_rel_src) { 4009 case HAL_WBM_REL_SRC_MODULE_REO: 4010 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rx_info, msdu_list); 4011 break; 4012 case HAL_WBM_REL_SRC_MODULE_RXDMA: 4013 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rx_info); 4014 break; 4015 default: 4016 /* msdu will get freed */ 4017 break; 4018 } 4019 4020 if (drop) { 4021 dev_kfree_skb_any(msdu); 4022 return; 4023 } 4024 4025 rx_info.rx_status->flag |= RX_FLAG_SKIP_MONITOR; 4026 4027 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_info); 4028 } 4029 4030 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 4031 struct napi_struct *napi, int budget) 4032 { 4033 struct list_head rx_desc_used_list[ATH12K_MAX_DEVICES]; 4034 struct ath12k_hw_group *ag = ab->ag; 4035 struct ath12k *ar; 4036 struct ath12k_dp *dp = &ab->dp; 4037 struct dp_rxdma_ring *rx_ring; 4038 struct hal_rx_wbm_rel_info err_info; 4039 struct hal_srng *srng; 4040 struct sk_buff *msdu; 4041 struct sk_buff_head msdu_list, scatter_msdu_list; 4042 struct ath12k_skb_rxcb *rxcb; 4043 void *rx_desc; 4044 int num_buffs_reaped[ATH12K_MAX_DEVICES] = {}; 4045 int total_num_buffs_reaped = 0; 4046 struct ath12k_rx_desc_info *desc_info; 4047 struct ath12k_device_dp_stats *device_stats = &ab->device_stats; 4048 struct ath12k_hw_link *hw_links = ag->hw_links; 4049 struct ath12k_base *partner_ab; 4050 u8 hw_link_id, device_id; 4051 int ret, pdev_id; 4052 struct hal_rx_desc *msdu_data; 4053 4054 __skb_queue_head_init(&msdu_list); 4055 __skb_queue_head_init(&scatter_msdu_list); 4056 4057 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) 4058 INIT_LIST_HEAD(&rx_desc_used_list[device_id]); 4059 4060 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 4061 spin_lock_bh(&srng->lock); 4062 4063 ath12k_hal_srng_access_begin(ab, srng); 4064 4065 while (budget) { 4066 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 4067 if (!rx_desc) 4068 break; 4069 4070 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 4071 if (ret) { 4072 ath12k_warn(ab, 4073 "failed to parse rx error in wbm_rel ring desc %d\n", 4074 ret); 4075 continue; 4076 } 4077 4078 desc_info = err_info.rx_desc; 4079 4080 /* retry manual desc retrieval if hw cc is not done */ 4081 if (!desc_info) { 4082 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 4083 if (!desc_info) { 4084 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n", 4085 err_info.cookie); 4086 continue; 4087 } 4088 } 4089 4090 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 4091 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 4092 4093 msdu = desc_info->skb; 4094 desc_info->skb = NULL; 4095 4096 device_id = desc_info->device_id; 4097 partner_ab = ath12k_ag_to_ab(ag, device_id); 4098 if (unlikely(!partner_ab)) { 4099 dev_kfree_skb_any(msdu); 4100 4101 /* In any case continuation bit is set 4102 * in the previous record, cleanup scatter_msdu_list 4103 */ 4104 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 4105 continue; 4106 } 4107 4108 list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]); 4109 4110 rxcb = ATH12K_SKB_RXCB(msdu); 4111 dma_unmap_single(partner_ab->dev, rxcb->paddr, 4112 msdu->len + skb_tailroom(msdu), 4113 DMA_FROM_DEVICE); 4114 4115 num_buffs_reaped[device_id]++; 4116 total_num_buffs_reaped++; 4117 4118 if (!err_info.continuation) 4119 budget--; 4120 4121 if (err_info.push_reason != 4122 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4123 dev_kfree_skb_any(msdu); 4124 continue; 4125 } 4126 4127 msdu_data = (struct hal_rx_desc *)msdu->data; 4128 rxcb->err_rel_src = err_info.err_rel_src; 4129 rxcb->err_code = err_info.err_code; 4130 rxcb->is_first_msdu = err_info.first_msdu; 4131 rxcb->is_last_msdu = err_info.last_msdu; 4132 rxcb->is_continuation = err_info.continuation; 4133 rxcb->rx_desc = msdu_data; 4134 4135 if (err_info.continuation) { 4136 __skb_queue_tail(&scatter_msdu_list, msdu); 4137 continue; 4138 } 4139 4140 hw_link_id = ath12k_dp_rx_get_msdu_src_link(partner_ab, 4141 msdu_data); 4142 if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) { 4143 dev_kfree_skb_any(msdu); 4144 4145 /* In any case continuation bit is set 4146 * in the previous record, cleanup scatter_msdu_list 4147 */ 4148 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 4149 continue; 4150 } 4151 4152 if (!skb_queue_empty(&scatter_msdu_list)) { 4153 struct sk_buff *msdu; 4154 4155 skb_queue_walk(&scatter_msdu_list, msdu) { 4156 rxcb = ATH12K_SKB_RXCB(msdu); 4157 rxcb->hw_link_id = hw_link_id; 4158 } 4159 4160 skb_queue_splice_tail_init(&scatter_msdu_list, 4161 &msdu_list); 4162 } 4163 4164 rxcb = ATH12K_SKB_RXCB(msdu); 4165 rxcb->hw_link_id = hw_link_id; 4166 __skb_queue_tail(&msdu_list, msdu); 4167 } 4168 4169 /* In any case continuation bit is set in the 4170 * last record, cleanup scatter_msdu_list 4171 */ 4172 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 4173 4174 ath12k_hal_srng_access_end(ab, srng); 4175 4176 spin_unlock_bh(&srng->lock); 4177 4178 if (!total_num_buffs_reaped) 4179 goto done; 4180 4181 for (device_id = 0; device_id < ATH12K_MAX_DEVICES; device_id++) { 4182 if (!num_buffs_reaped[device_id]) 4183 continue; 4184 4185 partner_ab = ath12k_ag_to_ab(ag, device_id); 4186 rx_ring = &partner_ab->dp.rx_refill_buf_ring; 4187 4188 ath12k_dp_rx_bufs_replenish(ab, rx_ring, 4189 &rx_desc_used_list[device_id], 4190 num_buffs_reaped[device_id]); 4191 } 4192 4193 rcu_read_lock(); 4194 while ((msdu = __skb_dequeue(&msdu_list))) { 4195 rxcb = ATH12K_SKB_RXCB(msdu); 4196 hw_link_id = rxcb->hw_link_id; 4197 4198 device_id = hw_links[hw_link_id].device_id; 4199 partner_ab = ath12k_ag_to_ab(ag, device_id); 4200 if (unlikely(!partner_ab)) { 4201 ath12k_dbg(ab, ATH12K_DBG_DATA, 4202 "Unable to process WBM error msdu due to invalid hw link id %d device id %d\n", 4203 hw_link_id, device_id); 4204 dev_kfree_skb_any(msdu); 4205 continue; 4206 } 4207 4208 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params, 4209 hw_links[hw_link_id].pdev_idx); 4210 ar = partner_ab->pdevs[pdev_id].ar; 4211 4212 if (!ar || !rcu_dereference(ar->ab->pdevs_active[pdev_id])) { 4213 dev_kfree_skb_any(msdu); 4214 continue; 4215 } 4216 4217 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) { 4218 dev_kfree_skb_any(msdu); 4219 continue; 4220 } 4221 4222 if (rxcb->err_rel_src < HAL_WBM_REL_SRC_MODULE_MAX) { 4223 device_id = ar->ab->device_id; 4224 device_stats->rx_wbm_rel_source[rxcb->err_rel_src][device_id]++; 4225 } 4226 4227 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); 4228 } 4229 rcu_read_unlock(); 4230 done: 4231 return total_num_buffs_reaped; 4232 } 4233 4234 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 4235 { 4236 struct ath12k_dp *dp = &ab->dp; 4237 struct hal_tlv_64_hdr *hdr; 4238 struct hal_srng *srng; 4239 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 4240 bool found = false; 4241 u16 tag; 4242 struct hal_reo_status reo_status; 4243 4244 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4245 4246 memset(&reo_status, 0, sizeof(reo_status)); 4247 4248 spin_lock_bh(&srng->lock); 4249 4250 ath12k_hal_srng_access_begin(ab, srng); 4251 4252 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 4253 tag = le64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 4254 4255 switch (tag) { 4256 case HAL_REO_GET_QUEUE_STATS_STATUS: 4257 ath12k_hal_reo_status_queue_stats(ab, hdr, 4258 &reo_status); 4259 break; 4260 case HAL_REO_FLUSH_QUEUE_STATUS: 4261 ath12k_hal_reo_flush_queue_status(ab, hdr, 4262 &reo_status); 4263 break; 4264 case HAL_REO_FLUSH_CACHE_STATUS: 4265 ath12k_hal_reo_flush_cache_status(ab, hdr, 4266 &reo_status); 4267 break; 4268 case HAL_REO_UNBLOCK_CACHE_STATUS: 4269 ath12k_hal_reo_unblk_cache_status(ab, hdr, 4270 &reo_status); 4271 break; 4272 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4273 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 4274 &reo_status); 4275 break; 4276 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4277 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 4278 &reo_status); 4279 break; 4280 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4281 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 4282 &reo_status); 4283 break; 4284 default: 4285 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 4286 continue; 4287 } 4288 4289 spin_lock_bh(&dp->reo_cmd_lock); 4290 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4291 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4292 found = true; 4293 list_del(&cmd->list); 4294 break; 4295 } 4296 } 4297 spin_unlock_bh(&dp->reo_cmd_lock); 4298 4299 if (found) { 4300 cmd->handler(dp, (void *)&cmd->data, 4301 reo_status.uniform_hdr.cmd_status); 4302 kfree(cmd); 4303 } 4304 4305 found = false; 4306 } 4307 4308 ath12k_hal_srng_access_end(ab, srng); 4309 4310 spin_unlock_bh(&srng->lock); 4311 } 4312 4313 void ath12k_dp_rx_free(struct ath12k_base *ab) 4314 { 4315 struct ath12k_dp *dp = &ab->dp; 4316 struct dp_srng *srng; 4317 int i; 4318 4319 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 4320 4321 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4322 if (ab->hw_params->rx_mac_buf_ring) 4323 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 4324 if (!ab->hw_params->rxdma1_enable) { 4325 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 4326 ath12k_dp_srng_cleanup(ab, srng); 4327 } 4328 } 4329 4330 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 4331 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 4332 4333 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 4334 4335 ath12k_dp_rxdma_buf_free(ab); 4336 } 4337 4338 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 4339 { 4340 struct ath12k *ar = ab->pdevs[mac_id].ar; 4341 4342 ath12k_dp_rx_pdev_srng_free(ar); 4343 } 4344 4345 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 4346 { 4347 struct ath12k_dp *dp = &ab->dp; 4348 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4349 u32 ring_id; 4350 int ret; 4351 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4352 4353 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4354 4355 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4356 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4357 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4358 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4359 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4360 tlv_filter.offset_valid = true; 4361 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4362 4363 tlv_filter.rx_mpdu_start_offset = 4364 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4365 tlv_filter.rx_msdu_end_offset = 4366 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4367 4368 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 4369 tlv_filter.rx_mpdu_start_wmask = 4370 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); 4371 tlv_filter.rx_msdu_end_wmask = 4372 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); 4373 ath12k_dbg(ab, ATH12K_DBG_DATA, 4374 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", 4375 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); 4376 } 4377 4378 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 4379 HAL_RXDMA_BUF, 4380 DP_RXDMA_REFILL_RING_SIZE, 4381 &tlv_filter); 4382 4383 return ret; 4384 } 4385 4386 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 4387 { 4388 struct ath12k_dp *dp = &ab->dp; 4389 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4390 u32 ring_id; 4391 int ret = 0; 4392 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4393 int i; 4394 4395 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4396 4397 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4398 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4399 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4400 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4401 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4402 tlv_filter.offset_valid = true; 4403 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4404 4405 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4406 4407 tlv_filter.rx_mpdu_start_offset = 4408 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4409 tlv_filter.rx_msdu_end_offset = 4410 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4411 4412 /* TODO: Selectively subscribe to required qwords within msdu_end 4413 * and mpdu_start and setup the mask in below msg 4414 * and modify the rx_desc struct 4415 */ 4416 4417 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4418 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4419 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4420 HAL_RXDMA_BUF, 4421 DP_RXDMA_REFILL_RING_SIZE, 4422 &tlv_filter); 4423 } 4424 4425 return ret; 4426 } 4427 4428 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4429 { 4430 struct ath12k_dp *dp = &ab->dp; 4431 u32 ring_id; 4432 int i, ret; 4433 4434 /* TODO: Need to verify the HTT setup for QCN9224 */ 4435 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4436 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4437 if (ret) { 4438 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4439 ret); 4440 return ret; 4441 } 4442 4443 if (ab->hw_params->rx_mac_buf_ring) { 4444 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4445 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4446 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4447 i, HAL_RXDMA_BUF); 4448 if (ret) { 4449 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4450 i, ret); 4451 return ret; 4452 } 4453 } 4454 } 4455 4456 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4457 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4458 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4459 i, HAL_RXDMA_DST); 4460 if (ret) { 4461 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4462 i, ret); 4463 return ret; 4464 } 4465 } 4466 4467 if (ab->hw_params->rxdma1_enable) { 4468 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4469 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4470 0, HAL_RXDMA_MONITOR_BUF); 4471 if (ret) { 4472 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4473 ret); 4474 return ret; 4475 } 4476 } else { 4477 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4478 ring_id = 4479 dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 4480 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, i, 4481 HAL_RXDMA_MONITOR_STATUS); 4482 if (ret) { 4483 ath12k_warn(ab, 4484 "failed to configure mon_status_refill_ring%d %d\n", 4485 i, ret); 4486 return ret; 4487 } 4488 } 4489 } 4490 4491 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4492 if (ret) { 4493 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4494 return ret; 4495 } 4496 4497 return 0; 4498 } 4499 4500 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4501 { 4502 struct ath12k_dp *dp = &ab->dp; 4503 struct dp_srng *srng; 4504 int i, ret; 4505 4506 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4507 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4508 4509 ret = ath12k_dp_srng_setup(ab, 4510 &dp->rx_refill_buf_ring.refill_buf_ring, 4511 HAL_RXDMA_BUF, 0, 0, 4512 DP_RXDMA_BUF_RING_SIZE); 4513 if (ret) { 4514 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4515 return ret; 4516 } 4517 4518 if (ab->hw_params->rx_mac_buf_ring) { 4519 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4520 ret = ath12k_dp_srng_setup(ab, 4521 &dp->rx_mac_buf_ring[i], 4522 HAL_RXDMA_BUF, 1, 4523 i, DP_RX_MAC_BUF_RING_SIZE); 4524 if (ret) { 4525 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4526 i); 4527 return ret; 4528 } 4529 } 4530 } 4531 4532 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4533 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4534 HAL_RXDMA_DST, 0, i, 4535 DP_RXDMA_ERR_DST_RING_SIZE); 4536 if (ret) { 4537 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4538 return ret; 4539 } 4540 } 4541 4542 if (ab->hw_params->rxdma1_enable) { 4543 ret = ath12k_dp_srng_setup(ab, 4544 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4545 HAL_RXDMA_MONITOR_BUF, 0, 0, 4546 DP_RXDMA_MONITOR_BUF_RING_SIZE); 4547 if (ret) { 4548 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4549 return ret; 4550 } 4551 } else { 4552 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4553 idr_init(&dp->rx_mon_status_refill_ring[i].bufs_idr); 4554 spin_lock_init(&dp->rx_mon_status_refill_ring[i].idr_lock); 4555 } 4556 4557 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4558 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 4559 ret = ath12k_dp_srng_setup(ab, srng, 4560 HAL_RXDMA_MONITOR_STATUS, 0, i, 4561 DP_RXDMA_MON_STATUS_RING_SIZE); 4562 if (ret) { 4563 ath12k_warn(ab, "failed to setup mon status ring %d\n", 4564 i); 4565 return ret; 4566 } 4567 } 4568 } 4569 4570 ret = ath12k_dp_rxdma_buf_setup(ab); 4571 if (ret) { 4572 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4573 return ret; 4574 } 4575 4576 return 0; 4577 } 4578 4579 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4580 { 4581 struct ath12k *ar = ab->pdevs[mac_id].ar; 4582 struct ath12k_pdev_dp *dp = &ar->dp; 4583 u32 ring_id; 4584 int i; 4585 int ret; 4586 4587 if (!ab->hw_params->rxdma1_enable) 4588 goto out; 4589 4590 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4591 if (ret) { 4592 ath12k_warn(ab, "failed to setup rx srngs\n"); 4593 return ret; 4594 } 4595 4596 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 4597 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4598 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4599 mac_id + i, 4600 HAL_RXDMA_MONITOR_DST); 4601 if (ret) { 4602 ath12k_warn(ab, 4603 "failed to configure rxdma_mon_dst_ring %d %d\n", 4604 i, ret); 4605 return ret; 4606 } 4607 } 4608 out: 4609 return 0; 4610 } 4611 4612 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4613 { 4614 struct ath12k_pdev_dp *dp = &ar->dp; 4615 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4616 4617 skb_queue_head_init(&pmon->rx_status_q); 4618 4619 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4620 4621 memset(&pmon->rx_mon_stats, 0, 4622 sizeof(pmon->rx_mon_stats)); 4623 return 0; 4624 } 4625 4626 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4627 { 4628 struct ath12k_pdev_dp *dp = &ar->dp; 4629 struct ath12k_mon_data *pmon = &dp->mon_data; 4630 int ret = 0; 4631 4632 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4633 if (ret) { 4634 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4635 return ret; 4636 } 4637 4638 pmon->mon_last_linkdesc_paddr = 0; 4639 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4640 spin_lock_init(&pmon->mon_lock); 4641 4642 if (!ar->ab->hw_params->rxdma1_enable) 4643 return 0; 4644 4645 INIT_LIST_HEAD(&pmon->dp_rx_mon_mpdu_list); 4646 pmon->mon_mpdu = NULL; 4647 4648 return 0; 4649 } 4650