1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 21 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22 23 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 24 struct hal_rx_desc *desc) 25 { 26 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) 27 return HAL_ENCRYPT_TYPE_OPEN; 28 29 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); 30 } 31 32 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 33 struct hal_rx_desc *desc) 34 { 35 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); 36 } 37 38 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 39 struct hal_rx_desc *desc) 40 { 41 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); 42 } 43 44 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 45 struct hal_rx_desc *desc) 46 { 47 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 48 } 49 50 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 51 struct hal_rx_desc *desc) 52 { 53 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); 54 } 55 56 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 57 struct sk_buff *skb) 58 { 59 struct ieee80211_hdr *hdr; 60 61 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 62 return ieee80211_has_morefrags(hdr->frame_control); 63 } 64 65 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 66 struct sk_buff *skb) 67 { 68 struct ieee80211_hdr *hdr; 69 70 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); 71 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 72 } 73 74 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 75 struct hal_rx_desc *desc) 76 { 77 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc); 78 } 79 80 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 81 struct hal_rx_desc *desc) 82 { 83 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc); 84 } 85 86 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 87 struct hal_rx_desc *desc) 88 { 89 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc); 90 } 91 92 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 93 struct hal_rx_desc *desc) 94 { 95 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc); 96 } 97 98 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 99 struct hal_rx_desc *desc) 100 { 101 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc); 102 } 103 104 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 105 struct hal_rx_desc *desc) 106 { 107 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc); 108 } 109 110 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 111 struct hal_rx_desc *desc) 112 { 113 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc); 114 } 115 116 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 117 struct hal_rx_desc *desc) 118 { 119 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc); 120 } 121 122 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 123 struct hal_rx_desc *desc) 124 { 125 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc); 126 } 127 128 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 129 struct hal_rx_desc *desc) 130 { 131 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc); 132 } 133 134 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 135 struct hal_rx_desc *desc) 136 { 137 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc); 138 } 139 140 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 141 struct hal_rx_desc *desc) 142 { 143 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc); 144 } 145 146 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 147 struct hal_rx_desc *desc) 148 { 149 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc)); 150 } 151 152 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 153 struct hal_rx_desc *desc) 154 { 155 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc); 156 } 157 158 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 159 struct hal_rx_desc *desc) 160 { 161 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc); 162 } 163 164 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 165 struct hal_rx_desc *desc) 166 { 167 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc); 168 } 169 170 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 171 struct hal_rx_desc *desc) 172 { 173 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc); 174 } 175 176 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 177 struct hal_rx_desc *desc) 178 { 179 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc); 180 } 181 182 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 183 struct hal_rx_desc *fdesc, 184 struct hal_rx_desc *ldesc) 185 { 186 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 187 } 188 189 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 190 struct hal_rx_desc *desc, 191 u16 len) 192 { 193 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len); 194 } 195 196 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 197 struct hal_rx_desc *desc) 198 { 199 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 200 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc)); 201 } 202 203 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 204 struct hal_rx_desc *desc) 205 { 206 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc); 207 } 208 209 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 210 struct hal_rx_desc *desc) 211 { 212 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc); 213 } 214 215 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 216 struct hal_rx_desc *desc, 217 struct ieee80211_hdr *hdr) 218 { 219 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr); 220 } 221 222 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 223 struct hal_rx_desc *desc, 224 u8 *crypto_hdr, 225 enum hal_encrypt_type enctype) 226 { 227 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 228 } 229 230 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab, 231 struct hal_rx_desc *desc) 232 { 233 return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc); 234 } 235 236 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, 237 struct hal_rx_desc *desc) 238 { 239 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc); 240 } 241 242 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list) 243 { 244 struct sk_buff *skb; 245 246 while ((skb = __skb_dequeue(skb_list))) 247 dev_kfree_skb_any(skb); 248 } 249 250 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 251 struct list_head *head, 252 size_t count) 253 { 254 struct list_head *cur; 255 struct ath12k_rx_desc_info *rx_desc; 256 size_t nodes = 0; 257 258 if (!count) { 259 INIT_LIST_HEAD(list); 260 goto out; 261 } 262 263 list_for_each(cur, head) { 264 if (!count) 265 break; 266 267 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 268 rx_desc->in_use = true; 269 270 count--; 271 nodes++; 272 } 273 274 list_cut_before(list, head, cur); 275 out: 276 return nodes; 277 } 278 279 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 280 struct list_head *used_list) 281 { 282 struct ath12k_rx_desc_info *rx_desc, *safe; 283 284 /* Reset the use flag */ 285 list_for_each_entry_safe(rx_desc, safe, used_list, list) 286 rx_desc->in_use = false; 287 288 spin_lock_bh(&dp->rx_desc_lock); 289 list_splice_tail(used_list, &dp->rx_desc_free_list); 290 spin_unlock_bh(&dp->rx_desc_lock); 291 } 292 293 /* Returns number of Rx buffers replenished */ 294 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, 295 struct dp_rxdma_ring *rx_ring, 296 struct list_head *used_list, 297 int req_entries) 298 { 299 struct ath12k_buffer_addr *desc; 300 struct hal_srng *srng; 301 struct sk_buff *skb; 302 int num_free; 303 int num_remain; 304 u32 cookie; 305 dma_addr_t paddr; 306 struct ath12k_dp *dp = &ab->dp; 307 struct ath12k_rx_desc_info *rx_desc; 308 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; 309 310 req_entries = min(req_entries, rx_ring->bufs_max); 311 312 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 313 314 spin_lock_bh(&srng->lock); 315 316 ath12k_hal_srng_access_begin(ab, srng); 317 318 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 319 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 320 req_entries = num_free; 321 322 req_entries = min(num_free, req_entries); 323 num_remain = req_entries; 324 325 if (!num_remain) 326 goto out; 327 328 /* Get the descriptor from free list */ 329 if (list_empty(used_list)) { 330 spin_lock_bh(&dp->rx_desc_lock); 331 req_entries = ath12k_dp_list_cut_nodes(used_list, 332 &dp->rx_desc_free_list, 333 num_remain); 334 spin_unlock_bh(&dp->rx_desc_lock); 335 num_remain = req_entries; 336 } 337 338 while (num_remain > 0) { 339 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 340 DP_RX_BUFFER_ALIGN_SIZE); 341 if (!skb) 342 break; 343 344 if (!IS_ALIGNED((unsigned long)skb->data, 345 DP_RX_BUFFER_ALIGN_SIZE)) { 346 skb_pull(skb, 347 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 348 skb->data); 349 } 350 351 paddr = dma_map_single(ab->dev, skb->data, 352 skb->len + skb_tailroom(skb), 353 DMA_FROM_DEVICE); 354 if (dma_mapping_error(ab->dev, paddr)) 355 goto fail_free_skb; 356 357 rx_desc = list_first_entry_or_null(used_list, 358 struct ath12k_rx_desc_info, 359 list); 360 if (!rx_desc) 361 goto fail_dma_unmap; 362 363 rx_desc->skb = skb; 364 cookie = rx_desc->cookie; 365 366 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 367 if (!desc) 368 goto fail_dma_unmap; 369 370 list_del(&rx_desc->list); 371 ATH12K_SKB_RXCB(skb)->paddr = paddr; 372 373 num_remain--; 374 375 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 376 } 377 378 goto out; 379 380 fail_dma_unmap: 381 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 382 DMA_FROM_DEVICE); 383 fail_free_skb: 384 dev_kfree_skb_any(skb); 385 out: 386 ath12k_hal_srng_access_end(ab, srng); 387 388 if (!list_empty(used_list)) 389 ath12k_dp_rx_enqueue_free(dp, used_list); 390 391 spin_unlock_bh(&srng->lock); 392 393 return req_entries - num_remain; 394 } 395 396 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 397 struct dp_rxdma_mon_ring *rx_ring) 398 { 399 struct sk_buff *skb; 400 int buf_id; 401 402 spin_lock_bh(&rx_ring->idr_lock); 403 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 404 idr_remove(&rx_ring->bufs_idr, buf_id); 405 /* TODO: Understand where internal driver does this dma_unmap 406 * of rxdma_buffer. 407 */ 408 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 409 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 410 dev_kfree_skb_any(skb); 411 } 412 413 idr_destroy(&rx_ring->bufs_idr); 414 spin_unlock_bh(&rx_ring->idr_lock); 415 416 return 0; 417 } 418 419 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 420 { 421 struct ath12k_dp *dp = &ab->dp; 422 423 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 424 425 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->tx_mon_buf_ring); 426 427 return 0; 428 } 429 430 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 431 struct dp_rxdma_mon_ring *rx_ring, 432 u32 ringtype) 433 { 434 int num_entries; 435 436 num_entries = rx_ring->refill_buf_ring.size / 437 ath12k_hal_srng_get_entrysize(ab, ringtype); 438 439 rx_ring->bufs_max = num_entries; 440 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 441 442 return 0; 443 } 444 445 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 446 struct dp_rxdma_ring *rx_ring) 447 { 448 LIST_HEAD(list); 449 450 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 451 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 452 453 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 454 455 return 0; 456 } 457 458 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 459 { 460 struct ath12k_dp *dp = &ab->dp; 461 int ret; 462 463 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 464 if (ret) { 465 ath12k_warn(ab, 466 "failed to setup HAL_RXDMA_BUF\n"); 467 return ret; 468 } 469 470 if (ab->hw_params->rxdma1_enable) { 471 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 472 &dp->rxdma_mon_buf_ring, 473 HAL_RXDMA_MONITOR_BUF); 474 if (ret) { 475 ath12k_warn(ab, 476 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 477 return ret; 478 } 479 480 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 481 &dp->tx_mon_buf_ring, 482 HAL_TX_MONITOR_BUF); 483 if (ret) { 484 ath12k_warn(ab, 485 "failed to setup HAL_TX_MONITOR_BUF\n"); 486 return ret; 487 } 488 } 489 490 return 0; 491 } 492 493 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 494 { 495 struct ath12k_pdev_dp *dp = &ar->dp; 496 struct ath12k_base *ab = ar->ab; 497 int i; 498 499 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 500 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 501 ath12k_dp_srng_cleanup(ab, &dp->tx_mon_dst_ring[i]); 502 } 503 } 504 505 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 506 { 507 struct ath12k_dp *dp = &ab->dp; 508 int i; 509 510 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 511 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 512 } 513 514 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 515 { 516 struct ath12k_dp *dp = &ab->dp; 517 int ret; 518 int i; 519 520 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 521 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 522 HAL_REO_DST, i, 0, 523 DP_REO_DST_RING_SIZE); 524 if (ret) { 525 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 526 goto err_reo_cleanup; 527 } 528 } 529 530 return 0; 531 532 err_reo_cleanup: 533 ath12k_dp_rx_pdev_reo_cleanup(ab); 534 535 return ret; 536 } 537 538 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 539 { 540 struct ath12k_pdev_dp *dp = &ar->dp; 541 struct ath12k_base *ab = ar->ab; 542 int i; 543 int ret; 544 u32 mac_id = dp->mac_id; 545 546 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 547 ret = ath12k_dp_srng_setup(ar->ab, 548 &dp->rxdma_mon_dst_ring[i], 549 HAL_RXDMA_MONITOR_DST, 550 0, mac_id + i, 551 DP_RXDMA_MONITOR_DST_RING_SIZE); 552 if (ret) { 553 ath12k_warn(ar->ab, 554 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 555 return ret; 556 } 557 558 ret = ath12k_dp_srng_setup(ar->ab, 559 &dp->tx_mon_dst_ring[i], 560 HAL_TX_MONITOR_DST, 561 0, mac_id + i, 562 DP_TX_MONITOR_DEST_RING_SIZE); 563 if (ret) { 564 ath12k_warn(ar->ab, 565 "failed to setup HAL_TX_MONITOR_DST\n"); 566 return ret; 567 } 568 } 569 570 return 0; 571 } 572 573 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 574 { 575 struct ath12k_dp *dp = &ab->dp; 576 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 577 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 578 579 spin_lock_bh(&dp->reo_cmd_lock); 580 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 581 list_del(&cmd->list); 582 dma_unmap_single(ab->dev, cmd->data.paddr, 583 cmd->data.size, DMA_BIDIRECTIONAL); 584 kfree(cmd->data.vaddr); 585 kfree(cmd); 586 } 587 588 list_for_each_entry_safe(cmd_cache, tmp_cache, 589 &dp->reo_cmd_cache_flush_list, list) { 590 list_del(&cmd_cache->list); 591 dp->reo_cmd_cache_flush_count--; 592 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 593 cmd_cache->data.size, DMA_BIDIRECTIONAL); 594 kfree(cmd_cache->data.vaddr); 595 kfree(cmd_cache); 596 } 597 spin_unlock_bh(&dp->reo_cmd_lock); 598 } 599 600 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 601 enum hal_reo_cmd_status status) 602 { 603 struct ath12k_dp_rx_tid *rx_tid = ctx; 604 605 if (status != HAL_REO_CMD_SUCCESS) 606 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 607 rx_tid->tid, status); 608 609 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 610 DMA_BIDIRECTIONAL); 611 kfree(rx_tid->vaddr); 612 rx_tid->vaddr = NULL; 613 } 614 615 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 616 enum hal_reo_cmd_type type, 617 struct ath12k_hal_reo_cmd *cmd, 618 void (*cb)(struct ath12k_dp *dp, void *ctx, 619 enum hal_reo_cmd_status status)) 620 { 621 struct ath12k_dp *dp = &ab->dp; 622 struct ath12k_dp_rx_reo_cmd *dp_cmd; 623 struct hal_srng *cmd_ring; 624 int cmd_num; 625 626 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 627 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 628 629 /* cmd_num should start from 1, during failure return the error code */ 630 if (cmd_num < 0) 631 return cmd_num; 632 633 /* reo cmd ring descriptors has cmd_num starting from 1 */ 634 if (cmd_num == 0) 635 return -EINVAL; 636 637 if (!cb) 638 return 0; 639 640 /* Can this be optimized so that we keep the pending command list only 641 * for tid delete command to free up the resource on the command status 642 * indication? 643 */ 644 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 645 646 if (!dp_cmd) 647 return -ENOMEM; 648 649 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 650 dp_cmd->cmd_num = cmd_num; 651 dp_cmd->handler = cb; 652 653 spin_lock_bh(&dp->reo_cmd_lock); 654 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 655 spin_unlock_bh(&dp->reo_cmd_lock); 656 657 return 0; 658 } 659 660 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 661 struct ath12k_dp_rx_tid *rx_tid) 662 { 663 struct ath12k_hal_reo_cmd cmd = {0}; 664 unsigned long tot_desc_sz, desc_sz; 665 int ret; 666 667 tot_desc_sz = rx_tid->size; 668 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 669 670 while (tot_desc_sz > desc_sz) { 671 tot_desc_sz -= desc_sz; 672 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 673 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 674 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 675 HAL_REO_CMD_FLUSH_CACHE, &cmd, 676 NULL); 677 if (ret) 678 ath12k_warn(ab, 679 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 680 rx_tid->tid, ret); 681 } 682 683 memset(&cmd, 0, sizeof(cmd)); 684 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 685 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 686 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 687 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 688 HAL_REO_CMD_FLUSH_CACHE, 689 &cmd, ath12k_dp_reo_cmd_free); 690 if (ret) { 691 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 692 rx_tid->tid, ret); 693 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 694 DMA_BIDIRECTIONAL); 695 kfree(rx_tid->vaddr); 696 rx_tid->vaddr = NULL; 697 } 698 } 699 700 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 701 enum hal_reo_cmd_status status) 702 { 703 struct ath12k_base *ab = dp->ab; 704 struct ath12k_dp_rx_tid *rx_tid = ctx; 705 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 706 707 if (status == HAL_REO_CMD_DRAIN) { 708 goto free_desc; 709 } else if (status != HAL_REO_CMD_SUCCESS) { 710 /* Shouldn't happen! Cleanup in case of other failure? */ 711 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 712 rx_tid->tid, status); 713 return; 714 } 715 716 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 717 if (!elem) 718 goto free_desc; 719 720 elem->ts = jiffies; 721 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 722 723 spin_lock_bh(&dp->reo_cmd_lock); 724 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 725 dp->reo_cmd_cache_flush_count++; 726 727 /* Flush and invalidate aged REO desc from HW cache */ 728 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 729 list) { 730 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 731 time_after(jiffies, elem->ts + 732 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 733 list_del(&elem->list); 734 dp->reo_cmd_cache_flush_count--; 735 736 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 737 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 738 * is used in only two contexts, one is in this function called 739 * from napi and the other in ath12k_dp_free during core destroy. 740 * Before dp_free, the irqs would be disabled and would wait to 741 * synchronize. Hence there wouldn’t be any race against add or 742 * delete to this list. Hence unlock-lock is safe here. 743 */ 744 spin_unlock_bh(&dp->reo_cmd_lock); 745 746 ath12k_dp_reo_cache_flush(ab, &elem->data); 747 kfree(elem); 748 spin_lock_bh(&dp->reo_cmd_lock); 749 } 750 } 751 spin_unlock_bh(&dp->reo_cmd_lock); 752 753 return; 754 free_desc: 755 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 756 DMA_BIDIRECTIONAL); 757 kfree(rx_tid->vaddr); 758 rx_tid->vaddr = NULL; 759 } 760 761 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 762 dma_addr_t paddr) 763 { 764 struct ath12k_reo_queue_ref *qref; 765 struct ath12k_dp *dp = &ab->dp; 766 767 if (!ab->hw_params->reoq_lut_support) 768 return; 769 770 /* TODO: based on ML peer or not, select the LUT. below assumes non 771 * ML peer 772 */ 773 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 774 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 775 776 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 777 BUFFER_ADDR_INFO0_ADDR); 778 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 779 BUFFER_ADDR_INFO1_ADDR) | 780 u32_encode_bits(tid, DP_REO_QREF_NUM); 781 } 782 783 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 784 { 785 struct ath12k_reo_queue_ref *qref; 786 struct ath12k_dp *dp = &ab->dp; 787 788 if (!ab->hw_params->reoq_lut_support) 789 return; 790 791 /* TODO: based on ML peer or not, select the LUT. below assumes non 792 * ML peer 793 */ 794 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 795 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 796 797 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 798 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 799 u32_encode_bits(tid, DP_REO_QREF_NUM); 800 } 801 802 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 803 struct ath12k_peer *peer, u8 tid) 804 { 805 struct ath12k_hal_reo_cmd cmd = {0}; 806 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 807 int ret; 808 809 if (!rx_tid->active) 810 return; 811 812 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 813 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 814 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 815 cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 816 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 817 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 818 ath12k_dp_rx_tid_del_func); 819 if (ret) { 820 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 821 tid, ret); 822 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 823 DMA_BIDIRECTIONAL); 824 kfree(rx_tid->vaddr); 825 rx_tid->vaddr = NULL; 826 } 827 828 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 829 830 rx_tid->active = false; 831 } 832 833 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted 834 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind 835 * that. 836 */ 837 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 838 struct hal_reo_dest_ring *ring, 839 enum hal_wbm_rel_bm_act action) 840 { 841 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring; 842 struct hal_wbm_release_ring *desc; 843 struct ath12k_dp *dp = &ab->dp; 844 struct hal_srng *srng; 845 int ret = 0; 846 847 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 848 849 spin_lock_bh(&srng->lock); 850 851 ath12k_hal_srng_access_begin(ab, srng); 852 853 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 854 if (!desc) { 855 ret = -ENOBUFS; 856 goto exit; 857 } 858 859 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action); 860 861 exit: 862 ath12k_hal_srng_access_end(ab, srng); 863 864 spin_unlock_bh(&srng->lock); 865 866 return ret; 867 } 868 869 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 870 bool rel_link_desc) 871 { 872 struct ath12k_base *ab = rx_tid->ab; 873 874 lockdep_assert_held(&ab->base_lock); 875 876 if (rx_tid->dst_ring_desc) { 877 if (rel_link_desc) 878 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc, 879 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 880 kfree(rx_tid->dst_ring_desc); 881 rx_tid->dst_ring_desc = NULL; 882 } 883 884 rx_tid->cur_sn = 0; 885 rx_tid->last_frag_no = 0; 886 rx_tid->rx_frag_bitmap = 0; 887 __skb_queue_purge(&rx_tid->rx_frags); 888 } 889 890 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 891 { 892 struct ath12k_dp_rx_tid *rx_tid; 893 int i; 894 895 lockdep_assert_held(&ar->ab->base_lock); 896 897 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 898 rx_tid = &peer->rx_tid[i]; 899 900 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 901 ath12k_dp_rx_frags_cleanup(rx_tid, true); 902 903 spin_unlock_bh(&ar->ab->base_lock); 904 del_timer_sync(&rx_tid->frag_timer); 905 spin_lock_bh(&ar->ab->base_lock); 906 } 907 } 908 909 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 910 struct ath12k_peer *peer, 911 struct ath12k_dp_rx_tid *rx_tid, 912 u32 ba_win_sz, u16 ssn, 913 bool update_ssn) 914 { 915 struct ath12k_hal_reo_cmd cmd = {0}; 916 int ret; 917 918 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 919 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 920 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 921 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 922 cmd.ba_window_size = ba_win_sz; 923 924 if (update_ssn) { 925 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 926 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 927 } 928 929 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 930 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 931 NULL); 932 if (ret) { 933 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 934 rx_tid->tid, ret); 935 return ret; 936 } 937 938 rx_tid->ba_win_sz = ba_win_sz; 939 940 return 0; 941 } 942 943 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 944 u8 tid, u32 ba_win_sz, u16 ssn, 945 enum hal_pn_type pn_type) 946 { 947 struct ath12k_base *ab = ar->ab; 948 struct ath12k_dp *dp = &ab->dp; 949 struct hal_rx_reo_queue *addr_aligned; 950 struct ath12k_peer *peer; 951 struct ath12k_dp_rx_tid *rx_tid; 952 u32 hw_desc_sz; 953 void *vaddr; 954 dma_addr_t paddr; 955 int ret; 956 957 spin_lock_bh(&ab->base_lock); 958 959 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 960 if (!peer) { 961 spin_unlock_bh(&ab->base_lock); 962 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 963 return -ENOENT; 964 } 965 966 if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) { 967 spin_unlock_bh(&ab->base_lock); 968 ath12k_warn(ab, "reo qref table is not setup\n"); 969 return -EINVAL; 970 } 971 972 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 973 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 974 peer->peer_id, tid); 975 spin_unlock_bh(&ab->base_lock); 976 return -EINVAL; 977 } 978 979 rx_tid = &peer->rx_tid[tid]; 980 /* Update the tid queue if it is already setup */ 981 if (rx_tid->active) { 982 paddr = rx_tid->paddr; 983 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 984 ba_win_sz, ssn, true); 985 spin_unlock_bh(&ab->base_lock); 986 if (ret) { 987 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 988 return ret; 989 } 990 991 if (!ab->hw_params->reoq_lut_support) { 992 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 993 peer_mac, 994 paddr, tid, 1, 995 ba_win_sz); 996 if (ret) { 997 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 998 tid, ret); 999 return ret; 1000 } 1001 } 1002 1003 return 0; 1004 } 1005 1006 rx_tid->tid = tid; 1007 1008 rx_tid->ba_win_sz = ba_win_sz; 1009 1010 /* TODO: Optimize the memory allocation for qos tid based on 1011 * the actual BA window size in REO tid update path. 1012 */ 1013 if (tid == HAL_DESC_REO_NON_QOS_TID) 1014 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 1015 else 1016 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1017 1018 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1019 if (!vaddr) { 1020 spin_unlock_bh(&ab->base_lock); 1021 return -ENOMEM; 1022 } 1023 1024 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1025 1026 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1027 ssn, pn_type); 1028 1029 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1030 DMA_BIDIRECTIONAL); 1031 1032 ret = dma_mapping_error(ab->dev, paddr); 1033 if (ret) { 1034 spin_unlock_bh(&ab->base_lock); 1035 goto err_mem_free; 1036 } 1037 1038 rx_tid->vaddr = vaddr; 1039 rx_tid->paddr = paddr; 1040 rx_tid->size = hw_desc_sz; 1041 rx_tid->active = true; 1042 1043 if (ab->hw_params->reoq_lut_support) { 1044 /* Update the REO queue LUT at the corresponding peer id 1045 * and tid with qaddr. 1046 */ 1047 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr); 1048 spin_unlock_bh(&ab->base_lock); 1049 } else { 1050 spin_unlock_bh(&ab->base_lock); 1051 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1052 paddr, tid, 1, ba_win_sz); 1053 } 1054 1055 return ret; 1056 1057 err_mem_free: 1058 kfree(vaddr); 1059 1060 return ret; 1061 } 1062 1063 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1064 struct ieee80211_ampdu_params *params) 1065 { 1066 struct ath12k_base *ab = ar->ab; 1067 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta); 1068 int vdev_id = arsta->arvif->vdev_id; 1069 int ret; 1070 1071 ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id, 1072 params->tid, params->buf_size, 1073 params->ssn, arsta->pn_type); 1074 if (ret) 1075 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1076 1077 return ret; 1078 } 1079 1080 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1081 struct ieee80211_ampdu_params *params) 1082 { 1083 struct ath12k_base *ab = ar->ab; 1084 struct ath12k_peer *peer; 1085 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta); 1086 int vdev_id = arsta->arvif->vdev_id; 1087 bool active; 1088 int ret; 1089 1090 spin_lock_bh(&ab->base_lock); 1091 1092 peer = ath12k_peer_find(ab, vdev_id, params->sta->addr); 1093 if (!peer) { 1094 spin_unlock_bh(&ab->base_lock); 1095 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1096 return -ENOENT; 1097 } 1098 1099 active = peer->rx_tid[params->tid].active; 1100 1101 if (!active) { 1102 spin_unlock_bh(&ab->base_lock); 1103 return 0; 1104 } 1105 1106 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1107 spin_unlock_bh(&ab->base_lock); 1108 if (ret) { 1109 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1110 params->tid, ret); 1111 return ret; 1112 } 1113 1114 return ret; 1115 } 1116 1117 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif, 1118 const u8 *peer_addr, 1119 enum set_key_cmd key_cmd, 1120 struct ieee80211_key_conf *key) 1121 { 1122 struct ath12k *ar = arvif->ar; 1123 struct ath12k_base *ab = ar->ab; 1124 struct ath12k_hal_reo_cmd cmd = {0}; 1125 struct ath12k_peer *peer; 1126 struct ath12k_dp_rx_tid *rx_tid; 1127 u8 tid; 1128 int ret = 0; 1129 1130 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1131 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1132 * for now. 1133 */ 1134 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1135 return 0; 1136 1137 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1138 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1139 HAL_REO_CMD_UPD0_PN_SIZE | 1140 HAL_REO_CMD_UPD0_PN_VALID | 1141 HAL_REO_CMD_UPD0_PN_CHECK | 1142 HAL_REO_CMD_UPD0_SVLD; 1143 1144 switch (key->cipher) { 1145 case WLAN_CIPHER_SUITE_TKIP: 1146 case WLAN_CIPHER_SUITE_CCMP: 1147 case WLAN_CIPHER_SUITE_CCMP_256: 1148 case WLAN_CIPHER_SUITE_GCMP: 1149 case WLAN_CIPHER_SUITE_GCMP_256: 1150 if (key_cmd == SET_KEY) { 1151 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1152 cmd.pn_size = 48; 1153 } 1154 break; 1155 default: 1156 break; 1157 } 1158 1159 spin_lock_bh(&ab->base_lock); 1160 1161 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1162 if (!peer) { 1163 spin_unlock_bh(&ab->base_lock); 1164 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1165 peer_addr); 1166 return -ENOENT; 1167 } 1168 1169 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1170 rx_tid = &peer->rx_tid[tid]; 1171 if (!rx_tid->active) 1172 continue; 1173 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1174 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1175 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1176 HAL_REO_CMD_UPDATE_RX_QUEUE, 1177 &cmd, NULL); 1178 if (ret) { 1179 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1180 tid, peer_addr, ret); 1181 break; 1182 } 1183 } 1184 1185 spin_unlock_bh(&ab->base_lock); 1186 1187 return ret; 1188 } 1189 1190 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1191 u16 peer_id) 1192 { 1193 int i; 1194 1195 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1196 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1197 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1198 return i; 1199 } else { 1200 return i; 1201 } 1202 } 1203 1204 return -EINVAL; 1205 } 1206 1207 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1208 u16 tag, u16 len, const void *ptr, 1209 void *data) 1210 { 1211 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1212 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1213 const struct htt_ppdu_stats_user_rate *user_rate; 1214 struct htt_ppdu_stats_info *ppdu_info; 1215 struct htt_ppdu_user_stats *user_stats; 1216 int cur_user; 1217 u16 peer_id; 1218 1219 ppdu_info = data; 1220 1221 switch (tag) { 1222 case HTT_PPDU_STATS_TAG_COMMON: 1223 if (len < sizeof(struct htt_ppdu_stats_common)) { 1224 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1225 len, tag); 1226 return -EINVAL; 1227 } 1228 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1229 sizeof(struct htt_ppdu_stats_common)); 1230 break; 1231 case HTT_PPDU_STATS_TAG_USR_RATE: 1232 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1233 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1234 len, tag); 1235 return -EINVAL; 1236 } 1237 user_rate = ptr; 1238 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1239 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1240 peer_id); 1241 if (cur_user < 0) 1242 return -EINVAL; 1243 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1244 user_stats->peer_id = peer_id; 1245 user_stats->is_valid_peer_id = true; 1246 memcpy(&user_stats->rate, ptr, 1247 sizeof(struct htt_ppdu_stats_user_rate)); 1248 user_stats->tlv_flags |= BIT(tag); 1249 break; 1250 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1251 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1252 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1253 len, tag); 1254 return -EINVAL; 1255 } 1256 1257 cmplt_cmn = ptr; 1258 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1259 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1260 peer_id); 1261 if (cur_user < 0) 1262 return -EINVAL; 1263 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1264 user_stats->peer_id = peer_id; 1265 user_stats->is_valid_peer_id = true; 1266 memcpy(&user_stats->cmpltn_cmn, ptr, 1267 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1268 user_stats->tlv_flags |= BIT(tag); 1269 break; 1270 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1271 if (len < 1272 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1273 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1274 len, tag); 1275 return -EINVAL; 1276 } 1277 1278 ba_status = ptr; 1279 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1280 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1281 peer_id); 1282 if (cur_user < 0) 1283 return -EINVAL; 1284 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1285 user_stats->peer_id = peer_id; 1286 user_stats->is_valid_peer_id = true; 1287 memcpy(&user_stats->ack_ba, ptr, 1288 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1289 user_stats->tlv_flags |= BIT(tag); 1290 break; 1291 } 1292 return 0; 1293 } 1294 1295 static int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1296 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1297 const void *ptr, void *data), 1298 void *data) 1299 { 1300 const struct htt_tlv *tlv; 1301 const void *begin = ptr; 1302 u16 tlv_tag, tlv_len; 1303 int ret = -EINVAL; 1304 1305 while (len > 0) { 1306 if (len < sizeof(*tlv)) { 1307 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1308 ptr - begin, len, sizeof(*tlv)); 1309 return -EINVAL; 1310 } 1311 tlv = (struct htt_tlv *)ptr; 1312 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1313 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1314 ptr += sizeof(*tlv); 1315 len -= sizeof(*tlv); 1316 1317 if (tlv_len > len) { 1318 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1319 tlv_tag, ptr - begin, len, tlv_len); 1320 return -EINVAL; 1321 } 1322 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1323 if (ret == -ENOMEM) 1324 return ret; 1325 1326 ptr += tlv_len; 1327 len -= tlv_len; 1328 } 1329 return 0; 1330 } 1331 1332 static void 1333 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1334 struct htt_ppdu_stats *ppdu_stats, u8 user) 1335 { 1336 struct ath12k_base *ab = ar->ab; 1337 struct ath12k_peer *peer; 1338 struct ieee80211_sta *sta; 1339 struct ath12k_sta *arsta; 1340 struct htt_ppdu_stats_user_rate *user_rate; 1341 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1342 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1343 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1344 int ret; 1345 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1346 u32 v, succ_bytes = 0; 1347 u16 tones, rate = 0, succ_pkts = 0; 1348 u32 tx_duration = 0; 1349 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1350 bool is_ampdu = false; 1351 1352 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1353 return; 1354 1355 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1356 is_ampdu = 1357 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1358 1359 if (usr_stats->tlv_flags & 1360 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1361 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1362 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1363 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1364 tid = le32_get_bits(usr_stats->ack_ba.info, 1365 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1366 } 1367 1368 if (common->fes_duration_us) 1369 tx_duration = le32_to_cpu(common->fes_duration_us); 1370 1371 user_rate = &usr_stats->rate; 1372 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1373 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1374 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1375 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1376 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1377 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1378 1379 /* Note: If host configured fixed rates and in some other special 1380 * cases, the broadcast/management frames are sent in different rates. 1381 * Firmware rate's control to be skipped for this? 1382 */ 1383 1384 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1385 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1386 return; 1387 } 1388 1389 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1390 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1391 return; 1392 } 1393 1394 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1395 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1396 mcs, nss); 1397 return; 1398 } 1399 1400 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1401 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1402 flags, 1403 &rate_idx, 1404 &rate); 1405 if (ret < 0) 1406 return; 1407 } 1408 1409 rcu_read_lock(); 1410 spin_lock_bh(&ab->base_lock); 1411 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1412 1413 if (!peer || !peer->sta) { 1414 spin_unlock_bh(&ab->base_lock); 1415 rcu_read_unlock(); 1416 return; 1417 } 1418 1419 sta = peer->sta; 1420 arsta = ath12k_sta_to_arsta(sta); 1421 1422 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1423 1424 switch (flags) { 1425 case WMI_RATE_PREAMBLE_OFDM: 1426 arsta->txrate.legacy = rate; 1427 break; 1428 case WMI_RATE_PREAMBLE_CCK: 1429 arsta->txrate.legacy = rate; 1430 break; 1431 case WMI_RATE_PREAMBLE_HT: 1432 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1433 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1434 if (sgi) 1435 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1436 break; 1437 case WMI_RATE_PREAMBLE_VHT: 1438 arsta->txrate.mcs = mcs; 1439 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1440 if (sgi) 1441 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1442 break; 1443 case WMI_RATE_PREAMBLE_HE: 1444 arsta->txrate.mcs = mcs; 1445 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1446 arsta->txrate.he_dcm = dcm; 1447 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1448 tones = le16_to_cpu(user_rate->ru_end) - 1449 le16_to_cpu(user_rate->ru_start) + 1; 1450 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1451 arsta->txrate.he_ru_alloc = v; 1452 break; 1453 } 1454 1455 arsta->txrate.nss = nss; 1456 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1457 arsta->tx_duration += tx_duration; 1458 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1459 1460 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1461 * So skip peer stats update for mgmt packets. 1462 */ 1463 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1464 memset(peer_stats, 0, sizeof(*peer_stats)); 1465 peer_stats->succ_pkts = succ_pkts; 1466 peer_stats->succ_bytes = succ_bytes; 1467 peer_stats->is_ampdu = is_ampdu; 1468 peer_stats->duration = tx_duration; 1469 peer_stats->ba_fails = 1470 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1471 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1472 } 1473 1474 spin_unlock_bh(&ab->base_lock); 1475 rcu_read_unlock(); 1476 } 1477 1478 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1479 struct htt_ppdu_stats *ppdu_stats) 1480 { 1481 u8 user; 1482 1483 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1484 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1485 } 1486 1487 static 1488 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1489 u32 ppdu_id) 1490 { 1491 struct htt_ppdu_stats_info *ppdu_info; 1492 1493 lockdep_assert_held(&ar->data_lock); 1494 if (!list_empty(&ar->ppdu_stats_info)) { 1495 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1496 if (ppdu_info->ppdu_id == ppdu_id) 1497 return ppdu_info; 1498 } 1499 1500 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1501 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1502 typeof(*ppdu_info), list); 1503 list_del(&ppdu_info->list); 1504 ar->ppdu_stat_list_depth--; 1505 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1506 kfree(ppdu_info); 1507 } 1508 } 1509 1510 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1511 if (!ppdu_info) 1512 return NULL; 1513 1514 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1515 ar->ppdu_stat_list_depth++; 1516 1517 return ppdu_info; 1518 } 1519 1520 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1521 struct htt_ppdu_user_stats *usr_stats) 1522 { 1523 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1524 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1525 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1526 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1527 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1528 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1529 peer->ppdu_stats_delayba.resp_rate_flags = 1530 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1531 1532 peer->delayba_flag = true; 1533 } 1534 1535 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1536 struct htt_ppdu_user_stats *usr_stats) 1537 { 1538 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1539 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1540 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1541 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1542 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1543 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1544 usr_stats->rate.resp_rate_flags = 1545 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1546 1547 peer->delayba_flag = false; 1548 } 1549 1550 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1551 struct sk_buff *skb) 1552 { 1553 struct ath12k_htt_ppdu_stats_msg *msg; 1554 struct htt_ppdu_stats_info *ppdu_info; 1555 struct ath12k_peer *peer = NULL; 1556 struct htt_ppdu_user_stats *usr_stats = NULL; 1557 u32 peer_id = 0; 1558 struct ath12k *ar; 1559 int ret, i; 1560 u8 pdev_id; 1561 u32 ppdu_id, len; 1562 1563 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1564 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1565 if (len > (skb->len - struct_size(msg, data, 0))) { 1566 ath12k_warn(ab, 1567 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1568 len, skb->len); 1569 return -EINVAL; 1570 } 1571 1572 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1573 ppdu_id = le32_to_cpu(msg->ppdu_id); 1574 1575 rcu_read_lock(); 1576 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1577 if (!ar) { 1578 ret = -EINVAL; 1579 goto exit; 1580 } 1581 1582 spin_lock_bh(&ar->data_lock); 1583 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1584 if (!ppdu_info) { 1585 spin_unlock_bh(&ar->data_lock); 1586 ret = -EINVAL; 1587 goto exit; 1588 } 1589 1590 ppdu_info->ppdu_id = ppdu_id; 1591 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1592 ath12k_htt_tlv_ppdu_stats_parse, 1593 (void *)ppdu_info); 1594 if (ret) { 1595 spin_unlock_bh(&ar->data_lock); 1596 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1597 goto exit; 1598 } 1599 1600 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1601 spin_unlock_bh(&ar->data_lock); 1602 ath12k_warn(ab, 1603 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1604 ppdu_info->ppdu_stats.common.num_users, 1605 HTT_PPDU_STATS_MAX_USERS); 1606 ret = -EINVAL; 1607 goto exit; 1608 } 1609 1610 /* back up data rate tlv for all peers */ 1611 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1612 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1613 ppdu_info->delay_ba) { 1614 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1615 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1616 spin_lock_bh(&ab->base_lock); 1617 peer = ath12k_peer_find_by_id(ab, peer_id); 1618 if (!peer) { 1619 spin_unlock_bh(&ab->base_lock); 1620 continue; 1621 } 1622 1623 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1624 if (usr_stats->delay_ba) 1625 ath12k_copy_to_delay_stats(peer, usr_stats); 1626 spin_unlock_bh(&ab->base_lock); 1627 } 1628 } 1629 1630 /* restore all peers' data rate tlv to mu-bar tlv */ 1631 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1632 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1633 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1634 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1635 spin_lock_bh(&ab->base_lock); 1636 peer = ath12k_peer_find_by_id(ab, peer_id); 1637 if (!peer) { 1638 spin_unlock_bh(&ab->base_lock); 1639 continue; 1640 } 1641 1642 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1643 if (peer->delayba_flag) 1644 ath12k_copy_to_bar(peer, usr_stats); 1645 spin_unlock_bh(&ab->base_lock); 1646 } 1647 } 1648 1649 spin_unlock_bh(&ar->data_lock); 1650 1651 exit: 1652 rcu_read_unlock(); 1653 1654 return ret; 1655 } 1656 1657 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1658 struct sk_buff *skb) 1659 { 1660 struct ath12k_htt_mlo_offset_msg *msg; 1661 struct ath12k_pdev *pdev; 1662 struct ath12k *ar; 1663 u8 pdev_id; 1664 1665 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1666 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1667 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1668 1669 rcu_read_lock(); 1670 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1671 if (!ar) { 1672 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id); 1673 goto exit; 1674 } 1675 1676 spin_lock_bh(&ar->data_lock); 1677 pdev = ar->pdev; 1678 1679 pdev->timestamp.info = __le32_to_cpu(msg->info); 1680 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1681 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1682 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1683 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1684 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1685 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1686 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1687 1688 spin_unlock_bh(&ar->data_lock); 1689 exit: 1690 rcu_read_unlock(); 1691 } 1692 1693 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1694 struct sk_buff *skb) 1695 { 1696 struct ath12k_dp *dp = &ab->dp; 1697 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1698 enum htt_t2h_msg_type type; 1699 u16 peer_id; 1700 u8 vdev_id; 1701 u8 mac_addr[ETH_ALEN]; 1702 u16 peer_mac_h16; 1703 u16 ast_hash = 0; 1704 u16 hw_peer_id; 1705 1706 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1707 1708 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1709 1710 switch (type) { 1711 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1712 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1713 HTT_T2H_VERSION_CONF_MAJOR); 1714 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1715 HTT_T2H_VERSION_CONF_MINOR); 1716 complete(&dp->htt_tgt_version_received); 1717 break; 1718 /* TODO: remove unused peer map versions after testing */ 1719 case HTT_T2H_MSG_TYPE_PEER_MAP: 1720 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1721 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1722 peer_id = le32_get_bits(resp->peer_map_ev.info, 1723 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1724 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1725 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1726 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1727 peer_mac_h16, mac_addr); 1728 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1729 break; 1730 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1731 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1732 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1733 peer_id = le32_get_bits(resp->peer_map_ev.info, 1734 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1735 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1736 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1737 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1738 peer_mac_h16, mac_addr); 1739 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1740 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1741 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1742 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1743 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1744 hw_peer_id); 1745 break; 1746 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1747 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1748 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1749 peer_id = le32_get_bits(resp->peer_map_ev.info, 1750 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1751 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1752 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1753 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1754 peer_mac_h16, mac_addr); 1755 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1756 peer_id); 1757 break; 1758 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1759 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1760 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1761 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1762 ath12k_peer_unmap_event(ab, peer_id); 1763 break; 1764 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1765 ath12k_htt_pull_ppdu_stats(ab, skb); 1766 break; 1767 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1768 break; 1769 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 1770 ath12k_htt_mlo_offset_event_handler(ab, skb); 1771 break; 1772 default: 1773 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 1774 type); 1775 break; 1776 } 1777 1778 dev_kfree_skb_any(skb); 1779 } 1780 1781 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 1782 struct sk_buff_head *msdu_list, 1783 struct sk_buff *first, struct sk_buff *last, 1784 u8 l3pad_bytes, int msdu_len) 1785 { 1786 struct ath12k_base *ab = ar->ab; 1787 struct sk_buff *skb; 1788 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1789 int buf_first_hdr_len, buf_first_len; 1790 struct hal_rx_desc *ldesc; 1791 int space_extra, rem_len, buf_len; 1792 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 1793 1794 /* As the msdu is spread across multiple rx buffers, 1795 * find the offset to the start of msdu for computing 1796 * the length of the msdu in the first buffer. 1797 */ 1798 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1799 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1800 1801 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1802 skb_put(first, buf_first_hdr_len + msdu_len); 1803 skb_pull(first, buf_first_hdr_len); 1804 return 0; 1805 } 1806 1807 ldesc = (struct hal_rx_desc *)last->data; 1808 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 1809 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 1810 1811 /* MSDU spans over multiple buffers because the length of the MSDU 1812 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1813 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1814 */ 1815 skb_put(first, DP_RX_BUFFER_SIZE); 1816 skb_pull(first, buf_first_hdr_len); 1817 1818 /* When an MSDU spread over multiple buffers MSDU_END 1819 * tlvs are valid only in the last buffer. Copy those tlvs. 1820 */ 1821 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1822 1823 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1824 if (space_extra > 0 && 1825 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1826 /* Free up all buffers of the MSDU */ 1827 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1828 rxcb = ATH12K_SKB_RXCB(skb); 1829 if (!rxcb->is_continuation) { 1830 dev_kfree_skb_any(skb); 1831 break; 1832 } 1833 dev_kfree_skb_any(skb); 1834 } 1835 return -ENOMEM; 1836 } 1837 1838 rem_len = msdu_len - buf_first_len; 1839 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1840 rxcb = ATH12K_SKB_RXCB(skb); 1841 if (rxcb->is_continuation) 1842 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1843 else 1844 buf_len = rem_len; 1845 1846 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1847 WARN_ON_ONCE(1); 1848 dev_kfree_skb_any(skb); 1849 return -EINVAL; 1850 } 1851 1852 skb_put(skb, buf_len + hal_rx_desc_sz); 1853 skb_pull(skb, hal_rx_desc_sz); 1854 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1855 buf_len); 1856 dev_kfree_skb_any(skb); 1857 1858 rem_len -= buf_len; 1859 if (!rxcb->is_continuation) 1860 break; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1867 struct sk_buff *first) 1868 { 1869 struct sk_buff *skb; 1870 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1871 1872 if (!rxcb->is_continuation) 1873 return first; 1874 1875 skb_queue_walk(msdu_list, skb) { 1876 rxcb = ATH12K_SKB_RXCB(skb); 1877 if (!rxcb->is_continuation) 1878 return skb; 1879 } 1880 1881 return NULL; 1882 } 1883 1884 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu) 1885 { 1886 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1887 struct ath12k_base *ab = ar->ab; 1888 bool ip_csum_fail, l4_csum_fail; 1889 1890 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc); 1891 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc); 1892 1893 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1894 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1895 } 1896 1897 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, 1898 enum hal_encrypt_type enctype) 1899 { 1900 switch (enctype) { 1901 case HAL_ENCRYPT_TYPE_OPEN: 1902 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1903 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1904 return 0; 1905 case HAL_ENCRYPT_TYPE_CCMP_128: 1906 return IEEE80211_CCMP_MIC_LEN; 1907 case HAL_ENCRYPT_TYPE_CCMP_256: 1908 return IEEE80211_CCMP_256_MIC_LEN; 1909 case HAL_ENCRYPT_TYPE_GCMP_128: 1910 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1911 return IEEE80211_GCMP_MIC_LEN; 1912 case HAL_ENCRYPT_TYPE_WEP_40: 1913 case HAL_ENCRYPT_TYPE_WEP_104: 1914 case HAL_ENCRYPT_TYPE_WEP_128: 1915 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1916 case HAL_ENCRYPT_TYPE_WAPI: 1917 break; 1918 } 1919 1920 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1921 return 0; 1922 } 1923 1924 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 1925 enum hal_encrypt_type enctype) 1926 { 1927 switch (enctype) { 1928 case HAL_ENCRYPT_TYPE_OPEN: 1929 return 0; 1930 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1931 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1932 return IEEE80211_TKIP_IV_LEN; 1933 case HAL_ENCRYPT_TYPE_CCMP_128: 1934 return IEEE80211_CCMP_HDR_LEN; 1935 case HAL_ENCRYPT_TYPE_CCMP_256: 1936 return IEEE80211_CCMP_256_HDR_LEN; 1937 case HAL_ENCRYPT_TYPE_GCMP_128: 1938 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1939 return IEEE80211_GCMP_HDR_LEN; 1940 case HAL_ENCRYPT_TYPE_WEP_40: 1941 case HAL_ENCRYPT_TYPE_WEP_104: 1942 case HAL_ENCRYPT_TYPE_WEP_128: 1943 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1944 case HAL_ENCRYPT_TYPE_WAPI: 1945 break; 1946 } 1947 1948 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1949 return 0; 1950 } 1951 1952 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 1953 enum hal_encrypt_type enctype) 1954 { 1955 switch (enctype) { 1956 case HAL_ENCRYPT_TYPE_OPEN: 1957 case HAL_ENCRYPT_TYPE_CCMP_128: 1958 case HAL_ENCRYPT_TYPE_CCMP_256: 1959 case HAL_ENCRYPT_TYPE_GCMP_128: 1960 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1961 return 0; 1962 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1963 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1964 return IEEE80211_TKIP_ICV_LEN; 1965 case HAL_ENCRYPT_TYPE_WEP_40: 1966 case HAL_ENCRYPT_TYPE_WEP_104: 1967 case HAL_ENCRYPT_TYPE_WEP_128: 1968 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1969 case HAL_ENCRYPT_TYPE_WAPI: 1970 break; 1971 } 1972 1973 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1974 return 0; 1975 } 1976 1977 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 1978 struct sk_buff *msdu, 1979 enum hal_encrypt_type enctype, 1980 struct ieee80211_rx_status *status) 1981 { 1982 struct ath12k_base *ab = ar->ab; 1983 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1984 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1985 struct ieee80211_hdr *hdr; 1986 size_t hdr_len; 1987 u8 *crypto_hdr; 1988 u16 qos_ctl; 1989 1990 /* pull decapped header */ 1991 hdr = (struct ieee80211_hdr *)msdu->data; 1992 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1993 skb_pull(msdu, hdr_len); 1994 1995 /* Rebuild qos header */ 1996 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1997 1998 /* Reset the order bit as the HT_Control header is stripped */ 1999 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2000 2001 qos_ctl = rxcb->tid; 2002 2003 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 2004 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2005 2006 /* TODO: Add other QoS ctl fields when required */ 2007 2008 /* copy decap header before overwriting for reuse below */ 2009 memcpy(decap_hdr, hdr, hdr_len); 2010 2011 /* Rebuild crypto header for mac80211 use */ 2012 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2013 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 2014 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 2015 rxcb->rx_desc, crypto_hdr, 2016 enctype); 2017 } 2018 2019 memcpy(skb_push(msdu, 2020 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2021 IEEE80211_QOS_CTL_LEN); 2022 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2023 } 2024 2025 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2026 enum hal_encrypt_type enctype, 2027 struct ieee80211_rx_status *status, 2028 bool decrypted) 2029 { 2030 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2031 struct ieee80211_hdr *hdr; 2032 size_t hdr_len; 2033 size_t crypto_len; 2034 2035 if (!rxcb->is_first_msdu || 2036 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2037 WARN_ON_ONCE(1); 2038 return; 2039 } 2040 2041 skb_trim(msdu, msdu->len - FCS_LEN); 2042 2043 if (!decrypted) 2044 return; 2045 2046 hdr = (void *)msdu->data; 2047 2048 /* Tail */ 2049 if (status->flag & RX_FLAG_IV_STRIPPED) { 2050 skb_trim(msdu, msdu->len - 2051 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2052 2053 skb_trim(msdu, msdu->len - 2054 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2055 } else { 2056 /* MIC */ 2057 if (status->flag & RX_FLAG_MIC_STRIPPED) 2058 skb_trim(msdu, msdu->len - 2059 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2060 2061 /* ICV */ 2062 if (status->flag & RX_FLAG_ICV_STRIPPED) 2063 skb_trim(msdu, msdu->len - 2064 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2065 } 2066 2067 /* MMIC */ 2068 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2069 !ieee80211_has_morefrags(hdr->frame_control) && 2070 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2071 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2072 2073 /* Head */ 2074 if (status->flag & RX_FLAG_IV_STRIPPED) { 2075 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2076 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2077 2078 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2079 skb_pull(msdu, crypto_len); 2080 } 2081 } 2082 2083 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2084 struct sk_buff *msdu, 2085 struct ath12k_skb_rxcb *rxcb, 2086 struct ieee80211_rx_status *status, 2087 enum hal_encrypt_type enctype) 2088 { 2089 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2090 struct ath12k_base *ab = ar->ab; 2091 size_t hdr_len, crypto_len; 2092 struct ieee80211_hdr *hdr; 2093 u16 qos_ctl; 2094 __le16 fc; 2095 u8 *crypto_hdr; 2096 2097 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2098 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2099 crypto_hdr = skb_push(msdu, crypto_len); 2100 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2101 } 2102 2103 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc)); 2104 hdr_len = ieee80211_hdrlen(fc); 2105 skb_push(msdu, hdr_len); 2106 hdr = (struct ieee80211_hdr *)msdu->data; 2107 hdr->frame_control = fc; 2108 2109 /* Get wifi header from rx_desc */ 2110 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr); 2111 2112 if (rxcb->is_mcbc) 2113 status->flag &= ~RX_FLAG_PN_VALIDATED; 2114 2115 /* Add QOS header */ 2116 if (ieee80211_is_data_qos(hdr->frame_control)) { 2117 qos_ctl = rxcb->tid; 2118 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc)) 2119 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2120 2121 /* TODO: Add other QoS ctl fields when required */ 2122 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN), 2123 &qos_ctl, IEEE80211_QOS_CTL_LEN); 2124 } 2125 } 2126 2127 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2128 struct sk_buff *msdu, 2129 enum hal_encrypt_type enctype, 2130 struct ieee80211_rx_status *status) 2131 { 2132 struct ieee80211_hdr *hdr; 2133 struct ethhdr *eth; 2134 u8 da[ETH_ALEN]; 2135 u8 sa[ETH_ALEN]; 2136 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2137 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2138 2139 eth = (struct ethhdr *)msdu->data; 2140 ether_addr_copy(da, eth->h_dest); 2141 ether_addr_copy(sa, eth->h_source); 2142 rfc.snap_type = eth->h_proto; 2143 skb_pull(msdu, sizeof(*eth)); 2144 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2145 sizeof(rfc)); 2146 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2147 2148 /* original 802.11 header has a different DA and in 2149 * case of 4addr it may also have different SA 2150 */ 2151 hdr = (struct ieee80211_hdr *)msdu->data; 2152 ether_addr_copy(ieee80211_get_DA(hdr), da); 2153 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2154 } 2155 2156 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2157 struct hal_rx_desc *rx_desc, 2158 enum hal_encrypt_type enctype, 2159 struct ieee80211_rx_status *status, 2160 bool decrypted) 2161 { 2162 struct ath12k_base *ab = ar->ab; 2163 u8 decap; 2164 struct ethhdr *ehdr; 2165 2166 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2167 2168 switch (decap) { 2169 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2170 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2171 break; 2172 case DP_RX_DECAP_TYPE_RAW: 2173 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2174 decrypted); 2175 break; 2176 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2177 ehdr = (struct ethhdr *)msdu->data; 2178 2179 /* mac80211 allows fast path only for authorized STA */ 2180 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2181 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2182 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2183 break; 2184 } 2185 2186 /* PN for mcast packets will be validated in mac80211; 2187 * remove eth header and add 802.11 header. 2188 */ 2189 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2190 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2191 break; 2192 case DP_RX_DECAP_TYPE_8023: 2193 /* TODO: Handle undecap for these formats */ 2194 break; 2195 } 2196 } 2197 2198 struct ath12k_peer * 2199 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu) 2200 { 2201 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2202 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2203 struct ath12k_peer *peer = NULL; 2204 2205 lockdep_assert_held(&ab->base_lock); 2206 2207 if (rxcb->peer_id) 2208 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2209 2210 if (peer) 2211 return peer; 2212 2213 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2214 return NULL; 2215 2216 peer = ath12k_peer_find_by_addr(ab, 2217 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, 2218 rx_desc)); 2219 return peer; 2220 } 2221 2222 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2223 struct sk_buff *msdu, 2224 struct hal_rx_desc *rx_desc, 2225 struct ieee80211_rx_status *rx_status) 2226 { 2227 bool fill_crypto_hdr; 2228 struct ath12k_base *ab = ar->ab; 2229 struct ath12k_skb_rxcb *rxcb; 2230 enum hal_encrypt_type enctype; 2231 bool is_decrypted = false; 2232 struct ieee80211_hdr *hdr; 2233 struct ath12k_peer *peer; 2234 u32 err_bitmap; 2235 2236 /* PN for multicast packets will be checked in mac80211 */ 2237 rxcb = ATH12K_SKB_RXCB(msdu); 2238 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc); 2239 rxcb->is_mcbc = fill_crypto_hdr; 2240 2241 if (rxcb->is_mcbc) 2242 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc); 2243 2244 spin_lock_bh(&ar->ab->base_lock); 2245 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 2246 if (peer) { 2247 if (rxcb->is_mcbc) 2248 enctype = peer->sec_type_grp; 2249 else 2250 enctype = peer->sec_type; 2251 } else { 2252 enctype = HAL_ENCRYPT_TYPE_OPEN; 2253 } 2254 spin_unlock_bh(&ar->ab->base_lock); 2255 2256 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2257 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2258 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2259 2260 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2261 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2262 RX_FLAG_MMIC_ERROR | 2263 RX_FLAG_DECRYPTED | 2264 RX_FLAG_IV_STRIPPED | 2265 RX_FLAG_MMIC_STRIPPED); 2266 2267 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2268 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2269 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2270 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2271 2272 if (is_decrypted) { 2273 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2274 2275 if (fill_crypto_hdr) 2276 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2277 RX_FLAG_ICV_STRIPPED; 2278 else 2279 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2280 RX_FLAG_PN_VALIDATED; 2281 } 2282 2283 ath12k_dp_rx_h_csum_offload(ar, msdu); 2284 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2285 enctype, rx_status, is_decrypted); 2286 2287 if (!is_decrypted || fill_crypto_hdr) 2288 return; 2289 2290 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) != 2291 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2292 hdr = (void *)msdu->data; 2293 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2294 } 2295 } 2296 2297 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2298 struct ieee80211_rx_status *rx_status) 2299 { 2300 struct ath12k_base *ab = ar->ab; 2301 struct ieee80211_supported_band *sband; 2302 enum rx_msdu_start_pkt_type pkt_type; 2303 u8 bw; 2304 u8 rate_mcs, nss; 2305 u8 sgi; 2306 bool is_cck; 2307 2308 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2309 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2310 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2311 nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2312 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2313 2314 switch (pkt_type) { 2315 case RX_MSDU_START_PKT_TYPE_11A: 2316 case RX_MSDU_START_PKT_TYPE_11B: 2317 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2318 sband = &ar->mac.sbands[rx_status->band]; 2319 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2320 is_cck); 2321 break; 2322 case RX_MSDU_START_PKT_TYPE_11N: 2323 rx_status->encoding = RX_ENC_HT; 2324 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2325 ath12k_warn(ar->ab, 2326 "Received with invalid mcs in HT mode %d\n", 2327 rate_mcs); 2328 break; 2329 } 2330 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2331 if (sgi) 2332 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2333 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2334 break; 2335 case RX_MSDU_START_PKT_TYPE_11AC: 2336 rx_status->encoding = RX_ENC_VHT; 2337 rx_status->rate_idx = rate_mcs; 2338 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2339 ath12k_warn(ar->ab, 2340 "Received with invalid mcs in VHT mode %d\n", 2341 rate_mcs); 2342 break; 2343 } 2344 rx_status->nss = nss; 2345 if (sgi) 2346 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2347 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2348 break; 2349 case RX_MSDU_START_PKT_TYPE_11AX: 2350 rx_status->rate_idx = rate_mcs; 2351 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2352 ath12k_warn(ar->ab, 2353 "Received with invalid mcs in HE mode %d\n", 2354 rate_mcs); 2355 break; 2356 } 2357 rx_status->encoding = RX_ENC_HE; 2358 rx_status->nss = nss; 2359 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2360 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2361 break; 2362 } 2363 } 2364 2365 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2366 struct ieee80211_rx_status *rx_status) 2367 { 2368 struct ath12k_base *ab = ar->ab; 2369 u8 channel_num; 2370 u32 center_freq, meta_data; 2371 struct ieee80211_channel *channel; 2372 2373 rx_status->freq = 0; 2374 rx_status->rate_idx = 0; 2375 rx_status->nss = 0; 2376 rx_status->encoding = RX_ENC_LEGACY; 2377 rx_status->bw = RATE_INFO_BW_20; 2378 rx_status->enc_flags = 0; 2379 2380 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2381 2382 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2383 channel_num = meta_data; 2384 center_freq = meta_data >> 16; 2385 2386 if (center_freq >= 5935 && center_freq <= 7105) { 2387 rx_status->band = NL80211_BAND_6GHZ; 2388 } else if (channel_num >= 1 && channel_num <= 14) { 2389 rx_status->band = NL80211_BAND_2GHZ; 2390 } else if (channel_num >= 36 && channel_num <= 173) { 2391 rx_status->band = NL80211_BAND_5GHZ; 2392 } else { 2393 spin_lock_bh(&ar->data_lock); 2394 channel = ar->rx_channel; 2395 if (channel) { 2396 rx_status->band = channel->band; 2397 channel_num = 2398 ieee80211_frequency_to_channel(channel->center_freq); 2399 } 2400 spin_unlock_bh(&ar->data_lock); 2401 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2402 rx_desc, sizeof(*rx_desc)); 2403 } 2404 2405 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2406 rx_status->band); 2407 2408 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status); 2409 } 2410 2411 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2412 struct sk_buff *msdu, 2413 struct ieee80211_rx_status *status) 2414 { 2415 struct ath12k_base *ab = ar->ab; 2416 static const struct ieee80211_radiotap_he known = { 2417 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2418 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2419 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2420 }; 2421 struct ieee80211_radiotap_he *he; 2422 struct ieee80211_rx_status *rx_status; 2423 struct ieee80211_sta *pubsta; 2424 struct ath12k_peer *peer; 2425 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2426 u8 decap = DP_RX_DECAP_TYPE_RAW; 2427 bool is_mcbc = rxcb->is_mcbc; 2428 bool is_eapol = rxcb->is_eapol; 2429 2430 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) && 2431 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2432 he = skb_push(msdu, sizeof(known)); 2433 memcpy(he, &known, sizeof(known)); 2434 status->flag |= RX_FLAG_RADIOTAP_HE; 2435 } 2436 2437 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2438 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc); 2439 2440 spin_lock_bh(&ab->base_lock); 2441 peer = ath12k_dp_rx_h_find_peer(ab, msdu); 2442 2443 pubsta = peer ? peer->sta : NULL; 2444 2445 spin_unlock_bh(&ab->base_lock); 2446 2447 ath12k_dbg(ab, ATH12K_DBG_DATA, 2448 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2449 msdu, 2450 msdu->len, 2451 peer ? peer->addr : NULL, 2452 rxcb->tid, 2453 is_mcbc ? "mcast" : "ucast", 2454 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2455 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2456 (status->encoding == RX_ENC_HT) ? "ht" : "", 2457 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2458 (status->encoding == RX_ENC_HE) ? "he" : "", 2459 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2460 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2461 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2462 (status->bw == RATE_INFO_BW_320) ? "320" : "", 2463 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2464 status->rate_idx, 2465 status->nss, 2466 status->freq, 2467 status->band, status->flag, 2468 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2469 !!(status->flag & RX_FLAG_MMIC_ERROR), 2470 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2471 2472 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2473 msdu->data, msdu->len); 2474 2475 rx_status = IEEE80211_SKB_RXCB(msdu); 2476 *rx_status = *status; 2477 2478 /* TODO: trace rx packet */ 2479 2480 /* PN for multicast packets are not validate in HW, 2481 * so skip 802.3 rx path 2482 * Also, fast_rx expects the STA to be authorized, hence 2483 * eapol packets are sent in slow path. 2484 */ 2485 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2486 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2487 rx_status->flag |= RX_FLAG_8023; 2488 2489 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 2490 } 2491 2492 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2493 struct sk_buff *msdu, 2494 struct sk_buff_head *msdu_list, 2495 struct ieee80211_rx_status *rx_status) 2496 { 2497 struct ath12k_base *ab = ar->ab; 2498 struct hal_rx_desc *rx_desc, *lrx_desc; 2499 struct ath12k_skb_rxcb *rxcb; 2500 struct sk_buff *last_buf; 2501 u8 l3_pad_bytes; 2502 u16 msdu_len; 2503 int ret; 2504 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2505 2506 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2507 if (!last_buf) { 2508 ath12k_warn(ab, 2509 "No valid Rx buffer to access MSDU_END tlv\n"); 2510 ret = -EIO; 2511 goto free_out; 2512 } 2513 2514 rx_desc = (struct hal_rx_desc *)msdu->data; 2515 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2516 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2517 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2518 ret = -EIO; 2519 goto free_out; 2520 } 2521 2522 rxcb = ATH12K_SKB_RXCB(msdu); 2523 rxcb->rx_desc = rx_desc; 2524 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2525 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2526 2527 if (rxcb->is_frag) { 2528 skb_pull(msdu, hal_rx_desc_sz); 2529 } else if (!rxcb->is_continuation) { 2530 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2531 ret = -EINVAL; 2532 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2533 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2534 sizeof(*rx_desc)); 2535 goto free_out; 2536 } 2537 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2538 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2539 } else { 2540 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2541 msdu, last_buf, 2542 l3_pad_bytes, msdu_len); 2543 if (ret) { 2544 ath12k_warn(ab, 2545 "failed to coalesce msdu rx buffer%d\n", ret); 2546 goto free_out; 2547 } 2548 } 2549 2550 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2551 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2552 2553 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2554 2555 return 0; 2556 2557 free_out: 2558 return ret; 2559 } 2560 2561 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2562 struct napi_struct *napi, 2563 struct sk_buff_head *msdu_list, 2564 int ring_id) 2565 { 2566 struct ieee80211_rx_status rx_status = {0}; 2567 struct ath12k_skb_rxcb *rxcb; 2568 struct sk_buff *msdu; 2569 struct ath12k *ar; 2570 u8 mac_id, pdev_id; 2571 int ret; 2572 2573 if (skb_queue_empty(msdu_list)) 2574 return; 2575 2576 rcu_read_lock(); 2577 2578 while ((msdu = __skb_dequeue(msdu_list))) { 2579 rxcb = ATH12K_SKB_RXCB(msdu); 2580 mac_id = rxcb->mac_id; 2581 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 2582 ar = ab->pdevs[pdev_id].ar; 2583 if (!rcu_dereference(ab->pdevs_active[pdev_id])) { 2584 dev_kfree_skb_any(msdu); 2585 continue; 2586 } 2587 2588 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 2589 dev_kfree_skb_any(msdu); 2590 continue; 2591 } 2592 2593 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2594 if (ret) { 2595 ath12k_dbg(ab, ATH12K_DBG_DATA, 2596 "Unable to process msdu %d", ret); 2597 dev_kfree_skb_any(msdu); 2598 continue; 2599 } 2600 2601 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2602 } 2603 2604 rcu_read_unlock(); 2605 } 2606 2607 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2608 struct napi_struct *napi, int budget) 2609 { 2610 LIST_HEAD(rx_desc_used_list); 2611 struct ath12k_rx_desc_info *desc_info; 2612 struct ath12k_dp *dp = &ab->dp; 2613 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2614 struct hal_reo_dest_ring *desc; 2615 int num_buffs_reaped = 0; 2616 struct sk_buff_head msdu_list; 2617 struct ath12k_skb_rxcb *rxcb; 2618 int total_msdu_reaped = 0; 2619 struct hal_srng *srng; 2620 struct sk_buff *msdu; 2621 bool done = false; 2622 int mac_id; 2623 u64 desc_va; 2624 2625 __skb_queue_head_init(&msdu_list); 2626 2627 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2628 2629 spin_lock_bh(&srng->lock); 2630 2631 try_again: 2632 ath12k_hal_srng_access_begin(ab, srng); 2633 2634 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2635 enum hal_reo_dest_ring_push_reason push_reason; 2636 u32 cookie; 2637 2638 cookie = le32_get_bits(desc->buf_addr_info.info1, 2639 BUFFER_ADDR_INFO1_SW_COOKIE); 2640 2641 mac_id = le32_get_bits(desc->info0, 2642 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2643 2644 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2645 le32_to_cpu(desc->buf_va_lo)); 2646 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2647 2648 /* retry manual desc retrieval */ 2649 if (!desc_info) { 2650 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 2651 if (!desc_info) { 2652 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 2653 continue; 2654 } 2655 } 2656 2657 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 2658 ath12k_warn(ab, "Check HW CC implementation"); 2659 2660 msdu = desc_info->skb; 2661 desc_info->skb = NULL; 2662 2663 list_add_tail(&desc_info->list, &rx_desc_used_list); 2664 2665 rxcb = ATH12K_SKB_RXCB(msdu); 2666 dma_unmap_single(ab->dev, rxcb->paddr, 2667 msdu->len + skb_tailroom(msdu), 2668 DMA_FROM_DEVICE); 2669 2670 num_buffs_reaped++; 2671 2672 push_reason = le32_get_bits(desc->info0, 2673 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 2674 if (push_reason != 2675 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2676 dev_kfree_skb_any(msdu); 2677 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2678 continue; 2679 } 2680 2681 rxcb->is_first_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2682 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2683 rxcb->is_last_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2684 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2685 rxcb->is_continuation = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2686 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2687 rxcb->mac_id = mac_id; 2688 rxcb->peer_id = le32_get_bits(desc->rx_mpdu_info.peer_meta_data, 2689 RX_MPDU_DESC_META_DATA_PEER_ID); 2690 rxcb->tid = le32_get_bits(desc->rx_mpdu_info.info0, 2691 RX_MPDU_DESC_INFO0_TID); 2692 2693 __skb_queue_tail(&msdu_list, msdu); 2694 2695 if (!rxcb->is_continuation) { 2696 total_msdu_reaped++; 2697 done = true; 2698 } else { 2699 done = false; 2700 } 2701 2702 if (total_msdu_reaped >= budget) 2703 break; 2704 } 2705 2706 /* Hw might have updated the head pointer after we cached it. 2707 * In this case, even though there are entries in the ring we'll 2708 * get rx_desc NULL. Give the read another try with updated cached 2709 * head pointer so that we can reap complete MPDU in the current 2710 * rx processing. 2711 */ 2712 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 2713 ath12k_hal_srng_access_end(ab, srng); 2714 goto try_again; 2715 } 2716 2717 ath12k_hal_srng_access_end(ab, srng); 2718 2719 spin_unlock_bh(&srng->lock); 2720 2721 if (!total_msdu_reaped) 2722 goto exit; 2723 2724 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 2725 num_buffs_reaped); 2726 2727 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2728 ring_id); 2729 2730 exit: 2731 return total_msdu_reaped; 2732 } 2733 2734 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 2735 { 2736 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2737 2738 spin_lock_bh(&rx_tid->ab->base_lock); 2739 if (rx_tid->last_frag_no && 2740 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2741 spin_unlock_bh(&rx_tid->ab->base_lock); 2742 return; 2743 } 2744 ath12k_dp_rx_frags_cleanup(rx_tid, true); 2745 spin_unlock_bh(&rx_tid->ab->base_lock); 2746 } 2747 2748 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 2749 { 2750 struct ath12k_base *ab = ar->ab; 2751 struct crypto_shash *tfm; 2752 struct ath12k_peer *peer; 2753 struct ath12k_dp_rx_tid *rx_tid; 2754 int i; 2755 2756 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2757 if (IS_ERR(tfm)) 2758 return PTR_ERR(tfm); 2759 2760 spin_lock_bh(&ab->base_lock); 2761 2762 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 2763 if (!peer) { 2764 spin_unlock_bh(&ab->base_lock); 2765 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 2766 return -ENOENT; 2767 } 2768 2769 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 2770 rx_tid = &peer->rx_tid[i]; 2771 rx_tid->ab = ab; 2772 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 2773 skb_queue_head_init(&rx_tid->rx_frags); 2774 } 2775 2776 peer->tfm_mmic = tfm; 2777 peer->dp_setup_done = true; 2778 spin_unlock_bh(&ab->base_lock); 2779 2780 return 0; 2781 } 2782 2783 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 2784 struct ieee80211_hdr *hdr, u8 *data, 2785 size_t data_len, u8 *mic) 2786 { 2787 SHASH_DESC_ON_STACK(desc, tfm); 2788 u8 mic_hdr[16] = {0}; 2789 u8 tid = 0; 2790 int ret; 2791 2792 if (!tfm) 2793 return -EINVAL; 2794 2795 desc->tfm = tfm; 2796 2797 ret = crypto_shash_setkey(tfm, key, 8); 2798 if (ret) 2799 goto out; 2800 2801 ret = crypto_shash_init(desc); 2802 if (ret) 2803 goto out; 2804 2805 /* TKIP MIC header */ 2806 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 2807 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 2808 if (ieee80211_is_data_qos(hdr->frame_control)) 2809 tid = ieee80211_get_tid(hdr); 2810 mic_hdr[12] = tid; 2811 2812 ret = crypto_shash_update(desc, mic_hdr, 16); 2813 if (ret) 2814 goto out; 2815 ret = crypto_shash_update(desc, data, data_len); 2816 if (ret) 2817 goto out; 2818 ret = crypto_shash_final(desc, mic); 2819 out: 2820 shash_desc_zero(desc); 2821 return ret; 2822 } 2823 2824 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 2825 struct sk_buff *msdu) 2826 { 2827 struct ath12k_base *ab = ar->ab; 2828 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 2829 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 2830 struct ieee80211_key_conf *key_conf; 2831 struct ieee80211_hdr *hdr; 2832 u8 mic[IEEE80211_CCMP_MIC_LEN]; 2833 int head_len, tail_len, ret; 2834 size_t data_len; 2835 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2836 u8 *key, *data; 2837 u8 key_idx; 2838 2839 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 2840 return 0; 2841 2842 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2843 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2844 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 2845 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 2846 2847 if (!is_multicast_ether_addr(hdr->addr1)) 2848 key_idx = peer->ucast_keyidx; 2849 else 2850 key_idx = peer->mcast_keyidx; 2851 2852 key_conf = peer->keys[key_idx]; 2853 2854 data = msdu->data + head_len; 2855 data_len = msdu->len - head_len - tail_len; 2856 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 2857 2858 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 2859 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 2860 goto mic_fail; 2861 2862 return 0; 2863 2864 mic_fail: 2865 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 2866 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 2867 2868 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 2869 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 2870 skb_pull(msdu, hal_rx_desc_sz); 2871 2872 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 2873 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2874 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 2875 ieee80211_rx(ath12k_ar_to_hw(ar), msdu); 2876 return -EINVAL; 2877 } 2878 2879 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 2880 enum hal_encrypt_type enctype, u32 flags) 2881 { 2882 struct ieee80211_hdr *hdr; 2883 size_t hdr_len; 2884 size_t crypto_len; 2885 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2886 2887 if (!flags) 2888 return; 2889 2890 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2891 2892 if (flags & RX_FLAG_MIC_STRIPPED) 2893 skb_trim(msdu, msdu->len - 2894 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2895 2896 if (flags & RX_FLAG_ICV_STRIPPED) 2897 skb_trim(msdu, msdu->len - 2898 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2899 2900 if (flags & RX_FLAG_IV_STRIPPED) { 2901 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2902 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2903 2904 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 2905 msdu->data + hal_rx_desc_sz, hdr_len); 2906 skb_pull(msdu, crypto_len); 2907 } 2908 } 2909 2910 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 2911 struct ath12k_peer *peer, 2912 struct ath12k_dp_rx_tid *rx_tid, 2913 struct sk_buff **defrag_skb) 2914 { 2915 struct ath12k_base *ab = ar->ab; 2916 struct hal_rx_desc *rx_desc; 2917 struct sk_buff *skb, *first_frag, *last_frag; 2918 struct ieee80211_hdr *hdr; 2919 enum hal_encrypt_type enctype; 2920 bool is_decrypted = false; 2921 int msdu_len = 0; 2922 int extra_space; 2923 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 2924 2925 first_frag = skb_peek(&rx_tid->rx_frags); 2926 last_frag = skb_peek_tail(&rx_tid->rx_frags); 2927 2928 skb_queue_walk(&rx_tid->rx_frags, skb) { 2929 flags = 0; 2930 rx_desc = (struct hal_rx_desc *)skb->data; 2931 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 2932 2933 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 2934 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 2935 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 2936 rx_desc); 2937 2938 if (is_decrypted) { 2939 if (skb != first_frag) 2940 flags |= RX_FLAG_IV_STRIPPED; 2941 if (skb != last_frag) 2942 flags |= RX_FLAG_ICV_STRIPPED | 2943 RX_FLAG_MIC_STRIPPED; 2944 } 2945 2946 /* RX fragments are always raw packets */ 2947 if (skb != last_frag) 2948 skb_trim(skb, skb->len - FCS_LEN); 2949 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 2950 2951 if (skb != first_frag) 2952 skb_pull(skb, hal_rx_desc_sz + 2953 ieee80211_hdrlen(hdr->frame_control)); 2954 msdu_len += skb->len; 2955 } 2956 2957 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 2958 if (extra_space > 0 && 2959 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 2960 return -ENOMEM; 2961 2962 __skb_unlink(first_frag, &rx_tid->rx_frags); 2963 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 2964 skb_put_data(first_frag, skb->data, skb->len); 2965 dev_kfree_skb_any(skb); 2966 } 2967 2968 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 2969 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 2970 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 2971 2972 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 2973 first_frag = NULL; 2974 2975 *defrag_skb = first_frag; 2976 return 0; 2977 } 2978 2979 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 2980 struct ath12k_dp_rx_tid *rx_tid, 2981 struct sk_buff *defrag_skb) 2982 { 2983 struct ath12k_base *ab = ar->ab; 2984 struct ath12k_dp *dp = &ab->dp; 2985 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 2986 struct hal_reo_entrance_ring *reo_ent_ring; 2987 struct hal_reo_dest_ring *reo_dest_ring; 2988 struct dp_link_desc_bank *link_desc_banks; 2989 struct hal_rx_msdu_link *msdu_link; 2990 struct hal_rx_msdu_details *msdu0; 2991 struct hal_srng *srng; 2992 dma_addr_t link_paddr, buf_paddr; 2993 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 2994 u32 cookie, hal_rx_desc_sz, dest_ring_info0; 2995 int ret; 2996 struct ath12k_rx_desc_info *desc_info; 2997 u8 dst_ind; 2998 2999 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3000 link_desc_banks = dp->link_desc_banks; 3001 reo_dest_ring = rx_tid->dst_ring_desc; 3002 3003 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 3004 &link_paddr, &cookie); 3005 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 3006 3007 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3008 (link_paddr - link_desc_banks[desc_bank].paddr)); 3009 msdu0 = &msdu_link->msdu_link[0]; 3010 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 3011 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 3012 3013 memset(msdu0, 0, sizeof(*msdu0)); 3014 3015 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 3016 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 3017 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3018 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3019 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3020 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3021 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3022 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3023 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3024 3025 /* change msdu len in hal rx desc */ 3026 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3027 3028 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3029 defrag_skb->len + skb_tailroom(defrag_skb), 3030 DMA_FROM_DEVICE); 3031 if (dma_mapping_error(ab->dev, buf_paddr)) 3032 return -ENOMEM; 3033 3034 spin_lock_bh(&dp->rx_desc_lock); 3035 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3036 struct ath12k_rx_desc_info, 3037 list); 3038 if (!desc_info) { 3039 spin_unlock_bh(&dp->rx_desc_lock); 3040 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3041 ret = -ENOMEM; 3042 goto err_unmap_dma; 3043 } 3044 3045 desc_info->skb = defrag_skb; 3046 desc_info->in_use = true; 3047 3048 list_del(&desc_info->list); 3049 spin_unlock_bh(&dp->rx_desc_lock); 3050 3051 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3052 3053 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3054 desc_info->cookie, 3055 HAL_RX_BUF_RBM_SW3_BM); 3056 3057 /* Fill mpdu details into reo entrance ring */ 3058 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3059 3060 spin_lock_bh(&srng->lock); 3061 ath12k_hal_srng_access_begin(ab, srng); 3062 3063 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3064 if (!reo_ent_ring) { 3065 ath12k_hal_srng_access_end(ab, srng); 3066 spin_unlock_bh(&srng->lock); 3067 ret = -ENOSPC; 3068 goto err_free_desc; 3069 } 3070 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3071 3072 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3073 cookie, 3074 HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST); 3075 3076 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3077 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3078 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3079 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3080 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3081 3082 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3083 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3084 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3085 3086 /* Firmware expects physical address to be filled in queue_addr_lo in 3087 * the MLO scenario and in case of non MLO peer meta data needs to be 3088 * filled. 3089 * TODO: Need to handle for MLO scenario. 3090 */ 3091 reo_ent_ring->queue_addr_lo = reo_dest_ring->rx_mpdu_info.peer_meta_data; 3092 reo_ent_ring->info0 = le32_encode_bits(dst_ind, 3093 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3094 3095 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3096 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3097 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3098 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3099 reo_ent_ring->info2 = 3100 cpu_to_le32(u32_get_bits(dest_ring_info0, 3101 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3102 3103 ath12k_hal_srng_access_end(ab, srng); 3104 spin_unlock_bh(&srng->lock); 3105 3106 return 0; 3107 3108 err_free_desc: 3109 spin_lock_bh(&dp->rx_desc_lock); 3110 desc_info->in_use = false; 3111 desc_info->skb = NULL; 3112 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3113 spin_unlock_bh(&dp->rx_desc_lock); 3114 err_unmap_dma: 3115 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3116 DMA_FROM_DEVICE); 3117 return ret; 3118 } 3119 3120 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3121 struct sk_buff *a, struct sk_buff *b) 3122 { 3123 int frag1, frag2; 3124 3125 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3126 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3127 3128 return frag1 - frag2; 3129 } 3130 3131 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3132 struct sk_buff_head *frag_list, 3133 struct sk_buff *cur_frag) 3134 { 3135 struct sk_buff *skb; 3136 int cmp; 3137 3138 skb_queue_walk(frag_list, skb) { 3139 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3140 if (cmp < 0) 3141 continue; 3142 __skb_queue_before(frag_list, skb, cur_frag); 3143 return; 3144 } 3145 __skb_queue_tail(frag_list, cur_frag); 3146 } 3147 3148 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3149 { 3150 struct ieee80211_hdr *hdr; 3151 u64 pn = 0; 3152 u8 *ehdr; 3153 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3154 3155 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3156 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3157 3158 pn = ehdr[0]; 3159 pn |= (u64)ehdr[1] << 8; 3160 pn |= (u64)ehdr[4] << 16; 3161 pn |= (u64)ehdr[5] << 24; 3162 pn |= (u64)ehdr[6] << 32; 3163 pn |= (u64)ehdr[7] << 40; 3164 3165 return pn; 3166 } 3167 3168 static bool 3169 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3170 { 3171 struct ath12k_base *ab = ar->ab; 3172 enum hal_encrypt_type encrypt_type; 3173 struct sk_buff *first_frag, *skb; 3174 struct hal_rx_desc *desc; 3175 u64 last_pn; 3176 u64 cur_pn; 3177 3178 first_frag = skb_peek(&rx_tid->rx_frags); 3179 desc = (struct hal_rx_desc *)first_frag->data; 3180 3181 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3182 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3183 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3184 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3185 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3186 return true; 3187 3188 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3189 skb_queue_walk(&rx_tid->rx_frags, skb) { 3190 if (skb == first_frag) 3191 continue; 3192 3193 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3194 if (cur_pn != last_pn + 1) 3195 return false; 3196 last_pn = cur_pn; 3197 } 3198 return true; 3199 } 3200 3201 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3202 struct sk_buff *msdu, 3203 struct hal_reo_dest_ring *ring_desc) 3204 { 3205 struct ath12k_base *ab = ar->ab; 3206 struct hal_rx_desc *rx_desc; 3207 struct ath12k_peer *peer; 3208 struct ath12k_dp_rx_tid *rx_tid; 3209 struct sk_buff *defrag_skb = NULL; 3210 u32 peer_id; 3211 u16 seqno, frag_no; 3212 u8 tid; 3213 int ret = 0; 3214 bool more_frags; 3215 3216 rx_desc = (struct hal_rx_desc *)msdu->data; 3217 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3218 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3219 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3220 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3221 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3222 3223 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3224 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3225 tid > IEEE80211_NUM_TIDS) 3226 return -EINVAL; 3227 3228 /* received unfragmented packet in reo 3229 * exception ring, this shouldn't happen 3230 * as these packets typically come from 3231 * reo2sw srngs. 3232 */ 3233 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3234 return -EINVAL; 3235 3236 spin_lock_bh(&ab->base_lock); 3237 peer = ath12k_peer_find_by_id(ab, peer_id); 3238 if (!peer) { 3239 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3240 peer_id); 3241 ret = -ENOENT; 3242 goto out_unlock; 3243 } 3244 3245 if (!peer->dp_setup_done) { 3246 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3247 peer->addr, peer_id); 3248 ret = -ENOENT; 3249 goto out_unlock; 3250 } 3251 3252 rx_tid = &peer->rx_tid[tid]; 3253 3254 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3255 skb_queue_empty(&rx_tid->rx_frags)) { 3256 /* Flush stored fragments and start a new sequence */ 3257 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3258 rx_tid->cur_sn = seqno; 3259 } 3260 3261 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3262 /* Fragment already present */ 3263 ret = -EINVAL; 3264 goto out_unlock; 3265 } 3266 3267 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3268 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3269 else 3270 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3271 3272 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3273 if (!more_frags) 3274 rx_tid->last_frag_no = frag_no; 3275 3276 if (frag_no == 0) { 3277 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3278 sizeof(*rx_tid->dst_ring_desc), 3279 GFP_ATOMIC); 3280 if (!rx_tid->dst_ring_desc) { 3281 ret = -ENOMEM; 3282 goto out_unlock; 3283 } 3284 } else { 3285 ath12k_dp_rx_link_desc_return(ab, ring_desc, 3286 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3287 } 3288 3289 if (!rx_tid->last_frag_no || 3290 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3291 mod_timer(&rx_tid->frag_timer, jiffies + 3292 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3293 goto out_unlock; 3294 } 3295 3296 spin_unlock_bh(&ab->base_lock); 3297 del_timer_sync(&rx_tid->frag_timer); 3298 spin_lock_bh(&ab->base_lock); 3299 3300 peer = ath12k_peer_find_by_id(ab, peer_id); 3301 if (!peer) 3302 goto err_frags_cleanup; 3303 3304 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3305 goto err_frags_cleanup; 3306 3307 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3308 goto err_frags_cleanup; 3309 3310 if (!defrag_skb) 3311 goto err_frags_cleanup; 3312 3313 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3314 goto err_frags_cleanup; 3315 3316 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3317 goto out_unlock; 3318 3319 err_frags_cleanup: 3320 dev_kfree_skb_any(defrag_skb); 3321 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3322 out_unlock: 3323 spin_unlock_bh(&ab->base_lock); 3324 return ret; 3325 } 3326 3327 static int 3328 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3329 struct list_head *used_list, 3330 bool drop, u32 cookie) 3331 { 3332 struct ath12k_base *ab = ar->ab; 3333 struct sk_buff *msdu; 3334 struct ath12k_skb_rxcb *rxcb; 3335 struct hal_rx_desc *rx_desc; 3336 u16 msdu_len; 3337 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3338 struct ath12k_rx_desc_info *desc_info; 3339 u64 desc_va; 3340 3341 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3342 le32_to_cpu(desc->buf_va_lo)); 3343 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3344 3345 /* retry manual desc retrieval */ 3346 if (!desc_info) { 3347 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3348 if (!desc_info) { 3349 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 3350 return -EINVAL; 3351 } 3352 } 3353 3354 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3355 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3356 3357 msdu = desc_info->skb; 3358 desc_info->skb = NULL; 3359 3360 list_add_tail(&desc_info->list, used_list); 3361 3362 rxcb = ATH12K_SKB_RXCB(msdu); 3363 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3364 msdu->len + skb_tailroom(msdu), 3365 DMA_FROM_DEVICE); 3366 3367 if (drop) { 3368 dev_kfree_skb_any(msdu); 3369 return 0; 3370 } 3371 3372 rcu_read_lock(); 3373 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3374 dev_kfree_skb_any(msdu); 3375 goto exit; 3376 } 3377 3378 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3379 dev_kfree_skb_any(msdu); 3380 goto exit; 3381 } 3382 3383 rx_desc = (struct hal_rx_desc *)msdu->data; 3384 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3385 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3386 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3387 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3388 sizeof(*rx_desc)); 3389 dev_kfree_skb_any(msdu); 3390 goto exit; 3391 } 3392 3393 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3394 3395 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3396 dev_kfree_skb_any(msdu); 3397 ath12k_dp_rx_link_desc_return(ar->ab, desc, 3398 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3399 } 3400 exit: 3401 rcu_read_unlock(); 3402 return 0; 3403 } 3404 3405 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3406 int budget) 3407 { 3408 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3409 struct dp_link_desc_bank *link_desc_banks; 3410 enum hal_rx_buf_return_buf_manager rbm; 3411 struct hal_rx_msdu_link *link_desc_va; 3412 int tot_n_bufs_reaped, quota, ret, i; 3413 struct hal_reo_dest_ring *reo_desc; 3414 struct dp_rxdma_ring *rx_ring; 3415 struct dp_srng *reo_except; 3416 LIST_HEAD(rx_desc_used_list); 3417 u32 desc_bank, num_msdus; 3418 struct hal_srng *srng; 3419 struct ath12k_dp *dp; 3420 int mac_id; 3421 struct ath12k *ar; 3422 dma_addr_t paddr; 3423 bool is_frag; 3424 bool drop = false; 3425 int pdev_id; 3426 3427 tot_n_bufs_reaped = 0; 3428 quota = budget; 3429 3430 dp = &ab->dp; 3431 reo_except = &dp->reo_except_ring; 3432 link_desc_banks = dp->link_desc_banks; 3433 3434 srng = &ab->hal.srng_list[reo_except->ring_id]; 3435 3436 spin_lock_bh(&srng->lock); 3437 3438 ath12k_hal_srng_access_begin(ab, srng); 3439 3440 while (budget && 3441 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3442 ab->soc_stats.err_ring_pkts++; 3443 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3444 &desc_bank); 3445 if (ret) { 3446 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3447 ret); 3448 continue; 3449 } 3450 link_desc_va = link_desc_banks[desc_bank].vaddr + 3451 (paddr - link_desc_banks[desc_bank].paddr); 3452 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3453 &rbm); 3454 if (rbm != HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST && 3455 rbm != HAL_RX_BUF_RBM_SW3_BM && 3456 rbm != ab->hw_params->hal_params->rx_buf_rbm) { 3457 ab->soc_stats.invalid_rbm++; 3458 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3459 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3460 HAL_WBM_REL_BM_ACT_REL_MSDU); 3461 continue; 3462 } 3463 3464 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3465 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3466 3467 /* Process only rx fragments with one msdu per link desc below, and drop 3468 * msdu's indicated due to error reasons. 3469 */ 3470 if (!is_frag || num_msdus > 1) { 3471 drop = true; 3472 /* Return the link desc back to wbm idle list */ 3473 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3474 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3475 } 3476 3477 for (i = 0; i < num_msdus; i++) { 3478 mac_id = le32_get_bits(reo_desc->info0, 3479 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3480 3481 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3482 ar = ab->pdevs[pdev_id].ar; 3483 3484 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, 3485 &rx_desc_used_list, 3486 drop, 3487 msdu_cookies[i])) 3488 tot_n_bufs_reaped++; 3489 } 3490 3491 if (tot_n_bufs_reaped >= quota) { 3492 tot_n_bufs_reaped = quota; 3493 goto exit; 3494 } 3495 3496 budget = quota - tot_n_bufs_reaped; 3497 } 3498 3499 exit: 3500 ath12k_hal_srng_access_end(ab, srng); 3501 3502 spin_unlock_bh(&srng->lock); 3503 3504 rx_ring = &dp->rx_refill_buf_ring; 3505 3506 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3507 tot_n_bufs_reaped); 3508 3509 return tot_n_bufs_reaped; 3510 } 3511 3512 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3513 int msdu_len, 3514 struct sk_buff_head *msdu_list) 3515 { 3516 struct sk_buff *skb, *tmp; 3517 struct ath12k_skb_rxcb *rxcb; 3518 int n_buffs; 3519 3520 n_buffs = DIV_ROUND_UP(msdu_len, 3521 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz)); 3522 3523 skb_queue_walk_safe(msdu_list, skb, tmp) { 3524 rxcb = ATH12K_SKB_RXCB(skb); 3525 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3526 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3527 if (!n_buffs) 3528 break; 3529 __skb_unlink(skb, msdu_list); 3530 dev_kfree_skb_any(skb); 3531 n_buffs--; 3532 } 3533 } 3534 } 3535 3536 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 3537 struct ieee80211_rx_status *status, 3538 struct sk_buff_head *msdu_list) 3539 { 3540 struct ath12k_base *ab = ar->ab; 3541 u16 msdu_len; 3542 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3543 u8 l3pad_bytes; 3544 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3545 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3546 3547 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3548 3549 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3550 /* First buffer will be freed by the caller, so deduct it's length */ 3551 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3552 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3553 return -EINVAL; 3554 } 3555 3556 /* Even after cleaning up the sg buffers in the msdu list with above check 3557 * any msdu received with continuation flag needs to be dropped as invalid. 3558 * This protects against some random err frame with continuation flag. 3559 */ 3560 if (rxcb->is_continuation) 3561 return -EINVAL; 3562 3563 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 3564 ath12k_warn(ar->ab, 3565 "msdu_done bit not set in null_q_des processing\n"); 3566 __skb_queue_purge(msdu_list); 3567 return -EIO; 3568 } 3569 3570 /* Handle NULL queue descriptor violations arising out a missing 3571 * REO queue for a given peer or a given TID. This typically 3572 * may happen if a packet is received on a QOS enabled TID before the 3573 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3574 * it may also happen for MC/BC frames if they are not routed to the 3575 * non-QOS TID queue, in the absence of any other default TID queue. 3576 * This error can show up both in a REO destination or WBM release ring. 3577 */ 3578 3579 if (rxcb->is_frag) { 3580 skb_pull(msdu, hal_rx_desc_sz); 3581 } else { 3582 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3583 3584 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3585 return -EINVAL; 3586 3587 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3588 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3589 } 3590 ath12k_dp_rx_h_ppdu(ar, desc, status); 3591 3592 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status); 3593 3594 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc); 3595 3596 /* Please note that caller will having the access to msdu and completing 3597 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3598 */ 3599 3600 return 0; 3601 } 3602 3603 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 3604 struct ieee80211_rx_status *status, 3605 struct sk_buff_head *msdu_list) 3606 { 3607 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3608 bool drop = false; 3609 3610 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3611 3612 switch (rxcb->err_code) { 3613 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3614 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3615 drop = true; 3616 break; 3617 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3618 /* TODO: Do not drop PN failed packets in the driver; 3619 * instead, it is good to drop such packets in mac80211 3620 * after incrementing the replay counters. 3621 */ 3622 fallthrough; 3623 default: 3624 /* TODO: Review other errors and process them to mac80211 3625 * as appropriate. 3626 */ 3627 drop = true; 3628 break; 3629 } 3630 3631 return drop; 3632 } 3633 3634 static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 3635 struct ieee80211_rx_status *status) 3636 { 3637 struct ath12k_base *ab = ar->ab; 3638 u16 msdu_len; 3639 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3640 u8 l3pad_bytes; 3641 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3642 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz; 3643 3644 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 3645 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 3646 3647 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3648 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3649 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3650 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3651 3652 ath12k_dp_rx_h_ppdu(ar, desc, status); 3653 3654 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3655 RX_FLAG_DECRYPTED); 3656 3657 ath12k_dp_rx_h_undecap(ar, msdu, desc, 3658 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3659 } 3660 3661 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 3662 struct ieee80211_rx_status *status) 3663 { 3664 struct ath12k_base *ab = ar->ab; 3665 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3666 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3667 bool drop = false; 3668 u32 err_bitmap; 3669 3670 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3671 3672 switch (rxcb->err_code) { 3673 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 3674 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3675 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 3676 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 3677 ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3678 break; 3679 } 3680 fallthrough; 3681 default: 3682 /* TODO: Review other rxdma error code to check if anything is 3683 * worth reporting to mac80211 3684 */ 3685 drop = true; 3686 break; 3687 } 3688 3689 return drop; 3690 } 3691 3692 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 3693 struct napi_struct *napi, 3694 struct sk_buff *msdu, 3695 struct sk_buff_head *msdu_list) 3696 { 3697 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3698 struct ieee80211_rx_status rxs = {0}; 3699 bool drop = true; 3700 3701 switch (rxcb->err_rel_src) { 3702 case HAL_WBM_REL_SRC_MODULE_REO: 3703 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3704 break; 3705 case HAL_WBM_REL_SRC_MODULE_RXDMA: 3706 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3707 break; 3708 default: 3709 /* msdu will get freed */ 3710 break; 3711 } 3712 3713 if (drop) { 3714 dev_kfree_skb_any(msdu); 3715 return; 3716 } 3717 3718 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 3719 } 3720 3721 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 3722 struct napi_struct *napi, int budget) 3723 { 3724 LIST_HEAD(rx_desc_used_list); 3725 struct ath12k *ar; 3726 struct ath12k_dp *dp = &ab->dp; 3727 struct dp_rxdma_ring *rx_ring; 3728 struct hal_rx_wbm_rel_info err_info; 3729 struct hal_srng *srng; 3730 struct sk_buff *msdu; 3731 struct sk_buff_head msdu_list, scatter_msdu_list; 3732 struct ath12k_skb_rxcb *rxcb; 3733 void *rx_desc; 3734 u8 mac_id; 3735 int num_buffs_reaped = 0; 3736 struct ath12k_rx_desc_info *desc_info; 3737 int ret, pdev_id; 3738 struct hal_rx_desc *msdu_data; 3739 3740 __skb_queue_head_init(&msdu_list); 3741 __skb_queue_head_init(&scatter_msdu_list); 3742 3743 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3744 rx_ring = &dp->rx_refill_buf_ring; 3745 spin_lock_bh(&srng->lock); 3746 3747 ath12k_hal_srng_access_begin(ab, srng); 3748 3749 while (budget) { 3750 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 3751 if (!rx_desc) 3752 break; 3753 3754 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3755 if (ret) { 3756 ath12k_warn(ab, 3757 "failed to parse rx error in wbm_rel ring desc %d\n", 3758 ret); 3759 continue; 3760 } 3761 3762 desc_info = err_info.rx_desc; 3763 3764 /* retry manual desc retrieval if hw cc is not done */ 3765 if (!desc_info) { 3766 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 3767 if (!desc_info) { 3768 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 3769 continue; 3770 } 3771 } 3772 3773 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3774 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 3775 3776 msdu = desc_info->skb; 3777 desc_info->skb = NULL; 3778 3779 list_add_tail(&desc_info->list, &rx_desc_used_list); 3780 3781 rxcb = ATH12K_SKB_RXCB(msdu); 3782 dma_unmap_single(ab->dev, rxcb->paddr, 3783 msdu->len + skb_tailroom(msdu), 3784 DMA_FROM_DEVICE); 3785 3786 num_buffs_reaped++; 3787 3788 if (!err_info.continuation) 3789 budget--; 3790 3791 if (err_info.push_reason != 3792 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3793 dev_kfree_skb_any(msdu); 3794 continue; 3795 } 3796 3797 msdu_data = (struct hal_rx_desc *)msdu->data; 3798 rxcb->err_rel_src = err_info.err_rel_src; 3799 rxcb->err_code = err_info.err_code; 3800 rxcb->is_first_msdu = err_info.first_msdu; 3801 rxcb->is_last_msdu = err_info.last_msdu; 3802 rxcb->is_continuation = err_info.continuation; 3803 rxcb->rx_desc = msdu_data; 3804 3805 if (err_info.continuation) { 3806 __skb_queue_tail(&scatter_msdu_list, msdu); 3807 continue; 3808 } 3809 3810 mac_id = ath12k_dp_rx_get_msdu_src_link(ab, 3811 msdu_data); 3812 if (mac_id >= MAX_RADIOS) { 3813 dev_kfree_skb_any(msdu); 3814 3815 /* In any case continuation bit is set 3816 * in the previous record, cleanup scatter_msdu_list 3817 */ 3818 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 3819 continue; 3820 } 3821 3822 if (!skb_queue_empty(&scatter_msdu_list)) { 3823 struct sk_buff *msdu; 3824 3825 skb_queue_walk(&scatter_msdu_list, msdu) { 3826 rxcb = ATH12K_SKB_RXCB(msdu); 3827 rxcb->mac_id = mac_id; 3828 } 3829 3830 skb_queue_splice_tail_init(&scatter_msdu_list, 3831 &msdu_list); 3832 } 3833 3834 rxcb = ATH12K_SKB_RXCB(msdu); 3835 rxcb->mac_id = mac_id; 3836 __skb_queue_tail(&msdu_list, msdu); 3837 } 3838 3839 /* In any case continuation bit is set in the 3840 * last record, cleanup scatter_msdu_list 3841 */ 3842 ath12k_dp_clean_up_skb_list(&scatter_msdu_list); 3843 3844 ath12k_hal_srng_access_end(ab, srng); 3845 3846 spin_unlock_bh(&srng->lock); 3847 3848 if (!num_buffs_reaped) 3849 goto done; 3850 3851 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list, 3852 num_buffs_reaped); 3853 3854 rcu_read_lock(); 3855 while ((msdu = __skb_dequeue(&msdu_list))) { 3856 rxcb = ATH12K_SKB_RXCB(msdu); 3857 mac_id = rxcb->mac_id; 3858 3859 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3860 ar = ab->pdevs[pdev_id].ar; 3861 3862 if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) { 3863 dev_kfree_skb_any(msdu); 3864 continue; 3865 } 3866 3867 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3868 dev_kfree_skb_any(msdu); 3869 continue; 3870 } 3871 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); 3872 } 3873 rcu_read_unlock(); 3874 done: 3875 return num_buffs_reaped; 3876 } 3877 3878 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 3879 { 3880 struct ath12k_dp *dp = &ab->dp; 3881 struct hal_tlv_64_hdr *hdr; 3882 struct hal_srng *srng; 3883 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 3884 bool found = false; 3885 u16 tag; 3886 struct hal_reo_status reo_status; 3887 3888 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 3889 3890 memset(&reo_status, 0, sizeof(reo_status)); 3891 3892 spin_lock_bh(&srng->lock); 3893 3894 ath12k_hal_srng_access_begin(ab, srng); 3895 3896 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3897 tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 3898 3899 switch (tag) { 3900 case HAL_REO_GET_QUEUE_STATS_STATUS: 3901 ath12k_hal_reo_status_queue_stats(ab, hdr, 3902 &reo_status); 3903 break; 3904 case HAL_REO_FLUSH_QUEUE_STATUS: 3905 ath12k_hal_reo_flush_queue_status(ab, hdr, 3906 &reo_status); 3907 break; 3908 case HAL_REO_FLUSH_CACHE_STATUS: 3909 ath12k_hal_reo_flush_cache_status(ab, hdr, 3910 &reo_status); 3911 break; 3912 case HAL_REO_UNBLOCK_CACHE_STATUS: 3913 ath12k_hal_reo_unblk_cache_status(ab, hdr, 3914 &reo_status); 3915 break; 3916 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 3917 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 3918 &reo_status); 3919 break; 3920 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 3921 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 3922 &reo_status); 3923 break; 3924 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 3925 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 3926 &reo_status); 3927 break; 3928 default: 3929 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 3930 continue; 3931 } 3932 3933 spin_lock_bh(&dp->reo_cmd_lock); 3934 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 3935 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 3936 found = true; 3937 list_del(&cmd->list); 3938 break; 3939 } 3940 } 3941 spin_unlock_bh(&dp->reo_cmd_lock); 3942 3943 if (found) { 3944 cmd->handler(dp, (void *)&cmd->data, 3945 reo_status.uniform_hdr.cmd_status); 3946 kfree(cmd); 3947 } 3948 3949 found = false; 3950 } 3951 3952 ath12k_hal_srng_access_end(ab, srng); 3953 3954 spin_unlock_bh(&srng->lock); 3955 } 3956 3957 void ath12k_dp_rx_free(struct ath12k_base *ab) 3958 { 3959 struct ath12k_dp *dp = &ab->dp; 3960 int i; 3961 3962 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 3963 3964 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 3965 if (ab->hw_params->rx_mac_buf_ring) 3966 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 3967 } 3968 3969 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 3970 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 3971 3972 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 3973 ath12k_dp_srng_cleanup(ab, &dp->tx_mon_buf_ring.refill_buf_ring); 3974 3975 ath12k_dp_rxdma_buf_free(ab); 3976 } 3977 3978 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 3979 { 3980 struct ath12k *ar = ab->pdevs[mac_id].ar; 3981 3982 ath12k_dp_rx_pdev_srng_free(ar); 3983 } 3984 3985 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 3986 { 3987 struct ath12k_dp *dp = &ab->dp; 3988 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 3989 u32 ring_id; 3990 int ret; 3991 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 3992 3993 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 3994 3995 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 3996 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 3997 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 3998 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 3999 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4000 tlv_filter.offset_valid = true; 4001 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4002 4003 tlv_filter.rx_mpdu_start_offset = 4004 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4005 tlv_filter.rx_msdu_end_offset = 4006 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4007 4008 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 4009 tlv_filter.rx_mpdu_start_wmask = 4010 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); 4011 tlv_filter.rx_msdu_end_wmask = 4012 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); 4013 ath12k_dbg(ab, ATH12K_DBG_DATA, 4014 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", 4015 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); 4016 } 4017 4018 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 4019 HAL_RXDMA_BUF, 4020 DP_RXDMA_REFILL_RING_SIZE, 4021 &tlv_filter); 4022 4023 return ret; 4024 } 4025 4026 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 4027 { 4028 struct ath12k_dp *dp = &ab->dp; 4029 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 4030 u32 ring_id; 4031 int ret; 4032 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz; 4033 int i; 4034 4035 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4036 4037 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 4038 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 4039 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 4040 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4041 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4042 tlv_filter.offset_valid = true; 4043 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4044 4045 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4046 4047 tlv_filter.rx_mpdu_start_offset = 4048 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset(); 4049 tlv_filter.rx_msdu_end_offset = 4050 ab->hal_rx_ops->rx_desc_get_msdu_end_offset(); 4051 4052 /* TODO: Selectively subscribe to required qwords within msdu_end 4053 * and mpdu_start and setup the mask in below msg 4054 * and modify the rx_desc struct 4055 */ 4056 4057 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4058 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4059 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4060 HAL_RXDMA_BUF, 4061 DP_RXDMA_REFILL_RING_SIZE, 4062 &tlv_filter); 4063 } 4064 4065 return ret; 4066 } 4067 4068 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4069 { 4070 struct ath12k_dp *dp = &ab->dp; 4071 u32 ring_id; 4072 int i, ret; 4073 4074 /* TODO: Need to verify the HTT setup for QCN9224 */ 4075 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4076 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4077 if (ret) { 4078 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4079 ret); 4080 return ret; 4081 } 4082 4083 if (ab->hw_params->rx_mac_buf_ring) { 4084 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4085 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4086 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4087 i, HAL_RXDMA_BUF); 4088 if (ret) { 4089 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4090 i, ret); 4091 return ret; 4092 } 4093 } 4094 } 4095 4096 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4097 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4098 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4099 i, HAL_RXDMA_DST); 4100 if (ret) { 4101 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4102 i, ret); 4103 return ret; 4104 } 4105 } 4106 4107 if (ab->hw_params->rxdma1_enable) { 4108 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4109 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4110 0, HAL_RXDMA_MONITOR_BUF); 4111 if (ret) { 4112 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4113 ret); 4114 return ret; 4115 } 4116 4117 ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; 4118 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4119 0, HAL_TX_MONITOR_BUF); 4120 if (ret) { 4121 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4122 ret); 4123 return ret; 4124 } 4125 } 4126 4127 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4128 if (ret) { 4129 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4130 return ret; 4131 } 4132 4133 return 0; 4134 } 4135 4136 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4137 { 4138 struct ath12k_dp *dp = &ab->dp; 4139 int i, ret; 4140 4141 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4142 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4143 4144 idr_init(&dp->tx_mon_buf_ring.bufs_idr); 4145 spin_lock_init(&dp->tx_mon_buf_ring.idr_lock); 4146 4147 ret = ath12k_dp_srng_setup(ab, 4148 &dp->rx_refill_buf_ring.refill_buf_ring, 4149 HAL_RXDMA_BUF, 0, 0, 4150 DP_RXDMA_BUF_RING_SIZE); 4151 if (ret) { 4152 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4153 return ret; 4154 } 4155 4156 if (ab->hw_params->rx_mac_buf_ring) { 4157 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4158 ret = ath12k_dp_srng_setup(ab, 4159 &dp->rx_mac_buf_ring[i], 4160 HAL_RXDMA_BUF, 1, 4161 i, DP_RX_MAC_BUF_RING_SIZE); 4162 if (ret) { 4163 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4164 i); 4165 return ret; 4166 } 4167 } 4168 } 4169 4170 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4171 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4172 HAL_RXDMA_DST, 0, i, 4173 DP_RXDMA_ERR_DST_RING_SIZE); 4174 if (ret) { 4175 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4176 return ret; 4177 } 4178 } 4179 4180 if (ab->hw_params->rxdma1_enable) { 4181 ret = ath12k_dp_srng_setup(ab, 4182 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4183 HAL_RXDMA_MONITOR_BUF, 0, 0, 4184 DP_RXDMA_MONITOR_BUF_RING_SIZE); 4185 if (ret) { 4186 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4187 return ret; 4188 } 4189 4190 ret = ath12k_dp_srng_setup(ab, 4191 &dp->tx_mon_buf_ring.refill_buf_ring, 4192 HAL_TX_MONITOR_BUF, 0, 0, 4193 DP_TX_MONITOR_BUF_RING_SIZE); 4194 if (ret) { 4195 ath12k_warn(ab, "failed to setup DP_TX_MONITOR_BUF_RING_SIZE\n"); 4196 return ret; 4197 } 4198 } 4199 4200 ret = ath12k_dp_rxdma_buf_setup(ab); 4201 if (ret) { 4202 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4203 return ret; 4204 } 4205 4206 return 0; 4207 } 4208 4209 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4210 { 4211 struct ath12k *ar = ab->pdevs[mac_id].ar; 4212 struct ath12k_pdev_dp *dp = &ar->dp; 4213 u32 ring_id; 4214 int i; 4215 int ret; 4216 4217 if (!ab->hw_params->rxdma1_enable) 4218 goto out; 4219 4220 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4221 if (ret) { 4222 ath12k_warn(ab, "failed to setup rx srngs\n"); 4223 return ret; 4224 } 4225 4226 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4227 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4228 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4229 mac_id + i, 4230 HAL_RXDMA_MONITOR_DST); 4231 if (ret) { 4232 ath12k_warn(ab, 4233 "failed to configure rxdma_mon_dst_ring %d %d\n", 4234 i, ret); 4235 return ret; 4236 } 4237 4238 ring_id = dp->tx_mon_dst_ring[i].ring_id; 4239 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4240 mac_id + i, 4241 HAL_TX_MONITOR_DST); 4242 if (ret) { 4243 ath12k_warn(ab, 4244 "failed to configure tx_mon_dst_ring %d %d\n", 4245 i, ret); 4246 return ret; 4247 } 4248 } 4249 out: 4250 return 0; 4251 } 4252 4253 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4254 { 4255 struct ath12k_pdev_dp *dp = &ar->dp; 4256 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4257 4258 skb_queue_head_init(&pmon->rx_status_q); 4259 4260 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4261 4262 memset(&pmon->rx_mon_stats, 0, 4263 sizeof(pmon->rx_mon_stats)); 4264 return 0; 4265 } 4266 4267 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4268 { 4269 struct ath12k_pdev_dp *dp = &ar->dp; 4270 struct ath12k_mon_data *pmon = &dp->mon_data; 4271 int ret = 0; 4272 4273 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4274 if (ret) { 4275 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4276 return ret; 4277 } 4278 4279 /* if rxdma1_enable is false, no need to setup 4280 * rxdma_mon_desc_ring. 4281 */ 4282 if (!ar->ab->hw_params->rxdma1_enable) 4283 return 0; 4284 4285 pmon->mon_last_linkdesc_paddr = 0; 4286 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4287 spin_lock_init(&pmon->mon_lock); 4288 4289 return 0; 4290 } 4291