1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "dp_mon.h" 8 #include "debug.h" 9 #include "dp_rx.h" 10 #include "dp_tx.h" 11 #include "peer.h" 12 13 static void 14 ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user, 15 struct hal_rx_user_status *rx_user_status) 16 { 17 rx_user_status->ul_ofdma_user_v0_word0 = 18 __le32_to_cpu(ppdu_end_user->usr_resp_ref); 19 rx_user_status->ul_ofdma_user_v0_word1 = 20 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext); 21 } 22 23 static void 24 ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats, 25 void *ppduinfo, 26 struct hal_rx_user_status *rx_user_status) 27 { 28 rx_user_status->mpdu_ok_byte_count = 29 le32_get_bits(stats->info7, 30 HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT); 31 rx_user_status->mpdu_err_byte_count = 32 le32_get_bits(stats->info8, 33 HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT); 34 } 35 36 static void 37 ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv, 38 struct hal_rx_mon_ppdu_info *ppdu_info, 39 struct hal_rx_user_status *rx_user_status) 40 { 41 rx_user_status->ast_index = ppdu_info->ast_index; 42 rx_user_status->tid = ppdu_info->tid; 43 rx_user_status->tcp_ack_msdu_count = 44 ppdu_info->tcp_ack_msdu_count; 45 rx_user_status->tcp_msdu_count = 46 ppdu_info->tcp_msdu_count; 47 rx_user_status->udp_msdu_count = 48 ppdu_info->udp_msdu_count; 49 rx_user_status->other_msdu_count = 50 ppdu_info->other_msdu_count; 51 rx_user_status->frame_control = ppdu_info->frame_control; 52 rx_user_status->frame_control_info_valid = 53 ppdu_info->frame_control_info_valid; 54 rx_user_status->data_sequence_control_info_valid = 55 ppdu_info->data_sequence_control_info_valid; 56 rx_user_status->first_data_seq_ctrl = 57 ppdu_info->first_data_seq_ctrl; 58 rx_user_status->preamble_type = ppdu_info->preamble_type; 59 rx_user_status->ht_flags = ppdu_info->ht_flags; 60 rx_user_status->vht_flags = ppdu_info->vht_flags; 61 rx_user_status->he_flags = ppdu_info->he_flags; 62 rx_user_status->rs_flags = ppdu_info->rs_flags; 63 64 rx_user_status->mpdu_cnt_fcs_ok = 65 ppdu_info->num_mpdu_fcs_ok; 66 rx_user_status->mpdu_cnt_fcs_err = 67 ppdu_info->num_mpdu_fcs_err; 68 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0], 69 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 70 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 71 72 ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); 73 } 74 75 static void ath12k_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info *vht_sig, 76 struct hal_rx_mon_ppdu_info *ppdu_info) 77 { 78 u32 nsts, group_id, info0, info1; 79 u8 gi_setting; 80 81 info0 = __le32_to_cpu(vht_sig->info0); 82 info1 = __le32_to_cpu(vht_sig->info1); 83 84 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 85 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS); 86 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING); 87 switch (gi_setting) { 88 case HAL_RX_VHT_SIG_A_NORMAL_GI: 89 ppdu_info->gi = HAL_RX_GI_0_8_US; 90 break; 91 case HAL_RX_VHT_SIG_A_SHORT_GI: 92 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 93 ppdu_info->gi = HAL_RX_GI_0_4_US; 94 break; 95 } 96 97 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC); 98 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS); 99 if (ppdu_info->is_stbc && nsts > 0) 100 nsts = ((nsts + 1) >> 1) - 1; 101 102 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK); 103 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW); 104 ppdu_info->beamformed = u32_get_bits(info1, 105 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED); 106 group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID); 107 if (group_id == 0 || group_id == 63) 108 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 109 else 110 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 111 ppdu_info->vht_flag_values5 = group_id; 112 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | 113 ppdu_info->nss); 114 ppdu_info->vht_flag_values2 = ppdu_info->bw; 115 ppdu_info->vht_flag_values4 = 116 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 117 } 118 119 static void ath12k_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info *ht_sig, 120 struct hal_rx_mon_ppdu_info *ppdu_info) 121 { 122 u32 info0 = __le32_to_cpu(ht_sig->info0); 123 u32 info1 = __le32_to_cpu(ht_sig->info1); 124 125 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS); 126 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW); 127 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC); 128 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING); 129 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI); 130 ppdu_info->nss = (ppdu_info->mcs >> 3); 131 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 132 } 133 134 static void ath12k_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info *lsigb, 135 struct hal_rx_mon_ppdu_info *ppdu_info) 136 { 137 u32 info0 = __le32_to_cpu(lsigb->info0); 138 u8 rate; 139 140 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE); 141 switch (rate) { 142 case 1: 143 rate = HAL_RX_LEGACY_RATE_1_MBPS; 144 break; 145 case 2: 146 case 5: 147 rate = HAL_RX_LEGACY_RATE_2_MBPS; 148 break; 149 case 3: 150 case 6: 151 rate = HAL_RX_LEGACY_RATE_5_5_MBPS; 152 break; 153 case 4: 154 case 7: 155 rate = HAL_RX_LEGACY_RATE_11_MBPS; 156 break; 157 default: 158 rate = HAL_RX_LEGACY_RATE_INVALID; 159 } 160 161 ppdu_info->rate = rate; 162 ppdu_info->cck_flag = 1; 163 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 164 } 165 166 static void ath12k_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info *lsiga, 167 struct hal_rx_mon_ppdu_info *ppdu_info) 168 { 169 u32 info0 = __le32_to_cpu(lsiga->info0); 170 u8 rate; 171 172 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE); 173 switch (rate) { 174 case 8: 175 rate = HAL_RX_LEGACY_RATE_48_MBPS; 176 break; 177 case 9: 178 rate = HAL_RX_LEGACY_RATE_24_MBPS; 179 break; 180 case 10: 181 rate = HAL_RX_LEGACY_RATE_12_MBPS; 182 break; 183 case 11: 184 rate = HAL_RX_LEGACY_RATE_6_MBPS; 185 break; 186 case 12: 187 rate = HAL_RX_LEGACY_RATE_54_MBPS; 188 break; 189 case 13: 190 rate = HAL_RX_LEGACY_RATE_36_MBPS; 191 break; 192 case 14: 193 rate = HAL_RX_LEGACY_RATE_18_MBPS; 194 break; 195 case 15: 196 rate = HAL_RX_LEGACY_RATE_9_MBPS; 197 break; 198 default: 199 rate = HAL_RX_LEGACY_RATE_INVALID; 200 } 201 202 ppdu_info->rate = rate; 203 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 204 } 205 206 static void 207 ath12k_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info *ofdma, 208 struct hal_rx_mon_ppdu_info *ppdu_info) 209 { 210 u32 info0, value; 211 212 info0 = __le32_to_cpu(ofdma->info0); 213 214 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN; 215 216 /* HE-data2 */ 217 ppdu_info->he_data2 |= HE_TXBF_KNOWN; 218 219 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS); 220 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 221 ppdu_info->he_data3 |= value; 222 223 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM); 224 value = value << HE_DCM_SHIFT; 225 ppdu_info->he_data3 |= value; 226 227 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING); 228 ppdu_info->ldpc = value; 229 value = value << HE_CODING_SHIFT; 230 ppdu_info->he_data3 |= value; 231 232 /* HE-data4 */ 233 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID); 234 value = value << HE_STA_ID_SHIFT; 235 ppdu_info->he_data4 |= value; 236 237 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS); 238 ppdu_info->beamformed = u32_get_bits(info0, 239 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF); 240 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 241 } 242 243 static void 244 ath12k_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu, 245 struct hal_rx_mon_ppdu_info *ppdu_info) 246 { 247 u32 info0, value; 248 249 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 250 251 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN; 252 253 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS); 254 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 255 ppdu_info->he_data3 |= value; 256 257 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING); 258 ppdu_info->ldpc = value; 259 value = value << HE_CODING_SHIFT; 260 ppdu_info->he_data3 |= value; 261 262 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID); 263 value = value << HE_STA_ID_SHIFT; 264 ppdu_info->he_data4 |= value; 265 266 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS); 267 } 268 269 static void 270 ath12k_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu, 271 struct hal_rx_mon_ppdu_info *ppdu_info) 272 { 273 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 274 u16 ru_tones; 275 276 ru_tones = u32_get_bits(info0, 277 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION); 278 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 279 ppdu_info->he_RU[0] = ru_tones; 280 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 281 } 282 283 static void 284 ath12k_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl, 285 struct hal_rx_mon_ppdu_info *ppdu_info) 286 { 287 u32 info0, info1, value; 288 u16 he_gi = 0, he_ltf = 0; 289 290 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 291 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 292 293 ppdu_info->he_mu_flags = 1; 294 295 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE; 296 ppdu_info->he_data1 |= 297 HE_BSS_COLOR_KNOWN | 298 HE_DL_UL_KNOWN | 299 HE_LDPC_EXTRA_SYMBOL_KNOWN | 300 HE_STBC_KNOWN | 301 HE_DATA_BW_RU_KNOWN | 302 HE_DOPPLER_KNOWN; 303 304 ppdu_info->he_data2 = 305 HE_GI_KNOWN | 306 HE_LTF_SYMBOLS_KNOWN | 307 HE_PRE_FEC_PADDING_KNOWN | 308 HE_PE_DISAMBIGUITY_KNOWN | 309 HE_TXOP_KNOWN | 310 HE_MIDABLE_PERIODICITY_KNOWN; 311 312 /* data3 */ 313 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR); 314 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG); 315 value = value << HE_DL_UL_SHIFT; 316 ppdu_info->he_data3 |= value; 317 318 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA); 319 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 320 ppdu_info->he_data3 |= value; 321 322 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC); 323 value = value << HE_STBC_SHIFT; 324 ppdu_info->he_data3 |= value; 325 326 /* data4 */ 327 ppdu_info->he_data4 = u32_get_bits(info0, 328 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE); 329 ppdu_info->he_data4 = value; 330 331 /* data5 */ 332 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 333 ppdu_info->he_data5 = value; 334 ppdu_info->bw = value; 335 336 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE); 337 switch (value) { 338 case 0: 339 he_gi = HE_GI_0_8; 340 he_ltf = HE_LTF_4_X; 341 break; 342 case 1: 343 he_gi = HE_GI_0_8; 344 he_ltf = HE_LTF_2_X; 345 break; 346 case 2: 347 he_gi = HE_GI_1_6; 348 he_ltf = HE_LTF_2_X; 349 break; 350 case 3: 351 he_gi = HE_GI_3_2; 352 he_ltf = HE_LTF_4_X; 353 break; 354 } 355 356 ppdu_info->gi = he_gi; 357 value = he_gi << HE_GI_SHIFT; 358 ppdu_info->he_data5 |= value; 359 360 value = he_ltf << HE_LTF_SIZE_SHIFT; 361 ppdu_info->he_data5 |= value; 362 363 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB); 364 value = (value << HE_LTF_SYM_SHIFT); 365 ppdu_info->he_data5 |= value; 366 367 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR); 368 value = value << HE_PRE_FEC_PAD_SHIFT; 369 ppdu_info->he_data5 |= value; 370 371 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM); 372 value = value << HE_PE_DISAMBIGUITY_SHIFT; 373 ppdu_info->he_data5 |= value; 374 375 /*data6*/ 376 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION); 377 value = value << HE_DOPPLER_SHIFT; 378 ppdu_info->he_data6 |= value; 379 380 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION); 381 value = value << HE_TXOP_SHIFT; 382 ppdu_info->he_data6 |= value; 383 384 /* HE-MU Flags */ 385 /* HE-MU-flags1 */ 386 ppdu_info->he_flags1 = 387 HE_SIG_B_MCS_KNOWN | 388 HE_SIG_B_DCM_KNOWN | 389 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN | 390 HE_SIG_B_SYM_NUM_KNOWN | 391 HE_RU_0_KNOWN; 392 393 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB); 394 ppdu_info->he_flags1 |= value; 395 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB); 396 value = value << HE_DCM_FLAG_1_SHIFT; 397 ppdu_info->he_flags1 |= value; 398 399 /* HE-MU-flags2 */ 400 ppdu_info->he_flags2 = HE_BW_KNOWN; 401 402 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 403 ppdu_info->he_flags2 |= value; 404 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB); 405 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT; 406 ppdu_info->he_flags2 |= value; 407 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB); 408 value = value - 1; 409 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT; 410 ppdu_info->he_flags2 |= value; 411 412 ppdu_info->is_stbc = info1 & 413 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC; 414 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 415 } 416 417 static void ath12k_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info *he_sig_a, 418 struct hal_rx_mon_ppdu_info *ppdu_info) 419 { 420 u32 info0, info1, value; 421 u32 dcm; 422 u8 he_dcm = 0, he_stbc = 0; 423 u16 he_gi = 0, he_ltf = 0; 424 425 ppdu_info->he_flags = 1; 426 427 info0 = __le32_to_cpu(he_sig_a->info0); 428 info1 = __le32_to_cpu(he_sig_a->info1); 429 430 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND); 431 if (value == 0) 432 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE; 433 else 434 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE; 435 436 ppdu_info->he_data1 |= 437 HE_BSS_COLOR_KNOWN | 438 HE_BEAM_CHANGE_KNOWN | 439 HE_DL_UL_KNOWN | 440 HE_MCS_KNOWN | 441 HE_DCM_KNOWN | 442 HE_CODING_KNOWN | 443 HE_LDPC_EXTRA_SYMBOL_KNOWN | 444 HE_STBC_KNOWN | 445 HE_DATA_BW_RU_KNOWN | 446 HE_DOPPLER_KNOWN; 447 448 ppdu_info->he_data2 |= 449 HE_GI_KNOWN | 450 HE_TXBF_KNOWN | 451 HE_PE_DISAMBIGUITY_KNOWN | 452 HE_TXOP_KNOWN | 453 HE_LTF_SYMBOLS_KNOWN | 454 HE_PRE_FEC_PADDING_KNOWN | 455 HE_MIDABLE_PERIODICITY_KNOWN; 456 457 ppdu_info->he_data3 = u32_get_bits(info0, 458 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR); 459 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE); 460 value = value << HE_BEAM_CHANGE_SHIFT; 461 ppdu_info->he_data3 |= value; 462 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG); 463 value = value << HE_DL_UL_SHIFT; 464 ppdu_info->he_data3 |= value; 465 466 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 467 ppdu_info->mcs = value; 468 value = value << HE_TRANSMIT_MCS_SHIFT; 469 ppdu_info->he_data3 |= value; 470 471 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 472 he_dcm = value; 473 value = value << HE_DCM_SHIFT; 474 ppdu_info->he_data3 |= value; 475 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 476 value = value << HE_CODING_SHIFT; 477 ppdu_info->he_data3 |= value; 478 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA); 479 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 480 ppdu_info->he_data3 |= value; 481 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 482 he_stbc = value; 483 value = value << HE_STBC_SHIFT; 484 ppdu_info->he_data3 |= value; 485 486 /* data4 */ 487 ppdu_info->he_data4 = u32_get_bits(info0, 488 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE); 489 490 /* data5 */ 491 value = u32_get_bits(info0, 492 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 493 ppdu_info->he_data5 = value; 494 ppdu_info->bw = value; 495 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE); 496 switch (value) { 497 case 0: 498 he_gi = HE_GI_0_8; 499 he_ltf = HE_LTF_1_X; 500 break; 501 case 1: 502 he_gi = HE_GI_0_8; 503 he_ltf = HE_LTF_2_X; 504 break; 505 case 2: 506 he_gi = HE_GI_1_6; 507 he_ltf = HE_LTF_2_X; 508 break; 509 case 3: 510 if (he_dcm && he_stbc) { 511 he_gi = HE_GI_0_8; 512 he_ltf = HE_LTF_4_X; 513 } else { 514 he_gi = HE_GI_3_2; 515 he_ltf = HE_LTF_4_X; 516 } 517 break; 518 } 519 ppdu_info->gi = he_gi; 520 value = he_gi << HE_GI_SHIFT; 521 ppdu_info->he_data5 |= value; 522 value = he_ltf << HE_LTF_SIZE_SHIFT; 523 ppdu_info->ltf_size = he_ltf; 524 ppdu_info->he_data5 |= value; 525 526 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 527 value = (value << HE_LTF_SYM_SHIFT); 528 ppdu_info->he_data5 |= value; 529 530 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR); 531 value = value << HE_PRE_FEC_PAD_SHIFT; 532 ppdu_info->he_data5 |= value; 533 534 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 535 value = value << HE_TXBF_SHIFT; 536 ppdu_info->he_data5 |= value; 537 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM); 538 value = value << HE_PE_DISAMBIGUITY_SHIFT; 539 ppdu_info->he_data5 |= value; 540 541 /* data6 */ 542 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 543 value++; 544 ppdu_info->he_data6 = value; 545 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND); 546 value = value << HE_DOPPLER_SHIFT; 547 ppdu_info->he_data6 |= value; 548 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION); 549 value = value << HE_TXOP_SHIFT; 550 ppdu_info->he_data6 |= value; 551 552 ppdu_info->mcs = 553 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 554 ppdu_info->bw = 555 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 556 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 557 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 558 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 559 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 560 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 561 ppdu_info->dcm = dcm; 562 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 563 } 564 565 static enum hal_rx_mon_status 566 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab, 567 struct ath12k_mon_data *pmon, 568 u32 tlv_tag, const void *tlv_data, 569 u32 userid) 570 { 571 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 572 u32 info[7]; 573 574 switch (tlv_tag) { 575 case HAL_RX_PPDU_START: { 576 const struct hal_rx_ppdu_start *ppdu_start = tlv_data; 577 578 u64 ppdu_ts = ath12k_le32hilo_to_u64(ppdu_start->ppdu_start_ts_63_32, 579 ppdu_start->ppdu_start_ts_31_0); 580 581 info[0] = __le32_to_cpu(ppdu_start->info0); 582 583 ppdu_info->ppdu_id = u32_get_bits(info[0], 584 HAL_RX_PPDU_START_INFO0_PPDU_ID); 585 586 info[1] = __le32_to_cpu(ppdu_start->info1); 587 ppdu_info->chan_num = u32_get_bits(info[1], 588 HAL_RX_PPDU_START_INFO1_CHAN_NUM); 589 ppdu_info->freq = u32_get_bits(info[1], 590 HAL_RX_PPDU_START_INFO1_CHAN_FREQ); 591 ppdu_info->ppdu_ts = ppdu_ts; 592 593 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) { 594 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id; 595 ppdu_info->num_users = 0; 596 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0, 597 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 598 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 599 } 600 break; 601 } 602 case HAL_RX_PPDU_END_USER_STATS: { 603 const struct hal_rx_ppdu_end_user_stats *eu_stats = tlv_data; 604 u32 tid_bitmap; 605 606 info[0] = __le32_to_cpu(eu_stats->info0); 607 info[1] = __le32_to_cpu(eu_stats->info1); 608 info[2] = __le32_to_cpu(eu_stats->info2); 609 info[4] = __le32_to_cpu(eu_stats->info4); 610 info[5] = __le32_to_cpu(eu_stats->info5); 611 info[6] = __le32_to_cpu(eu_stats->info6); 612 613 ppdu_info->ast_index = 614 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX); 615 ppdu_info->fc_valid = 616 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID); 617 tid_bitmap = u32_get_bits(info[6], 618 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP); 619 ppdu_info->tid = ffs(tid_bitmap) - 1; 620 ppdu_info->tcp_msdu_count = 621 u32_get_bits(info[4], 622 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT); 623 ppdu_info->udp_msdu_count = 624 u32_get_bits(info[4], 625 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT); 626 ppdu_info->other_msdu_count = 627 u32_get_bits(info[5], 628 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT); 629 ppdu_info->tcp_ack_msdu_count = 630 u32_get_bits(info[5], 631 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT); 632 ppdu_info->preamble_type = 633 u32_get_bits(info[1], 634 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE); 635 ppdu_info->num_mpdu_fcs_ok = 636 u32_get_bits(info[1], 637 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK); 638 ppdu_info->num_mpdu_fcs_err = 639 u32_get_bits(info[0], 640 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR); 641 switch (ppdu_info->preamble_type) { 642 case HAL_RX_PREAMBLE_11N: 643 ppdu_info->ht_flags = 1; 644 break; 645 case HAL_RX_PREAMBLE_11AC: 646 ppdu_info->vht_flags = 1; 647 break; 648 case HAL_RX_PREAMBLE_11AX: 649 ppdu_info->he_flags = 1; 650 break; 651 default: 652 break; 653 } 654 655 if (userid < HAL_MAX_UL_MU_USERS) { 656 struct hal_rx_user_status *rxuser_stats = 657 &ppdu_info->userstats[userid]; 658 ppdu_info->num_users += 1; 659 660 ath12k_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats); 661 ath12k_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info, 662 rxuser_stats); 663 } 664 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]); 665 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]); 666 break; 667 } 668 case HAL_RX_PPDU_END_USER_STATS_EXT: { 669 const struct hal_rx_ppdu_end_user_stats_ext *eu_stats = tlv_data; 670 671 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1); 672 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2); 673 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3); 674 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4); 675 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5); 676 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6); 677 break; 678 } 679 case HAL_PHYRX_HT_SIG: 680 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info); 681 break; 682 683 case HAL_PHYRX_L_SIG_B: 684 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info); 685 break; 686 687 case HAL_PHYRX_L_SIG_A: 688 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info); 689 break; 690 691 case HAL_PHYRX_VHT_SIG_A: 692 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info); 693 break; 694 695 case HAL_PHYRX_HE_SIG_A_SU: 696 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info); 697 break; 698 699 case HAL_PHYRX_HE_SIG_A_MU_DL: 700 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info); 701 break; 702 703 case HAL_PHYRX_HE_SIG_B1_MU: 704 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info); 705 break; 706 707 case HAL_PHYRX_HE_SIG_B2_MU: 708 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info); 709 break; 710 711 case HAL_PHYRX_HE_SIG_B2_OFDMA: 712 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info); 713 break; 714 715 case HAL_PHYRX_RSSI_LEGACY: { 716 const struct hal_rx_phyrx_rssi_legacy_info *rssi = tlv_data; 717 718 info[0] = __le32_to_cpu(rssi->info0); 719 info[1] = __le32_to_cpu(rssi->info1); 720 721 /* TODO: Please note that the combined rssi will not be accurate 722 * in MU case. Rssi in MU needs to be retrieved from 723 * PHYRX_OTHER_RECEIVE_INFO TLV. 724 */ 725 ppdu_info->rssi_comb = 726 u32_get_bits(info[1], 727 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB); 728 729 ppdu_info->bw = u32_get_bits(info[0], 730 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW); 731 break; 732 } 733 case HAL_RXPCU_PPDU_END_INFO: { 734 const struct hal_rx_ppdu_end_duration *ppdu_rx_duration = tlv_data; 735 736 info[0] = __le32_to_cpu(ppdu_rx_duration->info0); 737 ppdu_info->rx_duration = 738 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION); 739 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]); 740 ppdu_info->tsft = (ppdu_info->tsft << 32) | 741 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]); 742 break; 743 } 744 case HAL_RX_MPDU_START: { 745 const struct hal_rx_mpdu_start *mpdu_start = tlv_data; 746 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 747 u16 peer_id; 748 749 info[1] = __le32_to_cpu(mpdu_start->info1); 750 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID); 751 if (peer_id) 752 ppdu_info->peer_id = peer_id; 753 754 ppdu_info->mpdu_len += u32_get_bits(info[1], 755 HAL_RX_MPDU_START_INFO2_MPDU_LEN); 756 if (userid < HAL_MAX_UL_MU_USERS) { 757 info[0] = __le32_to_cpu(mpdu_start->info0); 758 ppdu_info->userid = userid; 759 ppdu_info->ampdu_id[userid] = 760 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID); 761 } 762 763 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 764 if (!mon_mpdu) 765 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 766 767 break; 768 } 769 case HAL_RX_MSDU_START: 770 /* TODO: add msdu start parsing logic */ 771 break; 772 case HAL_MON_BUF_ADDR: { 773 struct dp_rxdma_mon_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring; 774 const struct dp_mon_packet_info *packet_info = tlv_data; 775 int buf_id = u32_get_bits(packet_info->cookie, 776 DP_RXDMA_BUF_COOKIE_BUF_ID); 777 struct sk_buff *msdu; 778 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 779 struct ath12k_skb_rxcb *rxcb; 780 781 spin_lock_bh(&buf_ring->idr_lock); 782 msdu = idr_remove(&buf_ring->bufs_idr, buf_id); 783 spin_unlock_bh(&buf_ring->idr_lock); 784 785 if (unlikely(!msdu)) { 786 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 787 buf_id); 788 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 789 } 790 791 rxcb = ATH12K_SKB_RXCB(msdu); 792 dma_unmap_single(ab->dev, rxcb->paddr, 793 msdu->len + skb_tailroom(msdu), 794 DMA_FROM_DEVICE); 795 796 if (mon_mpdu->tail) 797 mon_mpdu->tail->next = msdu; 798 else 799 mon_mpdu->tail = msdu; 800 801 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 802 803 break; 804 } 805 case HAL_RX_MSDU_END: { 806 const struct rx_msdu_end_qcn9274 *msdu_end = tlv_data; 807 bool is_first_msdu_in_mpdu; 808 u16 msdu_end_info; 809 810 msdu_end_info = __le16_to_cpu(msdu_end->info5); 811 is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info, 812 RX_MSDU_END_INFO5_FIRST_MSDU); 813 if (is_first_msdu_in_mpdu) { 814 pmon->mon_mpdu->head = pmon->mon_mpdu->tail; 815 pmon->mon_mpdu->tail = NULL; 816 } 817 break; 818 } 819 case HAL_RX_MPDU_END: 820 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list); 821 break; 822 case HAL_DUMMY: 823 return HAL_RX_MON_STATUS_BUF_DONE; 824 case HAL_RX_PPDU_END_STATUS_DONE: 825 case 0: 826 return HAL_RX_MON_STATUS_PPDU_DONE; 827 default: 828 break; 829 } 830 831 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 832 } 833 834 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar, 835 struct sk_buff *head_msdu, 836 struct sk_buff *tail_msdu) 837 { 838 u32 rx_pkt_offset, l2_hdr_offset; 839 840 rx_pkt_offset = ar->ab->hal.hal_desc_sz; 841 l2_hdr_offset = 842 ath12k_dp_rx_h_l3pad(ar->ab, (struct hal_rx_desc *)tail_msdu->data); 843 skb_pull(head_msdu, rx_pkt_offset + l2_hdr_offset); 844 } 845 846 static struct sk_buff * 847 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, u32 mac_id, 848 struct sk_buff *head_msdu, struct sk_buff *tail_msdu, 849 struct ieee80211_rx_status *rxs, bool *fcs_err) 850 { 851 struct ath12k_base *ab = ar->ab; 852 struct sk_buff *msdu, *mpdu_buf, *prev_buf, *head_frag_list; 853 struct hal_rx_desc *rx_desc, *tail_rx_desc; 854 u8 *hdr_desc, *dest, decap_format; 855 struct ieee80211_hdr_3addr *wh; 856 u32 err_bitmap, frag_list_sum_len = 0; 857 858 mpdu_buf = NULL; 859 860 if (!head_msdu) 861 goto err_merge_fail; 862 863 rx_desc = (struct hal_rx_desc *)head_msdu->data; 864 tail_rx_desc = (struct hal_rx_desc *)tail_msdu->data; 865 866 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, tail_rx_desc); 867 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 868 *fcs_err = true; 869 870 decap_format = ath12k_dp_rx_h_decap_type(ab, tail_rx_desc); 871 872 ath12k_dp_rx_h_ppdu(ar, tail_rx_desc, rxs); 873 874 if (decap_format == DP_RX_DECAP_TYPE_RAW) { 875 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu, tail_msdu); 876 877 prev_buf = head_msdu; 878 msdu = head_msdu->next; 879 head_frag_list = NULL; 880 881 while (msdu) { 882 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu); 883 884 if (!head_frag_list) 885 head_frag_list = msdu; 886 887 frag_list_sum_len += msdu->len; 888 prev_buf = msdu; 889 msdu = msdu->next; 890 } 891 892 prev_buf->next = NULL; 893 894 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 895 if (head_frag_list) { 896 skb_shinfo(head_msdu)->frag_list = head_frag_list; 897 head_msdu->data_len = frag_list_sum_len; 898 head_msdu->len += head_msdu->data_len; 899 head_msdu->next = NULL; 900 } 901 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 902 u8 qos_pkt = 0; 903 904 rx_desc = (struct hal_rx_desc *)head_msdu->data; 905 hdr_desc = 906 ab->hal_rx_ops->rx_desc_get_msdu_payload(rx_desc); 907 908 /* Base size */ 909 wh = (struct ieee80211_hdr_3addr *)hdr_desc; 910 911 if (ieee80211_is_data_qos(wh->frame_control)) 912 qos_pkt = 1; 913 914 msdu = head_msdu; 915 916 while (msdu) { 917 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu); 918 if (qos_pkt) { 919 dest = skb_push(msdu, sizeof(__le16)); 920 if (!dest) 921 goto err_merge_fail; 922 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); 923 } 924 prev_buf = msdu; 925 msdu = msdu->next; 926 } 927 dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 928 if (!dest) 929 goto err_merge_fail; 930 931 ath12k_dbg(ab, ATH12K_DBG_DATA, 932 "mpdu_buf %p mpdu_buf->len %u", 933 prev_buf, prev_buf->len); 934 } else { 935 ath12k_dbg(ab, ATH12K_DBG_DATA, 936 "decap format %d is not supported!\n", 937 decap_format); 938 goto err_merge_fail; 939 } 940 941 return head_msdu; 942 943 err_merge_fail: 944 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) { 945 ath12k_dbg(ab, ATH12K_DBG_DATA, 946 "err_merge_fail mpdu_buf %p", mpdu_buf); 947 /* Free the head buffer */ 948 dev_kfree_skb_any(mpdu_buf); 949 } 950 return NULL; 951 } 952 953 static void 954 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status, 955 u8 *rtap_buf) 956 { 957 u32 rtap_len = 0; 958 959 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]); 960 rtap_len += 2; 961 962 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]); 963 rtap_len += 2; 964 965 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]); 966 rtap_len += 2; 967 968 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]); 969 rtap_len += 2; 970 971 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]); 972 rtap_len += 2; 973 974 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]); 975 } 976 977 static void 978 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status, 979 u8 *rtap_buf) 980 { 981 u32 rtap_len = 0; 982 983 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]); 984 rtap_len += 2; 985 986 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]); 987 rtap_len += 2; 988 989 rtap_buf[rtap_len] = rx_status->he_RU[0]; 990 rtap_len += 1; 991 992 rtap_buf[rtap_len] = rx_status->he_RU[1]; 993 rtap_len += 1; 994 995 rtap_buf[rtap_len] = rx_status->he_RU[2]; 996 rtap_len += 1; 997 998 rtap_buf[rtap_len] = rx_status->he_RU[3]; 999 } 1000 1001 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar, 1002 struct hal_rx_mon_ppdu_info *ppduinfo, 1003 struct sk_buff *mon_skb, 1004 struct ieee80211_rx_status *rxs) 1005 { 1006 struct ieee80211_supported_band *sband; 1007 u8 *ptr = NULL; 1008 u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid]; 1009 1010 rxs->flag |= RX_FLAG_MACTIME_START; 1011 rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR; 1012 rxs->nss = ppduinfo->nss + 1; 1013 1014 if (ampdu_id) { 1015 rxs->flag |= RX_FLAG_AMPDU_DETAILS; 1016 rxs->ampdu_reference = ampdu_id; 1017 } 1018 1019 if (ppduinfo->he_mu_flags) { 1020 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; 1021 rxs->encoding = RX_ENC_HE; 1022 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); 1023 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr); 1024 } else if (ppduinfo->he_flags) { 1025 rxs->flag |= RX_FLAG_RADIOTAP_HE; 1026 rxs->encoding = RX_ENC_HE; 1027 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); 1028 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr); 1029 rxs->rate_idx = ppduinfo->rate; 1030 } else if (ppduinfo->vht_flags) { 1031 rxs->encoding = RX_ENC_VHT; 1032 rxs->rate_idx = ppduinfo->rate; 1033 } else if (ppduinfo->ht_flags) { 1034 rxs->encoding = RX_ENC_HT; 1035 rxs->rate_idx = ppduinfo->rate; 1036 } else { 1037 rxs->encoding = RX_ENC_LEGACY; 1038 sband = &ar->mac.sbands[rxs->band]; 1039 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate, 1040 ppduinfo->cck_flag); 1041 } 1042 1043 rxs->mactime = ppduinfo->tsft; 1044 } 1045 1046 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 1047 struct sk_buff *msdu, 1048 struct ieee80211_rx_status *status) 1049 { 1050 static const struct ieee80211_radiotap_he known = { 1051 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1052 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1053 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1054 }; 1055 struct ieee80211_rx_status *rx_status; 1056 struct ieee80211_radiotap_he *he = NULL; 1057 struct ieee80211_sta *pubsta = NULL; 1058 struct ath12k_peer *peer; 1059 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1060 u8 decap = DP_RX_DECAP_TYPE_RAW; 1061 bool is_mcbc = rxcb->is_mcbc; 1062 bool is_eapol_tkip = rxcb->is_eapol; 1063 1064 if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) && 1065 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 1066 he = skb_push(msdu, sizeof(known)); 1067 memcpy(he, &known, sizeof(known)); 1068 status->flag |= RX_FLAG_RADIOTAP_HE; 1069 } 1070 1071 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 1072 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc); 1073 spin_lock_bh(&ar->ab->base_lock); 1074 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 1075 if (peer && peer->sta) { 1076 pubsta = peer->sta; 1077 if (pubsta->valid_links) { 1078 status->link_valid = 1; 1079 status->link_id = peer->link_id; 1080 } 1081 } 1082 1083 spin_unlock_bh(&ar->ab->base_lock); 1084 1085 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 1086 "rx skb %p len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 1087 msdu, 1088 msdu->len, 1089 peer ? peer->addr : NULL, 1090 rxcb->tid, 1091 (is_mcbc) ? "mcast" : "ucast", 1092 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 1093 (status->encoding == RX_ENC_HT) ? "ht" : "", 1094 (status->encoding == RX_ENC_VHT) ? "vht" : "", 1095 (status->encoding == RX_ENC_HE) ? "he" : "", 1096 (status->bw == RATE_INFO_BW_40) ? "40" : "", 1097 (status->bw == RATE_INFO_BW_80) ? "80" : "", 1098 (status->bw == RATE_INFO_BW_160) ? "160" : "", 1099 (status->bw == RATE_INFO_BW_320) ? "320" : "", 1100 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 1101 status->rate_idx, 1102 status->nss, 1103 status->freq, 1104 status->band, status->flag, 1105 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 1106 !!(status->flag & RX_FLAG_MMIC_ERROR), 1107 !!(status->flag & RX_FLAG_AMSDU_MORE)); 1108 1109 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 1110 msdu->data, msdu->len); 1111 rx_status = IEEE80211_SKB_RXCB(msdu); 1112 *rx_status = *status; 1113 1114 /* TODO: trace rx packet */ 1115 1116 /* PN for multicast packets are not validate in HW, 1117 * so skip 802.3 rx path 1118 * Also, fast_rx expects the STA to be authorized, hence 1119 * eapol packets are sent in slow path. 1120 */ 1121 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip && 1122 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 1123 rx_status->flag |= RX_FLAG_8023; 1124 1125 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi); 1126 } 1127 1128 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id, 1129 struct sk_buff *head_msdu, struct sk_buff *tail_msdu, 1130 struct hal_rx_mon_ppdu_info *ppduinfo, 1131 struct napi_struct *napi) 1132 { 1133 struct ath12k_pdev_dp *dp = &ar->dp; 1134 struct sk_buff *mon_skb, *skb_next, *header; 1135 struct ieee80211_rx_status *rxs = &dp->rx_status; 1136 bool fcs_err = false; 1137 1138 mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id, 1139 head_msdu, tail_msdu, 1140 rxs, &fcs_err); 1141 if (!mon_skb) 1142 goto mon_deliver_fail; 1143 1144 header = mon_skb; 1145 rxs->flag = 0; 1146 1147 if (fcs_err) 1148 rxs->flag = RX_FLAG_FAILED_FCS_CRC; 1149 1150 do { 1151 skb_next = mon_skb->next; 1152 if (!skb_next) 1153 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 1154 else 1155 rxs->flag |= RX_FLAG_AMSDU_MORE; 1156 1157 if (mon_skb == header) { 1158 header = NULL; 1159 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 1160 } else { 1161 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 1162 } 1163 rxs->flag |= RX_FLAG_ONLY_MONITOR; 1164 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs); 1165 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs); 1166 mon_skb = skb_next; 1167 } while (mon_skb); 1168 rxs->flag = 0; 1169 1170 return 0; 1171 1172 mon_deliver_fail: 1173 mon_skb = head_msdu; 1174 while (mon_skb) { 1175 skb_next = mon_skb->next; 1176 dev_kfree_skb_any(mon_skb); 1177 mon_skb = skb_next; 1178 } 1179 return -EINVAL; 1180 } 1181 1182 static enum hal_rx_mon_status 1183 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon, 1184 struct sk_buff *skb) 1185 { 1186 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1187 struct hal_tlv_64_hdr *tlv; 1188 enum hal_rx_mon_status hal_status; 1189 u32 tlv_userid; 1190 u16 tlv_tag, tlv_len; 1191 u8 *ptr = skb->data; 1192 1193 memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info)); 1194 1195 do { 1196 tlv = (struct hal_tlv_64_hdr *)ptr; 1197 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG); 1198 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN); 1199 tlv_userid = le64_get_bits(tlv->tl, HAL_TLV_64_USR_ID); 1200 ptr += sizeof(*tlv); 1201 1202 /* The actual length of PPDU_END is the combined length of many PHY 1203 * TLVs that follow. Skip the TLV header and 1204 * rx_rxpcu_classification_overview that follows the header to get to 1205 * next TLV. 1206 */ 1207 1208 if (tlv_tag == HAL_RX_PPDU_END) 1209 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 1210 1211 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon, 1212 tlv_tag, ptr, tlv_userid); 1213 ptr += tlv_len; 1214 ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN); 1215 1216 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) 1217 break; 1218 1219 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); 1220 1221 return hal_status; 1222 } 1223 1224 enum hal_rx_mon_status 1225 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar, 1226 struct ath12k_mon_data *pmon, 1227 int mac_id, 1228 struct sk_buff *skb, 1229 struct napi_struct *napi) 1230 { 1231 struct ath12k_base *ab = ar->ab; 1232 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1233 struct dp_mon_mpdu *tmp; 1234 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 1235 struct sk_buff *head_msdu, *tail_msdu; 1236 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; 1237 1238 ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); 1239 1240 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) { 1241 list_del(&mon_mpdu->list); 1242 head_msdu = mon_mpdu->head; 1243 tail_msdu = mon_mpdu->tail; 1244 1245 if (head_msdu && tail_msdu) { 1246 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, 1247 tail_msdu, ppdu_info, napi); 1248 } 1249 1250 kfree(mon_mpdu); 1251 } 1252 return hal_status; 1253 } 1254 1255 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab, 1256 struct dp_rxdma_mon_ring *buf_ring, 1257 int req_entries) 1258 { 1259 struct hal_mon_buf_ring *mon_buf; 1260 struct sk_buff *skb; 1261 struct hal_srng *srng; 1262 dma_addr_t paddr; 1263 u32 cookie; 1264 int buf_id; 1265 1266 srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id]; 1267 spin_lock_bh(&srng->lock); 1268 ath12k_hal_srng_access_begin(ab, srng); 1269 1270 while (req_entries > 0) { 1271 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE); 1272 if (unlikely(!skb)) 1273 goto fail_alloc_skb; 1274 1275 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) { 1276 skb_pull(skb, 1277 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 1278 skb->data); 1279 } 1280 1281 paddr = dma_map_single(ab->dev, skb->data, 1282 skb->len + skb_tailroom(skb), 1283 DMA_FROM_DEVICE); 1284 1285 if (unlikely(dma_mapping_error(ab->dev, paddr))) 1286 goto fail_free_skb; 1287 1288 spin_lock_bh(&buf_ring->idr_lock); 1289 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0, 1290 buf_ring->bufs_max * 3, GFP_ATOMIC); 1291 spin_unlock_bh(&buf_ring->idr_lock); 1292 1293 if (unlikely(buf_id < 0)) 1294 goto fail_dma_unmap; 1295 1296 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng); 1297 if (unlikely(!mon_buf)) 1298 goto fail_idr_remove; 1299 1300 ATH12K_SKB_RXCB(skb)->paddr = paddr; 1301 1302 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID); 1303 1304 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr)); 1305 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr)); 1306 mon_buf->cookie = cpu_to_le64(cookie); 1307 1308 req_entries--; 1309 } 1310 1311 ath12k_hal_srng_access_end(ab, srng); 1312 spin_unlock_bh(&srng->lock); 1313 return 0; 1314 1315 fail_idr_remove: 1316 spin_lock_bh(&buf_ring->idr_lock); 1317 idr_remove(&buf_ring->bufs_idr, buf_id); 1318 spin_unlock_bh(&buf_ring->idr_lock); 1319 fail_dma_unmap: 1320 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 1321 DMA_FROM_DEVICE); 1322 fail_free_skb: 1323 dev_kfree_skb_any(skb); 1324 fail_alloc_skb: 1325 ath12k_hal_srng_access_end(ab, srng); 1326 spin_unlock_bh(&srng->lock); 1327 return -ENOMEM; 1328 } 1329 1330 static struct dp_mon_tx_ppdu_info * 1331 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon, 1332 unsigned int ppdu_id, 1333 enum dp_mon_tx_ppdu_info_type type) 1334 { 1335 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1336 1337 if (type == DP_MON_TX_PROT_PPDU_INFO) { 1338 tx_ppdu_info = pmon->tx_prot_ppdu_info; 1339 1340 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1341 return tx_ppdu_info; 1342 kfree(tx_ppdu_info); 1343 } else { 1344 tx_ppdu_info = pmon->tx_data_ppdu_info; 1345 1346 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1347 return tx_ppdu_info; 1348 kfree(tx_ppdu_info); 1349 } 1350 1351 /* allocate new tx_ppdu_info */ 1352 tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC); 1353 if (!tx_ppdu_info) 1354 return NULL; 1355 1356 tx_ppdu_info->is_used = 0; 1357 tx_ppdu_info->ppdu_id = ppdu_id; 1358 1359 if (type == DP_MON_TX_PROT_PPDU_INFO) 1360 pmon->tx_prot_ppdu_info = tx_ppdu_info; 1361 else 1362 pmon->tx_data_ppdu_info = tx_ppdu_info; 1363 1364 return tx_ppdu_info; 1365 } 1366 1367 static struct dp_mon_tx_ppdu_info * 1368 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon, 1369 u16 tlv_tag) 1370 { 1371 switch (tlv_tag) { 1372 case HAL_TX_FES_SETUP: 1373 case HAL_TX_FLUSH: 1374 case HAL_PCU_PPDU_SETUP_INIT: 1375 case HAL_TX_PEER_ENTRY: 1376 case HAL_TX_QUEUE_EXTENSION: 1377 case HAL_TX_MPDU_START: 1378 case HAL_TX_MSDU_START: 1379 case HAL_TX_DATA: 1380 case HAL_MON_BUF_ADDR: 1381 case HAL_TX_MPDU_END: 1382 case HAL_TX_LAST_MPDU_FETCHED: 1383 case HAL_TX_LAST_MPDU_END: 1384 case HAL_COEX_TX_REQ: 1385 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP: 1386 case HAL_SCH_CRITICAL_TLV_REFERENCE: 1387 case HAL_TX_FES_SETUP_COMPLETE: 1388 case HAL_TQM_MPDU_GLOBAL_START: 1389 case HAL_SCHEDULER_END: 1390 case HAL_TX_FES_STATUS_USER_PPDU: 1391 break; 1392 case HAL_TX_FES_STATUS_PROT: { 1393 if (!pmon->tx_prot_ppdu_info->is_used) 1394 pmon->tx_prot_ppdu_info->is_used = true; 1395 1396 return pmon->tx_prot_ppdu_info; 1397 } 1398 } 1399 1400 if (!pmon->tx_data_ppdu_info->is_used) 1401 pmon->tx_data_ppdu_info->is_used = true; 1402 1403 return pmon->tx_data_ppdu_info; 1404 } 1405 1406 #define MAX_MONITOR_HEADER 512 1407 #define MAX_DUMMY_FRM_BODY 128 1408 1409 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void) 1410 { 1411 struct sk_buff *skb; 1412 1413 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY); 1414 if (!skb) 1415 return NULL; 1416 1417 skb_reserve(skb, MAX_MONITOR_HEADER); 1418 1419 if (!IS_ALIGNED((unsigned long)skb->data, 4)) 1420 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data); 1421 1422 return skb; 1423 } 1424 1425 static int 1426 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1427 { 1428 struct sk_buff *skb; 1429 struct ieee80211_cts *cts; 1430 1431 skb = ath12k_dp_mon_tx_alloc_skb(); 1432 if (!skb) 1433 return -ENOMEM; 1434 1435 cts = (struct ieee80211_cts *)skb->data; 1436 memset(cts, 0, MAX_DUMMY_FRM_BODY); 1437 cts->frame_control = 1438 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS); 1439 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1440 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra)); 1441 1442 skb_put(skb, sizeof(*cts)); 1443 tx_ppdu_info->tx_mon_mpdu->head = skb; 1444 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1445 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1446 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1447 1448 return 0; 1449 } 1450 1451 static int 1452 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1453 { 1454 struct sk_buff *skb; 1455 struct ieee80211_rts *rts; 1456 1457 skb = ath12k_dp_mon_tx_alloc_skb(); 1458 if (!skb) 1459 return -ENOMEM; 1460 1461 rts = (struct ieee80211_rts *)skb->data; 1462 memset(rts, 0, MAX_DUMMY_FRM_BODY); 1463 rts->frame_control = 1464 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS); 1465 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1466 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra)); 1467 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta)); 1468 1469 skb_put(skb, sizeof(*rts)); 1470 tx_ppdu_info->tx_mon_mpdu->head = skb; 1471 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1472 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1473 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1474 1475 return 0; 1476 } 1477 1478 static int 1479 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1480 { 1481 struct sk_buff *skb; 1482 struct ieee80211_qos_hdr *qhdr; 1483 1484 skb = ath12k_dp_mon_tx_alloc_skb(); 1485 if (!skb) 1486 return -ENOMEM; 1487 1488 qhdr = (struct ieee80211_qos_hdr *)skb->data; 1489 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 1490 qhdr->frame_control = 1491 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 1492 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1493 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1494 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 1495 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 1496 1497 skb_put(skb, sizeof(*qhdr)); 1498 tx_ppdu_info->tx_mon_mpdu->head = skb; 1499 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1500 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1501 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1502 1503 return 0; 1504 } 1505 1506 static int 1507 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1508 { 1509 struct sk_buff *skb; 1510 struct dp_mon_qosframe_addr4 *qhdr; 1511 1512 skb = ath12k_dp_mon_tx_alloc_skb(); 1513 if (!skb) 1514 return -ENOMEM; 1515 1516 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data; 1517 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 1518 qhdr->frame_control = 1519 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 1520 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1521 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1522 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 1523 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 1524 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN); 1525 1526 skb_put(skb, sizeof(*qhdr)); 1527 tx_ppdu_info->tx_mon_mpdu->head = skb; 1528 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1529 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1530 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1531 1532 return 0; 1533 } 1534 1535 static int 1536 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1537 { 1538 struct sk_buff *skb; 1539 struct dp_mon_frame_min_one *fbmhdr; 1540 1541 skb = ath12k_dp_mon_tx_alloc_skb(); 1542 if (!skb) 1543 return -ENOMEM; 1544 1545 fbmhdr = (struct dp_mon_frame_min_one *)skb->data; 1546 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY); 1547 fbmhdr->frame_control = 1548 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK); 1549 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1550 1551 /* set duration zero for ack frame */ 1552 fbmhdr->duration = 0; 1553 1554 skb_put(skb, sizeof(*fbmhdr)); 1555 tx_ppdu_info->tx_mon_mpdu->head = skb; 1556 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1557 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1558 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1559 1560 return 0; 1561 } 1562 1563 static int 1564 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1565 { 1566 int ret = 0; 1567 1568 switch (tx_ppdu_info->rx_status.medium_prot_type) { 1569 case DP_MON_TX_MEDIUM_RTS_LEGACY: 1570 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW: 1571 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW: 1572 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info); 1573 break; 1574 case DP_MON_TX_MEDIUM_CTS2SELF: 1575 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 1576 break; 1577 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR: 1578 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info); 1579 break; 1580 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR: 1581 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info); 1582 break; 1583 } 1584 1585 return ret; 1586 } 1587 1588 static enum dp_mon_tx_tlv_status 1589 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab, 1590 struct ath12k_mon_data *pmon, 1591 u16 tlv_tag, const void *tlv_data, u32 userid) 1592 { 1593 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1594 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1595 u32 info[7]; 1596 1597 tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag); 1598 1599 switch (tlv_tag) { 1600 case HAL_TX_FES_SETUP: { 1601 const struct hal_tx_fes_setup *tx_fes_setup = tlv_data; 1602 1603 info[0] = __le32_to_cpu(tx_fes_setup->info0); 1604 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id); 1605 tx_ppdu_info->num_users = 1606 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 1607 status = DP_MON_TX_FES_SETUP; 1608 break; 1609 } 1610 1611 case HAL_TX_FES_STATUS_END: { 1612 const struct hal_tx_fes_status_end *tx_fes_status_end = tlv_data; 1613 u32 tst_15_0, tst_31_16; 1614 1615 info[0] = __le32_to_cpu(tx_fes_status_end->info0); 1616 tst_15_0 = 1617 u32_get_bits(info[0], 1618 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0); 1619 tst_31_16 = 1620 u32_get_bits(info[0], 1621 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16); 1622 1623 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16)); 1624 status = DP_MON_TX_FES_STATUS_END; 1625 break; 1626 } 1627 1628 case HAL_RX_RESPONSE_REQUIRED_INFO: { 1629 const struct hal_rx_resp_req_info *rx_resp_req_info = tlv_data; 1630 u32 addr_32; 1631 u16 addr_16; 1632 1633 info[0] = __le32_to_cpu(rx_resp_req_info->info0); 1634 info[1] = __le32_to_cpu(rx_resp_req_info->info1); 1635 info[2] = __le32_to_cpu(rx_resp_req_info->info2); 1636 info[3] = __le32_to_cpu(rx_resp_req_info->info3); 1637 info[4] = __le32_to_cpu(rx_resp_req_info->info4); 1638 info[5] = __le32_to_cpu(rx_resp_req_info->info5); 1639 1640 tx_ppdu_info->rx_status.ppdu_id = 1641 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID); 1642 tx_ppdu_info->rx_status.reception_type = 1643 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE); 1644 tx_ppdu_info->rx_status.rx_duration = 1645 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION); 1646 tx_ppdu_info->rx_status.mcs = 1647 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS); 1648 tx_ppdu_info->rx_status.sgi = 1649 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI); 1650 tx_ppdu_info->rx_status.is_stbc = 1651 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC); 1652 tx_ppdu_info->rx_status.ldpc = 1653 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC); 1654 tx_ppdu_info->rx_status.is_ampdu = 1655 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU); 1656 tx_ppdu_info->rx_status.num_users = 1657 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER); 1658 1659 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0); 1660 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32); 1661 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1662 1663 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0); 1664 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16); 1665 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 1666 1667 if (tx_ppdu_info->rx_status.reception_type == 0) 1668 ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 1669 status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 1670 break; 1671 } 1672 1673 case HAL_PCU_PPDU_SETUP_INIT: { 1674 const struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = tlv_data; 1675 u32 addr_32; 1676 u16 addr_16; 1677 1678 info[0] = __le32_to_cpu(ppdu_setup->info0); 1679 info[1] = __le32_to_cpu(ppdu_setup->info1); 1680 info[2] = __le32_to_cpu(ppdu_setup->info2); 1681 info[3] = __le32_to_cpu(ppdu_setup->info3); 1682 info[4] = __le32_to_cpu(ppdu_setup->info4); 1683 info[5] = __le32_to_cpu(ppdu_setup->info5); 1684 info[6] = __le32_to_cpu(ppdu_setup->info6); 1685 1686 /* protection frame address 1 */ 1687 addr_32 = u32_get_bits(info[1], 1688 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0); 1689 addr_16 = u32_get_bits(info[2], 1690 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32); 1691 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1692 1693 /* protection frame address 2 */ 1694 addr_16 = u32_get_bits(info[2], 1695 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0); 1696 addr_32 = u32_get_bits(info[3], 1697 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16); 1698 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 1699 1700 /* protection frame address 3 */ 1701 addr_32 = u32_get_bits(info[4], 1702 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0); 1703 addr_16 = u32_get_bits(info[5], 1704 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32); 1705 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3); 1706 1707 /* protection frame address 4 */ 1708 addr_16 = u32_get_bits(info[5], 1709 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0); 1710 addr_32 = u32_get_bits(info[6], 1711 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16); 1712 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4); 1713 1714 status = u32_get_bits(info[0], 1715 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE); 1716 break; 1717 } 1718 1719 case HAL_TX_QUEUE_EXTENSION: { 1720 const struct hal_tx_queue_exten *tx_q_exten = tlv_data; 1721 1722 info[0] = __le32_to_cpu(tx_q_exten->info0); 1723 1724 tx_ppdu_info->rx_status.frame_control = 1725 u32_get_bits(info[0], 1726 HAL_TX_Q_EXT_INFO0_FRAME_CTRL); 1727 tx_ppdu_info->rx_status.fc_valid = true; 1728 break; 1729 } 1730 1731 case HAL_TX_FES_STATUS_START: { 1732 const struct hal_tx_fes_status_start *tx_fes_start = tlv_data; 1733 1734 info[0] = __le32_to_cpu(tx_fes_start->info0); 1735 1736 tx_ppdu_info->rx_status.medium_prot_type = 1737 u32_get_bits(info[0], 1738 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE); 1739 break; 1740 } 1741 1742 case HAL_TX_FES_STATUS_PROT: { 1743 const struct hal_tx_fes_status_prot *tx_fes_status = tlv_data; 1744 u32 start_timestamp; 1745 u32 end_timestamp; 1746 1747 info[0] = __le32_to_cpu(tx_fes_status->info0); 1748 info[1] = __le32_to_cpu(tx_fes_status->info1); 1749 1750 start_timestamp = 1751 u32_get_bits(info[0], 1752 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0); 1753 start_timestamp |= 1754 u32_get_bits(info[0], 1755 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15; 1756 end_timestamp = 1757 u32_get_bits(info[1], 1758 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0); 1759 end_timestamp |= 1760 u32_get_bits(info[1], 1761 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15; 1762 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp; 1763 1764 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info); 1765 break; 1766 } 1767 1768 case HAL_TX_FES_STATUS_START_PPDU: 1769 case HAL_TX_FES_STATUS_START_PROT: { 1770 const struct hal_tx_fes_status_start_prot *tx_fes_stat_start = tlv_data; 1771 u64 ppdu_ts; 1772 1773 info[0] = __le32_to_cpu(tx_fes_stat_start->info0); 1774 1775 tx_ppdu_info->rx_status.ppdu_ts = 1776 u32_get_bits(info[0], 1777 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32); 1778 ppdu_ts = (u32_get_bits(info[1], 1779 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32)); 1780 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32; 1781 break; 1782 } 1783 1784 case HAL_TX_FES_STATUS_USER_PPDU: { 1785 const struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = tlv_data; 1786 1787 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0); 1788 1789 tx_ppdu_info->rx_status.rx_duration = 1790 u32_get_bits(info[0], 1791 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION); 1792 break; 1793 } 1794 1795 case HAL_MACTX_HE_SIG_A_SU: 1796 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status); 1797 break; 1798 1799 case HAL_MACTX_HE_SIG_A_MU_DL: 1800 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status); 1801 break; 1802 1803 case HAL_MACTX_HE_SIG_B1_MU: 1804 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status); 1805 break; 1806 1807 case HAL_MACTX_HE_SIG_B2_MU: 1808 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status); 1809 break; 1810 1811 case HAL_MACTX_HE_SIG_B2_OFDMA: 1812 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status); 1813 break; 1814 1815 case HAL_MACTX_VHT_SIG_A: 1816 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status); 1817 break; 1818 1819 case HAL_MACTX_L_SIG_A: 1820 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status); 1821 break; 1822 1823 case HAL_MACTX_L_SIG_B: 1824 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status); 1825 break; 1826 1827 case HAL_RX_FRAME_BITMAP_ACK: { 1828 const struct hal_rx_frame_bitmap_ack *fbm_ack = tlv_data; 1829 u32 addr_32; 1830 u16 addr_16; 1831 1832 info[0] = __le32_to_cpu(fbm_ack->info0); 1833 info[1] = __le32_to_cpu(fbm_ack->info1); 1834 1835 addr_32 = u32_get_bits(info[0], 1836 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0); 1837 addr_16 = u32_get_bits(info[1], 1838 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32); 1839 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1840 1841 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info); 1842 break; 1843 } 1844 1845 case HAL_MACTX_PHY_DESC: { 1846 const struct hal_tx_phy_desc *tx_phy_desc = tlv_data; 1847 1848 info[0] = __le32_to_cpu(tx_phy_desc->info0); 1849 info[1] = __le32_to_cpu(tx_phy_desc->info1); 1850 info[2] = __le32_to_cpu(tx_phy_desc->info2); 1851 info[3] = __le32_to_cpu(tx_phy_desc->info3); 1852 1853 tx_ppdu_info->rx_status.beamformed = 1854 u32_get_bits(info[0], 1855 HAL_TX_PHY_DESC_INFO0_BF_TYPE); 1856 tx_ppdu_info->rx_status.preamble_type = 1857 u32_get_bits(info[0], 1858 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B); 1859 tx_ppdu_info->rx_status.mcs = 1860 u32_get_bits(info[1], 1861 HAL_TX_PHY_DESC_INFO1_MCS); 1862 tx_ppdu_info->rx_status.ltf_size = 1863 u32_get_bits(info[3], 1864 HAL_TX_PHY_DESC_INFO3_LTF_SIZE); 1865 tx_ppdu_info->rx_status.nss = 1866 u32_get_bits(info[2], 1867 HAL_TX_PHY_DESC_INFO2_NSS); 1868 tx_ppdu_info->rx_status.chan_num = 1869 u32_get_bits(info[3], 1870 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL); 1871 tx_ppdu_info->rx_status.bw = 1872 u32_get_bits(info[0], 1873 HAL_TX_PHY_DESC_INFO0_BANDWIDTH); 1874 break; 1875 } 1876 1877 case HAL_TX_MPDU_START: { 1878 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu; 1879 1880 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 1881 if (!mon_mpdu) 1882 return DP_MON_TX_STATUS_PPDU_NOT_DONE; 1883 status = DP_MON_TX_MPDU_START; 1884 break; 1885 } 1886 1887 case HAL_TX_MPDU_END: 1888 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1889 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1890 break; 1891 } 1892 1893 return status; 1894 } 1895 1896 enum dp_mon_tx_tlv_status 1897 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag, 1898 struct hal_tlv_hdr *tx_tlv, 1899 u8 *num_users) 1900 { 1901 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1902 u32 info0; 1903 1904 switch (tlv_tag) { 1905 case HAL_TX_FES_SETUP: { 1906 struct hal_tx_fes_setup *tx_fes_setup = 1907 (struct hal_tx_fes_setup *)tx_tlv; 1908 1909 info0 = __le32_to_cpu(tx_fes_setup->info0); 1910 1911 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 1912 tlv_status = DP_MON_TX_FES_SETUP; 1913 break; 1914 } 1915 1916 case HAL_RX_RESPONSE_REQUIRED_INFO: { 1917 /* TODO: need to update *num_users */ 1918 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 1919 break; 1920 } 1921 } 1922 1923 return tlv_status; 1924 } 1925 1926 static void 1927 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id, 1928 struct napi_struct *napi, 1929 struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1930 { 1931 struct dp_mon_mpdu *tmp, *mon_mpdu; 1932 struct sk_buff *head_msdu, *tail_msdu; 1933 1934 list_for_each_entry_safe(mon_mpdu, tmp, 1935 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) { 1936 list_del(&mon_mpdu->list); 1937 head_msdu = mon_mpdu->head; 1938 tail_msdu = mon_mpdu->tail; 1939 1940 if (head_msdu) 1941 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, tail_msdu, 1942 &tx_ppdu_info->rx_status, napi); 1943 1944 kfree(mon_mpdu); 1945 } 1946 } 1947 1948 enum hal_rx_mon_status 1949 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar, 1950 struct ath12k_mon_data *pmon, 1951 int mac_id, 1952 struct sk_buff *skb, 1953 struct napi_struct *napi, 1954 u32 ppdu_id) 1955 { 1956 struct ath12k_base *ab = ar->ab; 1957 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info; 1958 struct hal_tlv_hdr *tlv; 1959 u8 *ptr = skb->data; 1960 u16 tlv_tag; 1961 u16 tlv_len; 1962 u32 tlv_userid = 0; 1963 u8 num_user; 1964 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1965 1966 tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 1967 DP_MON_TX_PROT_PPDU_INFO); 1968 if (!tx_prot_ppdu_info) 1969 return -ENOMEM; 1970 1971 tlv = (struct hal_tlv_hdr *)ptr; 1972 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 1973 1974 tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user); 1975 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user) 1976 return -EINVAL; 1977 1978 tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 1979 DP_MON_TX_DATA_PPDU_INFO); 1980 if (!tx_data_ppdu_info) 1981 return -ENOMEM; 1982 1983 do { 1984 tlv = (struct hal_tlv_hdr *)ptr; 1985 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 1986 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); 1987 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); 1988 1989 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon, 1990 tlv_tag, ptr, 1991 tlv_userid); 1992 ptr += tlv_len; 1993 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 1994 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE) 1995 break; 1996 } while (tlv_status != DP_MON_TX_FES_STATUS_END); 1997 1998 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info); 1999 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info); 2000 2001 return tlv_status; 2002 } 2003 2004 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget, 2005 enum dp_monitor_mode monitor_mode, 2006 struct napi_struct *napi) 2007 { 2008 struct hal_mon_dest_desc *mon_dst_desc; 2009 struct ath12k_pdev_dp *pdev_dp = &ar->dp; 2010 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 2011 struct ath12k_base *ab = ar->ab; 2012 struct ath12k_dp *dp = &ab->dp; 2013 struct sk_buff *skb; 2014 struct ath12k_skb_rxcb *rxcb; 2015 struct dp_srng *mon_dst_ring; 2016 struct hal_srng *srng; 2017 struct dp_rxdma_mon_ring *buf_ring; 2018 u64 cookie; 2019 u32 ppdu_id; 2020 int num_buffs_reaped = 0, srng_id, buf_id; 2021 u8 dest_idx = 0, i; 2022 bool end_of_ppdu; 2023 struct hal_rx_mon_ppdu_info *ppdu_info; 2024 struct ath12k_peer *peer = NULL; 2025 2026 ppdu_info = &pmon->mon_ppdu_info; 2027 memset(ppdu_info, 0, sizeof(*ppdu_info)); 2028 ppdu_info->peer_id = HAL_INVALID_PEERID; 2029 2030 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 2031 2032 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) { 2033 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 2034 buf_ring = &dp->rxdma_mon_buf_ring; 2035 } else { 2036 return 0; 2037 } 2038 2039 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 2040 2041 spin_lock_bh(&srng->lock); 2042 ath12k_hal_srng_access_begin(ab, srng); 2043 2044 while (likely(*budget)) { 2045 *budget -= 1; 2046 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 2047 if (unlikely(!mon_dst_desc)) 2048 break; 2049 2050 cookie = le32_to_cpu(mon_dst_desc->cookie); 2051 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2052 2053 spin_lock_bh(&buf_ring->idr_lock); 2054 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 2055 spin_unlock_bh(&buf_ring->idr_lock); 2056 2057 if (unlikely(!skb)) { 2058 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 2059 buf_id); 2060 goto move_next; 2061 } 2062 2063 rxcb = ATH12K_SKB_RXCB(skb); 2064 dma_unmap_single(ab->dev, rxcb->paddr, 2065 skb->len + skb_tailroom(skb), 2066 DMA_FROM_DEVICE); 2067 2068 pmon->dest_skb_q[dest_idx] = skb; 2069 dest_idx++; 2070 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id); 2071 end_of_ppdu = le32_get_bits(mon_dst_desc->info0, 2072 HAL_MON_DEST_INFO0_END_OF_PPDU); 2073 if (!end_of_ppdu) 2074 continue; 2075 2076 for (i = 0; i < dest_idx; i++) { 2077 skb = pmon->dest_skb_q[i]; 2078 2079 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) 2080 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id, 2081 skb, napi); 2082 else 2083 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id, 2084 skb, napi, ppdu_id); 2085 2086 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); 2087 2088 if (!peer || !peer->sta) { 2089 ath12k_dbg(ab, ATH12K_DBG_DATA, 2090 "failed to find the peer with peer_id %d\n", 2091 ppdu_info->peer_id); 2092 dev_kfree_skb_any(skb); 2093 continue; 2094 } 2095 2096 dev_kfree_skb_any(skb); 2097 pmon->dest_skb_q[i] = NULL; 2098 } 2099 2100 dest_idx = 0; 2101 move_next: 2102 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 2103 ath12k_hal_srng_src_get_next_entry(ab, srng); 2104 num_buffs_reaped++; 2105 } 2106 2107 ath12k_hal_srng_access_end(ab, srng); 2108 spin_unlock_bh(&srng->lock); 2109 2110 return num_buffs_reaped; 2111 } 2112 2113 static void 2114 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats, 2115 struct hal_rx_mon_ppdu_info *ppdu_info, 2116 struct hal_rx_user_status *user_stats, 2117 u32 num_msdu) 2118 { 2119 u32 rate_idx = 0; 2120 u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs; 2121 u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1; 2122 u32 bw_idx = ppdu_info->bw; 2123 u32 gi_idx = ppdu_info->gi; 2124 2125 if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) || 2126 (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) { 2127 return; 2128 } 2129 2130 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N || 2131 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) { 2132 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx; 2133 rate_idx += bw_idx * 2 + gi_idx; 2134 } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) { 2135 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi); 2136 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx; 2137 rate_idx += bw_idx * 3 + gi_idx; 2138 } else { 2139 return; 2140 } 2141 2142 rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu; 2143 if (user_stats) 2144 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count; 2145 else 2146 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len; 2147 } 2148 2149 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar, 2150 struct ath12k_link_sta *arsta, 2151 struct hal_rx_mon_ppdu_info *ppdu_info) 2152 { 2153 struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats; 2154 u32 num_msdu; 2155 2156 if (!rx_stats) 2157 return; 2158 2159 arsta->rssi_comb = ppdu_info->rssi_comb; 2160 2161 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2162 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2163 2164 rx_stats->num_msdu += num_msdu; 2165 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2166 ppdu_info->tcp_ack_msdu_count; 2167 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2168 rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2169 2170 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2171 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2172 ppdu_info->nss = 1; 2173 ppdu_info->mcs = HAL_RX_MAX_MCS; 2174 ppdu_info->tid = IEEE80211_NUM_TIDS; 2175 } 2176 2177 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2178 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2179 2180 if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2181 rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2182 2183 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2184 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2185 2186 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2187 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2188 2189 if (ppdu_info->is_stbc) 2190 rx_stats->stbc_count += num_msdu; 2191 2192 if (ppdu_info->beamformed) 2193 rx_stats->beamformed_count += num_msdu; 2194 2195 if (ppdu_info->num_mpdu_fcs_ok > 1) 2196 rx_stats->ampdu_msdu_count += num_msdu; 2197 else 2198 rx_stats->non_ampdu_msdu_count += num_msdu; 2199 2200 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2201 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 2202 rx_stats->dcm_count += ppdu_info->dcm; 2203 2204 rx_stats->rx_duration += ppdu_info->rx_duration; 2205 arsta->rx_duration = rx_stats->rx_duration; 2206 2207 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) { 2208 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu; 2209 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len; 2210 } 2211 2212 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N && 2213 ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) { 2214 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu; 2215 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2216 /* To fit into rate table for HT packets */ 2217 ppdu_info->mcs = ppdu_info->mcs % 8; 2218 } 2219 2220 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC && 2221 ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) { 2222 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu; 2223 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2224 } 2225 2226 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX && 2227 ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) { 2228 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu; 2229 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2230 } 2231 2232 if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2233 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) && 2234 ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) { 2235 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu; 2236 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len; 2237 } 2238 2239 if (ppdu_info->gi < HAL_RX_GI_MAX) { 2240 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu; 2241 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len; 2242 } 2243 2244 if (ppdu_info->bw < HAL_RX_BW_MAX) { 2245 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu; 2246 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len; 2247 } 2248 2249 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info, 2250 NULL, num_msdu); 2251 } 2252 2253 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info) 2254 { 2255 struct hal_rx_user_status *rx_user_status; 2256 u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size; 2257 2258 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO || 2259 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 2260 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)) 2261 return; 2262 2263 num_users = ppdu_info->num_users; 2264 if (num_users > HAL_MAX_UL_MU_USERS) 2265 num_users = HAL_MAX_UL_MU_USERS; 2266 2267 for (i = 0; i < num_users; i++) { 2268 rx_user_status = &ppdu_info->userstats[i]; 2269 mu_ul_user_v0_word0 = 2270 rx_user_status->ul_ofdma_user_v0_word0; 2271 mu_ul_user_v0_word1 = 2272 rx_user_status->ul_ofdma_user_v0_word1; 2273 2274 if (u32_get_bits(mu_ul_user_v0_word0, 2275 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) && 2276 !u32_get_bits(mu_ul_user_v0_word0, 2277 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) { 2278 rx_user_status->mcs = 2279 u32_get_bits(mu_ul_user_v0_word1, 2280 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS); 2281 rx_user_status->nss = 2282 u32_get_bits(mu_ul_user_v0_word1, 2283 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1; 2284 2285 rx_user_status->ofdma_info_valid = 1; 2286 rx_user_status->ul_ofdma_ru_start_index = 2287 u32_get_bits(mu_ul_user_v0_word1, 2288 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START); 2289 2290 ru_size = u32_get_bits(mu_ul_user_v0_word1, 2291 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE); 2292 rx_user_status->ul_ofdma_ru_width = ru_size; 2293 rx_user_status->ul_ofdma_ru_size = ru_size; 2294 } 2295 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1, 2296 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC); 2297 } 2298 ppdu_info->ldpc = 1; 2299 } 2300 2301 static void 2302 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar, 2303 struct hal_rx_mon_ppdu_info *ppdu_info, 2304 u32 uid) 2305 { 2306 struct ath12k_sta *ahsta; 2307 struct ath12k_link_sta *arsta; 2308 struct ath12k_rx_peer_stats *rx_stats = NULL; 2309 struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid]; 2310 struct ath12k_peer *peer; 2311 u32 num_msdu; 2312 2313 if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF) 2314 return; 2315 2316 peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index); 2317 2318 if (!peer) { 2319 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n", 2320 user_stats->ast_index); 2321 return; 2322 } 2323 2324 ahsta = ath12k_sta_to_ahsta(peer->sta); 2325 arsta = &ahsta->deflink; 2326 rx_stats = arsta->rx_stats; 2327 2328 if (!rx_stats) 2329 return; 2330 2331 arsta->rssi_comb = ppdu_info->rssi_comb; 2332 2333 num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count + 2334 user_stats->udp_msdu_count + user_stats->other_msdu_count; 2335 2336 rx_stats->num_msdu += num_msdu; 2337 rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count + 2338 user_stats->tcp_ack_msdu_count; 2339 rx_stats->udp_msdu_count += user_stats->udp_msdu_count; 2340 rx_stats->other_msdu_count += user_stats->other_msdu_count; 2341 2342 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2343 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2344 2345 if (user_stats->tid <= IEEE80211_NUM_TIDS) 2346 rx_stats->tid_count[user_stats->tid] += num_msdu; 2347 2348 if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX) 2349 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu; 2350 2351 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2352 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2353 2354 if (ppdu_info->is_stbc) 2355 rx_stats->stbc_count += num_msdu; 2356 2357 if (ppdu_info->beamformed) 2358 rx_stats->beamformed_count += num_msdu; 2359 2360 if (user_stats->mpdu_cnt_fcs_ok > 1) 2361 rx_stats->ampdu_msdu_count += num_msdu; 2362 else 2363 rx_stats->non_ampdu_msdu_count += num_msdu; 2364 2365 rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok; 2366 rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err; 2367 rx_stats->dcm_count += ppdu_info->dcm; 2368 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 2369 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO) 2370 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu; 2371 2372 rx_stats->rx_duration += ppdu_info->rx_duration; 2373 arsta->rx_duration = rx_stats->rx_duration; 2374 2375 if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) { 2376 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu; 2377 rx_stats->byte_stats.nss_count[user_stats->nss - 1] += 2378 user_stats->mpdu_ok_byte_count; 2379 } 2380 2381 if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX && 2382 user_stats->mcs <= HAL_RX_MAX_MCS_HE) { 2383 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu; 2384 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] += 2385 user_stats->mpdu_ok_byte_count; 2386 } 2387 2388 if (ppdu_info->gi < HAL_RX_GI_MAX) { 2389 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu; 2390 rx_stats->byte_stats.gi_count[ppdu_info->gi] += 2391 user_stats->mpdu_ok_byte_count; 2392 } 2393 2394 if (ppdu_info->bw < HAL_RX_BW_MAX) { 2395 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu; 2396 rx_stats->byte_stats.bw_count[ppdu_info->bw] += 2397 user_stats->mpdu_ok_byte_count; 2398 } 2399 2400 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info, 2401 user_stats, num_msdu); 2402 } 2403 2404 static void 2405 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar, 2406 struct hal_rx_mon_ppdu_info *ppdu_info) 2407 { 2408 u32 num_users, i; 2409 2410 num_users = ppdu_info->num_users; 2411 if (num_users > HAL_MAX_UL_MU_USERS) 2412 num_users = HAL_MAX_UL_MU_USERS; 2413 2414 for (i = 0; i < num_users; i++) 2415 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i); 2416 } 2417 2418 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id, 2419 struct napi_struct *napi, int *budget) 2420 { 2421 struct ath12k_base *ab = ar->ab; 2422 struct ath12k_pdev_dp *pdev_dp = &ar->dp; 2423 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 2424 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 2425 struct ath12k_dp *dp = &ab->dp; 2426 struct hal_mon_dest_desc *mon_dst_desc; 2427 struct sk_buff *skb; 2428 struct ath12k_skb_rxcb *rxcb; 2429 struct dp_srng *mon_dst_ring; 2430 struct hal_srng *srng; 2431 struct dp_rxdma_mon_ring *buf_ring; 2432 struct ath12k_sta *ahsta = NULL; 2433 struct ath12k_link_sta *arsta; 2434 struct ath12k_peer *peer; 2435 u64 cookie; 2436 int num_buffs_reaped = 0, srng_id, buf_id; 2437 u8 dest_idx = 0, i; 2438 bool end_of_ppdu; 2439 u32 hal_status; 2440 2441 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 2442 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 2443 buf_ring = &dp->rxdma_mon_buf_ring; 2444 2445 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 2446 spin_lock_bh(&srng->lock); 2447 ath12k_hal_srng_access_begin(ab, srng); 2448 2449 while (likely(*budget)) { 2450 *budget -= 1; 2451 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 2452 if (unlikely(!mon_dst_desc)) 2453 break; 2454 cookie = le32_to_cpu(mon_dst_desc->cookie); 2455 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2456 2457 spin_lock_bh(&buf_ring->idr_lock); 2458 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 2459 spin_unlock_bh(&buf_ring->idr_lock); 2460 2461 if (unlikely(!skb)) { 2462 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", 2463 buf_id); 2464 goto move_next; 2465 } 2466 2467 rxcb = ATH12K_SKB_RXCB(skb); 2468 dma_unmap_single(ab->dev, rxcb->paddr, 2469 skb->len + skb_tailroom(skb), 2470 DMA_FROM_DEVICE); 2471 pmon->dest_skb_q[dest_idx] = skb; 2472 dest_idx++; 2473 end_of_ppdu = le32_get_bits(mon_dst_desc->info0, 2474 HAL_MON_DEST_INFO0_END_OF_PPDU); 2475 if (!end_of_ppdu) 2476 continue; 2477 2478 for (i = 0; i < dest_idx; i++) { 2479 skb = pmon->dest_skb_q[i]; 2480 hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); 2481 2482 if (ppdu_info->peer_id == HAL_INVALID_PEERID || 2483 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 2484 dev_kfree_skb_any(skb); 2485 continue; 2486 } 2487 2488 rcu_read_lock(); 2489 spin_lock_bh(&ab->base_lock); 2490 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); 2491 if (!peer || !peer->sta) { 2492 ath12k_dbg(ab, ATH12K_DBG_DATA, 2493 "failed to find the peer with peer_id %d\n", 2494 ppdu_info->peer_id); 2495 spin_unlock_bh(&ab->base_lock); 2496 rcu_read_unlock(); 2497 dev_kfree_skb_any(skb); 2498 continue; 2499 } 2500 2501 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { 2502 ahsta = ath12k_sta_to_ahsta(peer->sta); 2503 arsta = &ahsta->deflink; 2504 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta, 2505 ppdu_info); 2506 } else if ((ppdu_info->fc_valid) && 2507 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { 2508 ath12k_dp_mon_rx_process_ulofdma(ppdu_info); 2509 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info); 2510 } 2511 2512 spin_unlock_bh(&ab->base_lock); 2513 rcu_read_unlock(); 2514 dev_kfree_skb_any(skb); 2515 memset(ppdu_info, 0, sizeof(*ppdu_info)); 2516 ppdu_info->peer_id = HAL_INVALID_PEERID; 2517 } 2518 2519 dest_idx = 0; 2520 move_next: 2521 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 2522 ath12k_hal_srng_src_get_next_entry(ab, srng); 2523 num_buffs_reaped++; 2524 } 2525 2526 ath12k_hal_srng_access_end(ab, srng); 2527 spin_unlock_bh(&srng->lock); 2528 return num_buffs_reaped; 2529 } 2530 2531 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id, 2532 struct napi_struct *napi, int budget, 2533 enum dp_monitor_mode monitor_mode) 2534 { 2535 struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id); 2536 int num_buffs_reaped = 0; 2537 2538 if (!ar->monitor_started) 2539 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget); 2540 else 2541 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget, 2542 monitor_mode, napi); 2543 2544 return num_buffs_reaped; 2545 } 2546