1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_desc.h" 11 #include "hal_rx.h" 12 #include "hw.h" 13 14 #define MAX_RXDMA_PER_PDEV 2 15 16 struct ath12k_base; 17 struct ath12k_peer; 18 struct ath12k_dp; 19 struct ath12k_vif; 20 struct ath12k_link_vif; 21 struct hal_tcl_status_ring; 22 struct ath12k_ext_irq_grp; 23 24 #define DP_MON_PURGE_TIMEOUT_MS 100 25 #define DP_MON_SERVICE_BUDGET 128 26 27 struct dp_srng { 28 u32 *vaddr_unaligned; 29 u32 *vaddr; 30 dma_addr_t paddr_unaligned; 31 dma_addr_t paddr; 32 int size; 33 u32 ring_id; 34 }; 35 36 struct dp_rxdma_mon_ring { 37 struct dp_srng refill_buf_ring; 38 struct idr bufs_idr; 39 /* Protects bufs_idr */ 40 spinlock_t idr_lock; 41 int bufs_max; 42 }; 43 44 struct dp_rxdma_ring { 45 struct dp_srng refill_buf_ring; 46 int bufs_max; 47 }; 48 49 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 50 51 struct dp_tx_ring { 52 u8 tcl_data_ring_id; 53 struct dp_srng tcl_data_ring; 54 struct dp_srng tcl_comp_ring; 55 struct hal_wbm_completion_ring_tx *tx_status; 56 int tx_status_head; 57 int tx_status_tail; 58 }; 59 60 struct ath12k_pdev_mon_stats { 61 u32 status_ppdu_state; 62 u32 status_ppdu_start; 63 u32 status_ppdu_end; 64 u32 status_ppdu_compl; 65 u32 status_ppdu_start_mis; 66 u32 status_ppdu_end_mis; 67 u32 status_ppdu_done; 68 u32 dest_ppdu_done; 69 u32 dest_mpdu_done; 70 u32 dest_mpdu_drop; 71 u32 dup_mon_linkdesc_cnt; 72 u32 dup_mon_buf_cnt; 73 u32 dest_mon_stuck; 74 u32 dest_mon_not_reaped; 75 }; 76 77 enum dp_mon_status_buf_state { 78 DP_MON_STATUS_MATCH, 79 DP_MON_STATUS_NO_DMA, 80 DP_MON_STATUS_LAG, 81 DP_MON_STATUS_LEAD, 82 DP_MON_STATUS_REPLINISH, 83 }; 84 85 struct dp_link_desc_bank { 86 void *vaddr_unaligned; 87 void *vaddr; 88 dma_addr_t paddr_unaligned; 89 dma_addr_t paddr; 90 u32 size; 91 }; 92 93 /* Size to enforce scatter idle list mode */ 94 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 95 #define DP_LINK_DESC_BANKS_MAX 8 96 97 #define DP_LINK_DESC_START 0x4000 98 #define DP_LINK_DESC_SHIFT 3 99 100 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 101 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 102 103 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 104 105 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 106 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 107 #define DP_RX_DESC_COOKIE_MAX \ 108 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 109 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 110 111 enum ath12k_dp_ppdu_state { 112 DP_PPDU_STATUS_START, 113 DP_PPDU_STATUS_DONE, 114 }; 115 116 struct dp_mon_mpdu { 117 struct list_head list; 118 struct sk_buff *head; 119 struct sk_buff *tail; 120 u32 err_bitmap; 121 u8 decap_format; 122 }; 123 124 #define DP_MON_MAX_STATUS_BUF 32 125 126 struct ath12k_mon_data { 127 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 128 struct hal_rx_mon_ppdu_info mon_ppdu_info; 129 130 u32 mon_ppdu_status; 131 u32 mon_last_buf_cookie; 132 u64 mon_last_linkdesc_paddr; 133 u16 chan_noise_floor; 134 u32 err_bitmap; 135 u8 decap_format; 136 137 struct ath12k_pdev_mon_stats rx_mon_stats; 138 enum dp_mon_status_buf_state buf_state; 139 /* lock for monitor data */ 140 spinlock_t mon_lock; 141 struct sk_buff_head rx_status_q; 142 struct dp_mon_mpdu *mon_mpdu; 143 struct list_head dp_rx_mon_mpdu_list; 144 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 145 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 146 }; 147 148 struct ath12k_pdev_dp { 149 u32 mac_id; 150 atomic_t num_tx_pending; 151 wait_queue_head_t tx_empty_waitq; 152 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 153 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 154 155 struct ieee80211_rx_status rx_status; 156 struct ath12k_mon_data mon_data; 157 }; 158 159 #define DP_NUM_CLIENTS_MAX 64 160 #define DP_AVG_TIDS_PER_CLIENT 2 161 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 162 #define DP_AVG_MSDUS_PER_FLOW 128 163 #define DP_AVG_FLOWS_PER_TID 2 164 #define DP_AVG_MPDUS_PER_TID_MAX 128 165 #define DP_AVG_MSDUS_PER_MPDU 4 166 167 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 168 169 #define DP_BA_WIN_SZ_MAX 1024 170 171 #define DP_TCL_NUM_RING_MAX 4 172 173 #define DP_IDLE_SCATTER_BUFS_MAX 16 174 175 #define DP_WBM_RELEASE_RING_SIZE 64 176 #define DP_TCL_DATA_RING_SIZE 512 177 #define DP_TX_COMP_RING_SIZE 32768 178 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 179 #define DP_TCL_CMD_RING_SIZE 32 180 #define DP_TCL_STATUS_RING_SIZE 32 181 #define DP_REO_DST_RING_MAX 8 182 #define DP_REO_DST_RING_SIZE 2048 183 #define DP_REO_REINJECT_RING_SIZE 32 184 #define DP_RX_RELEASE_RING_SIZE 1024 185 #define DP_REO_EXCEPTION_RING_SIZE 128 186 #define DP_REO_CMD_RING_SIZE 128 187 #define DP_REO_STATUS_RING_SIZE 2048 188 #define DP_RXDMA_BUF_RING_SIZE 4096 189 #define DP_RX_MAC_BUF_RING_SIZE 2048 190 #define DP_RXDMA_REFILL_RING_SIZE 2048 191 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 192 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 193 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 194 #define DP_RXDMA_MONITOR_DST_RING_SIZE 8092 195 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 196 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 197 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 198 199 #define DP_TX_MONITOR_BUF_SIZE 2048 200 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 201 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 202 203 #define DP_RX_BUFFER_SIZE 2048 204 #define DP_RX_BUFFER_SIZE_LITE 1024 205 #define DP_RX_BUFFER_ALIGN_SIZE 128 206 207 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 208 #define RX_MON_STATUS_BUF_ALIGN 128 209 #define RX_MON_STATUS_BUF_RESERVATION 128 210 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 211 (RX_MON_STATUS_BUF_RESERVATION + \ 212 RX_MON_STATUS_BUF_ALIGN + \ 213 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))) 214 215 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 216 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 217 218 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 219 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 220 221 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 222 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 223 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 224 225 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 226 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 227 228 #define ATH12K_NUM_POOL_TX_DESC 32768 229 230 /* TODO: revisit this count during testing */ 231 #define ATH12K_RX_DESC_COUNT (12288) 232 233 #define ATH12K_PAGE_SIZE PAGE_SIZE 234 235 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 236 * SPT pages which makes lower 12bits 0 237 */ 238 #define ATH12K_MAX_PPT_ENTRIES 1024 239 240 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 241 #define ATH12K_MAX_SPT_ENTRIES 512 242 243 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 244 245 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 246 ATH12K_MAX_SPT_ENTRIES) 247 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 248 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 249 250 #define ATH12K_TX_SPT_PAGE_OFFSET 0 251 #define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES 252 253 /* The SPT pages are divided for RX and TX, first block for RX 254 * and remaining for TX 255 */ 256 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 257 258 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 259 260 /* 4K aligned address have last 12 bits set to 0, this check is done 261 * so that two spt pages address can be stored per 8bytes 262 * of CMEM (PPT) 263 */ 264 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 265 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 266 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 267 268 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 269 #define ATH12K_CMEM_ADDR_MSB 0x10 270 271 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 272 #define ATH12K_CC_SPT_MSB 8 273 #define ATH12K_CC_PPT_MSB 19 274 #define ATH12K_CC_PPT_SHIFT 9 275 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 276 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 277 278 #define DP_REO_QREF_NUM GENMASK(31, 16) 279 #define DP_MAX_PEER_ID 2047 280 281 /* Total size of the LUT is based on 2K peers, each having reference 282 * for 17tids, note each entry is of type ath12k_reo_queue_ref 283 * hence total size is 2048 * 17 * 8 = 278528 284 */ 285 #define DP_REOQ_LUT_SIZE 278528 286 287 /* Invalid TX Bank ID value */ 288 #define DP_INVALID_BANK_ID -1 289 290 #define MAX_TQM_RELEASE_REASON 15 291 #define MAX_FW_TX_STATUS 7 292 293 struct ath12k_dp_tx_bank_profile { 294 u8 is_configured; 295 u32 num_users; 296 u32 bank_config; 297 }; 298 299 struct ath12k_hp_update_timer { 300 struct timer_list timer; 301 bool started; 302 bool init; 303 u32 tx_num; 304 u32 timer_tx_num; 305 u32 ring_id; 306 u32 interval; 307 struct ath12k_base *ab; 308 }; 309 310 struct ath12k_rx_desc_info { 311 struct list_head list; 312 struct sk_buff *skb; 313 u32 cookie; 314 u32 magic; 315 u8 in_use : 1, 316 device_id : 3, 317 reserved : 4; 318 }; 319 320 struct ath12k_tx_desc_info { 321 struct list_head list; 322 struct sk_buff *skb; 323 struct sk_buff *skb_ext_desc; 324 u32 desc_id; /* Cookie */ 325 u8 mac_id; 326 u8 pool_id; 327 }; 328 329 struct ath12k_tx_desc_params { 330 struct sk_buff *skb; 331 struct sk_buff *skb_ext_desc; 332 u8 mac_id; 333 }; 334 335 struct ath12k_spt_info { 336 dma_addr_t paddr; 337 u64 *vaddr; 338 }; 339 340 struct ath12k_reo_queue_ref { 341 u32 info0; 342 u32 info1; 343 } __packed; 344 345 struct ath12k_reo_q_addr_lut { 346 u32 *vaddr_unaligned; 347 u32 *vaddr; 348 dma_addr_t paddr_unaligned; 349 dma_addr_t paddr; 350 u32 size; 351 }; 352 353 struct ath12k_link_stats { 354 u32 tx_enqueued; 355 u32 tx_completed; 356 u32 tx_bcast_mcast; 357 u32 tx_dropped; 358 u32 tx_encap_type[HAL_TCL_ENCAP_TYPE_MAX]; 359 u32 tx_encrypt_type[HAL_ENCRYPT_TYPE_MAX]; 360 u32 tx_desc_type[HAL_TCL_DESC_TYPE_MAX]; 361 }; 362 363 struct ath12k_dp { 364 struct ath12k_base *ab; 365 u32 mon_dest_ring_stuck_cnt; 366 u8 num_bank_profiles; 367 /* protects the access and update of bank_profiles */ 368 spinlock_t tx_bank_lock; 369 struct ath12k_dp_tx_bank_profile *bank_profiles; 370 enum ath12k_htc_ep_id eid; 371 struct completion htt_tgt_version_received; 372 u8 htt_tgt_ver_major; 373 u8 htt_tgt_ver_minor; 374 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 375 enum hal_rx_buf_return_buf_manager idle_link_rbm; 376 struct dp_srng wbm_idle_ring; 377 struct dp_srng wbm_desc_rel_ring; 378 struct dp_srng reo_reinject_ring; 379 struct dp_srng rx_rel_ring; 380 struct dp_srng reo_except_ring; 381 struct dp_srng reo_cmd_ring; 382 struct dp_srng reo_status_ring; 383 enum ath12k_peer_metadata_version peer_metadata_ver; 384 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 385 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 386 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 387 struct list_head reo_cmd_list; 388 struct list_head reo_cmd_cache_flush_list; 389 u32 reo_cmd_cache_flush_count; 390 391 /* protects access to below fields, 392 * - reo_cmd_list 393 * - reo_cmd_cache_flush_list 394 * - reo_cmd_cache_flush_count 395 */ 396 spinlock_t reo_cmd_lock; 397 struct ath12k_hp_update_timer reo_cmd_timer; 398 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 399 struct ath12k_spt_info *spt_info; 400 u32 num_spt_pages; 401 u32 rx_ppt_base; 402 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 403 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 404 struct list_head rx_desc_free_list; 405 /* protects the free desc list */ 406 spinlock_t rx_desc_lock; 407 408 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 409 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 410 /* protects the free and used desc lists */ 411 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 412 413 struct dp_rxdma_ring rx_refill_buf_ring; 414 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 415 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 416 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 417 struct dp_rxdma_mon_ring tx_mon_buf_ring; 418 struct dp_rxdma_mon_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 419 struct ath12k_reo_q_addr_lut reoq_lut; 420 struct ath12k_reo_q_addr_lut ml_reoq_lut; 421 }; 422 423 /* HTT definitions */ 424 #define HTT_TAG_TCL_METADATA_VERSION 5 425 426 #define HTT_TCL_META_DATA_TYPE GENMASK(1, 0) 427 #define HTT_TCL_META_DATA_VALID_HTT BIT(2) 428 429 /* vdev meta data */ 430 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3) 431 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11) 432 #define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13) 433 434 /* peer meta data */ 435 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3) 436 437 /* Global sequence number */ 438 #define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3 439 #define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2) 440 #define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3) 441 #define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128 442 443 /* HTT tx completion is overlaid in wbm_release_ring */ 444 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 445 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 446 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 447 448 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 449 450 struct htt_tx_wbm_completion { 451 __le32 rsvd0[2]; 452 __le32 info0; 453 __le32 info1; 454 __le32 info2; 455 __le32 info3; 456 __le32 info4; 457 __le32 rsvd1; 458 459 } __packed; 460 461 enum htt_h2t_msg_type { 462 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 463 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 464 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 465 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 466 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 467 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 468 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 469 }; 470 471 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 472 #define HTT_OPTION_TCL_METADATA_VER_V2 2 473 #define HTT_OPTION_TAG GENMASK(7, 0) 474 #define HTT_OPTION_LEN GENMASK(15, 8) 475 #define HTT_OPTION_VALUE GENMASK(31, 16) 476 #define HTT_TCL_METADATA_VER_SZ 4 477 478 struct htt_ver_req_cmd { 479 __le32 ver_reg_info; 480 __le32 tcl_metadata_version; 481 } __packed; 482 483 enum htt_srng_ring_type { 484 HTT_HW_TO_SW_RING, 485 HTT_SW_TO_HW_RING, 486 HTT_SW_TO_SW_RING, 487 }; 488 489 enum htt_srng_ring_id { 490 HTT_RXDMA_HOST_BUF_RING, 491 HTT_RXDMA_MONITOR_STATUS_RING, 492 HTT_RXDMA_MONITOR_BUF_RING, 493 HTT_RXDMA_MONITOR_DESC_RING, 494 HTT_RXDMA_MONITOR_DEST_RING, 495 HTT_HOST1_TO_FW_RXBUF_RING, 496 HTT_HOST2_TO_FW_RXBUF_RING, 497 HTT_RXDMA_NON_MONITOR_DEST_RING, 498 HTT_RXDMA_HOST_BUF_RING2, 499 HTT_TX_MON_HOST2MON_BUF_RING, 500 HTT_TX_MON_MON2HOST_DEST_RING, 501 HTT_RX_MON_HOST2MON_BUF_RING, 502 HTT_RX_MON_MON2HOST_DEST_RING, 503 }; 504 505 /* host -> target HTT_SRING_SETUP message 506 * 507 * After target is booted up, Host can send SRING setup message for 508 * each host facing LMAC SRING. Target setups up HW registers based 509 * on setup message and confirms back to Host if response_required is set. 510 * Host should wait for confirmation message before sending new SRING 511 * setup message 512 * 513 * The message would appear as follows: 514 * 515 * |31 24|23 20|19|18 16|15|14 8|7 0| 516 * |--------------- +-----------------+----------------+------------------| 517 * | ring_type | ring_id | pdev_id | msg_type | 518 * |----------------------------------------------------------------------| 519 * | ring_base_addr_lo | 520 * |----------------------------------------------------------------------| 521 * | ring_base_addr_hi | 522 * |----------------------------------------------------------------------| 523 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 524 * |----------------------------------------------------------------------| 525 * | ring_head_offset32_remote_addr_lo | 526 * |----------------------------------------------------------------------| 527 * | ring_head_offset32_remote_addr_hi | 528 * |----------------------------------------------------------------------| 529 * | ring_tail_offset32_remote_addr_lo | 530 * |----------------------------------------------------------------------| 531 * | ring_tail_offset32_remote_addr_hi | 532 * |----------------------------------------------------------------------| 533 * | ring_msi_addr_lo | 534 * |----------------------------------------------------------------------| 535 * | ring_msi_addr_hi | 536 * |----------------------------------------------------------------------| 537 * | ring_msi_data | 538 * |----------------------------------------------------------------------| 539 * | intr_timer_th |IM| intr_batch_counter_th | 540 * |----------------------------------------------------------------------| 541 * | reserved |RR|PTCF| intr_low_threshold | 542 * |----------------------------------------------------------------------| 543 * Where 544 * IM = sw_intr_mode 545 * RR = response_required 546 * PTCF = prefetch_timer_cfg 547 * 548 * The message is interpreted as follows: 549 * dword0 - b'0:7 - msg_type: This will be set to 550 * HTT_H2T_MSG_TYPE_SRING_SETUP 551 * b'8:15 - pdev_id: 552 * 0 (for rings at SOC/UMAC level), 553 * 1/2/3 mac id (for rings at LMAC level) 554 * b'16:23 - ring_id: identify which ring is to setup, 555 * more details can be got from enum htt_srng_ring_id 556 * b'24:31 - ring_type: identify type of host rings, 557 * more details can be got from enum htt_srng_ring_type 558 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 559 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 560 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 561 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 562 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 563 * SW_TO_HW_RING. 564 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 565 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 566 * Lower 32 bits of memory address of the remote variable 567 * storing the 4-byte word offset that identifies the head 568 * element within the ring. 569 * (The head offset variable has type u32.) 570 * Valid for HW_TO_SW and SW_TO_SW rings. 571 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 572 * Upper 32 bits of memory address of the remote variable 573 * storing the 4-byte word offset that identifies the head 574 * element within the ring. 575 * (The head offset variable has type u32.) 576 * Valid for HW_TO_SW and SW_TO_SW rings. 577 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 578 * Lower 32 bits of memory address of the remote variable 579 * storing the 4-byte word offset that identifies the tail 580 * element within the ring. 581 * (The tail offset variable has type u32.) 582 * Valid for HW_TO_SW and SW_TO_SW rings. 583 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 584 * Upper 32 bits of memory address of the remote variable 585 * storing the 4-byte word offset that identifies the tail 586 * element within the ring. 587 * (The tail offset variable has type u32.) 588 * Valid for HW_TO_SW and SW_TO_SW rings. 589 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 590 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 591 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 592 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 593 * dword10 - b'0:31 - ring_msi_data: MSI data 594 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 595 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 596 * dword11 - b'0:14 - intr_batch_counter_th: 597 * batch counter threshold is in units of 4-byte words. 598 * HW internally maintains and increments batch count. 599 * (see SRING spec for detail description). 600 * When batch count reaches threshold value, an interrupt 601 * is generated by HW. 602 * b'15 - sw_intr_mode: 603 * This configuration shall be static. 604 * Only programmed at power up. 605 * 0: generate pulse style sw interrupts 606 * 1: generate level style sw interrupts 607 * b'16:31 - intr_timer_th: 608 * The timer init value when timer is idle or is 609 * initialized to start downcounting. 610 * In 8us units (to cover a range of 0 to 524 ms) 611 * dword12 - b'0:15 - intr_low_threshold: 612 * Used only by Consumer ring to generate ring_sw_int_p. 613 * Ring entries low threshold water mark, that is used 614 * in combination with the interrupt timer as well as 615 * the clearing of the level interrupt. 616 * b'16:18 - prefetch_timer_cfg: 617 * Used only by Consumer ring to set timer mode to 618 * support Application prefetch handling. 619 * The external tail offset/pointer will be updated 620 * at following intervals: 621 * 3'b000: (Prefetch feature disabled; used only for debug) 622 * 3'b001: 1 usec 623 * 3'b010: 4 usec 624 * 3'b011: 8 usec (default) 625 * 3'b100: 16 usec 626 * Others: Reserved 627 * b'19 - response_required: 628 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 629 * b'20:31 - reserved: reserved for future use 630 */ 631 632 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 633 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 634 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 635 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 636 637 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 638 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 639 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 640 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 641 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 642 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 643 644 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 645 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 646 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 647 648 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 649 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 650 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 651 652 struct htt_srng_setup_cmd { 653 __le32 info0; 654 __le32 ring_base_addr_lo; 655 __le32 ring_base_addr_hi; 656 __le32 info1; 657 __le32 ring_head_off32_remote_addr_lo; 658 __le32 ring_head_off32_remote_addr_hi; 659 __le32 ring_tail_off32_remote_addr_lo; 660 __le32 ring_tail_off32_remote_addr_hi; 661 __le32 ring_msi_addr_lo; 662 __le32 ring_msi_addr_hi; 663 __le32 msi_data; 664 __le32 intr_info; 665 __le32 info2; 666 } __packed; 667 668 /* host -> target FW PPDU_STATS config message 669 * 670 * @details 671 * The following field definitions describe the format of the HTT host 672 * to target FW for PPDU_STATS_CFG msg. 673 * The message allows the host to configure the PPDU_STATS_IND messages 674 * produced by the target. 675 * 676 * |31 24|23 16|15 8|7 0| 677 * |-----------------------------------------------------------| 678 * | REQ bit mask | pdev_mask | msg type | 679 * |-----------------------------------------------------------| 680 * Header fields: 681 * - MSG_TYPE 682 * Bits 7:0 683 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 684 * Value: 0x11 685 * - PDEV_MASK 686 * Bits 8:15 687 * Purpose: identifies which pdevs this PPDU stats configuration applies to 688 * Value: This is a overloaded field, refer to usage and interpretation of 689 * PDEV in interface document. 690 * Bit 8 : Reserved for SOC stats 691 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 692 * Indicates MACID_MASK in DBS 693 * - REQ_TLV_BIT_MASK 694 * Bits 16:31 695 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 696 * needs to be included in the target's PPDU_STATS_IND messages. 697 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 698 * 699 */ 700 701 struct htt_ppdu_stats_cfg_cmd { 702 __le32 msg; 703 } __packed; 704 705 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 706 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 707 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 708 709 enum htt_ppdu_stats_tag_type { 710 HTT_PPDU_STATS_TAG_COMMON, 711 HTT_PPDU_STATS_TAG_USR_COMMON, 712 HTT_PPDU_STATS_TAG_USR_RATE, 713 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 714 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 715 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 716 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 717 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 718 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 719 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 720 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 721 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 722 HTT_PPDU_STATS_TAG_INFO, 723 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 724 725 /* New TLV's are added above to this line */ 726 HTT_PPDU_STATS_TAG_MAX, 727 }; 728 729 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 730 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 731 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 732 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 733 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 734 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 735 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 736 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 737 738 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 739 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 740 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 741 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 742 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 743 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 744 HTT_PPDU_STATS_TAG_DEFAULT) 745 746 enum htt_stats_internal_ppdu_frametype { 747 HTT_STATS_PPDU_FTYPE_CTRL, 748 HTT_STATS_PPDU_FTYPE_DATA, 749 HTT_STATS_PPDU_FTYPE_BAR, 750 HTT_STATS_PPDU_FTYPE_MAX 751 }; 752 753 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 754 * 755 * details: 756 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 757 * configure RXDMA rings. 758 * The configuration is per ring based and includes both packet subtypes 759 * and PPDU/MPDU TLVs. 760 * 761 * The message would appear as follows: 762 * 763 * |31 29|28|27|26|25|24|23 16|15 8|7 0| 764 * |-------+--+--+--+--+--+-----------+----------------+---------------| 765 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 766 * |-------------------------------------------------------------------| 767 * | rsvd2 | ring_buffer_size | 768 * |-------------------------------------------------------------------| 769 * | packet_type_enable_flags_0 | 770 * |-------------------------------------------------------------------| 771 * | packet_type_enable_flags_1 | 772 * |-------------------------------------------------------------------| 773 * | packet_type_enable_flags_2 | 774 * |-------------------------------------------------------------------| 775 * | packet_type_enable_flags_3 | 776 * |-------------------------------------------------------------------| 777 * | tlv_filter_in_flags | 778 * |-------------------------------------------------------------------| 779 * Where: 780 * PS = pkt_swap 781 * SS = status_swap 782 * The message is interpreted as follows: 783 * dword0 - b'0:7 - msg_type: This will be set to 784 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 785 * b'8:15 - pdev_id: 786 * 0 (for rings at SOC/UMAC level), 787 * 1/2/3 mac id (for rings at LMAC level) 788 * b'16:23 - ring_id : Identify the ring to configure. 789 * More details can be got from enum htt_srng_ring_id 790 * b'24 - status_swap: 1 is to swap status TLV 791 * b'25 - pkt_swap: 1 is to swap packet TLV 792 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 793 * configuration fields are valid 794 * b'27 - drop_thresh_valid (DT): flag to indicate if the 795 * rx_drop_threshold field is valid 796 * b'28 - rx_mon_global_en: Enable/Disable global register 797 * configuration in Rx monitor module. 798 * b'29:31 - rsvd1: reserved for future use 799 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 800 * in byte units. 801 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 802 * - b'16:31 - rsvd2: Reserved for future use 803 * dword2 - b'0:31 - packet_type_enable_flags_0: 804 * Enable MGMT packet from 0b0000 to 0b1001 805 * bits from low to high: FP, MD, MO - 3 bits 806 * FP: Filter_Pass 807 * MD: Monitor_Direct 808 * MO: Monitor_Other 809 * 10 mgmt subtypes * 3 bits -> 30 bits 810 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 811 * dword3 - b'0:31 - packet_type_enable_flags_1: 812 * Enable MGMT packet from 0b1010 to 0b1111 813 * bits from low to high: FP, MD, MO - 3 bits 814 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 815 * dword4 - b'0:31 - packet_type_enable_flags_2: 816 * Enable CTRL packet from 0b0000 to 0b1001 817 * bits from low to high: FP, MD, MO - 3 bits 818 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 819 * dword5 - b'0:31 - packet_type_enable_flags_3: 820 * Enable CTRL packet from 0b1010 to 0b1111, 821 * MCAST_DATA, UCAST_DATA, NULL_DATA 822 * bits from low to high: FP, MD, MO - 3 bits 823 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 824 * dword6 - b'0:31 - tlv_filter_in_flags: 825 * Filter in Attention/MPDU/PPDU/Header/User tlvs 826 * Refer to CFG_TLV_FILTER_IN_FLAG defs 827 */ 828 829 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 830 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 831 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 832 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 833 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 834 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID BIT(26) 835 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL BIT(27) 836 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON BIT(28) 837 838 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 839 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16) 840 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19) 841 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22) 842 843 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0) 844 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE BIT(17) 845 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE BIT(18) 846 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE BIT(19) 847 848 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET BIT(0) 849 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1) 850 851 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 852 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 853 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 854 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 855 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 856 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 857 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 858 859 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23) 860 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) 861 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) 862 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) 863 864 enum htt_rx_filter_tlv_flags { 865 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 866 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 867 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 868 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 869 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 870 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 871 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 872 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 873 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 874 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 875 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 876 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 877 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 878 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13), 879 }; 880 881 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 882 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 883 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 884 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 885 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 886 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 887 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 888 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 889 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 890 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 891 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 892 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 893 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 894 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 895 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 896 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 897 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 898 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 899 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 900 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 901 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 902 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 903 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 904 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 905 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 906 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 907 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 908 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 909 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 910 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 911 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 912 }; 913 914 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 915 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 916 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 917 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 918 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 919 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 920 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 921 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 922 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 923 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 924 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 925 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 926 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 927 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 928 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 929 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 930 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 931 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 932 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 933 }; 934 935 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 936 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 937 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 938 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 939 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 940 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 941 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 942 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 943 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 944 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 945 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 946 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 947 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 948 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 949 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 950 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 951 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 952 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 953 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 954 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 955 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 956 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 957 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 958 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 959 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 960 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 961 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 962 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 963 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 964 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 965 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 966 }; 967 968 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 969 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 970 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 971 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 972 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 973 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 974 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 975 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 976 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 977 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 978 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 979 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 980 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 981 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 982 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 983 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 984 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 985 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 986 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 987 }; 988 989 enum htt_rx_data_pkt_filter_tlv_flasg3 { 990 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 991 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 992 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 993 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 994 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 995 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 996 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 997 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 998 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 999 }; 1000 1001 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 1002 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 1003 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1004 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1005 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1006 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1007 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1008 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1009 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1010 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1011 1012 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 1013 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 1014 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1015 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1016 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1017 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1018 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1019 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1020 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1021 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1022 1023 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 1024 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 1025 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1026 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1027 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1028 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1029 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1030 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1031 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1032 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1033 1034 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1035 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1036 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1037 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1038 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1039 1040 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1041 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1042 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1043 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1044 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1045 1046 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1047 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1048 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1049 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1050 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1051 1052 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1053 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1054 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1055 1056 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1057 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1058 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1059 1060 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1061 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1062 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1063 1064 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1065 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1066 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1067 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1068 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1069 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1070 1071 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1072 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1073 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1074 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1075 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1076 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1077 1078 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1079 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1080 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1081 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1082 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1083 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1084 1085 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1086 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1087 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1088 1089 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1090 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1091 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1092 1093 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1094 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1095 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1096 1097 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1098 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1099 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1100 1101 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1102 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1103 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1104 1105 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1106 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1107 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1108 1109 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1110 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1111 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1112 1113 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1114 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1115 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1116 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1117 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1118 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1119 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1120 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1121 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1122 1123 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1124 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1125 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1126 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1127 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1128 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1129 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1130 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1131 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1132 1133 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1134 1135 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1136 1137 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1138 1139 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1140 1141 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1142 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1143 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1144 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1145 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1146 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1147 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1148 1149 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1150 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1151 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1152 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1153 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1154 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1155 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1156 1157 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1158 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1159 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1160 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1161 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1162 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1163 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1164 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1165 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1166 1167 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \ 1168 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1169 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1170 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1171 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1172 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1173 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1174 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1175 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1176 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1177 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1178 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1179 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ 1180 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO) 1181 1182 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1183 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1184 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1185 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1186 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1187 1188 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1189 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1190 1191 struct htt_rx_ring_selection_cfg_cmd { 1192 __le32 info0; 1193 __le32 info1; 1194 __le32 pkt_type_en_flags0; 1195 __le32 pkt_type_en_flags1; 1196 __le32 pkt_type_en_flags2; 1197 __le32 pkt_type_en_flags3; 1198 __le32 rx_filter_tlv; 1199 __le32 rx_packet_offset; 1200 __le32 rx_mpdu_offset; 1201 __le32 rx_msdu_offset; 1202 __le32 rx_attn_offset; 1203 __le32 info2; 1204 __le32 reserved[2]; 1205 __le32 rx_mpdu_start_end_mask; 1206 __le32 rx_msdu_end_word_mask; 1207 __le32 info3; 1208 } __packed; 1209 1210 #define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32 1211 #define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7 1212 #define HTT_RX_RING_PKT_TLV_OFFSET 0x1 1213 1214 struct htt_rx_ring_tlv_filter { 1215 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1216 u32 pkt_filter_flags0; /* MGMT */ 1217 u32 pkt_filter_flags1; /* MGMT */ 1218 u32 pkt_filter_flags2; /* CTRL */ 1219 u32 pkt_filter_flags3; /* DATA */ 1220 bool offset_valid; 1221 u16 rx_packet_offset; 1222 u16 rx_header_offset; 1223 u16 rx_mpdu_end_offset; 1224 u16 rx_mpdu_start_offset; 1225 u16 rx_msdu_end_offset; 1226 u16 rx_msdu_start_offset; 1227 u16 rx_attn_offset; 1228 u16 rx_mpdu_start_wmask; 1229 u16 rx_mpdu_end_wmask; 1230 u32 rx_msdu_end_wmask; 1231 u32 conf_len_ctrl; 1232 u32 conf_len_mgmt; 1233 u32 conf_len_data; 1234 u16 rx_drop_threshold; 1235 bool enable_log_mgmt_type; 1236 bool enable_log_ctrl_type; 1237 bool enable_log_data_type; 1238 bool enable_rx_tlv_offset; 1239 u16 rx_tlv_offset; 1240 bool drop_threshold_valid; 1241 bool rxmon_disable; 1242 }; 1243 1244 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1245 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1246 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1247 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1248 1249 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1250 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1251 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1252 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1253 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1254 1255 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1256 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1257 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1258 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1259 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1260 1261 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1262 1263 struct htt_tx_ring_selection_cfg_cmd { 1264 __le32 info0; 1265 __le32 info1; 1266 __le32 info2; 1267 __le32 tlv_filter_mask_in0; 1268 __le32 tlv_filter_mask_in1; 1269 __le32 tlv_filter_mask_in2; 1270 __le32 tlv_filter_mask_in3; 1271 __le32 reserved[3]; 1272 } __packed; 1273 1274 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1275 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1276 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1277 1278 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1279 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1280 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1281 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1282 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1283 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1284 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1285 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1286 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1287 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1288 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1289 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1290 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1291 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1292 1293 struct htt_tx_ring_tlv_filter { 1294 u32 tx_mon_downstream_tlv_flags; 1295 u32 tx_mon_upstream_tlv_flags0; 1296 u32 tx_mon_upstream_tlv_flags1; 1297 u32 tx_mon_upstream_tlv_flags2; 1298 bool tx_mon_mgmt_filter; 1299 bool tx_mon_data_filter; 1300 bool tx_mon_ctrl_filter; 1301 u16 tx_mon_pkt_dma_len; 1302 } __packed; 1303 1304 enum htt_tx_mon_upstream_tlv_flags0 { 1305 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1306 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1307 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1308 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1309 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1310 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1311 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1312 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1313 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1314 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1315 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1316 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1317 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1318 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1319 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1320 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1321 }; 1322 1323 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1324 1325 /* HTT message target->host */ 1326 1327 enum htt_t2h_msg_type { 1328 HTT_T2H_MSG_TYPE_VERSION_CONF, 1329 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1330 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1331 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1332 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1333 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1334 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1335 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1336 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1337 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1338 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1339 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1340 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1341 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1342 }; 1343 1344 #define HTT_TARGET_VERSION_MAJOR 3 1345 1346 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1347 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1348 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1349 1350 struct htt_t2h_version_conf_msg { 1351 __le32 version; 1352 } __packed; 1353 1354 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1355 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1356 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1357 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1358 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1359 #define HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID GENMASK(15, 0) 1360 #define HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL GENMASK(31, 16) 1361 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1362 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1363 1364 struct htt_t2h_peer_map_event { 1365 __le32 info; 1366 __le32 mac_addr_l32; 1367 __le32 info1; 1368 __le32 info2; 1369 } __packed; 1370 1371 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1372 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1373 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1374 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1375 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1376 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1377 1378 struct htt_t2h_peer_unmap_event { 1379 __le32 info; 1380 __le32 mac_addr_l32; 1381 __le32 info1; 1382 } __packed; 1383 1384 struct htt_resp_msg { 1385 union { 1386 struct htt_t2h_version_conf_msg version_msg; 1387 struct htt_t2h_peer_map_event peer_map_ev; 1388 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1389 }; 1390 } __packed; 1391 1392 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1393 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1394 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1395 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1396 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1397 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1398 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1399 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1400 1401 struct htt_t2h_vdev_txrx_stats_ind { 1402 __le32 vdev_id; 1403 __le32 rx_msdu_byte_cnt_lo; 1404 __le32 rx_msdu_byte_cnt_hi; 1405 __le32 rx_msdu_cnt_lo; 1406 __le32 rx_msdu_cnt_hi; 1407 __le32 tx_msdu_byte_cnt_lo; 1408 __le32 tx_msdu_byte_cnt_hi; 1409 __le32 tx_msdu_cnt_lo; 1410 __le32 tx_msdu_cnt_hi; 1411 __le32 tx_retry_cnt_lo; 1412 __le32 tx_retry_cnt_hi; 1413 __le32 tx_retry_byte_cnt_lo; 1414 __le32 tx_retry_byte_cnt_hi; 1415 __le32 tx_drop_cnt_lo; 1416 __le32 tx_drop_cnt_hi; 1417 __le32 tx_drop_byte_cnt_lo; 1418 __le32 tx_drop_byte_cnt_hi; 1419 __le32 msdu_ttl_cnt_lo; 1420 __le32 msdu_ttl_cnt_hi; 1421 __le32 msdu_ttl_byte_cnt_lo; 1422 __le32 msdu_ttl_byte_cnt_hi; 1423 } __packed; 1424 1425 struct htt_t2h_vdev_common_stats_tlv { 1426 __le32 soc_drop_count_lo; 1427 __le32 soc_drop_count_hi; 1428 } __packed; 1429 1430 /* ppdu stats 1431 * 1432 * @details 1433 * The following field definitions describe the format of the HTT target 1434 * to host ppdu stats indication message. 1435 * 1436 * 1437 * |31 16|15 12|11 10|9 8|7 0 | 1438 * |----------------------------------------------------------------------| 1439 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1440 * |----------------------------------------------------------------------| 1441 * | ppdu_id | 1442 * |----------------------------------------------------------------------| 1443 * | Timestamp in us | 1444 * |----------------------------------------------------------------------| 1445 * | reserved | 1446 * |----------------------------------------------------------------------| 1447 * | type-specific stats info | 1448 * | (see htt_ppdu_stats.h) | 1449 * |----------------------------------------------------------------------| 1450 * Header fields: 1451 * - MSG_TYPE 1452 * Bits 7:0 1453 * Purpose: Identifies this is a PPDU STATS indication 1454 * message. 1455 * Value: 0x1d 1456 * - mac_id 1457 * Bits 9:8 1458 * Purpose: mac_id of this ppdu_id 1459 * Value: 0-3 1460 * - pdev_id 1461 * Bits 11:10 1462 * Purpose: pdev_id of this ppdu_id 1463 * Value: 0-3 1464 * 0 (for rings at SOC level), 1465 * 1/2/3 PDEV -> 0/1/2 1466 * - payload_size 1467 * Bits 31:16 1468 * Purpose: total tlv size 1469 * Value: payload_size in bytes 1470 */ 1471 1472 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1473 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1474 1475 struct ath12k_htt_ppdu_stats_msg { 1476 __le32 info; 1477 __le32 ppdu_id; 1478 __le32 timestamp; 1479 __le32 rsvd; 1480 u8 data[]; 1481 } __packed; 1482 1483 struct htt_tlv { 1484 __le32 header; 1485 u8 value[]; 1486 } __packed; 1487 1488 #define HTT_TLV_TAG GENMASK(11, 0) 1489 #define HTT_TLV_LEN GENMASK(23, 12) 1490 1491 enum HTT_PPDU_STATS_BW { 1492 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1493 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1494 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1495 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1496 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1497 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1498 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1499 }; 1500 1501 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1502 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1503 /* bw - HTT_PPDU_STATS_BW */ 1504 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1505 1506 struct htt_ppdu_stats_common { 1507 __le32 ppdu_id; 1508 __le16 sched_cmdid; 1509 u8 ring_id; 1510 u8 num_users; 1511 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1512 __le32 chain_mask; 1513 __le32 fes_duration_us; /* frame exchange sequence */ 1514 __le32 ppdu_sch_eval_start_tstmp_us; 1515 __le32 ppdu_sch_end_tstmp_us; 1516 __le32 ppdu_start_tstmp_us; 1517 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1518 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1519 */ 1520 __le16 phy_mode; 1521 __le16 bw_mhz; 1522 } __packed; 1523 1524 enum htt_ppdu_stats_gi { 1525 HTT_PPDU_STATS_SGI_0_8_US, 1526 HTT_PPDU_STATS_SGI_0_4_US, 1527 HTT_PPDU_STATS_SGI_1_6_US, 1528 HTT_PPDU_STATS_SGI_3_2_US, 1529 }; 1530 1531 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1532 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1533 1534 enum HTT_PPDU_STATS_PPDU_TYPE { 1535 HTT_PPDU_STATS_PPDU_TYPE_SU, 1536 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1537 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1538 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1539 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1540 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1541 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1542 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1543 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1544 HTT_PPDU_STATS_PPDU_TYPE_MAX 1545 }; 1546 1547 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1548 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1549 1550 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1551 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1552 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1553 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1554 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1555 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1556 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1557 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1558 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1559 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1560 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1561 1562 #define HTT_USR_RATE_PREAMBLE(_val) \ 1563 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1564 #define HTT_USR_RATE_BW(_val) \ 1565 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1566 #define HTT_USR_RATE_NSS(_val) \ 1567 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1568 #define HTT_USR_RATE_MCS(_val) \ 1569 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1570 #define HTT_USR_RATE_GI(_val) \ 1571 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1572 #define HTT_USR_RATE_DCM(_val) \ 1573 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1574 1575 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1576 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1577 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1578 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1579 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1580 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1581 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1582 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1583 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1584 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1585 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1586 1587 struct htt_ppdu_stats_user_rate { 1588 u8 tid_num; 1589 u8 reserved0; 1590 __le16 sw_peer_id; 1591 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1592 __le16 ru_end; 1593 __le16 ru_start; 1594 __le16 resp_ru_end; 1595 __le16 resp_ru_start; 1596 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1597 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1598 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1599 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1600 } __packed; 1601 1602 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1603 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1604 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1605 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1606 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1607 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1608 1609 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1610 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1611 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1612 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1613 #define HTT_TX_INFO_RATECODE(_flags) \ 1614 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1615 #define HTT_TX_INFO_PEERID(_flags) \ 1616 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1617 1618 enum htt_ppdu_stats_usr_compln_status { 1619 HTT_PPDU_STATS_USER_STATUS_OK, 1620 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1621 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1622 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1623 HTT_PPDU_STATS_USER_STATUS_ABORT, 1624 }; 1625 1626 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1627 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1628 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1629 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1630 1631 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1632 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1633 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1634 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1635 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1636 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1637 1638 struct htt_ppdu_stats_usr_cmpltn_cmn { 1639 u8 status; 1640 u8 tid_num; 1641 __le16 sw_peer_id; 1642 /* RSSI value of last ack packet (units = dB above noise floor) */ 1643 __le32 ack_rssi; 1644 __le16 mpdu_tried; 1645 __le16 mpdu_success; 1646 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1647 } __packed; 1648 1649 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1650 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1651 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1652 1653 #define HTT_PPDU_STATS_NON_QOS_TID 16 1654 1655 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1656 __le32 ppdu_id; 1657 __le16 sw_peer_id; 1658 __le16 reserved0; 1659 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1660 __le16 current_seq; 1661 __le16 start_seq; 1662 __le32 success_bytes; 1663 } __packed; 1664 1665 struct htt_ppdu_user_stats { 1666 u16 peer_id; 1667 u16 delay_ba; 1668 u32 tlv_flags; 1669 bool is_valid_peer_id; 1670 struct htt_ppdu_stats_user_rate rate; 1671 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1672 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1673 }; 1674 1675 #define HTT_PPDU_STATS_MAX_USERS 8 1676 #define HTT_PPDU_DESC_MAX_DEPTH 16 1677 1678 struct htt_ppdu_stats { 1679 struct htt_ppdu_stats_common common; 1680 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1681 }; 1682 1683 struct htt_ppdu_stats_info { 1684 u32 tlv_bitmap; 1685 u32 ppdu_id; 1686 u32 frame_type; 1687 u32 frame_ctrl; 1688 u32 delay_ba; 1689 u32 bar_num_users; 1690 struct htt_ppdu_stats ppdu_stats; 1691 struct list_head list; 1692 }; 1693 1694 /* @brief target -> host MLO offset indiciation message 1695 * 1696 * @details 1697 * The following field definitions describe the format of the HTT target 1698 * to host mlo offset indication message. 1699 * 1700 * 1701 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1702 * |---------------------------------------------------------------------| 1703 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1704 * |---------------------------------------------------------------------| 1705 * | sync_timestamp_lo_us | 1706 * |---------------------------------------------------------------------| 1707 * | sync_timestamp_hi_us | 1708 * |---------------------------------------------------------------------| 1709 * | mlo_offset_lo | 1710 * |---------------------------------------------------------------------| 1711 * | mlo_offset_hi | 1712 * |---------------------------------------------------------------------| 1713 * | mlo_offset_clcks | 1714 * |---------------------------------------------------------------------| 1715 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1716 * |---------------------------------------------------------------------| 1717 * | rsvd3 |mlo_comp_timer | 1718 * |---------------------------------------------------------------------| 1719 * Header fields 1720 * - MSG_TYPE 1721 * Bits 7:0 1722 * Purpose: Identifies this is a MLO offset indication msg 1723 * - PDEV_ID 1724 * Bits 9:8 1725 * Purpose: Pdev of this MLO offset 1726 * - CHIP_ID 1727 * Bits 12:10 1728 * Purpose: chip_id of this MLO offset 1729 * - MAC_FREQ 1730 * Bits 28:13 1731 * - SYNC_TIMESTAMP_LO_US 1732 * Purpose: clock frequency of the mac HW block in MHz 1733 * Bits: 31:0 1734 * Purpose: lower 32 bits of the WLAN global time stamp at which 1735 * last sync interrupt was received 1736 * - SYNC_TIMESTAMP_HI_US 1737 * Bits: 31:0 1738 * Purpose: upper 32 bits of WLAN global time stamp at which 1739 * last sync interrupt was received 1740 * - MLO_OFFSET_LO 1741 * Bits: 31:0 1742 * Purpose: lower 32 bits of the MLO offset in us 1743 * - MLO_OFFSET_HI 1744 * Bits: 31:0 1745 * Purpose: upper 32 bits of the MLO offset in us 1746 * - MLO_COMP_US 1747 * Bits: 15:0 1748 * Purpose: MLO time stamp compensation applied in us 1749 * - MLO_COMP_CLCKS 1750 * Bits: 25:16 1751 * Purpose: MLO time stamp compensation applied in clock ticks 1752 * - MLO_COMP_TIMER 1753 * Bits: 21:0 1754 * Purpose: Periodic timer at which compensation is applied 1755 */ 1756 1757 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1758 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1759 1760 struct ath12k_htt_mlo_offset_msg { 1761 __le32 info; 1762 __le32 sync_timestamp_lo_us; 1763 __le32 sync_timestamp_hi_us; 1764 __le32 mlo_offset_hi; 1765 __le32 mlo_offset_lo; 1766 __le32 mlo_offset_clks; 1767 __le32 mlo_comp_clks; 1768 __le32 mlo_comp_timer; 1769 } __packed; 1770 1771 /* @brief host -> target FW extended statistics retrieve 1772 * 1773 * @details 1774 * The following field definitions describe the format of the HTT host 1775 * to target FW extended stats retrieve message. 1776 * The message specifies the type of stats the host wants to retrieve. 1777 * 1778 * |31 24|23 16|15 8|7 0| 1779 * |-----------------------------------------------------------| 1780 * | reserved | stats type | pdev_mask | msg type | 1781 * |-----------------------------------------------------------| 1782 * | config param [0] | 1783 * |-----------------------------------------------------------| 1784 * | config param [1] | 1785 * |-----------------------------------------------------------| 1786 * | config param [2] | 1787 * |-----------------------------------------------------------| 1788 * | config param [3] | 1789 * |-----------------------------------------------------------| 1790 * | reserved | 1791 * |-----------------------------------------------------------| 1792 * | cookie LSBs | 1793 * |-----------------------------------------------------------| 1794 * | cookie MSBs | 1795 * |-----------------------------------------------------------| 1796 * Header fields: 1797 * - MSG_TYPE 1798 * Bits 7:0 1799 * Purpose: identifies this is a extended stats upload request message 1800 * Value: 0x10 1801 * - PDEV_MASK 1802 * Bits 8:15 1803 * Purpose: identifies the mask of PDEVs to retrieve stats from 1804 * Value: This is a overloaded field, refer to usage and interpretation of 1805 * PDEV in interface document. 1806 * Bit 8 : Reserved for SOC stats 1807 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1808 * Indicates MACID_MASK in DBS 1809 * - STATS_TYPE 1810 * Bits 23:16 1811 * Purpose: identifies which FW statistics to upload 1812 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1813 * - Reserved 1814 * Bits 31:24 1815 * - CONFIG_PARAM [0] 1816 * Bits 31:0 1817 * Purpose: give an opaque configuration value to the specified stats type 1818 * Value: stats-type specific configuration value 1819 * Refer to htt_stats.h for interpretation for each stats sub_type 1820 * - CONFIG_PARAM [1] 1821 * Bits 31:0 1822 * Purpose: give an opaque configuration value to the specified stats type 1823 * Value: stats-type specific configuration value 1824 * Refer to htt_stats.h for interpretation for each stats sub_type 1825 * - CONFIG_PARAM [2] 1826 * Bits 31:0 1827 * Purpose: give an opaque configuration value to the specified stats type 1828 * Value: stats-type specific configuration value 1829 * Refer to htt_stats.h for interpretation for each stats sub_type 1830 * - CONFIG_PARAM [3] 1831 * Bits 31:0 1832 * Purpose: give an opaque configuration value to the specified stats type 1833 * Value: stats-type specific configuration value 1834 * Refer to htt_stats.h for interpretation for each stats sub_type 1835 * - Reserved [31:0] for future use. 1836 * - COOKIE_LSBS 1837 * Bits 31:0 1838 * Purpose: Provide a mechanism to match a target->host stats confirmation 1839 * message with its preceding host->target stats request message. 1840 * Value: LSBs of the opaque cookie specified by the host-side requestor 1841 * - COOKIE_MSBS 1842 * Bits 31:0 1843 * Purpose: Provide a mechanism to match a target->host stats confirmation 1844 * message with its preceding host->target stats request message. 1845 * Value: MSBs of the opaque cookie specified by the host-side requestor 1846 */ 1847 1848 struct htt_ext_stats_cfg_hdr { 1849 u8 msg_type; 1850 u8 pdev_mask; 1851 u8 stats_type; 1852 u8 reserved; 1853 } __packed; 1854 1855 struct htt_ext_stats_cfg_cmd { 1856 struct htt_ext_stats_cfg_hdr hdr; 1857 __le32 cfg_param0; 1858 __le32 cfg_param1; 1859 __le32 cfg_param2; 1860 __le32 cfg_param3; 1861 __le32 reserved; 1862 __le32 cookie_lsb; 1863 __le32 cookie_msb; 1864 } __packed; 1865 1866 /* htt stats config default params */ 1867 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1868 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1869 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1870 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1871 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1872 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1873 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1874 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1875 1876 /* HTT_DBG_EXT_STATS_PEER_INFO 1877 * PARAMS: 1878 * @config_param0: 1879 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1880 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1881 * [Bit31 : Bit16] sw_peer_id 1882 * @config_param1: 1883 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1884 * 0 bit htt_peer_stats_cmn_tlv 1885 * 1 bit htt_peer_details_tlv 1886 * 2 bit htt_tx_peer_rate_stats_tlv 1887 * 3 bit htt_rx_peer_rate_stats_tlv 1888 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1889 * 5 bit htt_rx_tid_stats_tlv 1890 * 6 bit htt_msdu_flow_stats_tlv 1891 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1892 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1893 * [Bit31 : Bit16] reserved 1894 */ 1895 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1896 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1897 1898 /* Used to set different configs to the specified stats type.*/ 1899 struct htt_ext_stats_cfg_params { 1900 u32 cfg0; 1901 u32 cfg1; 1902 u32 cfg2; 1903 u32 cfg3; 1904 }; 1905 1906 enum vdev_stats_offload_timer_duration { 1907 ATH12K_STATS_TIMER_DUR_500MS = 1, 1908 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1909 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1910 }; 1911 1912 #define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1913 #define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1914 #define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1915 #define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1916 #define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1917 #define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1918 1919 struct htt_mac_addr { 1920 __le32 mac_addr_l32; 1921 __le32 mac_addr_h16; 1922 } __packed; 1923 1924 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1925 { 1926 memcpy(addr, &addr_l32, 4); 1927 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1928 } 1929 1930 int ath12k_dp_service_srng(struct ath12k_base *ab, 1931 struct ath12k_ext_irq_grp *irq_grp, 1932 int budget); 1933 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1934 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif); 1935 void ath12k_dp_free(struct ath12k_base *ab); 1936 int ath12k_dp_alloc(struct ath12k_base *ab); 1937 void ath12k_dp_cc_config(struct ath12k_base *ab); 1938 void ath12k_dp_partner_cc_init(struct ath12k_base *ab); 1939 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1940 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar); 1941 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1942 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1943 int mac_id, enum hal_ring_type ring_type); 1944 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1945 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1946 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1947 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1948 enum hal_ring_type type, int ring_num, 1949 int mac_id, int num_entries); 1950 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1951 struct dp_link_desc_bank *desc_bank, 1952 u32 ring_type, struct dp_srng *ring); 1953 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1954 struct dp_link_desc_bank *link_desc_banks, 1955 u32 ring_type, struct hal_srng *srng, 1956 u32 n_link_desc); 1957 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1958 u32 cookie); 1959 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1960 u32 desc_id); 1961 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab); 1962 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab); 1963 #endif 1964