1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_rx.h" 11 #include "hw.h" 12 13 #define MAX_RXDMA_PER_PDEV 2 14 15 struct ath12k_base; 16 struct ath12k_peer; 17 struct ath12k_dp; 18 struct ath12k_vif; 19 struct hal_tcl_status_ring; 20 struct ath12k_ext_irq_grp; 21 22 #define DP_MON_PURGE_TIMEOUT_MS 100 23 #define DP_MON_SERVICE_BUDGET 128 24 25 struct dp_srng { 26 u32 *vaddr_unaligned; 27 u32 *vaddr; 28 dma_addr_t paddr_unaligned; 29 dma_addr_t paddr; 30 int size; 31 u32 ring_id; 32 }; 33 34 struct dp_rxdma_mon_ring { 35 struct dp_srng refill_buf_ring; 36 struct idr bufs_idr; 37 /* Protects bufs_idr */ 38 spinlock_t idr_lock; 39 int bufs_max; 40 }; 41 42 struct dp_rxdma_ring { 43 struct dp_srng refill_buf_ring; 44 int bufs_max; 45 }; 46 47 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 48 49 struct dp_tx_ring { 50 u8 tcl_data_ring_id; 51 struct dp_srng tcl_data_ring; 52 struct dp_srng tcl_comp_ring; 53 struct hal_wbm_completion_ring_tx *tx_status; 54 int tx_status_head; 55 int tx_status_tail; 56 }; 57 58 struct ath12k_pdev_mon_stats { 59 u32 status_ppdu_state; 60 u32 status_ppdu_start; 61 u32 status_ppdu_end; 62 u32 status_ppdu_compl; 63 u32 status_ppdu_start_mis; 64 u32 status_ppdu_end_mis; 65 u32 status_ppdu_done; 66 u32 dest_ppdu_done; 67 u32 dest_mpdu_done; 68 u32 dest_mpdu_drop; 69 u32 dup_mon_linkdesc_cnt; 70 u32 dup_mon_buf_cnt; 71 }; 72 73 struct dp_link_desc_bank { 74 void *vaddr_unaligned; 75 void *vaddr; 76 dma_addr_t paddr_unaligned; 77 dma_addr_t paddr; 78 u32 size; 79 }; 80 81 /* Size to enforce scatter idle list mode */ 82 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 83 #define DP_LINK_DESC_BANKS_MAX 8 84 85 #define DP_LINK_DESC_START 0x4000 86 #define DP_LINK_DESC_SHIFT 3 87 88 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 89 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 90 91 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 92 93 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 94 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 95 #define DP_RX_DESC_COOKIE_MAX \ 96 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 97 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 98 99 enum ath12k_dp_ppdu_state { 100 DP_PPDU_STATUS_START, 101 DP_PPDU_STATUS_DONE, 102 }; 103 104 struct dp_mon_mpdu { 105 struct list_head list; 106 struct sk_buff *head; 107 struct sk_buff *tail; 108 }; 109 110 #define DP_MON_MAX_STATUS_BUF 32 111 112 struct ath12k_mon_data { 113 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 114 struct hal_rx_mon_ppdu_info mon_ppdu_info; 115 116 u32 mon_ppdu_status; 117 u32 mon_last_buf_cookie; 118 u64 mon_last_linkdesc_paddr; 119 u16 chan_noise_floor; 120 121 struct ath12k_pdev_mon_stats rx_mon_stats; 122 /* lock for monitor data */ 123 spinlock_t mon_lock; 124 struct sk_buff_head rx_status_q; 125 struct dp_mon_mpdu *mon_mpdu; 126 struct list_head dp_rx_mon_mpdu_list; 127 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF]; 128 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 129 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 130 }; 131 132 struct ath12k_pdev_dp { 133 u32 mac_id; 134 atomic_t num_tx_pending; 135 wait_queue_head_t tx_empty_waitq; 136 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 137 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 138 139 struct ieee80211_rx_status rx_status; 140 struct ath12k_mon_data mon_data; 141 }; 142 143 #define DP_NUM_CLIENTS_MAX 64 144 #define DP_AVG_TIDS_PER_CLIENT 2 145 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 146 #define DP_AVG_MSDUS_PER_FLOW 128 147 #define DP_AVG_FLOWS_PER_TID 2 148 #define DP_AVG_MPDUS_PER_TID_MAX 128 149 #define DP_AVG_MSDUS_PER_MPDU 4 150 151 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 152 153 #define DP_BA_WIN_SZ_MAX 1024 154 155 #define DP_TCL_NUM_RING_MAX 4 156 157 #define DP_IDLE_SCATTER_BUFS_MAX 16 158 159 #define DP_WBM_RELEASE_RING_SIZE 64 160 #define DP_TCL_DATA_RING_SIZE 512 161 #define DP_TX_COMP_RING_SIZE 32768 162 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 163 #define DP_TCL_CMD_RING_SIZE 32 164 #define DP_TCL_STATUS_RING_SIZE 32 165 #define DP_REO_DST_RING_MAX 8 166 #define DP_REO_DST_RING_SIZE 2048 167 #define DP_REO_REINJECT_RING_SIZE 32 168 #define DP_RX_RELEASE_RING_SIZE 1024 169 #define DP_REO_EXCEPTION_RING_SIZE 128 170 #define DP_REO_CMD_RING_SIZE 128 171 #define DP_REO_STATUS_RING_SIZE 2048 172 #define DP_RXDMA_BUF_RING_SIZE 4096 173 #define DP_RX_MAC_BUF_RING_SIZE 2048 174 #define DP_RXDMA_REFILL_RING_SIZE 2048 175 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 176 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 177 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 178 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 179 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 180 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 181 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 182 183 #define DP_TX_MONITOR_BUF_SIZE 2048 184 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 185 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 186 187 #define DP_RX_BUFFER_SIZE 2048 188 #define DP_RX_BUFFER_SIZE_LITE 1024 189 #define DP_RX_BUFFER_ALIGN_SIZE 128 190 191 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 192 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 193 194 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 195 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 196 197 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 198 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 199 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 200 201 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 202 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 203 204 #define ATH12K_NUM_POOL_TX_DESC 32768 205 206 /* TODO: revisit this count during testing */ 207 #define ATH12K_RX_DESC_COUNT (12288) 208 209 #define ATH12K_PAGE_SIZE PAGE_SIZE 210 211 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 212 * SPT pages which makes lower 12bits 0 213 */ 214 #define ATH12K_MAX_PPT_ENTRIES 1024 215 216 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 217 #define ATH12K_MAX_SPT_ENTRIES 512 218 219 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 220 221 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 222 ATH12K_MAX_SPT_ENTRIES) 223 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 224 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 225 226 /* The SPT pages are divided for RX and TX, first block for RX 227 * and remaining for TX 228 */ 229 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 230 231 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 232 233 /* 4K aligned address have last 12 bits set to 0, this check is done 234 * so that two spt pages address can be stored per 8bytes 235 * of CMEM (PPT) 236 */ 237 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 238 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 239 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 240 241 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 242 #define ATH12K_CMEM_ADDR_MSB 0x10 243 244 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 245 #define ATH12K_CC_SPT_MSB 8 246 #define ATH12K_CC_PPT_MSB 19 247 #define ATH12K_CC_PPT_SHIFT 9 248 #define ATH12k_DP_CC_COOKIE_SPT GENMASK(8, 0) 249 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 250 251 #define DP_REO_QREF_NUM GENMASK(31, 16) 252 #define DP_MAX_PEER_ID 2047 253 254 /* Total size of the LUT is based on 2K peers, each having reference 255 * for 17tids, note each entry is of type ath12k_reo_queue_ref 256 * hence total size is 2048 * 17 * 8 = 278528 257 */ 258 #define DP_REOQ_LUT_SIZE 278528 259 260 /* Invalid TX Bank ID value */ 261 #define DP_INVALID_BANK_ID -1 262 263 struct ath12k_dp_tx_bank_profile { 264 u8 is_configured; 265 u32 num_users; 266 u32 bank_config; 267 }; 268 269 struct ath12k_hp_update_timer { 270 struct timer_list timer; 271 bool started; 272 bool init; 273 u32 tx_num; 274 u32 timer_tx_num; 275 u32 ring_id; 276 u32 interval; 277 struct ath12k_base *ab; 278 }; 279 280 struct ath12k_rx_desc_info { 281 struct list_head list; 282 struct sk_buff *skb; 283 u32 cookie; 284 u32 magic; 285 }; 286 287 struct ath12k_tx_desc_info { 288 struct list_head list; 289 struct sk_buff *skb; 290 u32 desc_id; /* Cookie */ 291 u8 mac_id; 292 u8 pool_id; 293 }; 294 295 struct ath12k_spt_info { 296 dma_addr_t paddr; 297 u64 *vaddr; 298 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 299 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 300 }; 301 302 struct ath12k_reo_queue_ref { 303 u32 info0; 304 u32 info1; 305 } __packed; 306 307 struct ath12k_reo_q_addr_lut { 308 dma_addr_t paddr; 309 u32 *vaddr; 310 }; 311 312 struct ath12k_dp { 313 struct ath12k_base *ab; 314 u8 num_bank_profiles; 315 /* protects the access and update of bank_profiles */ 316 spinlock_t tx_bank_lock; 317 struct ath12k_dp_tx_bank_profile *bank_profiles; 318 enum ath12k_htc_ep_id eid; 319 struct completion htt_tgt_version_received; 320 u8 htt_tgt_ver_major; 321 u8 htt_tgt_ver_minor; 322 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 323 struct dp_srng wbm_idle_ring; 324 struct dp_srng wbm_desc_rel_ring; 325 struct dp_srng tcl_cmd_ring; 326 struct dp_srng tcl_status_ring; 327 struct dp_srng reo_reinject_ring; 328 struct dp_srng rx_rel_ring; 329 struct dp_srng reo_except_ring; 330 struct dp_srng reo_cmd_ring; 331 struct dp_srng reo_status_ring; 332 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 333 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 334 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 335 struct list_head reo_cmd_list; 336 struct list_head reo_cmd_cache_flush_list; 337 u32 reo_cmd_cache_flush_count; 338 339 /* protects access to below fields, 340 * - reo_cmd_list 341 * - reo_cmd_cache_flush_list 342 * - reo_cmd_cache_flush_count 343 */ 344 spinlock_t reo_cmd_lock; 345 struct ath12k_hp_update_timer reo_cmd_timer; 346 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 347 struct ath12k_spt_info *spt_info; 348 u32 num_spt_pages; 349 struct list_head rx_desc_free_list; 350 struct list_head rx_desc_used_list; 351 /* protects the free and used desc list */ 352 spinlock_t rx_desc_lock; 353 354 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 355 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 356 /* protects the free and used desc lists */ 357 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 358 359 struct dp_rxdma_ring rx_refill_buf_ring; 360 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 361 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 362 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 363 struct dp_rxdma_mon_ring tx_mon_buf_ring; 364 struct ath12k_reo_q_addr_lut reoq_lut; 365 }; 366 367 /* HTT definitions */ 368 369 #define HTT_TCL_META_DATA_TYPE BIT(0) 370 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 371 372 /* vdev meta data */ 373 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 374 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 375 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 376 377 /* peer meta data */ 378 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 379 380 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 381 382 /* HTT tx completion is overlaid in wbm_release_ring */ 383 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 384 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 385 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 386 387 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 388 389 struct htt_tx_wbm_completion { 390 __le32 rsvd0[2]; 391 __le32 info0; 392 __le32 info1; 393 __le32 info2; 394 __le32 info3; 395 __le32 info4; 396 __le32 rsvd1; 397 398 } __packed; 399 400 enum htt_h2t_msg_type { 401 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 402 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 403 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 404 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 405 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 406 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 407 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 408 }; 409 410 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 411 412 struct htt_ver_req_cmd { 413 __le32 ver_reg_info; 414 } __packed; 415 416 enum htt_srng_ring_type { 417 HTT_HW_TO_SW_RING, 418 HTT_SW_TO_HW_RING, 419 HTT_SW_TO_SW_RING, 420 }; 421 422 enum htt_srng_ring_id { 423 HTT_RXDMA_HOST_BUF_RING, 424 HTT_RXDMA_MONITOR_STATUS_RING, 425 HTT_RXDMA_MONITOR_BUF_RING, 426 HTT_RXDMA_MONITOR_DESC_RING, 427 HTT_RXDMA_MONITOR_DEST_RING, 428 HTT_HOST1_TO_FW_RXBUF_RING, 429 HTT_HOST2_TO_FW_RXBUF_RING, 430 HTT_RXDMA_NON_MONITOR_DEST_RING, 431 HTT_TX_MON_HOST2MON_BUF_RING, 432 HTT_TX_MON_MON2HOST_DEST_RING, 433 }; 434 435 /* host -> target HTT_SRING_SETUP message 436 * 437 * After target is booted up, Host can send SRING setup message for 438 * each host facing LMAC SRING. Target setups up HW registers based 439 * on setup message and confirms back to Host if response_required is set. 440 * Host should wait for confirmation message before sending new SRING 441 * setup message 442 * 443 * The message would appear as follows: 444 * 445 * |31 24|23 20|19|18 16|15|14 8|7 0| 446 * |--------------- +-----------------+----------------+------------------| 447 * | ring_type | ring_id | pdev_id | msg_type | 448 * |----------------------------------------------------------------------| 449 * | ring_base_addr_lo | 450 * |----------------------------------------------------------------------| 451 * | ring_base_addr_hi | 452 * |----------------------------------------------------------------------| 453 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 454 * |----------------------------------------------------------------------| 455 * | ring_head_offset32_remote_addr_lo | 456 * |----------------------------------------------------------------------| 457 * | ring_head_offset32_remote_addr_hi | 458 * |----------------------------------------------------------------------| 459 * | ring_tail_offset32_remote_addr_lo | 460 * |----------------------------------------------------------------------| 461 * | ring_tail_offset32_remote_addr_hi | 462 * |----------------------------------------------------------------------| 463 * | ring_msi_addr_lo | 464 * |----------------------------------------------------------------------| 465 * | ring_msi_addr_hi | 466 * |----------------------------------------------------------------------| 467 * | ring_msi_data | 468 * |----------------------------------------------------------------------| 469 * | intr_timer_th |IM| intr_batch_counter_th | 470 * |----------------------------------------------------------------------| 471 * | reserved |RR|PTCF| intr_low_threshold | 472 * |----------------------------------------------------------------------| 473 * Where 474 * IM = sw_intr_mode 475 * RR = response_required 476 * PTCF = prefetch_timer_cfg 477 * 478 * The message is interpreted as follows: 479 * dword0 - b'0:7 - msg_type: This will be set to 480 * HTT_H2T_MSG_TYPE_SRING_SETUP 481 * b'8:15 - pdev_id: 482 * 0 (for rings at SOC/UMAC level), 483 * 1/2/3 mac id (for rings at LMAC level) 484 * b'16:23 - ring_id: identify which ring is to setup, 485 * more details can be got from enum htt_srng_ring_id 486 * b'24:31 - ring_type: identify type of host rings, 487 * more details can be got from enum htt_srng_ring_type 488 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 489 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 490 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 491 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 492 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 493 * SW_TO_HW_RING. 494 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 495 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 496 * Lower 32 bits of memory address of the remote variable 497 * storing the 4-byte word offset that identifies the head 498 * element within the ring. 499 * (The head offset variable has type u32.) 500 * Valid for HW_TO_SW and SW_TO_SW rings. 501 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 502 * Upper 32 bits of memory address of the remote variable 503 * storing the 4-byte word offset that identifies the head 504 * element within the ring. 505 * (The head offset variable has type u32.) 506 * Valid for HW_TO_SW and SW_TO_SW rings. 507 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 508 * Lower 32 bits of memory address of the remote variable 509 * storing the 4-byte word offset that identifies the tail 510 * element within the ring. 511 * (The tail offset variable has type u32.) 512 * Valid for HW_TO_SW and SW_TO_SW rings. 513 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 514 * Upper 32 bits of memory address of the remote variable 515 * storing the 4-byte word offset that identifies the tail 516 * element within the ring. 517 * (The tail offset variable has type u32.) 518 * Valid for HW_TO_SW and SW_TO_SW rings. 519 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 520 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 521 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 522 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 523 * dword10 - b'0:31 - ring_msi_data: MSI data 524 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 525 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 526 * dword11 - b'0:14 - intr_batch_counter_th: 527 * batch counter threshold is in units of 4-byte words. 528 * HW internally maintains and increments batch count. 529 * (see SRING spec for detail description). 530 * When batch count reaches threshold value, an interrupt 531 * is generated by HW. 532 * b'15 - sw_intr_mode: 533 * This configuration shall be static. 534 * Only programmed at power up. 535 * 0: generate pulse style sw interrupts 536 * 1: generate level style sw interrupts 537 * b'16:31 - intr_timer_th: 538 * The timer init value when timer is idle or is 539 * initialized to start downcounting. 540 * In 8us units (to cover a range of 0 to 524 ms) 541 * dword12 - b'0:15 - intr_low_threshold: 542 * Used only by Consumer ring to generate ring_sw_int_p. 543 * Ring entries low threshold water mark, that is used 544 * in combination with the interrupt timer as well as 545 * the clearing of the level interrupt. 546 * b'16:18 - prefetch_timer_cfg: 547 * Used only by Consumer ring to set timer mode to 548 * support Application prefetch handling. 549 * The external tail offset/pointer will be updated 550 * at following intervals: 551 * 3'b000: (Prefetch feature disabled; used only for debug) 552 * 3'b001: 1 usec 553 * 3'b010: 4 usec 554 * 3'b011: 8 usec (default) 555 * 3'b100: 16 usec 556 * Others: Reserved 557 * b'19 - response_required: 558 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 559 * b'20:31 - reserved: reserved for future use 560 */ 561 562 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 563 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 564 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 565 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 566 567 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 568 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 569 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 570 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 571 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 572 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 573 574 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 575 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 576 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 577 578 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 579 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 580 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 581 582 struct htt_srng_setup_cmd { 583 __le32 info0; 584 __le32 ring_base_addr_lo; 585 __le32 ring_base_addr_hi; 586 __le32 info1; 587 __le32 ring_head_off32_remote_addr_lo; 588 __le32 ring_head_off32_remote_addr_hi; 589 __le32 ring_tail_off32_remote_addr_lo; 590 __le32 ring_tail_off32_remote_addr_hi; 591 __le32 ring_msi_addr_lo; 592 __le32 ring_msi_addr_hi; 593 __le32 msi_data; 594 __le32 intr_info; 595 __le32 info2; 596 } __packed; 597 598 /* host -> target FW PPDU_STATS config message 599 * 600 * @details 601 * The following field definitions describe the format of the HTT host 602 * to target FW for PPDU_STATS_CFG msg. 603 * The message allows the host to configure the PPDU_STATS_IND messages 604 * produced by the target. 605 * 606 * |31 24|23 16|15 8|7 0| 607 * |-----------------------------------------------------------| 608 * | REQ bit mask | pdev_mask | msg type | 609 * |-----------------------------------------------------------| 610 * Header fields: 611 * - MSG_TYPE 612 * Bits 7:0 613 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 614 * Value: 0x11 615 * - PDEV_MASK 616 * Bits 8:15 617 * Purpose: identifies which pdevs this PPDU stats configuration applies to 618 * Value: This is a overloaded field, refer to usage and interpretation of 619 * PDEV in interface document. 620 * Bit 8 : Reserved for SOC stats 621 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 622 * Indicates MACID_MASK in DBS 623 * - REQ_TLV_BIT_MASK 624 * Bits 16:31 625 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 626 * needs to be included in the target's PPDU_STATS_IND messages. 627 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 628 * 629 */ 630 631 struct htt_ppdu_stats_cfg_cmd { 632 __le32 msg; 633 } __packed; 634 635 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 636 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 637 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 638 639 enum htt_ppdu_stats_tag_type { 640 HTT_PPDU_STATS_TAG_COMMON, 641 HTT_PPDU_STATS_TAG_USR_COMMON, 642 HTT_PPDU_STATS_TAG_USR_RATE, 643 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 644 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 645 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 646 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 647 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 648 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 649 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 650 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 651 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 652 HTT_PPDU_STATS_TAG_INFO, 653 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 654 655 /* New TLV's are added above to this line */ 656 HTT_PPDU_STATS_TAG_MAX, 657 }; 658 659 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 660 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 661 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 662 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 663 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 664 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 665 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 666 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 667 668 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 669 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 670 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 671 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 672 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 673 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 674 HTT_PPDU_STATS_TAG_DEFAULT) 675 676 enum htt_stats_internal_ppdu_frametype { 677 HTT_STATS_PPDU_FTYPE_CTRL, 678 HTT_STATS_PPDU_FTYPE_DATA, 679 HTT_STATS_PPDU_FTYPE_BAR, 680 HTT_STATS_PPDU_FTYPE_MAX 681 }; 682 683 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 684 * 685 * details: 686 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 687 * configure RXDMA rings. 688 * The configuration is per ring based and includes both packet subtypes 689 * and PPDU/MPDU TLVs. 690 * 691 * The message would appear as follows: 692 * 693 * |31 26|25|24|23 16|15 8|7 0| 694 * |-----------------+----------------+----------------+---------------| 695 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 696 * |-------------------------------------------------------------------| 697 * | rsvd2 | ring_buffer_size | 698 * |-------------------------------------------------------------------| 699 * | packet_type_enable_flags_0 | 700 * |-------------------------------------------------------------------| 701 * | packet_type_enable_flags_1 | 702 * |-------------------------------------------------------------------| 703 * | packet_type_enable_flags_2 | 704 * |-------------------------------------------------------------------| 705 * | packet_type_enable_flags_3 | 706 * |-------------------------------------------------------------------| 707 * | tlv_filter_in_flags | 708 * |-------------------------------------------------------------------| 709 * Where: 710 * PS = pkt_swap 711 * SS = status_swap 712 * The message is interpreted as follows: 713 * dword0 - b'0:7 - msg_type: This will be set to 714 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 715 * b'8:15 - pdev_id: 716 * 0 (for rings at SOC/UMAC level), 717 * 1/2/3 mac id (for rings at LMAC level) 718 * b'16:23 - ring_id : Identify the ring to configure. 719 * More details can be got from enum htt_srng_ring_id 720 * b'24 - status_swap: 1 is to swap status TLV 721 * b'25 - pkt_swap: 1 is to swap packet TLV 722 * b'26:31 - rsvd1: reserved for future use 723 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 724 * in byte units. 725 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 726 * - b'16:31 - rsvd2: Reserved for future use 727 * dword2 - b'0:31 - packet_type_enable_flags_0: 728 * Enable MGMT packet from 0b0000 to 0b1001 729 * bits from low to high: FP, MD, MO - 3 bits 730 * FP: Filter_Pass 731 * MD: Monitor_Direct 732 * MO: Monitor_Other 733 * 10 mgmt subtypes * 3 bits -> 30 bits 734 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 735 * dword3 - b'0:31 - packet_type_enable_flags_1: 736 * Enable MGMT packet from 0b1010 to 0b1111 737 * bits from low to high: FP, MD, MO - 3 bits 738 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 739 * dword4 - b'0:31 - packet_type_enable_flags_2: 740 * Enable CTRL packet from 0b0000 to 0b1001 741 * bits from low to high: FP, MD, MO - 3 bits 742 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 743 * dword5 - b'0:31 - packet_type_enable_flags_3: 744 * Enable CTRL packet from 0b1010 to 0b1111, 745 * MCAST_DATA, UCAST_DATA, NULL_DATA 746 * bits from low to high: FP, MD, MO - 3 bits 747 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 748 * dword6 - b'0:31 - tlv_filter_in_flags: 749 * Filter in Attention/MPDU/PPDU/Header/User tlvs 750 * Refer to CFG_TLV_FILTER_IN_FLAG defs 751 */ 752 753 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 754 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 755 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 756 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 757 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 758 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 759 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26) 760 761 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 762 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 763 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 764 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 765 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 766 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 767 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 768 769 enum htt_rx_filter_tlv_flags { 770 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 771 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 772 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 773 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 774 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 775 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 776 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 777 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 778 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 779 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 780 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 781 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 782 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 783 }; 784 785 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 786 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 787 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 788 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 789 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 790 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 791 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 792 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 793 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 794 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 795 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 796 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 797 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 798 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 799 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 800 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 801 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 802 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 803 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 804 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 805 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 806 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 807 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 808 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 809 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 810 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 811 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 812 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 813 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 814 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 815 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 816 }; 817 818 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 819 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 820 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 821 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 822 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 823 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 824 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 825 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 826 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 827 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 828 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 829 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 830 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 831 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 832 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 833 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 834 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 835 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 836 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 837 }; 838 839 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 840 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 841 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 842 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 843 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 844 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 845 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 846 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 847 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 848 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 849 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 850 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 851 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 852 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 853 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 854 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 855 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 856 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 857 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 858 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 859 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 860 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 861 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 862 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 863 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 864 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 865 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 866 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 867 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 868 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 869 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 870 }; 871 872 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 873 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 874 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 875 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 876 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 877 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 878 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 879 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 880 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 881 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 882 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 883 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 884 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 885 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 886 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 887 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 888 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 889 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 890 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 891 }; 892 893 enum htt_rx_data_pkt_filter_tlv_flasg3 { 894 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 895 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 896 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 897 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 898 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 899 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 900 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 901 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 902 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 903 }; 904 905 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 906 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 907 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 908 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 909 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 910 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 911 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 912 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 913 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 914 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 915 916 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 917 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 918 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 919 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 920 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 921 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 922 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 923 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 924 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 925 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 926 927 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 928 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 929 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 930 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 931 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 932 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 933 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 934 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 935 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 936 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 937 938 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 939 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 940 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 941 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 942 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 943 944 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 945 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 946 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 947 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 948 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 949 950 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 951 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 952 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 953 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 954 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 955 956 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 957 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 958 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 959 960 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 961 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 962 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 963 964 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 965 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 966 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 967 968 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 969 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 970 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 971 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 972 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 973 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 974 975 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 976 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 977 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 978 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 979 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 980 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 981 982 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 983 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 984 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 985 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 986 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 987 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 988 989 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 990 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 991 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 992 993 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 994 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 995 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 996 997 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 998 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 999 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1000 1001 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1002 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1003 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1004 1005 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1006 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1007 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1008 1009 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1010 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1011 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1012 1013 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1014 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1015 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1016 1017 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1018 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1019 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1020 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1021 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1022 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1023 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1024 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1025 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1026 1027 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1028 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1029 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1030 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1031 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1032 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1033 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1034 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1035 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1036 1037 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1038 1039 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1040 1041 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1042 1043 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1044 1045 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1046 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1047 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1048 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1049 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1050 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1051 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1052 1053 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1054 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1055 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1056 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1057 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1058 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1059 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1060 1061 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1062 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1063 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1064 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1065 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1066 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1067 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1068 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1069 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1070 1071 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1072 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1073 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1074 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1075 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1076 1077 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1078 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1079 1080 struct htt_rx_ring_selection_cfg_cmd { 1081 __le32 info0; 1082 __le32 info1; 1083 __le32 pkt_type_en_flags0; 1084 __le32 pkt_type_en_flags1; 1085 __le32 pkt_type_en_flags2; 1086 __le32 pkt_type_en_flags3; 1087 __le32 rx_filter_tlv; 1088 __le32 rx_packet_offset; 1089 __le32 rx_mpdu_offset; 1090 __le32 rx_msdu_offset; 1091 __le32 rx_attn_offset; 1092 } __packed; 1093 1094 struct htt_rx_ring_tlv_filter { 1095 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1096 u32 pkt_filter_flags0; /* MGMT */ 1097 u32 pkt_filter_flags1; /* MGMT */ 1098 u32 pkt_filter_flags2; /* CTRL */ 1099 u32 pkt_filter_flags3; /* DATA */ 1100 bool offset_valid; 1101 u16 rx_packet_offset; 1102 u16 rx_header_offset; 1103 u16 rx_mpdu_end_offset; 1104 u16 rx_mpdu_start_offset; 1105 u16 rx_msdu_end_offset; 1106 u16 rx_msdu_start_offset; 1107 u16 rx_attn_offset; 1108 }; 1109 1110 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1111 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1112 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1113 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1114 1115 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1116 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1117 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1118 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1119 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1120 1121 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1122 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1123 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1124 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1125 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1126 1127 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1128 1129 struct htt_tx_ring_selection_cfg_cmd { 1130 __le32 info0; 1131 __le32 info1; 1132 __le32 info2; 1133 __le32 tlv_filter_mask_in0; 1134 __le32 tlv_filter_mask_in1; 1135 __le32 tlv_filter_mask_in2; 1136 __le32 tlv_filter_mask_in3; 1137 __le32 reserved[3]; 1138 } __packed; 1139 1140 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1141 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1142 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1143 1144 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1145 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1146 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1147 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1148 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1149 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1150 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1151 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1152 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1153 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1154 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1155 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1156 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1157 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1158 1159 struct htt_tx_ring_tlv_filter { 1160 u32 tx_mon_downstream_tlv_flags; 1161 u32 tx_mon_upstream_tlv_flags0; 1162 u32 tx_mon_upstream_tlv_flags1; 1163 u32 tx_mon_upstream_tlv_flags2; 1164 bool tx_mon_mgmt_filter; 1165 bool tx_mon_data_filter; 1166 bool tx_mon_ctrl_filter; 1167 u16 tx_mon_pkt_dma_len; 1168 } __packed; 1169 1170 enum htt_tx_mon_upstream_tlv_flags0 { 1171 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1172 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1173 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1174 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1175 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1176 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1177 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1178 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1179 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1180 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1181 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1182 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1183 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1184 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1185 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1186 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1187 }; 1188 1189 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1190 1191 /* HTT message target->host */ 1192 1193 enum htt_t2h_msg_type { 1194 HTT_T2H_MSG_TYPE_VERSION_CONF, 1195 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1196 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1197 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1198 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1199 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1200 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1201 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1202 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1203 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1204 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1205 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1206 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1207 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1208 }; 1209 1210 #define HTT_TARGET_VERSION_MAJOR 3 1211 1212 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1213 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1214 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1215 1216 struct htt_t2h_version_conf_msg { 1217 __le32 version; 1218 } __packed; 1219 1220 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1221 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1222 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1223 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1224 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1225 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1226 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1227 1228 struct htt_t2h_peer_map_event { 1229 __le32 info; 1230 __le32 mac_addr_l32; 1231 __le32 info1; 1232 __le32 info2; 1233 } __packed; 1234 1235 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1236 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1237 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1238 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1239 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1240 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1241 1242 struct htt_t2h_peer_unmap_event { 1243 __le32 info; 1244 __le32 mac_addr_l32; 1245 __le32 info1; 1246 } __packed; 1247 1248 struct htt_resp_msg { 1249 union { 1250 struct htt_t2h_version_conf_msg version_msg; 1251 struct htt_t2h_peer_map_event peer_map_ev; 1252 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1253 }; 1254 } __packed; 1255 1256 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1257 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1258 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1259 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1260 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1261 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1262 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1263 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1264 1265 struct htt_t2h_vdev_txrx_stats_ind { 1266 __le32 vdev_id; 1267 __le32 rx_msdu_byte_cnt_lo; 1268 __le32 rx_msdu_byte_cnt_hi; 1269 __le32 rx_msdu_cnt_lo; 1270 __le32 rx_msdu_cnt_hi; 1271 __le32 tx_msdu_byte_cnt_lo; 1272 __le32 tx_msdu_byte_cnt_hi; 1273 __le32 tx_msdu_cnt_lo; 1274 __le32 tx_msdu_cnt_hi; 1275 __le32 tx_retry_cnt_lo; 1276 __le32 tx_retry_cnt_hi; 1277 __le32 tx_retry_byte_cnt_lo; 1278 __le32 tx_retry_byte_cnt_hi; 1279 __le32 tx_drop_cnt_lo; 1280 __le32 tx_drop_cnt_hi; 1281 __le32 tx_drop_byte_cnt_lo; 1282 __le32 tx_drop_byte_cnt_hi; 1283 __le32 msdu_ttl_cnt_lo; 1284 __le32 msdu_ttl_cnt_hi; 1285 __le32 msdu_ttl_byte_cnt_lo; 1286 __le32 msdu_ttl_byte_cnt_hi; 1287 } __packed; 1288 1289 struct htt_t2h_vdev_common_stats_tlv { 1290 __le32 soc_drop_count_lo; 1291 __le32 soc_drop_count_hi; 1292 } __packed; 1293 1294 /* ppdu stats 1295 * 1296 * @details 1297 * The following field definitions describe the format of the HTT target 1298 * to host ppdu stats indication message. 1299 * 1300 * 1301 * |31 16|15 12|11 10|9 8|7 0 | 1302 * |----------------------------------------------------------------------| 1303 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1304 * |----------------------------------------------------------------------| 1305 * | ppdu_id | 1306 * |----------------------------------------------------------------------| 1307 * | Timestamp in us | 1308 * |----------------------------------------------------------------------| 1309 * | reserved | 1310 * |----------------------------------------------------------------------| 1311 * | type-specific stats info | 1312 * | (see htt_ppdu_stats.h) | 1313 * |----------------------------------------------------------------------| 1314 * Header fields: 1315 * - MSG_TYPE 1316 * Bits 7:0 1317 * Purpose: Identifies this is a PPDU STATS indication 1318 * message. 1319 * Value: 0x1d 1320 * - mac_id 1321 * Bits 9:8 1322 * Purpose: mac_id of this ppdu_id 1323 * Value: 0-3 1324 * - pdev_id 1325 * Bits 11:10 1326 * Purpose: pdev_id of this ppdu_id 1327 * Value: 0-3 1328 * 0 (for rings at SOC level), 1329 * 1/2/3 PDEV -> 0/1/2 1330 * - payload_size 1331 * Bits 31:16 1332 * Purpose: total tlv size 1333 * Value: payload_size in bytes 1334 */ 1335 1336 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1337 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1338 1339 struct ath12k_htt_ppdu_stats_msg { 1340 __le32 info; 1341 __le32 ppdu_id; 1342 __le32 timestamp; 1343 __le32 rsvd; 1344 u8 data[]; 1345 } __packed; 1346 1347 struct htt_tlv { 1348 __le32 header; 1349 u8 value[]; 1350 } __packed; 1351 1352 #define HTT_TLV_TAG GENMASK(11, 0) 1353 #define HTT_TLV_LEN GENMASK(23, 12) 1354 1355 enum HTT_PPDU_STATS_BW { 1356 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1357 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1358 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1359 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1360 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1361 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1362 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1363 }; 1364 1365 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1366 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1367 /* bw - HTT_PPDU_STATS_BW */ 1368 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1369 1370 struct htt_ppdu_stats_common { 1371 __le32 ppdu_id; 1372 __le16 sched_cmdid; 1373 u8 ring_id; 1374 u8 num_users; 1375 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1376 __le32 chain_mask; 1377 __le32 fes_duration_us; /* frame exchange sequence */ 1378 __le32 ppdu_sch_eval_start_tstmp_us; 1379 __le32 ppdu_sch_end_tstmp_us; 1380 __le32 ppdu_start_tstmp_us; 1381 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1382 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1383 */ 1384 __le16 phy_mode; 1385 __le16 bw_mhz; 1386 } __packed; 1387 1388 enum htt_ppdu_stats_gi { 1389 HTT_PPDU_STATS_SGI_0_8_US, 1390 HTT_PPDU_STATS_SGI_0_4_US, 1391 HTT_PPDU_STATS_SGI_1_6_US, 1392 HTT_PPDU_STATS_SGI_3_2_US, 1393 }; 1394 1395 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1396 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1397 1398 enum HTT_PPDU_STATS_PPDU_TYPE { 1399 HTT_PPDU_STATS_PPDU_TYPE_SU, 1400 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1401 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1402 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1403 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1404 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1405 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1406 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1407 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1408 HTT_PPDU_STATS_PPDU_TYPE_MAX 1409 }; 1410 1411 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1412 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1413 1414 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1415 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1416 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1417 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1418 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1419 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1420 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1421 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1422 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1423 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1424 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1425 1426 #define HTT_USR_RATE_PREAMBLE(_val) \ 1427 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1428 #define HTT_USR_RATE_BW(_val) \ 1429 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1430 #define HTT_USR_RATE_NSS(_val) \ 1431 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1432 #define HTT_USR_RATE_MCS(_val) \ 1433 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1434 #define HTT_USR_RATE_GI(_val) \ 1435 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1436 #define HTT_USR_RATE_DCM(_val) \ 1437 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1438 1439 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1440 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1441 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1442 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1443 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1444 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1445 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1446 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1447 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1448 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1449 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1450 1451 struct htt_ppdu_stats_user_rate { 1452 u8 tid_num; 1453 u8 reserved0; 1454 __le16 sw_peer_id; 1455 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1456 __le16 ru_end; 1457 __le16 ru_start; 1458 __le16 resp_ru_end; 1459 __le16 resp_ru_start; 1460 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1461 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1462 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1463 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1464 } __packed; 1465 1466 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1467 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1468 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1469 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1470 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1471 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1472 1473 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1474 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1475 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1476 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1477 #define HTT_TX_INFO_RATECODE(_flags) \ 1478 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1479 #define HTT_TX_INFO_PEERID(_flags) \ 1480 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1481 1482 struct htt_tx_ppdu_stats_info { 1483 struct htt_tlv tlv_hdr; 1484 __le32 tx_success_bytes; 1485 __le32 tx_retry_bytes; 1486 __le32 tx_failed_bytes; 1487 __le32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1488 __le16 tx_success_msdus; 1489 __le16 tx_retry_msdus; 1490 __le16 tx_failed_msdus; 1491 __le16 tx_duration; /* united in us */ 1492 } __packed; 1493 1494 enum htt_ppdu_stats_usr_compln_status { 1495 HTT_PPDU_STATS_USER_STATUS_OK, 1496 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1497 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1498 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1499 HTT_PPDU_STATS_USER_STATUS_ABORT, 1500 }; 1501 1502 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1503 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1504 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1505 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1506 1507 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1508 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1509 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1510 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1511 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1512 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1513 1514 struct htt_ppdu_stats_usr_cmpltn_cmn { 1515 u8 status; 1516 u8 tid_num; 1517 __le16 sw_peer_id; 1518 /* RSSI value of last ack packet (units = dB above noise floor) */ 1519 __le32 ack_rssi; 1520 __le16 mpdu_tried; 1521 __le16 mpdu_success; 1522 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1523 } __packed; 1524 1525 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1526 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1527 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1528 1529 #define HTT_PPDU_STATS_NON_QOS_TID 16 1530 1531 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1532 __le32 ppdu_id; 1533 __le16 sw_peer_id; 1534 __le16 reserved0; 1535 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1536 __le16 current_seq; 1537 __le16 start_seq; 1538 __le32 success_bytes; 1539 } __packed; 1540 1541 struct htt_ppdu_user_stats { 1542 u16 peer_id; 1543 u16 delay_ba; 1544 u32 tlv_flags; 1545 bool is_valid_peer_id; 1546 struct htt_ppdu_stats_user_rate rate; 1547 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1548 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1549 }; 1550 1551 #define HTT_PPDU_STATS_MAX_USERS 8 1552 #define HTT_PPDU_DESC_MAX_DEPTH 16 1553 1554 struct htt_ppdu_stats { 1555 struct htt_ppdu_stats_common common; 1556 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1557 }; 1558 1559 struct htt_ppdu_stats_info { 1560 u32 tlv_bitmap; 1561 u32 ppdu_id; 1562 u32 frame_type; 1563 u32 frame_ctrl; 1564 u32 delay_ba; 1565 u32 bar_num_users; 1566 struct htt_ppdu_stats ppdu_stats; 1567 struct list_head list; 1568 }; 1569 1570 /* @brief target -> host MLO offset indiciation message 1571 * 1572 * @details 1573 * The following field definitions describe the format of the HTT target 1574 * to host mlo offset indication message. 1575 * 1576 * 1577 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1578 * |---------------------------------------------------------------------| 1579 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1580 * |---------------------------------------------------------------------| 1581 * | sync_timestamp_lo_us | 1582 * |---------------------------------------------------------------------| 1583 * | sync_timestamp_hi_us | 1584 * |---------------------------------------------------------------------| 1585 * | mlo_offset_lo | 1586 * |---------------------------------------------------------------------| 1587 * | mlo_offset_hi | 1588 * |---------------------------------------------------------------------| 1589 * | mlo_offset_clcks | 1590 * |---------------------------------------------------------------------| 1591 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1592 * |---------------------------------------------------------------------| 1593 * | rsvd3 |mlo_comp_timer | 1594 * |---------------------------------------------------------------------| 1595 * Header fields 1596 * - MSG_TYPE 1597 * Bits 7:0 1598 * Purpose: Identifies this is a MLO offset indication msg 1599 * - PDEV_ID 1600 * Bits 9:8 1601 * Purpose: Pdev of this MLO offset 1602 * - CHIP_ID 1603 * Bits 12:10 1604 * Purpose: chip_id of this MLO offset 1605 * - MAC_FREQ 1606 * Bits 28:13 1607 * - SYNC_TIMESTAMP_LO_US 1608 * Purpose: clock frequency of the mac HW block in MHz 1609 * Bits: 31:0 1610 * Purpose: lower 32 bits of the WLAN global time stamp at which 1611 * last sync interrupt was received 1612 * - SYNC_TIMESTAMP_HI_US 1613 * Bits: 31:0 1614 * Purpose: upper 32 bits of WLAN global time stamp at which 1615 * last sync interrupt was received 1616 * - MLO_OFFSET_LO 1617 * Bits: 31:0 1618 * Purpose: lower 32 bits of the MLO offset in us 1619 * - MLO_OFFSET_HI 1620 * Bits: 31:0 1621 * Purpose: upper 32 bits of the MLO offset in us 1622 * - MLO_COMP_US 1623 * Bits: 15:0 1624 * Purpose: MLO time stamp compensation applied in us 1625 * - MLO_COMP_CLCKS 1626 * Bits: 25:16 1627 * Purpose: MLO time stamp compensation applied in clock ticks 1628 * - MLO_COMP_TIMER 1629 * Bits: 21:0 1630 * Purpose: Periodic timer at which compensation is applied 1631 */ 1632 1633 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1634 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1635 1636 struct ath12k_htt_mlo_offset_msg { 1637 __le32 info; 1638 __le32 sync_timestamp_lo_us; 1639 __le32 sync_timestamp_hi_us; 1640 __le32 mlo_offset_hi; 1641 __le32 mlo_offset_lo; 1642 __le32 mlo_offset_clks; 1643 __le32 mlo_comp_clks; 1644 __le32 mlo_comp_timer; 1645 } __packed; 1646 1647 /* @brief host -> target FW extended statistics retrieve 1648 * 1649 * @details 1650 * The following field definitions describe the format of the HTT host 1651 * to target FW extended stats retrieve message. 1652 * The message specifies the type of stats the host wants to retrieve. 1653 * 1654 * |31 24|23 16|15 8|7 0| 1655 * |-----------------------------------------------------------| 1656 * | reserved | stats type | pdev_mask | msg type | 1657 * |-----------------------------------------------------------| 1658 * | config param [0] | 1659 * |-----------------------------------------------------------| 1660 * | config param [1] | 1661 * |-----------------------------------------------------------| 1662 * | config param [2] | 1663 * |-----------------------------------------------------------| 1664 * | config param [3] | 1665 * |-----------------------------------------------------------| 1666 * | reserved | 1667 * |-----------------------------------------------------------| 1668 * | cookie LSBs | 1669 * |-----------------------------------------------------------| 1670 * | cookie MSBs | 1671 * |-----------------------------------------------------------| 1672 * Header fields: 1673 * - MSG_TYPE 1674 * Bits 7:0 1675 * Purpose: identifies this is a extended stats upload request message 1676 * Value: 0x10 1677 * - PDEV_MASK 1678 * Bits 8:15 1679 * Purpose: identifies the mask of PDEVs to retrieve stats from 1680 * Value: This is a overloaded field, refer to usage and interpretation of 1681 * PDEV in interface document. 1682 * Bit 8 : Reserved for SOC stats 1683 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1684 * Indicates MACID_MASK in DBS 1685 * - STATS_TYPE 1686 * Bits 23:16 1687 * Purpose: identifies which FW statistics to upload 1688 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1689 * - Reserved 1690 * Bits 31:24 1691 * - CONFIG_PARAM [0] 1692 * Bits 31:0 1693 * Purpose: give an opaque configuration value to the specified stats type 1694 * Value: stats-type specific configuration value 1695 * Refer to htt_stats.h for interpretation for each stats sub_type 1696 * - CONFIG_PARAM [1] 1697 * Bits 31:0 1698 * Purpose: give an opaque configuration value to the specified stats type 1699 * Value: stats-type specific configuration value 1700 * Refer to htt_stats.h for interpretation for each stats sub_type 1701 * - CONFIG_PARAM [2] 1702 * Bits 31:0 1703 * Purpose: give an opaque configuration value to the specified stats type 1704 * Value: stats-type specific configuration value 1705 * Refer to htt_stats.h for interpretation for each stats sub_type 1706 * - CONFIG_PARAM [3] 1707 * Bits 31:0 1708 * Purpose: give an opaque configuration value to the specified stats type 1709 * Value: stats-type specific configuration value 1710 * Refer to htt_stats.h for interpretation for each stats sub_type 1711 * - Reserved [31:0] for future use. 1712 * - COOKIE_LSBS 1713 * Bits 31:0 1714 * Purpose: Provide a mechanism to match a target->host stats confirmation 1715 * message with its preceding host->target stats request message. 1716 * Value: LSBs of the opaque cookie specified by the host-side requestor 1717 * - COOKIE_MSBS 1718 * Bits 31:0 1719 * Purpose: Provide a mechanism to match a target->host stats confirmation 1720 * message with its preceding host->target stats request message. 1721 * Value: MSBs of the opaque cookie specified by the host-side requestor 1722 */ 1723 1724 struct htt_ext_stats_cfg_hdr { 1725 u8 msg_type; 1726 u8 pdev_mask; 1727 u8 stats_type; 1728 u8 reserved; 1729 } __packed; 1730 1731 struct htt_ext_stats_cfg_cmd { 1732 struct htt_ext_stats_cfg_hdr hdr; 1733 __le32 cfg_param0; 1734 __le32 cfg_param1; 1735 __le32 cfg_param2; 1736 __le32 cfg_param3; 1737 __le32 reserved; 1738 __le32 cookie_lsb; 1739 __le32 cookie_msb; 1740 } __packed; 1741 1742 /* htt stats config default params */ 1743 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1744 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1745 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1746 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1747 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1748 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1749 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1750 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1751 1752 /* HTT_DBG_EXT_STATS_PEER_INFO 1753 * PARAMS: 1754 * @config_param0: 1755 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1756 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1757 * [Bit31 : Bit16] sw_peer_id 1758 * @config_param1: 1759 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1760 * 0 bit htt_peer_stats_cmn_tlv 1761 * 1 bit htt_peer_details_tlv 1762 * 2 bit htt_tx_peer_rate_stats_tlv 1763 * 3 bit htt_rx_peer_rate_stats_tlv 1764 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1765 * 5 bit htt_rx_tid_stats_tlv 1766 * 6 bit htt_msdu_flow_stats_tlv 1767 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1768 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1769 * [Bit31 : Bit16] reserved 1770 */ 1771 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1772 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1773 1774 /* Used to set different configs to the specified stats type.*/ 1775 struct htt_ext_stats_cfg_params { 1776 u32 cfg0; 1777 u32 cfg1; 1778 u32 cfg2; 1779 u32 cfg3; 1780 }; 1781 1782 enum vdev_stats_offload_timer_duration { 1783 ATH12K_STATS_TIMER_DUR_500MS = 1, 1784 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1785 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1786 }; 1787 1788 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1789 { 1790 memcpy(addr, &addr_l32, 4); 1791 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1792 } 1793 1794 int ath12k_dp_service_srng(struct ath12k_base *ab, 1795 struct ath12k_ext_irq_grp *irq_grp, 1796 int budget); 1797 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1798 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif); 1799 void ath12k_dp_free(struct ath12k_base *ab); 1800 int ath12k_dp_alloc(struct ath12k_base *ab); 1801 void ath12k_dp_cc_config(struct ath12k_base *ab); 1802 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1803 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab); 1804 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1805 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1806 int mac_id, enum hal_ring_type ring_type); 1807 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1808 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1809 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1810 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1811 enum hal_ring_type type, int ring_num, 1812 int mac_id, int num_entries); 1813 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1814 struct dp_link_desc_bank *desc_bank, 1815 u32 ring_type, struct dp_srng *ring); 1816 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1817 struct dp_link_desc_bank *link_desc_banks, 1818 u32 ring_type, struct hal_srng *srng, 1819 u32 n_link_desc); 1820 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1821 u32 cookie); 1822 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1823 u32 desc_id); 1824 #endif 1825