1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_rx.h" 11 #include "hw.h" 12 13 #define MAX_RXDMA_PER_PDEV 2 14 15 struct ath12k_base; 16 struct ath12k_peer; 17 struct ath12k_dp; 18 struct ath12k_vif; 19 struct ath12k_link_vif; 20 struct hal_tcl_status_ring; 21 struct ath12k_ext_irq_grp; 22 23 #define DP_MON_PURGE_TIMEOUT_MS 100 24 #define DP_MON_SERVICE_BUDGET 128 25 26 struct dp_srng { 27 u32 *vaddr_unaligned; 28 u32 *vaddr; 29 dma_addr_t paddr_unaligned; 30 dma_addr_t paddr; 31 int size; 32 u32 ring_id; 33 }; 34 35 struct dp_rxdma_mon_ring { 36 struct dp_srng refill_buf_ring; 37 struct idr bufs_idr; 38 /* Protects bufs_idr */ 39 spinlock_t idr_lock; 40 int bufs_max; 41 }; 42 43 struct dp_rxdma_ring { 44 struct dp_srng refill_buf_ring; 45 int bufs_max; 46 }; 47 48 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 49 50 struct dp_tx_ring { 51 u8 tcl_data_ring_id; 52 struct dp_srng tcl_data_ring; 53 struct dp_srng tcl_comp_ring; 54 struct hal_wbm_completion_ring_tx *tx_status; 55 int tx_status_head; 56 int tx_status_tail; 57 }; 58 59 struct ath12k_pdev_mon_stats { 60 u32 status_ppdu_state; 61 u32 status_ppdu_start; 62 u32 status_ppdu_end; 63 u32 status_ppdu_compl; 64 u32 status_ppdu_start_mis; 65 u32 status_ppdu_end_mis; 66 u32 status_ppdu_done; 67 u32 dest_ppdu_done; 68 u32 dest_mpdu_done; 69 u32 dest_mpdu_drop; 70 u32 dup_mon_linkdesc_cnt; 71 u32 dup_mon_buf_cnt; 72 }; 73 74 struct dp_link_desc_bank { 75 void *vaddr_unaligned; 76 void *vaddr; 77 dma_addr_t paddr_unaligned; 78 dma_addr_t paddr; 79 u32 size; 80 }; 81 82 /* Size to enforce scatter idle list mode */ 83 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 84 #define DP_LINK_DESC_BANKS_MAX 8 85 86 #define DP_LINK_DESC_START 0x4000 87 #define DP_LINK_DESC_SHIFT 3 88 89 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 90 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 91 92 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 93 94 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 95 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 96 #define DP_RX_DESC_COOKIE_MAX \ 97 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 98 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 99 100 enum ath12k_dp_ppdu_state { 101 DP_PPDU_STATUS_START, 102 DP_PPDU_STATUS_DONE, 103 }; 104 105 struct dp_mon_mpdu { 106 struct list_head list; 107 struct sk_buff *head; 108 struct sk_buff *tail; 109 }; 110 111 #define DP_MON_MAX_STATUS_BUF 32 112 113 struct ath12k_mon_data { 114 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 115 struct hal_rx_mon_ppdu_info mon_ppdu_info; 116 117 u32 mon_ppdu_status; 118 u32 mon_last_buf_cookie; 119 u64 mon_last_linkdesc_paddr; 120 u16 chan_noise_floor; 121 122 struct ath12k_pdev_mon_stats rx_mon_stats; 123 /* lock for monitor data */ 124 spinlock_t mon_lock; 125 struct sk_buff_head rx_status_q; 126 struct dp_mon_mpdu *mon_mpdu; 127 struct list_head dp_rx_mon_mpdu_list; 128 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 129 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 130 }; 131 132 struct ath12k_pdev_dp { 133 u32 mac_id; 134 atomic_t num_tx_pending; 135 wait_queue_head_t tx_empty_waitq; 136 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 137 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 138 139 struct ieee80211_rx_status rx_status; 140 struct ath12k_mon_data mon_data; 141 }; 142 143 #define DP_NUM_CLIENTS_MAX 64 144 #define DP_AVG_TIDS_PER_CLIENT 2 145 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 146 #define DP_AVG_MSDUS_PER_FLOW 128 147 #define DP_AVG_FLOWS_PER_TID 2 148 #define DP_AVG_MPDUS_PER_TID_MAX 128 149 #define DP_AVG_MSDUS_PER_MPDU 4 150 151 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 152 153 #define DP_BA_WIN_SZ_MAX 1024 154 155 #define DP_TCL_NUM_RING_MAX 4 156 157 #define DP_IDLE_SCATTER_BUFS_MAX 16 158 159 #define DP_WBM_RELEASE_RING_SIZE 64 160 #define DP_TCL_DATA_RING_SIZE 512 161 #define DP_TX_COMP_RING_SIZE 32768 162 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 163 #define DP_TCL_CMD_RING_SIZE 32 164 #define DP_TCL_STATUS_RING_SIZE 32 165 #define DP_REO_DST_RING_MAX 8 166 #define DP_REO_DST_RING_SIZE 2048 167 #define DP_REO_REINJECT_RING_SIZE 32 168 #define DP_RX_RELEASE_RING_SIZE 1024 169 #define DP_REO_EXCEPTION_RING_SIZE 128 170 #define DP_REO_CMD_RING_SIZE 128 171 #define DP_REO_STATUS_RING_SIZE 2048 172 #define DP_RXDMA_BUF_RING_SIZE 4096 173 #define DP_RX_MAC_BUF_RING_SIZE 2048 174 #define DP_RXDMA_REFILL_RING_SIZE 2048 175 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 176 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 177 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 178 #define DP_RXDMA_MONITOR_DST_RING_SIZE 8092 179 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 180 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 181 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 182 183 #define DP_TX_MONITOR_BUF_SIZE 2048 184 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 185 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 186 187 #define DP_RX_BUFFER_SIZE 2048 188 #define DP_RX_BUFFER_SIZE_LITE 1024 189 #define DP_RX_BUFFER_ALIGN_SIZE 128 190 191 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 192 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 193 194 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 195 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 196 197 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 198 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 199 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 200 201 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 202 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 203 204 #define ATH12K_NUM_POOL_TX_DESC 32768 205 206 /* TODO: revisit this count during testing */ 207 #define ATH12K_RX_DESC_COUNT (12288) 208 209 #define ATH12K_PAGE_SIZE PAGE_SIZE 210 211 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 212 * SPT pages which makes lower 12bits 0 213 */ 214 #define ATH12K_MAX_PPT_ENTRIES 1024 215 216 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 217 #define ATH12K_MAX_SPT_ENTRIES 512 218 219 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 220 221 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 222 ATH12K_MAX_SPT_ENTRIES) 223 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 224 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 225 226 #define ATH12K_TX_SPT_PAGE_OFFSET 0 227 #define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES 228 229 /* The SPT pages are divided for RX and TX, first block for RX 230 * and remaining for TX 231 */ 232 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 233 234 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 235 236 /* 4K aligned address have last 12 bits set to 0, this check is done 237 * so that two spt pages address can be stored per 8bytes 238 * of CMEM (PPT) 239 */ 240 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 241 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 242 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 243 244 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 245 #define ATH12K_CMEM_ADDR_MSB 0x10 246 247 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 248 #define ATH12K_CC_SPT_MSB 8 249 #define ATH12K_CC_PPT_MSB 19 250 #define ATH12K_CC_PPT_SHIFT 9 251 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 252 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 253 254 #define DP_REO_QREF_NUM GENMASK(31, 16) 255 #define DP_MAX_PEER_ID 2047 256 257 /* Total size of the LUT is based on 2K peers, each having reference 258 * for 17tids, note each entry is of type ath12k_reo_queue_ref 259 * hence total size is 2048 * 17 * 8 = 278528 260 */ 261 #define DP_REOQ_LUT_SIZE 278528 262 263 /* Invalid TX Bank ID value */ 264 #define DP_INVALID_BANK_ID -1 265 266 struct ath12k_dp_tx_bank_profile { 267 u8 is_configured; 268 u32 num_users; 269 u32 bank_config; 270 }; 271 272 struct ath12k_hp_update_timer { 273 struct timer_list timer; 274 bool started; 275 bool init; 276 u32 tx_num; 277 u32 timer_tx_num; 278 u32 ring_id; 279 u32 interval; 280 struct ath12k_base *ab; 281 }; 282 283 struct ath12k_rx_desc_info { 284 struct list_head list; 285 struct sk_buff *skb; 286 u32 cookie; 287 u32 magic; 288 u8 in_use : 1, 289 device_id : 3, 290 reserved : 4; 291 }; 292 293 struct ath12k_tx_desc_info { 294 struct list_head list; 295 struct sk_buff *skb; 296 u32 desc_id; /* Cookie */ 297 u8 mac_id; 298 u8 pool_id; 299 }; 300 301 struct ath12k_spt_info { 302 dma_addr_t paddr; 303 u64 *vaddr; 304 }; 305 306 struct ath12k_reo_queue_ref { 307 u32 info0; 308 u32 info1; 309 } __packed; 310 311 struct ath12k_reo_q_addr_lut { 312 dma_addr_t paddr; 313 u32 *vaddr; 314 }; 315 316 struct ath12k_dp { 317 struct ath12k_base *ab; 318 u8 num_bank_profiles; 319 /* protects the access and update of bank_profiles */ 320 spinlock_t tx_bank_lock; 321 struct ath12k_dp_tx_bank_profile *bank_profiles; 322 enum ath12k_htc_ep_id eid; 323 struct completion htt_tgt_version_received; 324 u8 htt_tgt_ver_major; 325 u8 htt_tgt_ver_minor; 326 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 327 enum hal_rx_buf_return_buf_manager idle_link_rbm; 328 struct dp_srng wbm_idle_ring; 329 struct dp_srng wbm_desc_rel_ring; 330 struct dp_srng reo_reinject_ring; 331 struct dp_srng rx_rel_ring; 332 struct dp_srng reo_except_ring; 333 struct dp_srng reo_cmd_ring; 334 struct dp_srng reo_status_ring; 335 enum ath12k_peer_metadata_version peer_metadata_ver; 336 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 337 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 338 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 339 struct list_head reo_cmd_list; 340 struct list_head reo_cmd_cache_flush_list; 341 u32 reo_cmd_cache_flush_count; 342 343 /* protects access to below fields, 344 * - reo_cmd_list 345 * - reo_cmd_cache_flush_list 346 * - reo_cmd_cache_flush_count 347 */ 348 spinlock_t reo_cmd_lock; 349 struct ath12k_hp_update_timer reo_cmd_timer; 350 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 351 struct ath12k_spt_info *spt_info; 352 u32 num_spt_pages; 353 u32 rx_ppt_base; 354 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 355 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 356 struct list_head rx_desc_free_list; 357 /* protects the free desc list */ 358 spinlock_t rx_desc_lock; 359 360 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 361 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 362 /* protects the free and used desc lists */ 363 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 364 365 struct dp_rxdma_ring rx_refill_buf_ring; 366 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 367 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 368 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 369 struct dp_rxdma_mon_ring tx_mon_buf_ring; 370 struct ath12k_reo_q_addr_lut reoq_lut; 371 struct ath12k_reo_q_addr_lut ml_reoq_lut; 372 }; 373 374 /* HTT definitions */ 375 #define HTT_TAG_TCL_METADATA_VERSION 5 376 377 #define HTT_TCL_META_DATA_TYPE GENMASK(1, 0) 378 #define HTT_TCL_META_DATA_VALID_HTT BIT(2) 379 380 /* vdev meta data */ 381 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3) 382 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11) 383 #define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13) 384 385 /* peer meta data */ 386 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3) 387 388 /* Global sequence number */ 389 #define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3 390 #define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2) 391 #define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3) 392 #define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128 393 394 /* HTT tx completion is overlaid in wbm_release_ring */ 395 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 396 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 397 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 398 399 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 400 401 struct htt_tx_wbm_completion { 402 __le32 rsvd0[2]; 403 __le32 info0; 404 __le32 info1; 405 __le32 info2; 406 __le32 info3; 407 __le32 info4; 408 __le32 rsvd1; 409 410 } __packed; 411 412 enum htt_h2t_msg_type { 413 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 414 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 415 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 416 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 417 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 418 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 419 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 420 }; 421 422 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 423 #define HTT_OPTION_TCL_METADATA_VER_V2 2 424 #define HTT_OPTION_TAG GENMASK(7, 0) 425 #define HTT_OPTION_LEN GENMASK(15, 8) 426 #define HTT_OPTION_VALUE GENMASK(31, 16) 427 #define HTT_TCL_METADATA_VER_SZ 4 428 429 struct htt_ver_req_cmd { 430 __le32 ver_reg_info; 431 __le32 tcl_metadata_version; 432 } __packed; 433 434 enum htt_srng_ring_type { 435 HTT_HW_TO_SW_RING, 436 HTT_SW_TO_HW_RING, 437 HTT_SW_TO_SW_RING, 438 }; 439 440 enum htt_srng_ring_id { 441 HTT_RXDMA_HOST_BUF_RING, 442 HTT_RXDMA_MONITOR_STATUS_RING, 443 HTT_RXDMA_MONITOR_BUF_RING, 444 HTT_RXDMA_MONITOR_DESC_RING, 445 HTT_RXDMA_MONITOR_DEST_RING, 446 HTT_HOST1_TO_FW_RXBUF_RING, 447 HTT_HOST2_TO_FW_RXBUF_RING, 448 HTT_RXDMA_NON_MONITOR_DEST_RING, 449 HTT_RXDMA_HOST_BUF_RING2, 450 HTT_TX_MON_HOST2MON_BUF_RING, 451 HTT_TX_MON_MON2HOST_DEST_RING, 452 HTT_RX_MON_HOST2MON_BUF_RING, 453 HTT_RX_MON_MON2HOST_DEST_RING, 454 }; 455 456 /* host -> target HTT_SRING_SETUP message 457 * 458 * After target is booted up, Host can send SRING setup message for 459 * each host facing LMAC SRING. Target setups up HW registers based 460 * on setup message and confirms back to Host if response_required is set. 461 * Host should wait for confirmation message before sending new SRING 462 * setup message 463 * 464 * The message would appear as follows: 465 * 466 * |31 24|23 20|19|18 16|15|14 8|7 0| 467 * |--------------- +-----------------+----------------+------------------| 468 * | ring_type | ring_id | pdev_id | msg_type | 469 * |----------------------------------------------------------------------| 470 * | ring_base_addr_lo | 471 * |----------------------------------------------------------------------| 472 * | ring_base_addr_hi | 473 * |----------------------------------------------------------------------| 474 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 475 * |----------------------------------------------------------------------| 476 * | ring_head_offset32_remote_addr_lo | 477 * |----------------------------------------------------------------------| 478 * | ring_head_offset32_remote_addr_hi | 479 * |----------------------------------------------------------------------| 480 * | ring_tail_offset32_remote_addr_lo | 481 * |----------------------------------------------------------------------| 482 * | ring_tail_offset32_remote_addr_hi | 483 * |----------------------------------------------------------------------| 484 * | ring_msi_addr_lo | 485 * |----------------------------------------------------------------------| 486 * | ring_msi_addr_hi | 487 * |----------------------------------------------------------------------| 488 * | ring_msi_data | 489 * |----------------------------------------------------------------------| 490 * | intr_timer_th |IM| intr_batch_counter_th | 491 * |----------------------------------------------------------------------| 492 * | reserved |RR|PTCF| intr_low_threshold | 493 * |----------------------------------------------------------------------| 494 * Where 495 * IM = sw_intr_mode 496 * RR = response_required 497 * PTCF = prefetch_timer_cfg 498 * 499 * The message is interpreted as follows: 500 * dword0 - b'0:7 - msg_type: This will be set to 501 * HTT_H2T_MSG_TYPE_SRING_SETUP 502 * b'8:15 - pdev_id: 503 * 0 (for rings at SOC/UMAC level), 504 * 1/2/3 mac id (for rings at LMAC level) 505 * b'16:23 - ring_id: identify which ring is to setup, 506 * more details can be got from enum htt_srng_ring_id 507 * b'24:31 - ring_type: identify type of host rings, 508 * more details can be got from enum htt_srng_ring_type 509 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 510 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 511 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 512 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 513 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 514 * SW_TO_HW_RING. 515 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 516 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 517 * Lower 32 bits of memory address of the remote variable 518 * storing the 4-byte word offset that identifies the head 519 * element within the ring. 520 * (The head offset variable has type u32.) 521 * Valid for HW_TO_SW and SW_TO_SW rings. 522 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 523 * Upper 32 bits of memory address of the remote variable 524 * storing the 4-byte word offset that identifies the head 525 * element within the ring. 526 * (The head offset variable has type u32.) 527 * Valid for HW_TO_SW and SW_TO_SW rings. 528 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 529 * Lower 32 bits of memory address of the remote variable 530 * storing the 4-byte word offset that identifies the tail 531 * element within the ring. 532 * (The tail offset variable has type u32.) 533 * Valid for HW_TO_SW and SW_TO_SW rings. 534 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 535 * Upper 32 bits of memory address of the remote variable 536 * storing the 4-byte word offset that identifies the tail 537 * element within the ring. 538 * (The tail offset variable has type u32.) 539 * Valid for HW_TO_SW and SW_TO_SW rings. 540 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 541 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 542 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 543 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 544 * dword10 - b'0:31 - ring_msi_data: MSI data 545 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 546 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 547 * dword11 - b'0:14 - intr_batch_counter_th: 548 * batch counter threshold is in units of 4-byte words. 549 * HW internally maintains and increments batch count. 550 * (see SRING spec for detail description). 551 * When batch count reaches threshold value, an interrupt 552 * is generated by HW. 553 * b'15 - sw_intr_mode: 554 * This configuration shall be static. 555 * Only programmed at power up. 556 * 0: generate pulse style sw interrupts 557 * 1: generate level style sw interrupts 558 * b'16:31 - intr_timer_th: 559 * The timer init value when timer is idle or is 560 * initialized to start downcounting. 561 * In 8us units (to cover a range of 0 to 524 ms) 562 * dword12 - b'0:15 - intr_low_threshold: 563 * Used only by Consumer ring to generate ring_sw_int_p. 564 * Ring entries low threshold water mark, that is used 565 * in combination with the interrupt timer as well as 566 * the clearing of the level interrupt. 567 * b'16:18 - prefetch_timer_cfg: 568 * Used only by Consumer ring to set timer mode to 569 * support Application prefetch handling. 570 * The external tail offset/pointer will be updated 571 * at following intervals: 572 * 3'b000: (Prefetch feature disabled; used only for debug) 573 * 3'b001: 1 usec 574 * 3'b010: 4 usec 575 * 3'b011: 8 usec (default) 576 * 3'b100: 16 usec 577 * Others: Reserved 578 * b'19 - response_required: 579 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 580 * b'20:31 - reserved: reserved for future use 581 */ 582 583 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 584 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 585 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 586 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 587 588 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 589 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 590 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 591 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 592 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 593 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 594 595 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 596 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 597 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 598 599 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 600 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 601 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 602 603 struct htt_srng_setup_cmd { 604 __le32 info0; 605 __le32 ring_base_addr_lo; 606 __le32 ring_base_addr_hi; 607 __le32 info1; 608 __le32 ring_head_off32_remote_addr_lo; 609 __le32 ring_head_off32_remote_addr_hi; 610 __le32 ring_tail_off32_remote_addr_lo; 611 __le32 ring_tail_off32_remote_addr_hi; 612 __le32 ring_msi_addr_lo; 613 __le32 ring_msi_addr_hi; 614 __le32 msi_data; 615 __le32 intr_info; 616 __le32 info2; 617 } __packed; 618 619 /* host -> target FW PPDU_STATS config message 620 * 621 * @details 622 * The following field definitions describe the format of the HTT host 623 * to target FW for PPDU_STATS_CFG msg. 624 * The message allows the host to configure the PPDU_STATS_IND messages 625 * produced by the target. 626 * 627 * |31 24|23 16|15 8|7 0| 628 * |-----------------------------------------------------------| 629 * | REQ bit mask | pdev_mask | msg type | 630 * |-----------------------------------------------------------| 631 * Header fields: 632 * - MSG_TYPE 633 * Bits 7:0 634 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 635 * Value: 0x11 636 * - PDEV_MASK 637 * Bits 8:15 638 * Purpose: identifies which pdevs this PPDU stats configuration applies to 639 * Value: This is a overloaded field, refer to usage and interpretation of 640 * PDEV in interface document. 641 * Bit 8 : Reserved for SOC stats 642 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 643 * Indicates MACID_MASK in DBS 644 * - REQ_TLV_BIT_MASK 645 * Bits 16:31 646 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 647 * needs to be included in the target's PPDU_STATS_IND messages. 648 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 649 * 650 */ 651 652 struct htt_ppdu_stats_cfg_cmd { 653 __le32 msg; 654 } __packed; 655 656 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 657 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 658 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 659 660 enum htt_ppdu_stats_tag_type { 661 HTT_PPDU_STATS_TAG_COMMON, 662 HTT_PPDU_STATS_TAG_USR_COMMON, 663 HTT_PPDU_STATS_TAG_USR_RATE, 664 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 665 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 666 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 667 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 668 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 669 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 670 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 671 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 672 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 673 HTT_PPDU_STATS_TAG_INFO, 674 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 675 676 /* New TLV's are added above to this line */ 677 HTT_PPDU_STATS_TAG_MAX, 678 }; 679 680 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 681 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 682 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 683 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 684 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 685 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 686 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 687 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 688 689 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 690 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 691 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 692 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 693 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 694 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 695 HTT_PPDU_STATS_TAG_DEFAULT) 696 697 enum htt_stats_internal_ppdu_frametype { 698 HTT_STATS_PPDU_FTYPE_CTRL, 699 HTT_STATS_PPDU_FTYPE_DATA, 700 HTT_STATS_PPDU_FTYPE_BAR, 701 HTT_STATS_PPDU_FTYPE_MAX 702 }; 703 704 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 705 * 706 * details: 707 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 708 * configure RXDMA rings. 709 * The configuration is per ring based and includes both packet subtypes 710 * and PPDU/MPDU TLVs. 711 * 712 * The message would appear as follows: 713 * 714 * |31 29|28|27|26|25|24|23 16|15 8|7 0| 715 * |-------+--+--+--+--+--+-----------+----------------+---------------| 716 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 717 * |-------------------------------------------------------------------| 718 * | rsvd2 | ring_buffer_size | 719 * |-------------------------------------------------------------------| 720 * | packet_type_enable_flags_0 | 721 * |-------------------------------------------------------------------| 722 * | packet_type_enable_flags_1 | 723 * |-------------------------------------------------------------------| 724 * | packet_type_enable_flags_2 | 725 * |-------------------------------------------------------------------| 726 * | packet_type_enable_flags_3 | 727 * |-------------------------------------------------------------------| 728 * | tlv_filter_in_flags | 729 * |-------------------------------------------------------------------| 730 * Where: 731 * PS = pkt_swap 732 * SS = status_swap 733 * The message is interpreted as follows: 734 * dword0 - b'0:7 - msg_type: This will be set to 735 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 736 * b'8:15 - pdev_id: 737 * 0 (for rings at SOC/UMAC level), 738 * 1/2/3 mac id (for rings at LMAC level) 739 * b'16:23 - ring_id : Identify the ring to configure. 740 * More details can be got from enum htt_srng_ring_id 741 * b'24 - status_swap: 1 is to swap status TLV 742 * b'25 - pkt_swap: 1 is to swap packet TLV 743 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 744 * configuration fields are valid 745 * b'27 - drop_thresh_valid (DT): flag to indicate if the 746 * rx_drop_threshold field is valid 747 * b'28 - rx_mon_global_en: Enable/Disable global register 748 * configuration in Rx monitor module. 749 * b'29:31 - rsvd1: reserved for future use 750 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 751 * in byte units. 752 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 753 * - b'16:31 - rsvd2: Reserved for future use 754 * dword2 - b'0:31 - packet_type_enable_flags_0: 755 * Enable MGMT packet from 0b0000 to 0b1001 756 * bits from low to high: FP, MD, MO - 3 bits 757 * FP: Filter_Pass 758 * MD: Monitor_Direct 759 * MO: Monitor_Other 760 * 10 mgmt subtypes * 3 bits -> 30 bits 761 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 762 * dword3 - b'0:31 - packet_type_enable_flags_1: 763 * Enable MGMT packet from 0b1010 to 0b1111 764 * bits from low to high: FP, MD, MO - 3 bits 765 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 766 * dword4 - b'0:31 - packet_type_enable_flags_2: 767 * Enable CTRL packet from 0b0000 to 0b1001 768 * bits from low to high: FP, MD, MO - 3 bits 769 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 770 * dword5 - b'0:31 - packet_type_enable_flags_3: 771 * Enable CTRL packet from 0b1010 to 0b1111, 772 * MCAST_DATA, UCAST_DATA, NULL_DATA 773 * bits from low to high: FP, MD, MO - 3 bits 774 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 775 * dword6 - b'0:31 - tlv_filter_in_flags: 776 * Filter in Attention/MPDU/PPDU/Header/User tlvs 777 * Refer to CFG_TLV_FILTER_IN_FLAG defs 778 */ 779 780 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 781 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 782 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 783 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 784 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 785 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID BIT(26) 786 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL BIT(27) 787 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON BIT(28) 788 789 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 790 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16) 791 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19) 792 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22) 793 794 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0) 795 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE BIT(17) 796 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE BIT(18) 797 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE BIT(19) 798 799 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET BIT(0) 800 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1) 801 802 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 803 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 804 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 805 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 806 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 807 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 808 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 809 810 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23) 811 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) 812 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) 813 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) 814 815 enum htt_rx_filter_tlv_flags { 816 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 817 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 818 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 819 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 820 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 821 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 822 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 823 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 824 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 825 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 826 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 827 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 828 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 829 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13), 830 }; 831 832 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 833 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 834 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 835 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 836 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 837 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 838 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 839 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 840 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 841 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 842 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 843 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 844 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 845 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 846 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 847 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 848 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 849 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 850 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 851 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 852 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 853 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 854 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 855 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 856 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 857 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 858 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 859 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 860 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 861 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 862 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 863 }; 864 865 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 866 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 867 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 868 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 869 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 870 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 871 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 872 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 873 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 874 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 875 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 876 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 877 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 878 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 879 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 880 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 881 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 882 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 883 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 884 }; 885 886 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 888 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 889 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 891 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 892 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 894 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 895 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 896 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 897 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 899 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 900 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 902 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 903 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 904 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 905 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 906 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 907 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 908 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 909 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 910 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 911 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 912 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 913 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 914 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 915 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 916 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 917 }; 918 919 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 920 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 921 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 922 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 923 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 924 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 925 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 926 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 927 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 928 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 929 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 930 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 931 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 932 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 933 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 934 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 935 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 936 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 937 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 938 }; 939 940 enum htt_rx_data_pkt_filter_tlv_flasg3 { 941 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 942 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 943 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 944 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 945 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 946 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 947 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 948 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 949 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 950 }; 951 952 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 953 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 954 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 955 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 956 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 957 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 958 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 959 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 960 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 961 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 962 963 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 964 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 965 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 966 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 967 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 968 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 969 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 970 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 971 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 972 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 973 974 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 975 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 976 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 977 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 978 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 979 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 980 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 981 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 982 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 983 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 984 985 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 986 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 987 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 988 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 989 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 990 991 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 992 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 993 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 994 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 995 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 996 997 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 998 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 999 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1000 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1001 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1002 1003 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1004 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1005 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1006 1007 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1008 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1009 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1010 1011 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1012 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1013 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1014 1015 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1016 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1017 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1018 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1019 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1020 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1021 1022 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1023 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1024 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1025 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1026 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1027 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1028 1029 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1030 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1031 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1032 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1033 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1034 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1035 1036 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1037 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1038 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1039 1040 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1041 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1042 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1043 1044 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1045 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1046 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1047 1048 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1049 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1050 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1051 1052 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1053 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1054 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1055 1056 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1057 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1058 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1059 1060 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1061 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1062 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1063 1064 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1065 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1066 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1067 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1068 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1069 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1070 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1071 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1072 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1073 1074 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1075 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1076 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1077 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1078 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1079 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1080 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1081 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1082 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1083 1084 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1085 1086 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1087 1088 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1089 1090 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1091 1092 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1093 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1094 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1095 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1096 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1097 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1098 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1099 1100 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1101 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1102 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1103 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1104 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1105 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1106 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1107 1108 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1109 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1110 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1111 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1112 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1113 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1114 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1115 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1116 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1117 1118 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \ 1119 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1120 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1121 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1122 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1123 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1124 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1125 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1126 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1127 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1128 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1129 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1130 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ 1131 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO) 1132 1133 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1134 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1135 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1136 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1137 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1138 1139 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1140 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1141 1142 struct htt_rx_ring_selection_cfg_cmd { 1143 __le32 info0; 1144 __le32 info1; 1145 __le32 pkt_type_en_flags0; 1146 __le32 pkt_type_en_flags1; 1147 __le32 pkt_type_en_flags2; 1148 __le32 pkt_type_en_flags3; 1149 __le32 rx_filter_tlv; 1150 __le32 rx_packet_offset; 1151 __le32 rx_mpdu_offset; 1152 __le32 rx_msdu_offset; 1153 __le32 rx_attn_offset; 1154 __le32 info2; 1155 __le32 reserved[2]; 1156 __le32 rx_mpdu_start_end_mask; 1157 __le32 rx_msdu_end_word_mask; 1158 __le32 info3; 1159 } __packed; 1160 1161 #define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32 1162 #define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7 1163 #define HTT_RX_RING_PKT_TLV_OFFSET 0x1 1164 1165 struct htt_rx_ring_tlv_filter { 1166 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1167 u32 pkt_filter_flags0; /* MGMT */ 1168 u32 pkt_filter_flags1; /* MGMT */ 1169 u32 pkt_filter_flags2; /* CTRL */ 1170 u32 pkt_filter_flags3; /* DATA */ 1171 bool offset_valid; 1172 u16 rx_packet_offset; 1173 u16 rx_header_offset; 1174 u16 rx_mpdu_end_offset; 1175 u16 rx_mpdu_start_offset; 1176 u16 rx_msdu_end_offset; 1177 u16 rx_msdu_start_offset; 1178 u16 rx_attn_offset; 1179 u16 rx_mpdu_start_wmask; 1180 u16 rx_mpdu_end_wmask; 1181 u32 rx_msdu_end_wmask; 1182 u32 conf_len_ctrl; 1183 u32 conf_len_mgmt; 1184 u32 conf_len_data; 1185 u16 rx_drop_threshold; 1186 bool enable_log_mgmt_type; 1187 bool enable_log_ctrl_type; 1188 bool enable_log_data_type; 1189 bool enable_rx_tlv_offset; 1190 u16 rx_tlv_offset; 1191 bool drop_threshold_valid; 1192 bool rxmon_disable; 1193 }; 1194 1195 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1196 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1197 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1198 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1199 1200 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1201 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1202 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1203 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1204 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1205 1206 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1207 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1208 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1209 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1210 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1211 1212 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1213 1214 struct htt_tx_ring_selection_cfg_cmd { 1215 __le32 info0; 1216 __le32 info1; 1217 __le32 info2; 1218 __le32 tlv_filter_mask_in0; 1219 __le32 tlv_filter_mask_in1; 1220 __le32 tlv_filter_mask_in2; 1221 __le32 tlv_filter_mask_in3; 1222 __le32 reserved[3]; 1223 } __packed; 1224 1225 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1226 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1227 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1228 1229 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1230 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1231 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1232 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1233 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1234 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1235 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1236 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1237 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1238 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1239 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1240 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1241 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1242 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1243 1244 struct htt_tx_ring_tlv_filter { 1245 u32 tx_mon_downstream_tlv_flags; 1246 u32 tx_mon_upstream_tlv_flags0; 1247 u32 tx_mon_upstream_tlv_flags1; 1248 u32 tx_mon_upstream_tlv_flags2; 1249 bool tx_mon_mgmt_filter; 1250 bool tx_mon_data_filter; 1251 bool tx_mon_ctrl_filter; 1252 u16 tx_mon_pkt_dma_len; 1253 } __packed; 1254 1255 enum htt_tx_mon_upstream_tlv_flags0 { 1256 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1257 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1258 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1259 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1260 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1261 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1262 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1263 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1264 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1265 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1266 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1267 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1268 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1269 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1270 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1271 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1272 }; 1273 1274 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1275 1276 /* HTT message target->host */ 1277 1278 enum htt_t2h_msg_type { 1279 HTT_T2H_MSG_TYPE_VERSION_CONF, 1280 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1281 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1282 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1283 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1284 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1285 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1286 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1287 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1288 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1289 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1290 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1291 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1292 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1293 }; 1294 1295 #define HTT_TARGET_VERSION_MAJOR 3 1296 1297 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1298 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1299 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1300 1301 struct htt_t2h_version_conf_msg { 1302 __le32 version; 1303 } __packed; 1304 1305 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1306 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1307 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1308 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1309 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1310 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1311 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1312 1313 struct htt_t2h_peer_map_event { 1314 __le32 info; 1315 __le32 mac_addr_l32; 1316 __le32 info1; 1317 __le32 info2; 1318 } __packed; 1319 1320 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1321 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1322 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1323 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1324 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1325 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1326 1327 struct htt_t2h_peer_unmap_event { 1328 __le32 info; 1329 __le32 mac_addr_l32; 1330 __le32 info1; 1331 } __packed; 1332 1333 struct htt_resp_msg { 1334 union { 1335 struct htt_t2h_version_conf_msg version_msg; 1336 struct htt_t2h_peer_map_event peer_map_ev; 1337 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1338 }; 1339 } __packed; 1340 1341 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1342 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1343 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1344 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1345 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1346 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1347 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1348 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1349 1350 struct htt_t2h_vdev_txrx_stats_ind { 1351 __le32 vdev_id; 1352 __le32 rx_msdu_byte_cnt_lo; 1353 __le32 rx_msdu_byte_cnt_hi; 1354 __le32 rx_msdu_cnt_lo; 1355 __le32 rx_msdu_cnt_hi; 1356 __le32 tx_msdu_byte_cnt_lo; 1357 __le32 tx_msdu_byte_cnt_hi; 1358 __le32 tx_msdu_cnt_lo; 1359 __le32 tx_msdu_cnt_hi; 1360 __le32 tx_retry_cnt_lo; 1361 __le32 tx_retry_cnt_hi; 1362 __le32 tx_retry_byte_cnt_lo; 1363 __le32 tx_retry_byte_cnt_hi; 1364 __le32 tx_drop_cnt_lo; 1365 __le32 tx_drop_cnt_hi; 1366 __le32 tx_drop_byte_cnt_lo; 1367 __le32 tx_drop_byte_cnt_hi; 1368 __le32 msdu_ttl_cnt_lo; 1369 __le32 msdu_ttl_cnt_hi; 1370 __le32 msdu_ttl_byte_cnt_lo; 1371 __le32 msdu_ttl_byte_cnt_hi; 1372 } __packed; 1373 1374 struct htt_t2h_vdev_common_stats_tlv { 1375 __le32 soc_drop_count_lo; 1376 __le32 soc_drop_count_hi; 1377 } __packed; 1378 1379 /* ppdu stats 1380 * 1381 * @details 1382 * The following field definitions describe the format of the HTT target 1383 * to host ppdu stats indication message. 1384 * 1385 * 1386 * |31 16|15 12|11 10|9 8|7 0 | 1387 * |----------------------------------------------------------------------| 1388 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1389 * |----------------------------------------------------------------------| 1390 * | ppdu_id | 1391 * |----------------------------------------------------------------------| 1392 * | Timestamp in us | 1393 * |----------------------------------------------------------------------| 1394 * | reserved | 1395 * |----------------------------------------------------------------------| 1396 * | type-specific stats info | 1397 * | (see htt_ppdu_stats.h) | 1398 * |----------------------------------------------------------------------| 1399 * Header fields: 1400 * - MSG_TYPE 1401 * Bits 7:0 1402 * Purpose: Identifies this is a PPDU STATS indication 1403 * message. 1404 * Value: 0x1d 1405 * - mac_id 1406 * Bits 9:8 1407 * Purpose: mac_id of this ppdu_id 1408 * Value: 0-3 1409 * - pdev_id 1410 * Bits 11:10 1411 * Purpose: pdev_id of this ppdu_id 1412 * Value: 0-3 1413 * 0 (for rings at SOC level), 1414 * 1/2/3 PDEV -> 0/1/2 1415 * - payload_size 1416 * Bits 31:16 1417 * Purpose: total tlv size 1418 * Value: payload_size in bytes 1419 */ 1420 1421 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1422 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1423 1424 struct ath12k_htt_ppdu_stats_msg { 1425 __le32 info; 1426 __le32 ppdu_id; 1427 __le32 timestamp; 1428 __le32 rsvd; 1429 u8 data[]; 1430 } __packed; 1431 1432 struct htt_tlv { 1433 __le32 header; 1434 u8 value[]; 1435 } __packed; 1436 1437 #define HTT_TLV_TAG GENMASK(11, 0) 1438 #define HTT_TLV_LEN GENMASK(23, 12) 1439 1440 enum HTT_PPDU_STATS_BW { 1441 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1442 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1443 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1444 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1445 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1446 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1447 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1448 }; 1449 1450 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1451 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1452 /* bw - HTT_PPDU_STATS_BW */ 1453 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1454 1455 struct htt_ppdu_stats_common { 1456 __le32 ppdu_id; 1457 __le16 sched_cmdid; 1458 u8 ring_id; 1459 u8 num_users; 1460 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1461 __le32 chain_mask; 1462 __le32 fes_duration_us; /* frame exchange sequence */ 1463 __le32 ppdu_sch_eval_start_tstmp_us; 1464 __le32 ppdu_sch_end_tstmp_us; 1465 __le32 ppdu_start_tstmp_us; 1466 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1467 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1468 */ 1469 __le16 phy_mode; 1470 __le16 bw_mhz; 1471 } __packed; 1472 1473 enum htt_ppdu_stats_gi { 1474 HTT_PPDU_STATS_SGI_0_8_US, 1475 HTT_PPDU_STATS_SGI_0_4_US, 1476 HTT_PPDU_STATS_SGI_1_6_US, 1477 HTT_PPDU_STATS_SGI_3_2_US, 1478 }; 1479 1480 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1481 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1482 1483 enum HTT_PPDU_STATS_PPDU_TYPE { 1484 HTT_PPDU_STATS_PPDU_TYPE_SU, 1485 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1486 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1487 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1488 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1489 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1490 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1491 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1492 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1493 HTT_PPDU_STATS_PPDU_TYPE_MAX 1494 }; 1495 1496 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1497 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1498 1499 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1500 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1501 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1502 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1503 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1504 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1505 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1506 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1507 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1508 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1509 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1510 1511 #define HTT_USR_RATE_PREAMBLE(_val) \ 1512 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1513 #define HTT_USR_RATE_BW(_val) \ 1514 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1515 #define HTT_USR_RATE_NSS(_val) \ 1516 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1517 #define HTT_USR_RATE_MCS(_val) \ 1518 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1519 #define HTT_USR_RATE_GI(_val) \ 1520 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1521 #define HTT_USR_RATE_DCM(_val) \ 1522 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1523 1524 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1525 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1526 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1527 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1528 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1529 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1530 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1531 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1532 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1533 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1534 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1535 1536 struct htt_ppdu_stats_user_rate { 1537 u8 tid_num; 1538 u8 reserved0; 1539 __le16 sw_peer_id; 1540 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1541 __le16 ru_end; 1542 __le16 ru_start; 1543 __le16 resp_ru_end; 1544 __le16 resp_ru_start; 1545 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1546 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1547 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1548 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1549 } __packed; 1550 1551 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1552 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1553 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1554 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1555 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1556 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1557 1558 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1559 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1560 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1561 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1562 #define HTT_TX_INFO_RATECODE(_flags) \ 1563 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1564 #define HTT_TX_INFO_PEERID(_flags) \ 1565 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1566 1567 enum htt_ppdu_stats_usr_compln_status { 1568 HTT_PPDU_STATS_USER_STATUS_OK, 1569 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1570 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1571 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1572 HTT_PPDU_STATS_USER_STATUS_ABORT, 1573 }; 1574 1575 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1576 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1577 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1578 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1579 1580 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1581 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1582 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1583 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1584 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1585 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1586 1587 struct htt_ppdu_stats_usr_cmpltn_cmn { 1588 u8 status; 1589 u8 tid_num; 1590 __le16 sw_peer_id; 1591 /* RSSI value of last ack packet (units = dB above noise floor) */ 1592 __le32 ack_rssi; 1593 __le16 mpdu_tried; 1594 __le16 mpdu_success; 1595 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1596 } __packed; 1597 1598 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1599 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1600 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1601 1602 #define HTT_PPDU_STATS_NON_QOS_TID 16 1603 1604 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1605 __le32 ppdu_id; 1606 __le16 sw_peer_id; 1607 __le16 reserved0; 1608 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1609 __le16 current_seq; 1610 __le16 start_seq; 1611 __le32 success_bytes; 1612 } __packed; 1613 1614 struct htt_ppdu_user_stats { 1615 u16 peer_id; 1616 u16 delay_ba; 1617 u32 tlv_flags; 1618 bool is_valid_peer_id; 1619 struct htt_ppdu_stats_user_rate rate; 1620 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1621 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1622 }; 1623 1624 #define HTT_PPDU_STATS_MAX_USERS 8 1625 #define HTT_PPDU_DESC_MAX_DEPTH 16 1626 1627 struct htt_ppdu_stats { 1628 struct htt_ppdu_stats_common common; 1629 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1630 }; 1631 1632 struct htt_ppdu_stats_info { 1633 u32 tlv_bitmap; 1634 u32 ppdu_id; 1635 u32 frame_type; 1636 u32 frame_ctrl; 1637 u32 delay_ba; 1638 u32 bar_num_users; 1639 struct htt_ppdu_stats ppdu_stats; 1640 struct list_head list; 1641 }; 1642 1643 /* @brief target -> host MLO offset indiciation message 1644 * 1645 * @details 1646 * The following field definitions describe the format of the HTT target 1647 * to host mlo offset indication message. 1648 * 1649 * 1650 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1651 * |---------------------------------------------------------------------| 1652 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1653 * |---------------------------------------------------------------------| 1654 * | sync_timestamp_lo_us | 1655 * |---------------------------------------------------------------------| 1656 * | sync_timestamp_hi_us | 1657 * |---------------------------------------------------------------------| 1658 * | mlo_offset_lo | 1659 * |---------------------------------------------------------------------| 1660 * | mlo_offset_hi | 1661 * |---------------------------------------------------------------------| 1662 * | mlo_offset_clcks | 1663 * |---------------------------------------------------------------------| 1664 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1665 * |---------------------------------------------------------------------| 1666 * | rsvd3 |mlo_comp_timer | 1667 * |---------------------------------------------------------------------| 1668 * Header fields 1669 * - MSG_TYPE 1670 * Bits 7:0 1671 * Purpose: Identifies this is a MLO offset indication msg 1672 * - PDEV_ID 1673 * Bits 9:8 1674 * Purpose: Pdev of this MLO offset 1675 * - CHIP_ID 1676 * Bits 12:10 1677 * Purpose: chip_id of this MLO offset 1678 * - MAC_FREQ 1679 * Bits 28:13 1680 * - SYNC_TIMESTAMP_LO_US 1681 * Purpose: clock frequency of the mac HW block in MHz 1682 * Bits: 31:0 1683 * Purpose: lower 32 bits of the WLAN global time stamp at which 1684 * last sync interrupt was received 1685 * - SYNC_TIMESTAMP_HI_US 1686 * Bits: 31:0 1687 * Purpose: upper 32 bits of WLAN global time stamp at which 1688 * last sync interrupt was received 1689 * - MLO_OFFSET_LO 1690 * Bits: 31:0 1691 * Purpose: lower 32 bits of the MLO offset in us 1692 * - MLO_OFFSET_HI 1693 * Bits: 31:0 1694 * Purpose: upper 32 bits of the MLO offset in us 1695 * - MLO_COMP_US 1696 * Bits: 15:0 1697 * Purpose: MLO time stamp compensation applied in us 1698 * - MLO_COMP_CLCKS 1699 * Bits: 25:16 1700 * Purpose: MLO time stamp compensation applied in clock ticks 1701 * - MLO_COMP_TIMER 1702 * Bits: 21:0 1703 * Purpose: Periodic timer at which compensation is applied 1704 */ 1705 1706 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1707 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1708 1709 struct ath12k_htt_mlo_offset_msg { 1710 __le32 info; 1711 __le32 sync_timestamp_lo_us; 1712 __le32 sync_timestamp_hi_us; 1713 __le32 mlo_offset_hi; 1714 __le32 mlo_offset_lo; 1715 __le32 mlo_offset_clks; 1716 __le32 mlo_comp_clks; 1717 __le32 mlo_comp_timer; 1718 } __packed; 1719 1720 /* @brief host -> target FW extended statistics retrieve 1721 * 1722 * @details 1723 * The following field definitions describe the format of the HTT host 1724 * to target FW extended stats retrieve message. 1725 * The message specifies the type of stats the host wants to retrieve. 1726 * 1727 * |31 24|23 16|15 8|7 0| 1728 * |-----------------------------------------------------------| 1729 * | reserved | stats type | pdev_mask | msg type | 1730 * |-----------------------------------------------------------| 1731 * | config param [0] | 1732 * |-----------------------------------------------------------| 1733 * | config param [1] | 1734 * |-----------------------------------------------------------| 1735 * | config param [2] | 1736 * |-----------------------------------------------------------| 1737 * | config param [3] | 1738 * |-----------------------------------------------------------| 1739 * | reserved | 1740 * |-----------------------------------------------------------| 1741 * | cookie LSBs | 1742 * |-----------------------------------------------------------| 1743 * | cookie MSBs | 1744 * |-----------------------------------------------------------| 1745 * Header fields: 1746 * - MSG_TYPE 1747 * Bits 7:0 1748 * Purpose: identifies this is a extended stats upload request message 1749 * Value: 0x10 1750 * - PDEV_MASK 1751 * Bits 8:15 1752 * Purpose: identifies the mask of PDEVs to retrieve stats from 1753 * Value: This is a overloaded field, refer to usage and interpretation of 1754 * PDEV in interface document. 1755 * Bit 8 : Reserved for SOC stats 1756 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1757 * Indicates MACID_MASK in DBS 1758 * - STATS_TYPE 1759 * Bits 23:16 1760 * Purpose: identifies which FW statistics to upload 1761 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1762 * - Reserved 1763 * Bits 31:24 1764 * - CONFIG_PARAM [0] 1765 * Bits 31:0 1766 * Purpose: give an opaque configuration value to the specified stats type 1767 * Value: stats-type specific configuration value 1768 * Refer to htt_stats.h for interpretation for each stats sub_type 1769 * - CONFIG_PARAM [1] 1770 * Bits 31:0 1771 * Purpose: give an opaque configuration value to the specified stats type 1772 * Value: stats-type specific configuration value 1773 * Refer to htt_stats.h for interpretation for each stats sub_type 1774 * - CONFIG_PARAM [2] 1775 * Bits 31:0 1776 * Purpose: give an opaque configuration value to the specified stats type 1777 * Value: stats-type specific configuration value 1778 * Refer to htt_stats.h for interpretation for each stats sub_type 1779 * - CONFIG_PARAM [3] 1780 * Bits 31:0 1781 * Purpose: give an opaque configuration value to the specified stats type 1782 * Value: stats-type specific configuration value 1783 * Refer to htt_stats.h for interpretation for each stats sub_type 1784 * - Reserved [31:0] for future use. 1785 * - COOKIE_LSBS 1786 * Bits 31:0 1787 * Purpose: Provide a mechanism to match a target->host stats confirmation 1788 * message with its preceding host->target stats request message. 1789 * Value: LSBs of the opaque cookie specified by the host-side requestor 1790 * - COOKIE_MSBS 1791 * Bits 31:0 1792 * Purpose: Provide a mechanism to match a target->host stats confirmation 1793 * message with its preceding host->target stats request message. 1794 * Value: MSBs of the opaque cookie specified by the host-side requestor 1795 */ 1796 1797 struct htt_ext_stats_cfg_hdr { 1798 u8 msg_type; 1799 u8 pdev_mask; 1800 u8 stats_type; 1801 u8 reserved; 1802 } __packed; 1803 1804 struct htt_ext_stats_cfg_cmd { 1805 struct htt_ext_stats_cfg_hdr hdr; 1806 __le32 cfg_param0; 1807 __le32 cfg_param1; 1808 __le32 cfg_param2; 1809 __le32 cfg_param3; 1810 __le32 reserved; 1811 __le32 cookie_lsb; 1812 __le32 cookie_msb; 1813 } __packed; 1814 1815 /* htt stats config default params */ 1816 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1817 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1818 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1819 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1820 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1821 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1822 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1823 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1824 1825 /* HTT_DBG_EXT_STATS_PEER_INFO 1826 * PARAMS: 1827 * @config_param0: 1828 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1829 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1830 * [Bit31 : Bit16] sw_peer_id 1831 * @config_param1: 1832 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1833 * 0 bit htt_peer_stats_cmn_tlv 1834 * 1 bit htt_peer_details_tlv 1835 * 2 bit htt_tx_peer_rate_stats_tlv 1836 * 3 bit htt_rx_peer_rate_stats_tlv 1837 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1838 * 5 bit htt_rx_tid_stats_tlv 1839 * 6 bit htt_msdu_flow_stats_tlv 1840 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1841 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1842 * [Bit31 : Bit16] reserved 1843 */ 1844 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1845 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1846 1847 /* Used to set different configs to the specified stats type.*/ 1848 struct htt_ext_stats_cfg_params { 1849 u32 cfg0; 1850 u32 cfg1; 1851 u32 cfg2; 1852 u32 cfg3; 1853 }; 1854 1855 enum vdev_stats_offload_timer_duration { 1856 ATH12K_STATS_TIMER_DUR_500MS = 1, 1857 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1858 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1859 }; 1860 1861 #define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1862 #define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1863 #define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1864 #define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1865 #define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1866 #define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1867 1868 struct htt_mac_addr { 1869 __le32 mac_addr_l32; 1870 __le32 mac_addr_h16; 1871 } __packed; 1872 1873 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1874 { 1875 memcpy(addr, &addr_l32, 4); 1876 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1877 } 1878 1879 int ath12k_dp_service_srng(struct ath12k_base *ab, 1880 struct ath12k_ext_irq_grp *irq_grp, 1881 int budget); 1882 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1883 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif); 1884 void ath12k_dp_free(struct ath12k_base *ab); 1885 int ath12k_dp_alloc(struct ath12k_base *ab); 1886 void ath12k_dp_cc_config(struct ath12k_base *ab); 1887 void ath12k_dp_partner_cc_init(struct ath12k_base *ab); 1888 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1889 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar); 1890 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1891 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1892 int mac_id, enum hal_ring_type ring_type); 1893 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1894 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1895 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1896 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1897 enum hal_ring_type type, int ring_num, 1898 int mac_id, int num_entries); 1899 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1900 struct dp_link_desc_bank *desc_bank, 1901 u32 ring_type, struct dp_srng *ring); 1902 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1903 struct dp_link_desc_bank *link_desc_banks, 1904 u32 ring_type, struct hal_srng *srng, 1905 u32 n_link_desc); 1906 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1907 u32 cookie); 1908 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1909 u32 desc_id); 1910 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab); 1911 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab); 1912 #endif 1913