1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_desc.h" 11 #include "hal_rx.h" 12 #include "hw.h" 13 14 #define MAX_RXDMA_PER_PDEV 2 15 16 struct ath12k_base; 17 struct ath12k_peer; 18 struct ath12k_dp; 19 struct ath12k_vif; 20 struct ath12k_link_vif; 21 struct hal_tcl_status_ring; 22 struct ath12k_ext_irq_grp; 23 24 #define DP_MON_PURGE_TIMEOUT_MS 100 25 #define DP_MON_SERVICE_BUDGET 128 26 27 struct dp_srng { 28 u32 *vaddr_unaligned; 29 u32 *vaddr; 30 dma_addr_t paddr_unaligned; 31 dma_addr_t paddr; 32 int size; 33 u32 ring_id; 34 }; 35 36 struct dp_rxdma_mon_ring { 37 struct dp_srng refill_buf_ring; 38 struct idr bufs_idr; 39 /* Protects bufs_idr */ 40 spinlock_t idr_lock; 41 int bufs_max; 42 }; 43 44 struct dp_rxdma_ring { 45 struct dp_srng refill_buf_ring; 46 int bufs_max; 47 }; 48 49 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 50 51 struct dp_tx_ring { 52 u8 tcl_data_ring_id; 53 struct dp_srng tcl_data_ring; 54 struct dp_srng tcl_comp_ring; 55 struct hal_wbm_completion_ring_tx *tx_status; 56 int tx_status_head; 57 int tx_status_tail; 58 }; 59 60 struct ath12k_pdev_mon_stats { 61 u32 status_ppdu_state; 62 u32 status_ppdu_start; 63 u32 status_ppdu_end; 64 u32 status_ppdu_compl; 65 u32 status_ppdu_start_mis; 66 u32 status_ppdu_end_mis; 67 u32 status_ppdu_done; 68 u32 dest_ppdu_done; 69 u32 dest_mpdu_done; 70 u32 dest_mpdu_drop; 71 u32 dup_mon_linkdesc_cnt; 72 u32 dup_mon_buf_cnt; 73 }; 74 75 struct dp_link_desc_bank { 76 void *vaddr_unaligned; 77 void *vaddr; 78 dma_addr_t paddr_unaligned; 79 dma_addr_t paddr; 80 u32 size; 81 }; 82 83 /* Size to enforce scatter idle list mode */ 84 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 85 #define DP_LINK_DESC_BANKS_MAX 8 86 87 #define DP_LINK_DESC_START 0x4000 88 #define DP_LINK_DESC_SHIFT 3 89 90 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 91 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 92 93 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 94 95 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 96 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 97 #define DP_RX_DESC_COOKIE_MAX \ 98 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 99 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 100 101 enum ath12k_dp_ppdu_state { 102 DP_PPDU_STATUS_START, 103 DP_PPDU_STATUS_DONE, 104 }; 105 106 struct dp_mon_mpdu { 107 struct list_head list; 108 struct sk_buff *head; 109 struct sk_buff *tail; 110 u32 err_bitmap; 111 u8 decap_format; 112 }; 113 114 #define DP_MON_MAX_STATUS_BUF 32 115 116 struct ath12k_mon_data { 117 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 118 struct hal_rx_mon_ppdu_info mon_ppdu_info; 119 120 u32 mon_ppdu_status; 121 u32 mon_last_buf_cookie; 122 u64 mon_last_linkdesc_paddr; 123 u16 chan_noise_floor; 124 125 struct ath12k_pdev_mon_stats rx_mon_stats; 126 /* lock for monitor data */ 127 spinlock_t mon_lock; 128 struct sk_buff_head rx_status_q; 129 struct dp_mon_mpdu *mon_mpdu; 130 struct list_head dp_rx_mon_mpdu_list; 131 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 132 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 133 }; 134 135 struct ath12k_pdev_dp { 136 u32 mac_id; 137 atomic_t num_tx_pending; 138 wait_queue_head_t tx_empty_waitq; 139 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 140 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 141 142 struct ieee80211_rx_status rx_status; 143 struct ath12k_mon_data mon_data; 144 }; 145 146 #define DP_NUM_CLIENTS_MAX 64 147 #define DP_AVG_TIDS_PER_CLIENT 2 148 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 149 #define DP_AVG_MSDUS_PER_FLOW 128 150 #define DP_AVG_FLOWS_PER_TID 2 151 #define DP_AVG_MPDUS_PER_TID_MAX 128 152 #define DP_AVG_MSDUS_PER_MPDU 4 153 154 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 155 156 #define DP_BA_WIN_SZ_MAX 1024 157 158 #define DP_TCL_NUM_RING_MAX 4 159 160 #define DP_IDLE_SCATTER_BUFS_MAX 16 161 162 #define DP_WBM_RELEASE_RING_SIZE 64 163 #define DP_TCL_DATA_RING_SIZE 512 164 #define DP_TX_COMP_RING_SIZE 32768 165 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 166 #define DP_TCL_CMD_RING_SIZE 32 167 #define DP_TCL_STATUS_RING_SIZE 32 168 #define DP_REO_DST_RING_MAX 8 169 #define DP_REO_DST_RING_SIZE 2048 170 #define DP_REO_REINJECT_RING_SIZE 32 171 #define DP_RX_RELEASE_RING_SIZE 1024 172 #define DP_REO_EXCEPTION_RING_SIZE 128 173 #define DP_REO_CMD_RING_SIZE 128 174 #define DP_REO_STATUS_RING_SIZE 2048 175 #define DP_RXDMA_BUF_RING_SIZE 4096 176 #define DP_RX_MAC_BUF_RING_SIZE 2048 177 #define DP_RXDMA_REFILL_RING_SIZE 2048 178 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 179 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 180 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 181 #define DP_RXDMA_MONITOR_DST_RING_SIZE 8092 182 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 183 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 184 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 185 186 #define DP_TX_MONITOR_BUF_SIZE 2048 187 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 188 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 189 190 #define DP_RX_BUFFER_SIZE 2048 191 #define DP_RX_BUFFER_SIZE_LITE 1024 192 #define DP_RX_BUFFER_ALIGN_SIZE 128 193 194 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 195 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 196 197 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 198 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 199 200 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 201 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 202 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 203 204 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 205 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 206 207 #define ATH12K_NUM_POOL_TX_DESC 32768 208 209 /* TODO: revisit this count during testing */ 210 #define ATH12K_RX_DESC_COUNT (12288) 211 212 #define ATH12K_PAGE_SIZE PAGE_SIZE 213 214 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 215 * SPT pages which makes lower 12bits 0 216 */ 217 #define ATH12K_MAX_PPT_ENTRIES 1024 218 219 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 220 #define ATH12K_MAX_SPT_ENTRIES 512 221 222 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 223 224 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 225 ATH12K_MAX_SPT_ENTRIES) 226 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 227 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 228 229 #define ATH12K_TX_SPT_PAGE_OFFSET 0 230 #define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES 231 232 /* The SPT pages are divided for RX and TX, first block for RX 233 * and remaining for TX 234 */ 235 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 236 237 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 238 239 /* 4K aligned address have last 12 bits set to 0, this check is done 240 * so that two spt pages address can be stored per 8bytes 241 * of CMEM (PPT) 242 */ 243 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 244 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 245 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 246 247 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 248 #define ATH12K_CMEM_ADDR_MSB 0x10 249 250 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 251 #define ATH12K_CC_SPT_MSB 8 252 #define ATH12K_CC_PPT_MSB 19 253 #define ATH12K_CC_PPT_SHIFT 9 254 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 255 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 256 257 #define DP_REO_QREF_NUM GENMASK(31, 16) 258 #define DP_MAX_PEER_ID 2047 259 260 /* Total size of the LUT is based on 2K peers, each having reference 261 * for 17tids, note each entry is of type ath12k_reo_queue_ref 262 * hence total size is 2048 * 17 * 8 = 278528 263 */ 264 #define DP_REOQ_LUT_SIZE 278528 265 266 /* Invalid TX Bank ID value */ 267 #define DP_INVALID_BANK_ID -1 268 269 struct ath12k_dp_tx_bank_profile { 270 u8 is_configured; 271 u32 num_users; 272 u32 bank_config; 273 }; 274 275 struct ath12k_hp_update_timer { 276 struct timer_list timer; 277 bool started; 278 bool init; 279 u32 tx_num; 280 u32 timer_tx_num; 281 u32 ring_id; 282 u32 interval; 283 struct ath12k_base *ab; 284 }; 285 286 struct ath12k_rx_desc_info { 287 struct list_head list; 288 struct sk_buff *skb; 289 u32 cookie; 290 u32 magic; 291 u8 in_use : 1, 292 device_id : 3, 293 reserved : 4; 294 }; 295 296 struct ath12k_tx_desc_info { 297 struct list_head list; 298 struct sk_buff *skb; 299 struct sk_buff *skb_ext_desc; 300 u32 desc_id; /* Cookie */ 301 u8 mac_id; 302 u8 pool_id; 303 }; 304 305 struct ath12k_tx_desc_params { 306 struct sk_buff *skb; 307 struct sk_buff *skb_ext_desc; 308 u8 mac_id; 309 }; 310 311 struct ath12k_spt_info { 312 dma_addr_t paddr; 313 u64 *vaddr; 314 }; 315 316 struct ath12k_reo_queue_ref { 317 u32 info0; 318 u32 info1; 319 } __packed; 320 321 struct ath12k_reo_q_addr_lut { 322 u32 *vaddr_unaligned; 323 u32 *vaddr; 324 dma_addr_t paddr_unaligned; 325 dma_addr_t paddr; 326 u32 size; 327 }; 328 329 struct ath12k_link_stats { 330 u32 tx_enqueued; 331 u32 tx_completed; 332 u32 tx_bcast_mcast; 333 u32 tx_dropped; 334 u32 tx_encap_type[HAL_TCL_ENCAP_TYPE_MAX]; 335 u32 tx_encrypt_type[HAL_ENCRYPT_TYPE_MAX]; 336 u32 tx_desc_type[HAL_TCL_DESC_TYPE_MAX]; 337 }; 338 339 struct ath12k_dp { 340 struct ath12k_base *ab; 341 u8 num_bank_profiles; 342 /* protects the access and update of bank_profiles */ 343 spinlock_t tx_bank_lock; 344 struct ath12k_dp_tx_bank_profile *bank_profiles; 345 enum ath12k_htc_ep_id eid; 346 struct completion htt_tgt_version_received; 347 u8 htt_tgt_ver_major; 348 u8 htt_tgt_ver_minor; 349 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 350 enum hal_rx_buf_return_buf_manager idle_link_rbm; 351 struct dp_srng wbm_idle_ring; 352 struct dp_srng wbm_desc_rel_ring; 353 struct dp_srng reo_reinject_ring; 354 struct dp_srng rx_rel_ring; 355 struct dp_srng reo_except_ring; 356 struct dp_srng reo_cmd_ring; 357 struct dp_srng reo_status_ring; 358 enum ath12k_peer_metadata_version peer_metadata_ver; 359 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 360 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 361 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 362 struct list_head reo_cmd_list; 363 struct list_head reo_cmd_cache_flush_list; 364 u32 reo_cmd_cache_flush_count; 365 366 /* protects access to below fields, 367 * - reo_cmd_list 368 * - reo_cmd_cache_flush_list 369 * - reo_cmd_cache_flush_count 370 */ 371 spinlock_t reo_cmd_lock; 372 struct ath12k_hp_update_timer reo_cmd_timer; 373 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 374 struct ath12k_spt_info *spt_info; 375 u32 num_spt_pages; 376 u32 rx_ppt_base; 377 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 378 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 379 struct list_head rx_desc_free_list; 380 /* protects the free desc list */ 381 spinlock_t rx_desc_lock; 382 383 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 384 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 385 /* protects the free and used desc lists */ 386 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 387 388 struct dp_rxdma_ring rx_refill_buf_ring; 389 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 390 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 391 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 392 struct dp_rxdma_mon_ring tx_mon_buf_ring; 393 struct ath12k_reo_q_addr_lut reoq_lut; 394 struct ath12k_reo_q_addr_lut ml_reoq_lut; 395 }; 396 397 /* HTT definitions */ 398 #define HTT_TAG_TCL_METADATA_VERSION 5 399 400 #define HTT_TCL_META_DATA_TYPE GENMASK(1, 0) 401 #define HTT_TCL_META_DATA_VALID_HTT BIT(2) 402 403 /* vdev meta data */ 404 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3) 405 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11) 406 #define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13) 407 408 /* peer meta data */ 409 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3) 410 411 /* Global sequence number */ 412 #define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3 413 #define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2) 414 #define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3) 415 #define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128 416 417 /* HTT tx completion is overlaid in wbm_release_ring */ 418 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 419 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 420 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 421 422 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 423 424 struct htt_tx_wbm_completion { 425 __le32 rsvd0[2]; 426 __le32 info0; 427 __le32 info1; 428 __le32 info2; 429 __le32 info3; 430 __le32 info4; 431 __le32 rsvd1; 432 433 } __packed; 434 435 enum htt_h2t_msg_type { 436 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 437 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 438 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 439 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 440 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 441 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 442 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 443 }; 444 445 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 446 #define HTT_OPTION_TCL_METADATA_VER_V2 2 447 #define HTT_OPTION_TAG GENMASK(7, 0) 448 #define HTT_OPTION_LEN GENMASK(15, 8) 449 #define HTT_OPTION_VALUE GENMASK(31, 16) 450 #define HTT_TCL_METADATA_VER_SZ 4 451 452 struct htt_ver_req_cmd { 453 __le32 ver_reg_info; 454 __le32 tcl_metadata_version; 455 } __packed; 456 457 enum htt_srng_ring_type { 458 HTT_HW_TO_SW_RING, 459 HTT_SW_TO_HW_RING, 460 HTT_SW_TO_SW_RING, 461 }; 462 463 enum htt_srng_ring_id { 464 HTT_RXDMA_HOST_BUF_RING, 465 HTT_RXDMA_MONITOR_STATUS_RING, 466 HTT_RXDMA_MONITOR_BUF_RING, 467 HTT_RXDMA_MONITOR_DESC_RING, 468 HTT_RXDMA_MONITOR_DEST_RING, 469 HTT_HOST1_TO_FW_RXBUF_RING, 470 HTT_HOST2_TO_FW_RXBUF_RING, 471 HTT_RXDMA_NON_MONITOR_DEST_RING, 472 HTT_RXDMA_HOST_BUF_RING2, 473 HTT_TX_MON_HOST2MON_BUF_RING, 474 HTT_TX_MON_MON2HOST_DEST_RING, 475 HTT_RX_MON_HOST2MON_BUF_RING, 476 HTT_RX_MON_MON2HOST_DEST_RING, 477 }; 478 479 /* host -> target HTT_SRING_SETUP message 480 * 481 * After target is booted up, Host can send SRING setup message for 482 * each host facing LMAC SRING. Target setups up HW registers based 483 * on setup message and confirms back to Host if response_required is set. 484 * Host should wait for confirmation message before sending new SRING 485 * setup message 486 * 487 * The message would appear as follows: 488 * 489 * |31 24|23 20|19|18 16|15|14 8|7 0| 490 * |--------------- +-----------------+----------------+------------------| 491 * | ring_type | ring_id | pdev_id | msg_type | 492 * |----------------------------------------------------------------------| 493 * | ring_base_addr_lo | 494 * |----------------------------------------------------------------------| 495 * | ring_base_addr_hi | 496 * |----------------------------------------------------------------------| 497 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 498 * |----------------------------------------------------------------------| 499 * | ring_head_offset32_remote_addr_lo | 500 * |----------------------------------------------------------------------| 501 * | ring_head_offset32_remote_addr_hi | 502 * |----------------------------------------------------------------------| 503 * | ring_tail_offset32_remote_addr_lo | 504 * |----------------------------------------------------------------------| 505 * | ring_tail_offset32_remote_addr_hi | 506 * |----------------------------------------------------------------------| 507 * | ring_msi_addr_lo | 508 * |----------------------------------------------------------------------| 509 * | ring_msi_addr_hi | 510 * |----------------------------------------------------------------------| 511 * | ring_msi_data | 512 * |----------------------------------------------------------------------| 513 * | intr_timer_th |IM| intr_batch_counter_th | 514 * |----------------------------------------------------------------------| 515 * | reserved |RR|PTCF| intr_low_threshold | 516 * |----------------------------------------------------------------------| 517 * Where 518 * IM = sw_intr_mode 519 * RR = response_required 520 * PTCF = prefetch_timer_cfg 521 * 522 * The message is interpreted as follows: 523 * dword0 - b'0:7 - msg_type: This will be set to 524 * HTT_H2T_MSG_TYPE_SRING_SETUP 525 * b'8:15 - pdev_id: 526 * 0 (for rings at SOC/UMAC level), 527 * 1/2/3 mac id (for rings at LMAC level) 528 * b'16:23 - ring_id: identify which ring is to setup, 529 * more details can be got from enum htt_srng_ring_id 530 * b'24:31 - ring_type: identify type of host rings, 531 * more details can be got from enum htt_srng_ring_type 532 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 533 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 534 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 535 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 536 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 537 * SW_TO_HW_RING. 538 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 539 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 540 * Lower 32 bits of memory address of the remote variable 541 * storing the 4-byte word offset that identifies the head 542 * element within the ring. 543 * (The head offset variable has type u32.) 544 * Valid for HW_TO_SW and SW_TO_SW rings. 545 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 546 * Upper 32 bits of memory address of the remote variable 547 * storing the 4-byte word offset that identifies the head 548 * element within the ring. 549 * (The head offset variable has type u32.) 550 * Valid for HW_TO_SW and SW_TO_SW rings. 551 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 552 * Lower 32 bits of memory address of the remote variable 553 * storing the 4-byte word offset that identifies the tail 554 * element within the ring. 555 * (The tail offset variable has type u32.) 556 * Valid for HW_TO_SW and SW_TO_SW rings. 557 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 558 * Upper 32 bits of memory address of the remote variable 559 * storing the 4-byte word offset that identifies the tail 560 * element within the ring. 561 * (The tail offset variable has type u32.) 562 * Valid for HW_TO_SW and SW_TO_SW rings. 563 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 564 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 565 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 566 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 567 * dword10 - b'0:31 - ring_msi_data: MSI data 568 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 569 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 570 * dword11 - b'0:14 - intr_batch_counter_th: 571 * batch counter threshold is in units of 4-byte words. 572 * HW internally maintains and increments batch count. 573 * (see SRING spec for detail description). 574 * When batch count reaches threshold value, an interrupt 575 * is generated by HW. 576 * b'15 - sw_intr_mode: 577 * This configuration shall be static. 578 * Only programmed at power up. 579 * 0: generate pulse style sw interrupts 580 * 1: generate level style sw interrupts 581 * b'16:31 - intr_timer_th: 582 * The timer init value when timer is idle or is 583 * initialized to start downcounting. 584 * In 8us units (to cover a range of 0 to 524 ms) 585 * dword12 - b'0:15 - intr_low_threshold: 586 * Used only by Consumer ring to generate ring_sw_int_p. 587 * Ring entries low threshold water mark, that is used 588 * in combination with the interrupt timer as well as 589 * the clearing of the level interrupt. 590 * b'16:18 - prefetch_timer_cfg: 591 * Used only by Consumer ring to set timer mode to 592 * support Application prefetch handling. 593 * The external tail offset/pointer will be updated 594 * at following intervals: 595 * 3'b000: (Prefetch feature disabled; used only for debug) 596 * 3'b001: 1 usec 597 * 3'b010: 4 usec 598 * 3'b011: 8 usec (default) 599 * 3'b100: 16 usec 600 * Others: Reserved 601 * b'19 - response_required: 602 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 603 * b'20:31 - reserved: reserved for future use 604 */ 605 606 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 607 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 608 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 609 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 610 611 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 612 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 613 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 614 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 615 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 616 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 617 618 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 619 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 620 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 621 622 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 623 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 624 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 625 626 struct htt_srng_setup_cmd { 627 __le32 info0; 628 __le32 ring_base_addr_lo; 629 __le32 ring_base_addr_hi; 630 __le32 info1; 631 __le32 ring_head_off32_remote_addr_lo; 632 __le32 ring_head_off32_remote_addr_hi; 633 __le32 ring_tail_off32_remote_addr_lo; 634 __le32 ring_tail_off32_remote_addr_hi; 635 __le32 ring_msi_addr_lo; 636 __le32 ring_msi_addr_hi; 637 __le32 msi_data; 638 __le32 intr_info; 639 __le32 info2; 640 } __packed; 641 642 /* host -> target FW PPDU_STATS config message 643 * 644 * @details 645 * The following field definitions describe the format of the HTT host 646 * to target FW for PPDU_STATS_CFG msg. 647 * The message allows the host to configure the PPDU_STATS_IND messages 648 * produced by the target. 649 * 650 * |31 24|23 16|15 8|7 0| 651 * |-----------------------------------------------------------| 652 * | REQ bit mask | pdev_mask | msg type | 653 * |-----------------------------------------------------------| 654 * Header fields: 655 * - MSG_TYPE 656 * Bits 7:0 657 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 658 * Value: 0x11 659 * - PDEV_MASK 660 * Bits 8:15 661 * Purpose: identifies which pdevs this PPDU stats configuration applies to 662 * Value: This is a overloaded field, refer to usage and interpretation of 663 * PDEV in interface document. 664 * Bit 8 : Reserved for SOC stats 665 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 666 * Indicates MACID_MASK in DBS 667 * - REQ_TLV_BIT_MASK 668 * Bits 16:31 669 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 670 * needs to be included in the target's PPDU_STATS_IND messages. 671 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 672 * 673 */ 674 675 struct htt_ppdu_stats_cfg_cmd { 676 __le32 msg; 677 } __packed; 678 679 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 680 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 681 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 682 683 enum htt_ppdu_stats_tag_type { 684 HTT_PPDU_STATS_TAG_COMMON, 685 HTT_PPDU_STATS_TAG_USR_COMMON, 686 HTT_PPDU_STATS_TAG_USR_RATE, 687 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 688 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 689 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 690 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 691 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 692 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 693 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 694 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 695 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 696 HTT_PPDU_STATS_TAG_INFO, 697 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 698 699 /* New TLV's are added above to this line */ 700 HTT_PPDU_STATS_TAG_MAX, 701 }; 702 703 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 704 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 705 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 706 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 707 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 708 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 709 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 710 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 711 712 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 713 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 714 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 715 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 716 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 717 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 718 HTT_PPDU_STATS_TAG_DEFAULT) 719 720 enum htt_stats_internal_ppdu_frametype { 721 HTT_STATS_PPDU_FTYPE_CTRL, 722 HTT_STATS_PPDU_FTYPE_DATA, 723 HTT_STATS_PPDU_FTYPE_BAR, 724 HTT_STATS_PPDU_FTYPE_MAX 725 }; 726 727 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 728 * 729 * details: 730 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 731 * configure RXDMA rings. 732 * The configuration is per ring based and includes both packet subtypes 733 * and PPDU/MPDU TLVs. 734 * 735 * The message would appear as follows: 736 * 737 * |31 29|28|27|26|25|24|23 16|15 8|7 0| 738 * |-------+--+--+--+--+--+-----------+----------------+---------------| 739 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 740 * |-------------------------------------------------------------------| 741 * | rsvd2 | ring_buffer_size | 742 * |-------------------------------------------------------------------| 743 * | packet_type_enable_flags_0 | 744 * |-------------------------------------------------------------------| 745 * | packet_type_enable_flags_1 | 746 * |-------------------------------------------------------------------| 747 * | packet_type_enable_flags_2 | 748 * |-------------------------------------------------------------------| 749 * | packet_type_enable_flags_3 | 750 * |-------------------------------------------------------------------| 751 * | tlv_filter_in_flags | 752 * |-------------------------------------------------------------------| 753 * Where: 754 * PS = pkt_swap 755 * SS = status_swap 756 * The message is interpreted as follows: 757 * dword0 - b'0:7 - msg_type: This will be set to 758 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 759 * b'8:15 - pdev_id: 760 * 0 (for rings at SOC/UMAC level), 761 * 1/2/3 mac id (for rings at LMAC level) 762 * b'16:23 - ring_id : Identify the ring to configure. 763 * More details can be got from enum htt_srng_ring_id 764 * b'24 - status_swap: 1 is to swap status TLV 765 * b'25 - pkt_swap: 1 is to swap packet TLV 766 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 767 * configuration fields are valid 768 * b'27 - drop_thresh_valid (DT): flag to indicate if the 769 * rx_drop_threshold field is valid 770 * b'28 - rx_mon_global_en: Enable/Disable global register 771 * configuration in Rx monitor module. 772 * b'29:31 - rsvd1: reserved for future use 773 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 774 * in byte units. 775 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 776 * - b'16:31 - rsvd2: Reserved for future use 777 * dword2 - b'0:31 - packet_type_enable_flags_0: 778 * Enable MGMT packet from 0b0000 to 0b1001 779 * bits from low to high: FP, MD, MO - 3 bits 780 * FP: Filter_Pass 781 * MD: Monitor_Direct 782 * MO: Monitor_Other 783 * 10 mgmt subtypes * 3 bits -> 30 bits 784 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 785 * dword3 - b'0:31 - packet_type_enable_flags_1: 786 * Enable MGMT packet from 0b1010 to 0b1111 787 * bits from low to high: FP, MD, MO - 3 bits 788 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 789 * dword4 - b'0:31 - packet_type_enable_flags_2: 790 * Enable CTRL packet from 0b0000 to 0b1001 791 * bits from low to high: FP, MD, MO - 3 bits 792 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 793 * dword5 - b'0:31 - packet_type_enable_flags_3: 794 * Enable CTRL packet from 0b1010 to 0b1111, 795 * MCAST_DATA, UCAST_DATA, NULL_DATA 796 * bits from low to high: FP, MD, MO - 3 bits 797 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 798 * dword6 - b'0:31 - tlv_filter_in_flags: 799 * Filter in Attention/MPDU/PPDU/Header/User tlvs 800 * Refer to CFG_TLV_FILTER_IN_FLAG defs 801 */ 802 803 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 804 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 805 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 806 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 807 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 808 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID BIT(26) 809 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL BIT(27) 810 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON BIT(28) 811 812 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 813 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16) 814 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19) 815 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22) 816 817 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0) 818 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE BIT(17) 819 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE BIT(18) 820 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE BIT(19) 821 822 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET BIT(0) 823 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1) 824 825 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 826 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 827 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 828 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 829 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 830 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 831 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 832 833 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23) 834 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) 835 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) 836 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) 837 838 enum htt_rx_filter_tlv_flags { 839 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 840 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 841 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 842 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 843 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 844 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 845 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 846 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 847 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 848 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 849 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 850 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 851 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 852 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13), 853 }; 854 855 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 856 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 857 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 858 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 859 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 860 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 861 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 862 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 863 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 864 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 865 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 866 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 867 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 868 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 869 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 870 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 871 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 872 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 873 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 874 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 875 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 876 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 877 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 878 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 879 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 880 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 881 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 882 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 883 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 884 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 885 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 886 }; 887 888 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 889 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 890 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 891 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 892 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 893 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 894 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 895 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 896 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 897 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 898 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 899 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 900 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 901 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 902 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 903 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 904 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 905 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 906 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 907 }; 908 909 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 910 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 911 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 912 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 913 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 914 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 915 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 916 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 917 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 918 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 919 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 920 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 921 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 922 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 923 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 924 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 925 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 926 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 927 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 928 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 929 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 930 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 931 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 932 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 933 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 934 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 935 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 936 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 937 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 938 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 939 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 940 }; 941 942 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 943 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 944 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 945 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 946 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 947 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 948 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 949 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 950 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 951 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 952 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 953 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 954 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 955 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 956 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 957 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 958 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 959 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 960 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 961 }; 962 963 enum htt_rx_data_pkt_filter_tlv_flasg3 { 964 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 965 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 966 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 967 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 968 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 969 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 970 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 971 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 972 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 973 }; 974 975 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 976 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 977 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 978 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 979 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 980 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 981 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 982 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 983 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 984 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 985 986 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 987 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 988 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 989 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 990 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 991 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 992 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 993 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 994 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 995 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 996 997 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 998 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 999 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1000 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1001 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1002 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1003 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1004 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1005 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1006 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1007 1008 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1009 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1010 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1011 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1012 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1013 1014 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1015 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1016 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1017 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1018 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1019 1020 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1021 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1022 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1023 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1024 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1025 1026 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1027 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1028 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1029 1030 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1031 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1032 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1033 1034 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1035 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1036 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1037 1038 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1039 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1040 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1041 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1042 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1043 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1044 1045 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1046 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1047 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1048 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1049 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1050 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1051 1052 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1053 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1054 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1055 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1056 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1057 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1058 1059 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1060 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1061 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1062 1063 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1064 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1065 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1066 1067 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1068 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1069 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1070 1071 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1072 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1073 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1074 1075 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1076 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1077 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1078 1079 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1080 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1081 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1082 1083 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1084 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1085 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1086 1087 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1088 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1089 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1090 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1091 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1092 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1093 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1094 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1095 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1096 1097 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1098 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1099 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1100 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1101 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1102 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1103 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1104 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1105 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1106 1107 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1108 1109 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1110 1111 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1112 1113 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1114 1115 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1116 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1117 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1118 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1119 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1120 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1121 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1122 1123 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1124 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1125 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1126 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1127 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1128 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1129 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1130 1131 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1132 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1133 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1134 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1135 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1136 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1137 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1138 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1139 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1140 1141 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \ 1142 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1143 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1144 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1145 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1146 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1147 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1148 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1149 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1150 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1151 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1152 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1153 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ 1154 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO) 1155 1156 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1157 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1158 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1159 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1160 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1161 1162 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1163 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1164 1165 struct htt_rx_ring_selection_cfg_cmd { 1166 __le32 info0; 1167 __le32 info1; 1168 __le32 pkt_type_en_flags0; 1169 __le32 pkt_type_en_flags1; 1170 __le32 pkt_type_en_flags2; 1171 __le32 pkt_type_en_flags3; 1172 __le32 rx_filter_tlv; 1173 __le32 rx_packet_offset; 1174 __le32 rx_mpdu_offset; 1175 __le32 rx_msdu_offset; 1176 __le32 rx_attn_offset; 1177 __le32 info2; 1178 __le32 reserved[2]; 1179 __le32 rx_mpdu_start_end_mask; 1180 __le32 rx_msdu_end_word_mask; 1181 __le32 info3; 1182 } __packed; 1183 1184 #define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32 1185 #define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7 1186 #define HTT_RX_RING_PKT_TLV_OFFSET 0x1 1187 1188 struct htt_rx_ring_tlv_filter { 1189 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1190 u32 pkt_filter_flags0; /* MGMT */ 1191 u32 pkt_filter_flags1; /* MGMT */ 1192 u32 pkt_filter_flags2; /* CTRL */ 1193 u32 pkt_filter_flags3; /* DATA */ 1194 bool offset_valid; 1195 u16 rx_packet_offset; 1196 u16 rx_header_offset; 1197 u16 rx_mpdu_end_offset; 1198 u16 rx_mpdu_start_offset; 1199 u16 rx_msdu_end_offset; 1200 u16 rx_msdu_start_offset; 1201 u16 rx_attn_offset; 1202 u16 rx_mpdu_start_wmask; 1203 u16 rx_mpdu_end_wmask; 1204 u32 rx_msdu_end_wmask; 1205 u32 conf_len_ctrl; 1206 u32 conf_len_mgmt; 1207 u32 conf_len_data; 1208 u16 rx_drop_threshold; 1209 bool enable_log_mgmt_type; 1210 bool enable_log_ctrl_type; 1211 bool enable_log_data_type; 1212 bool enable_rx_tlv_offset; 1213 u16 rx_tlv_offset; 1214 bool drop_threshold_valid; 1215 bool rxmon_disable; 1216 }; 1217 1218 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1219 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1220 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1221 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1222 1223 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1224 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1225 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1226 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1227 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1228 1229 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1230 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1231 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1232 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1233 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1234 1235 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1236 1237 struct htt_tx_ring_selection_cfg_cmd { 1238 __le32 info0; 1239 __le32 info1; 1240 __le32 info2; 1241 __le32 tlv_filter_mask_in0; 1242 __le32 tlv_filter_mask_in1; 1243 __le32 tlv_filter_mask_in2; 1244 __le32 tlv_filter_mask_in3; 1245 __le32 reserved[3]; 1246 } __packed; 1247 1248 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1249 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1250 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1251 1252 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1253 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1254 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1255 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1256 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1257 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1258 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1259 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1260 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1261 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1262 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1263 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1264 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1265 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1266 1267 struct htt_tx_ring_tlv_filter { 1268 u32 tx_mon_downstream_tlv_flags; 1269 u32 tx_mon_upstream_tlv_flags0; 1270 u32 tx_mon_upstream_tlv_flags1; 1271 u32 tx_mon_upstream_tlv_flags2; 1272 bool tx_mon_mgmt_filter; 1273 bool tx_mon_data_filter; 1274 bool tx_mon_ctrl_filter; 1275 u16 tx_mon_pkt_dma_len; 1276 } __packed; 1277 1278 enum htt_tx_mon_upstream_tlv_flags0 { 1279 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1280 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1281 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1282 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1283 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1284 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1285 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1286 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1287 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1288 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1289 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1290 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1291 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1292 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1293 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1294 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1295 }; 1296 1297 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1298 1299 /* HTT message target->host */ 1300 1301 enum htt_t2h_msg_type { 1302 HTT_T2H_MSG_TYPE_VERSION_CONF, 1303 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1304 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1305 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1306 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1307 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1308 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1309 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1310 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1311 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1312 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1313 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1314 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1315 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1316 }; 1317 1318 #define HTT_TARGET_VERSION_MAJOR 3 1319 1320 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1321 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1322 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1323 1324 struct htt_t2h_version_conf_msg { 1325 __le32 version; 1326 } __packed; 1327 1328 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1329 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1330 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1331 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1332 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1333 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1334 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1335 1336 struct htt_t2h_peer_map_event { 1337 __le32 info; 1338 __le32 mac_addr_l32; 1339 __le32 info1; 1340 __le32 info2; 1341 } __packed; 1342 1343 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1344 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1345 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1346 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1347 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1348 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1349 1350 struct htt_t2h_peer_unmap_event { 1351 __le32 info; 1352 __le32 mac_addr_l32; 1353 __le32 info1; 1354 } __packed; 1355 1356 struct htt_resp_msg { 1357 union { 1358 struct htt_t2h_version_conf_msg version_msg; 1359 struct htt_t2h_peer_map_event peer_map_ev; 1360 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1361 }; 1362 } __packed; 1363 1364 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1365 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1366 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1367 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1368 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1369 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1370 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1371 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1372 1373 struct htt_t2h_vdev_txrx_stats_ind { 1374 __le32 vdev_id; 1375 __le32 rx_msdu_byte_cnt_lo; 1376 __le32 rx_msdu_byte_cnt_hi; 1377 __le32 rx_msdu_cnt_lo; 1378 __le32 rx_msdu_cnt_hi; 1379 __le32 tx_msdu_byte_cnt_lo; 1380 __le32 tx_msdu_byte_cnt_hi; 1381 __le32 tx_msdu_cnt_lo; 1382 __le32 tx_msdu_cnt_hi; 1383 __le32 tx_retry_cnt_lo; 1384 __le32 tx_retry_cnt_hi; 1385 __le32 tx_retry_byte_cnt_lo; 1386 __le32 tx_retry_byte_cnt_hi; 1387 __le32 tx_drop_cnt_lo; 1388 __le32 tx_drop_cnt_hi; 1389 __le32 tx_drop_byte_cnt_lo; 1390 __le32 tx_drop_byte_cnt_hi; 1391 __le32 msdu_ttl_cnt_lo; 1392 __le32 msdu_ttl_cnt_hi; 1393 __le32 msdu_ttl_byte_cnt_lo; 1394 __le32 msdu_ttl_byte_cnt_hi; 1395 } __packed; 1396 1397 struct htt_t2h_vdev_common_stats_tlv { 1398 __le32 soc_drop_count_lo; 1399 __le32 soc_drop_count_hi; 1400 } __packed; 1401 1402 /* ppdu stats 1403 * 1404 * @details 1405 * The following field definitions describe the format of the HTT target 1406 * to host ppdu stats indication message. 1407 * 1408 * 1409 * |31 16|15 12|11 10|9 8|7 0 | 1410 * |----------------------------------------------------------------------| 1411 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1412 * |----------------------------------------------------------------------| 1413 * | ppdu_id | 1414 * |----------------------------------------------------------------------| 1415 * | Timestamp in us | 1416 * |----------------------------------------------------------------------| 1417 * | reserved | 1418 * |----------------------------------------------------------------------| 1419 * | type-specific stats info | 1420 * | (see htt_ppdu_stats.h) | 1421 * |----------------------------------------------------------------------| 1422 * Header fields: 1423 * - MSG_TYPE 1424 * Bits 7:0 1425 * Purpose: Identifies this is a PPDU STATS indication 1426 * message. 1427 * Value: 0x1d 1428 * - mac_id 1429 * Bits 9:8 1430 * Purpose: mac_id of this ppdu_id 1431 * Value: 0-3 1432 * - pdev_id 1433 * Bits 11:10 1434 * Purpose: pdev_id of this ppdu_id 1435 * Value: 0-3 1436 * 0 (for rings at SOC level), 1437 * 1/2/3 PDEV -> 0/1/2 1438 * - payload_size 1439 * Bits 31:16 1440 * Purpose: total tlv size 1441 * Value: payload_size in bytes 1442 */ 1443 1444 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1445 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1446 1447 struct ath12k_htt_ppdu_stats_msg { 1448 __le32 info; 1449 __le32 ppdu_id; 1450 __le32 timestamp; 1451 __le32 rsvd; 1452 u8 data[]; 1453 } __packed; 1454 1455 struct htt_tlv { 1456 __le32 header; 1457 u8 value[]; 1458 } __packed; 1459 1460 #define HTT_TLV_TAG GENMASK(11, 0) 1461 #define HTT_TLV_LEN GENMASK(23, 12) 1462 1463 enum HTT_PPDU_STATS_BW { 1464 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1465 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1466 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1467 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1468 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1469 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1470 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1471 }; 1472 1473 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1474 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1475 /* bw - HTT_PPDU_STATS_BW */ 1476 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1477 1478 struct htt_ppdu_stats_common { 1479 __le32 ppdu_id; 1480 __le16 sched_cmdid; 1481 u8 ring_id; 1482 u8 num_users; 1483 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1484 __le32 chain_mask; 1485 __le32 fes_duration_us; /* frame exchange sequence */ 1486 __le32 ppdu_sch_eval_start_tstmp_us; 1487 __le32 ppdu_sch_end_tstmp_us; 1488 __le32 ppdu_start_tstmp_us; 1489 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1490 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1491 */ 1492 __le16 phy_mode; 1493 __le16 bw_mhz; 1494 } __packed; 1495 1496 enum htt_ppdu_stats_gi { 1497 HTT_PPDU_STATS_SGI_0_8_US, 1498 HTT_PPDU_STATS_SGI_0_4_US, 1499 HTT_PPDU_STATS_SGI_1_6_US, 1500 HTT_PPDU_STATS_SGI_3_2_US, 1501 }; 1502 1503 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1504 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1505 1506 enum HTT_PPDU_STATS_PPDU_TYPE { 1507 HTT_PPDU_STATS_PPDU_TYPE_SU, 1508 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1509 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1510 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1511 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1512 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1513 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1514 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1515 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1516 HTT_PPDU_STATS_PPDU_TYPE_MAX 1517 }; 1518 1519 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1520 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1521 1522 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1523 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1524 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1525 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1526 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1527 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1528 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1529 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1530 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1531 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1532 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1533 1534 #define HTT_USR_RATE_PREAMBLE(_val) \ 1535 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1536 #define HTT_USR_RATE_BW(_val) \ 1537 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1538 #define HTT_USR_RATE_NSS(_val) \ 1539 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1540 #define HTT_USR_RATE_MCS(_val) \ 1541 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1542 #define HTT_USR_RATE_GI(_val) \ 1543 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1544 #define HTT_USR_RATE_DCM(_val) \ 1545 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1546 1547 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1548 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1549 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1550 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1551 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1552 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1553 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1554 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1555 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1556 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1557 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1558 1559 struct htt_ppdu_stats_user_rate { 1560 u8 tid_num; 1561 u8 reserved0; 1562 __le16 sw_peer_id; 1563 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1564 __le16 ru_end; 1565 __le16 ru_start; 1566 __le16 resp_ru_end; 1567 __le16 resp_ru_start; 1568 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1569 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1570 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1571 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1572 } __packed; 1573 1574 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1575 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1576 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1577 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1578 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1579 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1580 1581 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1582 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1583 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1584 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1585 #define HTT_TX_INFO_RATECODE(_flags) \ 1586 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1587 #define HTT_TX_INFO_PEERID(_flags) \ 1588 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1589 1590 enum htt_ppdu_stats_usr_compln_status { 1591 HTT_PPDU_STATS_USER_STATUS_OK, 1592 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1593 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1594 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1595 HTT_PPDU_STATS_USER_STATUS_ABORT, 1596 }; 1597 1598 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1599 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1600 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1601 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1602 1603 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1604 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1605 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1606 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1607 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1608 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1609 1610 struct htt_ppdu_stats_usr_cmpltn_cmn { 1611 u8 status; 1612 u8 tid_num; 1613 __le16 sw_peer_id; 1614 /* RSSI value of last ack packet (units = dB above noise floor) */ 1615 __le32 ack_rssi; 1616 __le16 mpdu_tried; 1617 __le16 mpdu_success; 1618 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1619 } __packed; 1620 1621 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1622 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1623 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1624 1625 #define HTT_PPDU_STATS_NON_QOS_TID 16 1626 1627 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1628 __le32 ppdu_id; 1629 __le16 sw_peer_id; 1630 __le16 reserved0; 1631 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1632 __le16 current_seq; 1633 __le16 start_seq; 1634 __le32 success_bytes; 1635 } __packed; 1636 1637 struct htt_ppdu_user_stats { 1638 u16 peer_id; 1639 u16 delay_ba; 1640 u32 tlv_flags; 1641 bool is_valid_peer_id; 1642 struct htt_ppdu_stats_user_rate rate; 1643 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1644 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1645 }; 1646 1647 #define HTT_PPDU_STATS_MAX_USERS 8 1648 #define HTT_PPDU_DESC_MAX_DEPTH 16 1649 1650 struct htt_ppdu_stats { 1651 struct htt_ppdu_stats_common common; 1652 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1653 }; 1654 1655 struct htt_ppdu_stats_info { 1656 u32 tlv_bitmap; 1657 u32 ppdu_id; 1658 u32 frame_type; 1659 u32 frame_ctrl; 1660 u32 delay_ba; 1661 u32 bar_num_users; 1662 struct htt_ppdu_stats ppdu_stats; 1663 struct list_head list; 1664 }; 1665 1666 /* @brief target -> host MLO offset indiciation message 1667 * 1668 * @details 1669 * The following field definitions describe the format of the HTT target 1670 * to host mlo offset indication message. 1671 * 1672 * 1673 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1674 * |---------------------------------------------------------------------| 1675 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1676 * |---------------------------------------------------------------------| 1677 * | sync_timestamp_lo_us | 1678 * |---------------------------------------------------------------------| 1679 * | sync_timestamp_hi_us | 1680 * |---------------------------------------------------------------------| 1681 * | mlo_offset_lo | 1682 * |---------------------------------------------------------------------| 1683 * | mlo_offset_hi | 1684 * |---------------------------------------------------------------------| 1685 * | mlo_offset_clcks | 1686 * |---------------------------------------------------------------------| 1687 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1688 * |---------------------------------------------------------------------| 1689 * | rsvd3 |mlo_comp_timer | 1690 * |---------------------------------------------------------------------| 1691 * Header fields 1692 * - MSG_TYPE 1693 * Bits 7:0 1694 * Purpose: Identifies this is a MLO offset indication msg 1695 * - PDEV_ID 1696 * Bits 9:8 1697 * Purpose: Pdev of this MLO offset 1698 * - CHIP_ID 1699 * Bits 12:10 1700 * Purpose: chip_id of this MLO offset 1701 * - MAC_FREQ 1702 * Bits 28:13 1703 * - SYNC_TIMESTAMP_LO_US 1704 * Purpose: clock frequency of the mac HW block in MHz 1705 * Bits: 31:0 1706 * Purpose: lower 32 bits of the WLAN global time stamp at which 1707 * last sync interrupt was received 1708 * - SYNC_TIMESTAMP_HI_US 1709 * Bits: 31:0 1710 * Purpose: upper 32 bits of WLAN global time stamp at which 1711 * last sync interrupt was received 1712 * - MLO_OFFSET_LO 1713 * Bits: 31:0 1714 * Purpose: lower 32 bits of the MLO offset in us 1715 * - MLO_OFFSET_HI 1716 * Bits: 31:0 1717 * Purpose: upper 32 bits of the MLO offset in us 1718 * - MLO_COMP_US 1719 * Bits: 15:0 1720 * Purpose: MLO time stamp compensation applied in us 1721 * - MLO_COMP_CLCKS 1722 * Bits: 25:16 1723 * Purpose: MLO time stamp compensation applied in clock ticks 1724 * - MLO_COMP_TIMER 1725 * Bits: 21:0 1726 * Purpose: Periodic timer at which compensation is applied 1727 */ 1728 1729 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1730 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1731 1732 struct ath12k_htt_mlo_offset_msg { 1733 __le32 info; 1734 __le32 sync_timestamp_lo_us; 1735 __le32 sync_timestamp_hi_us; 1736 __le32 mlo_offset_hi; 1737 __le32 mlo_offset_lo; 1738 __le32 mlo_offset_clks; 1739 __le32 mlo_comp_clks; 1740 __le32 mlo_comp_timer; 1741 } __packed; 1742 1743 /* @brief host -> target FW extended statistics retrieve 1744 * 1745 * @details 1746 * The following field definitions describe the format of the HTT host 1747 * to target FW extended stats retrieve message. 1748 * The message specifies the type of stats the host wants to retrieve. 1749 * 1750 * |31 24|23 16|15 8|7 0| 1751 * |-----------------------------------------------------------| 1752 * | reserved | stats type | pdev_mask | msg type | 1753 * |-----------------------------------------------------------| 1754 * | config param [0] | 1755 * |-----------------------------------------------------------| 1756 * | config param [1] | 1757 * |-----------------------------------------------------------| 1758 * | config param [2] | 1759 * |-----------------------------------------------------------| 1760 * | config param [3] | 1761 * |-----------------------------------------------------------| 1762 * | reserved | 1763 * |-----------------------------------------------------------| 1764 * | cookie LSBs | 1765 * |-----------------------------------------------------------| 1766 * | cookie MSBs | 1767 * |-----------------------------------------------------------| 1768 * Header fields: 1769 * - MSG_TYPE 1770 * Bits 7:0 1771 * Purpose: identifies this is a extended stats upload request message 1772 * Value: 0x10 1773 * - PDEV_MASK 1774 * Bits 8:15 1775 * Purpose: identifies the mask of PDEVs to retrieve stats from 1776 * Value: This is a overloaded field, refer to usage and interpretation of 1777 * PDEV in interface document. 1778 * Bit 8 : Reserved for SOC stats 1779 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1780 * Indicates MACID_MASK in DBS 1781 * - STATS_TYPE 1782 * Bits 23:16 1783 * Purpose: identifies which FW statistics to upload 1784 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1785 * - Reserved 1786 * Bits 31:24 1787 * - CONFIG_PARAM [0] 1788 * Bits 31:0 1789 * Purpose: give an opaque configuration value to the specified stats type 1790 * Value: stats-type specific configuration value 1791 * Refer to htt_stats.h for interpretation for each stats sub_type 1792 * - CONFIG_PARAM [1] 1793 * Bits 31:0 1794 * Purpose: give an opaque configuration value to the specified stats type 1795 * Value: stats-type specific configuration value 1796 * Refer to htt_stats.h for interpretation for each stats sub_type 1797 * - CONFIG_PARAM [2] 1798 * Bits 31:0 1799 * Purpose: give an opaque configuration value to the specified stats type 1800 * Value: stats-type specific configuration value 1801 * Refer to htt_stats.h for interpretation for each stats sub_type 1802 * - CONFIG_PARAM [3] 1803 * Bits 31:0 1804 * Purpose: give an opaque configuration value to the specified stats type 1805 * Value: stats-type specific configuration value 1806 * Refer to htt_stats.h for interpretation for each stats sub_type 1807 * - Reserved [31:0] for future use. 1808 * - COOKIE_LSBS 1809 * Bits 31:0 1810 * Purpose: Provide a mechanism to match a target->host stats confirmation 1811 * message with its preceding host->target stats request message. 1812 * Value: LSBs of the opaque cookie specified by the host-side requestor 1813 * - COOKIE_MSBS 1814 * Bits 31:0 1815 * Purpose: Provide a mechanism to match a target->host stats confirmation 1816 * message with its preceding host->target stats request message. 1817 * Value: MSBs of the opaque cookie specified by the host-side requestor 1818 */ 1819 1820 struct htt_ext_stats_cfg_hdr { 1821 u8 msg_type; 1822 u8 pdev_mask; 1823 u8 stats_type; 1824 u8 reserved; 1825 } __packed; 1826 1827 struct htt_ext_stats_cfg_cmd { 1828 struct htt_ext_stats_cfg_hdr hdr; 1829 __le32 cfg_param0; 1830 __le32 cfg_param1; 1831 __le32 cfg_param2; 1832 __le32 cfg_param3; 1833 __le32 reserved; 1834 __le32 cookie_lsb; 1835 __le32 cookie_msb; 1836 } __packed; 1837 1838 /* htt stats config default params */ 1839 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1840 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1841 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1842 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1843 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1844 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1845 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1846 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1847 1848 /* HTT_DBG_EXT_STATS_PEER_INFO 1849 * PARAMS: 1850 * @config_param0: 1851 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1852 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1853 * [Bit31 : Bit16] sw_peer_id 1854 * @config_param1: 1855 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1856 * 0 bit htt_peer_stats_cmn_tlv 1857 * 1 bit htt_peer_details_tlv 1858 * 2 bit htt_tx_peer_rate_stats_tlv 1859 * 3 bit htt_rx_peer_rate_stats_tlv 1860 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1861 * 5 bit htt_rx_tid_stats_tlv 1862 * 6 bit htt_msdu_flow_stats_tlv 1863 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1864 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1865 * [Bit31 : Bit16] reserved 1866 */ 1867 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1868 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1869 1870 /* Used to set different configs to the specified stats type.*/ 1871 struct htt_ext_stats_cfg_params { 1872 u32 cfg0; 1873 u32 cfg1; 1874 u32 cfg2; 1875 u32 cfg3; 1876 }; 1877 1878 enum vdev_stats_offload_timer_duration { 1879 ATH12K_STATS_TIMER_DUR_500MS = 1, 1880 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1881 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1882 }; 1883 1884 #define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1885 #define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1886 #define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1887 #define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1888 #define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1889 #define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1890 1891 struct htt_mac_addr { 1892 __le32 mac_addr_l32; 1893 __le32 mac_addr_h16; 1894 } __packed; 1895 1896 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1897 { 1898 memcpy(addr, &addr_l32, 4); 1899 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1900 } 1901 1902 int ath12k_dp_service_srng(struct ath12k_base *ab, 1903 struct ath12k_ext_irq_grp *irq_grp, 1904 int budget); 1905 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1906 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif); 1907 void ath12k_dp_free(struct ath12k_base *ab); 1908 int ath12k_dp_alloc(struct ath12k_base *ab); 1909 void ath12k_dp_cc_config(struct ath12k_base *ab); 1910 void ath12k_dp_partner_cc_init(struct ath12k_base *ab); 1911 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1912 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar); 1913 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1914 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1915 int mac_id, enum hal_ring_type ring_type); 1916 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1917 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1918 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1919 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1920 enum hal_ring_type type, int ring_num, 1921 int mac_id, int num_entries); 1922 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1923 struct dp_link_desc_bank *desc_bank, 1924 u32 ring_type, struct dp_srng *ring); 1925 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1926 struct dp_link_desc_bank *link_desc_banks, 1927 u32 ring_type, struct hal_srng *srng, 1928 u32 n_link_desc); 1929 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1930 u32 cookie); 1931 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1932 u32 desc_id); 1933 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab); 1934 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab); 1935 #endif 1936