1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_rx.h" 11 #include "hw.h" 12 13 #define MAX_RXDMA_PER_PDEV 2 14 15 struct ath12k_base; 16 struct ath12k_peer; 17 struct ath12k_dp; 18 struct ath12k_vif; 19 struct hal_tcl_status_ring; 20 struct ath12k_ext_irq_grp; 21 22 #define DP_MON_PURGE_TIMEOUT_MS 100 23 #define DP_MON_SERVICE_BUDGET 128 24 25 struct dp_srng { 26 u32 *vaddr_unaligned; 27 u32 *vaddr; 28 dma_addr_t paddr_unaligned; 29 dma_addr_t paddr; 30 int size; 31 u32 ring_id; 32 }; 33 34 struct dp_rxdma_mon_ring { 35 struct dp_srng refill_buf_ring; 36 struct idr bufs_idr; 37 /* Protects bufs_idr */ 38 spinlock_t idr_lock; 39 int bufs_max; 40 }; 41 42 struct dp_rxdma_ring { 43 struct dp_srng refill_buf_ring; 44 int bufs_max; 45 }; 46 47 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 48 49 struct dp_tx_ring { 50 u8 tcl_data_ring_id; 51 struct dp_srng tcl_data_ring; 52 struct dp_srng tcl_comp_ring; 53 struct hal_wbm_completion_ring_tx *tx_status; 54 int tx_status_head; 55 int tx_status_tail; 56 }; 57 58 struct ath12k_pdev_mon_stats { 59 u32 status_ppdu_state; 60 u32 status_ppdu_start; 61 u32 status_ppdu_end; 62 u32 status_ppdu_compl; 63 u32 status_ppdu_start_mis; 64 u32 status_ppdu_end_mis; 65 u32 status_ppdu_done; 66 u32 dest_ppdu_done; 67 u32 dest_mpdu_done; 68 u32 dest_mpdu_drop; 69 u32 dup_mon_linkdesc_cnt; 70 u32 dup_mon_buf_cnt; 71 }; 72 73 struct dp_link_desc_bank { 74 void *vaddr_unaligned; 75 void *vaddr; 76 dma_addr_t paddr_unaligned; 77 dma_addr_t paddr; 78 u32 size; 79 }; 80 81 /* Size to enforce scatter idle list mode */ 82 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 83 #define DP_LINK_DESC_BANKS_MAX 8 84 85 #define DP_LINK_DESC_START 0x4000 86 #define DP_LINK_DESC_SHIFT 3 87 88 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 89 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 90 91 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 92 93 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 94 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 95 #define DP_RX_DESC_COOKIE_MAX \ 96 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 97 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 98 99 enum ath12k_dp_ppdu_state { 100 DP_PPDU_STATUS_START, 101 DP_PPDU_STATUS_DONE, 102 }; 103 104 struct dp_mon_mpdu { 105 struct list_head list; 106 struct sk_buff *head; 107 struct sk_buff *tail; 108 }; 109 110 #define DP_MON_MAX_STATUS_BUF 32 111 112 struct ath12k_mon_data { 113 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 114 struct hal_rx_mon_ppdu_info mon_ppdu_info; 115 116 u32 mon_ppdu_status; 117 u32 mon_last_buf_cookie; 118 u64 mon_last_linkdesc_paddr; 119 u16 chan_noise_floor; 120 121 struct ath12k_pdev_mon_stats rx_mon_stats; 122 /* lock for monitor data */ 123 spinlock_t mon_lock; 124 struct sk_buff_head rx_status_q; 125 struct dp_mon_mpdu *mon_mpdu; 126 struct list_head dp_rx_mon_mpdu_list; 127 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF]; 128 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 129 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 130 }; 131 132 struct ath12k_pdev_dp { 133 u32 mac_id; 134 atomic_t num_tx_pending; 135 wait_queue_head_t tx_empty_waitq; 136 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 137 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 138 139 struct ieee80211_rx_status rx_status; 140 struct ath12k_mon_data mon_data; 141 }; 142 143 #define DP_NUM_CLIENTS_MAX 64 144 #define DP_AVG_TIDS_PER_CLIENT 2 145 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 146 #define DP_AVG_MSDUS_PER_FLOW 128 147 #define DP_AVG_FLOWS_PER_TID 2 148 #define DP_AVG_MPDUS_PER_TID_MAX 128 149 #define DP_AVG_MSDUS_PER_MPDU 4 150 151 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 152 153 #define DP_BA_WIN_SZ_MAX 1024 154 155 #define DP_TCL_NUM_RING_MAX 4 156 157 #define DP_IDLE_SCATTER_BUFS_MAX 16 158 159 #define DP_WBM_RELEASE_RING_SIZE 64 160 #define DP_TCL_DATA_RING_SIZE 512 161 #define DP_TX_COMP_RING_SIZE 32768 162 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 163 #define DP_TCL_CMD_RING_SIZE 32 164 #define DP_TCL_STATUS_RING_SIZE 32 165 #define DP_REO_DST_RING_MAX 8 166 #define DP_REO_DST_RING_SIZE 2048 167 #define DP_REO_REINJECT_RING_SIZE 32 168 #define DP_RX_RELEASE_RING_SIZE 1024 169 #define DP_REO_EXCEPTION_RING_SIZE 128 170 #define DP_REO_CMD_RING_SIZE 128 171 #define DP_REO_STATUS_RING_SIZE 2048 172 #define DP_RXDMA_BUF_RING_SIZE 4096 173 #define DP_RX_MAC_BUF_RING_SIZE 2048 174 #define DP_RXDMA_REFILL_RING_SIZE 2048 175 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 176 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 177 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 178 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 179 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 180 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 181 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 182 183 #define DP_TX_MONITOR_BUF_SIZE 2048 184 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 185 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 186 187 #define DP_RX_BUFFER_SIZE 2048 188 #define DP_RX_BUFFER_SIZE_LITE 1024 189 #define DP_RX_BUFFER_ALIGN_SIZE 128 190 191 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 192 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 193 194 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 195 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 196 197 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 198 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 199 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 200 201 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 202 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 203 204 #define ATH12K_NUM_POOL_TX_DESC 32768 205 206 /* TODO: revisit this count during testing */ 207 #define ATH12K_RX_DESC_COUNT (12288) 208 209 #define ATH12K_PAGE_SIZE PAGE_SIZE 210 211 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 212 * SPT pages which makes lower 12bits 0 213 */ 214 #define ATH12K_MAX_PPT_ENTRIES 1024 215 216 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 217 #define ATH12K_MAX_SPT_ENTRIES 512 218 219 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 220 221 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 222 ATH12K_MAX_SPT_ENTRIES) 223 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 224 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 225 226 #define ATH12K_TX_SPT_PAGE_OFFSET 0 227 #define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES 228 229 /* The SPT pages are divided for RX and TX, first block for RX 230 * and remaining for TX 231 */ 232 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 233 234 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 235 236 /* 4K aligned address have last 12 bits set to 0, this check is done 237 * so that two spt pages address can be stored per 8bytes 238 * of CMEM (PPT) 239 */ 240 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 241 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 242 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 243 244 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 245 #define ATH12K_CMEM_ADDR_MSB 0x10 246 247 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 248 #define ATH12K_CC_SPT_MSB 8 249 #define ATH12K_CC_PPT_MSB 19 250 #define ATH12K_CC_PPT_SHIFT 9 251 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 252 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 253 254 #define DP_REO_QREF_NUM GENMASK(31, 16) 255 #define DP_MAX_PEER_ID 2047 256 257 /* Total size of the LUT is based on 2K peers, each having reference 258 * for 17tids, note each entry is of type ath12k_reo_queue_ref 259 * hence total size is 2048 * 17 * 8 = 278528 260 */ 261 #define DP_REOQ_LUT_SIZE 278528 262 263 /* Invalid TX Bank ID value */ 264 #define DP_INVALID_BANK_ID -1 265 266 struct ath12k_dp_tx_bank_profile { 267 u8 is_configured; 268 u32 num_users; 269 u32 bank_config; 270 }; 271 272 struct ath12k_hp_update_timer { 273 struct timer_list timer; 274 bool started; 275 bool init; 276 u32 tx_num; 277 u32 timer_tx_num; 278 u32 ring_id; 279 u32 interval; 280 struct ath12k_base *ab; 281 }; 282 283 struct ath12k_rx_desc_info { 284 struct list_head list; 285 struct sk_buff *skb; 286 u32 cookie; 287 u32 magic; 288 u8 in_use : 1, 289 reserved : 7; 290 }; 291 292 struct ath12k_tx_desc_info { 293 struct list_head list; 294 struct sk_buff *skb; 295 u32 desc_id; /* Cookie */ 296 u8 mac_id; 297 u8 pool_id; 298 }; 299 300 struct ath12k_spt_info { 301 dma_addr_t paddr; 302 u64 *vaddr; 303 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 304 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 305 }; 306 307 struct ath12k_reo_queue_ref { 308 u32 info0; 309 u32 info1; 310 } __packed; 311 312 struct ath12k_reo_q_addr_lut { 313 dma_addr_t paddr; 314 u32 *vaddr; 315 }; 316 317 struct ath12k_dp { 318 struct ath12k_base *ab; 319 u8 num_bank_profiles; 320 /* protects the access and update of bank_profiles */ 321 spinlock_t tx_bank_lock; 322 struct ath12k_dp_tx_bank_profile *bank_profiles; 323 enum ath12k_htc_ep_id eid; 324 struct completion htt_tgt_version_received; 325 u8 htt_tgt_ver_major; 326 u8 htt_tgt_ver_minor; 327 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 328 struct dp_srng wbm_idle_ring; 329 struct dp_srng wbm_desc_rel_ring; 330 struct dp_srng tcl_cmd_ring; 331 struct dp_srng tcl_status_ring; 332 struct dp_srng reo_reinject_ring; 333 struct dp_srng rx_rel_ring; 334 struct dp_srng reo_except_ring; 335 struct dp_srng reo_cmd_ring; 336 struct dp_srng reo_status_ring; 337 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 338 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 339 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 340 struct list_head reo_cmd_list; 341 struct list_head reo_cmd_cache_flush_list; 342 u32 reo_cmd_cache_flush_count; 343 344 /* protects access to below fields, 345 * - reo_cmd_list 346 * - reo_cmd_cache_flush_list 347 * - reo_cmd_cache_flush_count 348 */ 349 spinlock_t reo_cmd_lock; 350 struct ath12k_hp_update_timer reo_cmd_timer; 351 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 352 struct ath12k_spt_info *spt_info; 353 u32 num_spt_pages; 354 struct list_head rx_desc_free_list; 355 /* protects the free desc list */ 356 spinlock_t rx_desc_lock; 357 358 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 359 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 360 /* protects the free and used desc lists */ 361 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 362 363 struct dp_rxdma_ring rx_refill_buf_ring; 364 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 365 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 366 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 367 struct dp_rxdma_mon_ring tx_mon_buf_ring; 368 struct ath12k_reo_q_addr_lut reoq_lut; 369 }; 370 371 /* HTT definitions */ 372 373 #define HTT_TCL_META_DATA_TYPE BIT(0) 374 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 375 376 /* vdev meta data */ 377 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 378 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 379 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 380 381 /* peer meta data */ 382 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 383 384 /* HTT tx completion is overlaid in wbm_release_ring */ 385 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 386 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 387 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 388 389 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 390 391 struct htt_tx_wbm_completion { 392 __le32 rsvd0[2]; 393 __le32 info0; 394 __le32 info1; 395 __le32 info2; 396 __le32 info3; 397 __le32 info4; 398 __le32 rsvd1; 399 400 } __packed; 401 402 enum htt_h2t_msg_type { 403 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 404 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 405 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 406 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 407 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 408 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 409 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 410 }; 411 412 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 413 414 struct htt_ver_req_cmd { 415 __le32 ver_reg_info; 416 } __packed; 417 418 enum htt_srng_ring_type { 419 HTT_HW_TO_SW_RING, 420 HTT_SW_TO_HW_RING, 421 HTT_SW_TO_SW_RING, 422 }; 423 424 enum htt_srng_ring_id { 425 HTT_RXDMA_HOST_BUF_RING, 426 HTT_RXDMA_MONITOR_STATUS_RING, 427 HTT_RXDMA_MONITOR_BUF_RING, 428 HTT_RXDMA_MONITOR_DESC_RING, 429 HTT_RXDMA_MONITOR_DEST_RING, 430 HTT_HOST1_TO_FW_RXBUF_RING, 431 HTT_HOST2_TO_FW_RXBUF_RING, 432 HTT_RXDMA_NON_MONITOR_DEST_RING, 433 HTT_TX_MON_HOST2MON_BUF_RING, 434 HTT_TX_MON_MON2HOST_DEST_RING, 435 }; 436 437 /* host -> target HTT_SRING_SETUP message 438 * 439 * After target is booted up, Host can send SRING setup message for 440 * each host facing LMAC SRING. Target setups up HW registers based 441 * on setup message and confirms back to Host if response_required is set. 442 * Host should wait for confirmation message before sending new SRING 443 * setup message 444 * 445 * The message would appear as follows: 446 * 447 * |31 24|23 20|19|18 16|15|14 8|7 0| 448 * |--------------- +-----------------+----------------+------------------| 449 * | ring_type | ring_id | pdev_id | msg_type | 450 * |----------------------------------------------------------------------| 451 * | ring_base_addr_lo | 452 * |----------------------------------------------------------------------| 453 * | ring_base_addr_hi | 454 * |----------------------------------------------------------------------| 455 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 456 * |----------------------------------------------------------------------| 457 * | ring_head_offset32_remote_addr_lo | 458 * |----------------------------------------------------------------------| 459 * | ring_head_offset32_remote_addr_hi | 460 * |----------------------------------------------------------------------| 461 * | ring_tail_offset32_remote_addr_lo | 462 * |----------------------------------------------------------------------| 463 * | ring_tail_offset32_remote_addr_hi | 464 * |----------------------------------------------------------------------| 465 * | ring_msi_addr_lo | 466 * |----------------------------------------------------------------------| 467 * | ring_msi_addr_hi | 468 * |----------------------------------------------------------------------| 469 * | ring_msi_data | 470 * |----------------------------------------------------------------------| 471 * | intr_timer_th |IM| intr_batch_counter_th | 472 * |----------------------------------------------------------------------| 473 * | reserved |RR|PTCF| intr_low_threshold | 474 * |----------------------------------------------------------------------| 475 * Where 476 * IM = sw_intr_mode 477 * RR = response_required 478 * PTCF = prefetch_timer_cfg 479 * 480 * The message is interpreted as follows: 481 * dword0 - b'0:7 - msg_type: This will be set to 482 * HTT_H2T_MSG_TYPE_SRING_SETUP 483 * b'8:15 - pdev_id: 484 * 0 (for rings at SOC/UMAC level), 485 * 1/2/3 mac id (for rings at LMAC level) 486 * b'16:23 - ring_id: identify which ring is to setup, 487 * more details can be got from enum htt_srng_ring_id 488 * b'24:31 - ring_type: identify type of host rings, 489 * more details can be got from enum htt_srng_ring_type 490 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 491 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 492 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 493 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 494 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 495 * SW_TO_HW_RING. 496 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 497 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 498 * Lower 32 bits of memory address of the remote variable 499 * storing the 4-byte word offset that identifies the head 500 * element within the ring. 501 * (The head offset variable has type u32.) 502 * Valid for HW_TO_SW and SW_TO_SW rings. 503 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 504 * Upper 32 bits of memory address of the remote variable 505 * storing the 4-byte word offset that identifies the head 506 * element within the ring. 507 * (The head offset variable has type u32.) 508 * Valid for HW_TO_SW and SW_TO_SW rings. 509 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 510 * Lower 32 bits of memory address of the remote variable 511 * storing the 4-byte word offset that identifies the tail 512 * element within the ring. 513 * (The tail offset variable has type u32.) 514 * Valid for HW_TO_SW and SW_TO_SW rings. 515 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 516 * Upper 32 bits of memory address of the remote variable 517 * storing the 4-byte word offset that identifies the tail 518 * element within the ring. 519 * (The tail offset variable has type u32.) 520 * Valid for HW_TO_SW and SW_TO_SW rings. 521 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 522 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 523 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 524 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 525 * dword10 - b'0:31 - ring_msi_data: MSI data 526 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 527 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 528 * dword11 - b'0:14 - intr_batch_counter_th: 529 * batch counter threshold is in units of 4-byte words. 530 * HW internally maintains and increments batch count. 531 * (see SRING spec for detail description). 532 * When batch count reaches threshold value, an interrupt 533 * is generated by HW. 534 * b'15 - sw_intr_mode: 535 * This configuration shall be static. 536 * Only programmed at power up. 537 * 0: generate pulse style sw interrupts 538 * 1: generate level style sw interrupts 539 * b'16:31 - intr_timer_th: 540 * The timer init value when timer is idle or is 541 * initialized to start downcounting. 542 * In 8us units (to cover a range of 0 to 524 ms) 543 * dword12 - b'0:15 - intr_low_threshold: 544 * Used only by Consumer ring to generate ring_sw_int_p. 545 * Ring entries low threshold water mark, that is used 546 * in combination with the interrupt timer as well as 547 * the clearing of the level interrupt. 548 * b'16:18 - prefetch_timer_cfg: 549 * Used only by Consumer ring to set timer mode to 550 * support Application prefetch handling. 551 * The external tail offset/pointer will be updated 552 * at following intervals: 553 * 3'b000: (Prefetch feature disabled; used only for debug) 554 * 3'b001: 1 usec 555 * 3'b010: 4 usec 556 * 3'b011: 8 usec (default) 557 * 3'b100: 16 usec 558 * Others: Reserved 559 * b'19 - response_required: 560 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 561 * b'20:31 - reserved: reserved for future use 562 */ 563 564 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 565 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 566 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 567 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 568 569 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 570 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 571 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 572 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 573 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 574 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 575 576 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 577 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 578 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 579 580 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 581 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 582 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 583 584 struct htt_srng_setup_cmd { 585 __le32 info0; 586 __le32 ring_base_addr_lo; 587 __le32 ring_base_addr_hi; 588 __le32 info1; 589 __le32 ring_head_off32_remote_addr_lo; 590 __le32 ring_head_off32_remote_addr_hi; 591 __le32 ring_tail_off32_remote_addr_lo; 592 __le32 ring_tail_off32_remote_addr_hi; 593 __le32 ring_msi_addr_lo; 594 __le32 ring_msi_addr_hi; 595 __le32 msi_data; 596 __le32 intr_info; 597 __le32 info2; 598 } __packed; 599 600 /* host -> target FW PPDU_STATS config message 601 * 602 * @details 603 * The following field definitions describe the format of the HTT host 604 * to target FW for PPDU_STATS_CFG msg. 605 * The message allows the host to configure the PPDU_STATS_IND messages 606 * produced by the target. 607 * 608 * |31 24|23 16|15 8|7 0| 609 * |-----------------------------------------------------------| 610 * | REQ bit mask | pdev_mask | msg type | 611 * |-----------------------------------------------------------| 612 * Header fields: 613 * - MSG_TYPE 614 * Bits 7:0 615 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 616 * Value: 0x11 617 * - PDEV_MASK 618 * Bits 8:15 619 * Purpose: identifies which pdevs this PPDU stats configuration applies to 620 * Value: This is a overloaded field, refer to usage and interpretation of 621 * PDEV in interface document. 622 * Bit 8 : Reserved for SOC stats 623 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 624 * Indicates MACID_MASK in DBS 625 * - REQ_TLV_BIT_MASK 626 * Bits 16:31 627 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 628 * needs to be included in the target's PPDU_STATS_IND messages. 629 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 630 * 631 */ 632 633 struct htt_ppdu_stats_cfg_cmd { 634 __le32 msg; 635 } __packed; 636 637 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 638 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 639 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 640 641 enum htt_ppdu_stats_tag_type { 642 HTT_PPDU_STATS_TAG_COMMON, 643 HTT_PPDU_STATS_TAG_USR_COMMON, 644 HTT_PPDU_STATS_TAG_USR_RATE, 645 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 646 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 647 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 648 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 649 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 650 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 651 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 652 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 653 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 654 HTT_PPDU_STATS_TAG_INFO, 655 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 656 657 /* New TLV's are added above to this line */ 658 HTT_PPDU_STATS_TAG_MAX, 659 }; 660 661 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 662 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 663 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 664 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 665 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 666 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 667 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 668 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 669 670 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 671 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 672 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 673 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 674 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 675 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 676 HTT_PPDU_STATS_TAG_DEFAULT) 677 678 enum htt_stats_internal_ppdu_frametype { 679 HTT_STATS_PPDU_FTYPE_CTRL, 680 HTT_STATS_PPDU_FTYPE_DATA, 681 HTT_STATS_PPDU_FTYPE_BAR, 682 HTT_STATS_PPDU_FTYPE_MAX 683 }; 684 685 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 686 * 687 * details: 688 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 689 * configure RXDMA rings. 690 * The configuration is per ring based and includes both packet subtypes 691 * and PPDU/MPDU TLVs. 692 * 693 * The message would appear as follows: 694 * 695 * |31 26|25|24|23 16|15 8|7 0| 696 * |-----------------+----------------+----------------+---------------| 697 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 698 * |-------------------------------------------------------------------| 699 * | rsvd2 | ring_buffer_size | 700 * |-------------------------------------------------------------------| 701 * | packet_type_enable_flags_0 | 702 * |-------------------------------------------------------------------| 703 * | packet_type_enable_flags_1 | 704 * |-------------------------------------------------------------------| 705 * | packet_type_enable_flags_2 | 706 * |-------------------------------------------------------------------| 707 * | packet_type_enable_flags_3 | 708 * |-------------------------------------------------------------------| 709 * | tlv_filter_in_flags | 710 * |-------------------------------------------------------------------| 711 * Where: 712 * PS = pkt_swap 713 * SS = status_swap 714 * The message is interpreted as follows: 715 * dword0 - b'0:7 - msg_type: This will be set to 716 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 717 * b'8:15 - pdev_id: 718 * 0 (for rings at SOC/UMAC level), 719 * 1/2/3 mac id (for rings at LMAC level) 720 * b'16:23 - ring_id : Identify the ring to configure. 721 * More details can be got from enum htt_srng_ring_id 722 * b'24 - status_swap: 1 is to swap status TLV 723 * b'25 - pkt_swap: 1 is to swap packet TLV 724 * b'26:31 - rsvd1: reserved for future use 725 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 726 * in byte units. 727 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 728 * - b'16:31 - rsvd2: Reserved for future use 729 * dword2 - b'0:31 - packet_type_enable_flags_0: 730 * Enable MGMT packet from 0b0000 to 0b1001 731 * bits from low to high: FP, MD, MO - 3 bits 732 * FP: Filter_Pass 733 * MD: Monitor_Direct 734 * MO: Monitor_Other 735 * 10 mgmt subtypes * 3 bits -> 30 bits 736 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 737 * dword3 - b'0:31 - packet_type_enable_flags_1: 738 * Enable MGMT packet from 0b1010 to 0b1111 739 * bits from low to high: FP, MD, MO - 3 bits 740 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 741 * dword4 - b'0:31 - packet_type_enable_flags_2: 742 * Enable CTRL packet from 0b0000 to 0b1001 743 * bits from low to high: FP, MD, MO - 3 bits 744 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 745 * dword5 - b'0:31 - packet_type_enable_flags_3: 746 * Enable CTRL packet from 0b1010 to 0b1111, 747 * MCAST_DATA, UCAST_DATA, NULL_DATA 748 * bits from low to high: FP, MD, MO - 3 bits 749 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 750 * dword6 - b'0:31 - tlv_filter_in_flags: 751 * Filter in Attention/MPDU/PPDU/Header/User tlvs 752 * Refer to CFG_TLV_FILTER_IN_FLAG defs 753 */ 754 755 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 756 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 757 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 758 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 759 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 760 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 761 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26) 762 763 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 764 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 765 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 766 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 767 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 768 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 769 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 770 771 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23) 772 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) 773 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) 774 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) 775 776 enum htt_rx_filter_tlv_flags { 777 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 778 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 779 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 780 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 781 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 782 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 783 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 784 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 785 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 786 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 787 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 788 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 789 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 790 }; 791 792 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 793 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 794 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 795 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 796 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 797 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 798 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 799 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 800 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 801 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 802 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 803 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 804 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 805 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 806 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 807 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 808 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 809 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 810 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 811 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 812 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 813 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 814 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 815 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 816 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 817 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 818 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 819 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 820 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 821 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 822 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 823 }; 824 825 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 826 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 827 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 828 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 829 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 830 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 831 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 832 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 833 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 834 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 835 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 836 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 837 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 838 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 839 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 840 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 841 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 842 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 843 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 844 }; 845 846 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 847 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 848 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 849 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 850 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 851 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 852 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 853 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 854 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 855 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 856 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 857 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 858 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 859 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 860 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 861 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 862 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 863 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 864 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 865 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 866 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 867 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 868 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 869 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 870 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 871 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 872 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 873 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 874 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 875 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 876 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 877 }; 878 879 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 880 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 881 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 882 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 883 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 884 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 885 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 886 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 887 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 888 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 889 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 890 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 891 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 892 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 893 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 894 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 895 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 896 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 897 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 898 }; 899 900 enum htt_rx_data_pkt_filter_tlv_flasg3 { 901 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 902 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 903 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 904 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 905 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 906 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 907 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 908 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 909 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 910 }; 911 912 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 913 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 914 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 915 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 916 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 917 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 918 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 919 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 920 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 921 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 922 923 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 924 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 925 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 926 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 927 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 928 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 929 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 930 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 931 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 932 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 933 934 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 935 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 936 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 937 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 938 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 939 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 940 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 941 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 942 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 943 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 944 945 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 946 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 947 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 948 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 949 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 950 951 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 952 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 953 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 954 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 955 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 956 957 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 958 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 959 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 960 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 961 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 962 963 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 964 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 965 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 966 967 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 968 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 969 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 970 971 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 972 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 973 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 974 975 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 976 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 977 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 978 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 979 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 980 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 981 982 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 983 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 984 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 985 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 986 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 987 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 988 989 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 990 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 991 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 992 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 993 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 994 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 995 996 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 997 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 998 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 999 1000 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1001 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1002 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1003 1004 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1005 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1006 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1007 1008 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1009 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1010 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1011 1012 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1013 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1014 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1015 1016 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1017 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1018 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1019 1020 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1021 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1022 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1023 1024 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1025 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1026 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1027 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1028 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1029 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1030 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1031 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1032 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1033 1034 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1035 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1036 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1037 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1038 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1039 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1040 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1041 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1042 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1043 1044 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1045 1046 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1047 1048 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1049 1050 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1051 1052 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1053 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1054 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1055 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1056 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1057 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1058 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1059 1060 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1061 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1062 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1063 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1064 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1065 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1066 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1067 1068 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1069 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1070 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1071 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1072 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1073 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1074 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1075 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1076 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1077 1078 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1079 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1080 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1081 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1082 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1083 1084 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1085 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1086 1087 struct htt_rx_ring_selection_cfg_cmd { 1088 __le32 info0; 1089 __le32 info1; 1090 __le32 pkt_type_en_flags0; 1091 __le32 pkt_type_en_flags1; 1092 __le32 pkt_type_en_flags2; 1093 __le32 pkt_type_en_flags3; 1094 __le32 rx_filter_tlv; 1095 __le32 rx_packet_offset; 1096 __le32 rx_mpdu_offset; 1097 __le32 rx_msdu_offset; 1098 __le32 rx_attn_offset; 1099 __le32 info2; 1100 __le32 reserved[2]; 1101 __le32 rx_mpdu_start_end_mask; 1102 __le32 rx_msdu_end_word_mask; 1103 __le32 info3; 1104 } __packed; 1105 1106 struct htt_rx_ring_tlv_filter { 1107 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1108 u32 pkt_filter_flags0; /* MGMT */ 1109 u32 pkt_filter_flags1; /* MGMT */ 1110 u32 pkt_filter_flags2; /* CTRL */ 1111 u32 pkt_filter_flags3; /* DATA */ 1112 bool offset_valid; 1113 u16 rx_packet_offset; 1114 u16 rx_header_offset; 1115 u16 rx_mpdu_end_offset; 1116 u16 rx_mpdu_start_offset; 1117 u16 rx_msdu_end_offset; 1118 u16 rx_msdu_start_offset; 1119 u16 rx_attn_offset; 1120 u16 rx_mpdu_start_wmask; 1121 u16 rx_mpdu_end_wmask; 1122 u32 rx_msdu_end_wmask; 1123 }; 1124 1125 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1126 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1127 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1128 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1129 1130 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1131 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1132 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1133 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1134 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1135 1136 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1137 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1138 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1139 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1140 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1141 1142 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1143 1144 struct htt_tx_ring_selection_cfg_cmd { 1145 __le32 info0; 1146 __le32 info1; 1147 __le32 info2; 1148 __le32 tlv_filter_mask_in0; 1149 __le32 tlv_filter_mask_in1; 1150 __le32 tlv_filter_mask_in2; 1151 __le32 tlv_filter_mask_in3; 1152 __le32 reserved[3]; 1153 } __packed; 1154 1155 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1156 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1157 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1158 1159 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1160 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1161 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1162 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1163 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1164 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1165 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1166 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1167 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1168 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1169 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1170 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1171 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1172 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1173 1174 struct htt_tx_ring_tlv_filter { 1175 u32 tx_mon_downstream_tlv_flags; 1176 u32 tx_mon_upstream_tlv_flags0; 1177 u32 tx_mon_upstream_tlv_flags1; 1178 u32 tx_mon_upstream_tlv_flags2; 1179 bool tx_mon_mgmt_filter; 1180 bool tx_mon_data_filter; 1181 bool tx_mon_ctrl_filter; 1182 u16 tx_mon_pkt_dma_len; 1183 } __packed; 1184 1185 enum htt_tx_mon_upstream_tlv_flags0 { 1186 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1187 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1188 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1189 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1190 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1191 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1192 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1193 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1194 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1195 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1196 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1197 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1198 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1199 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1200 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1201 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1202 }; 1203 1204 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1205 1206 /* HTT message target->host */ 1207 1208 enum htt_t2h_msg_type { 1209 HTT_T2H_MSG_TYPE_VERSION_CONF, 1210 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1211 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1212 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1213 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1214 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1215 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1216 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1217 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1218 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1219 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1220 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1221 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1222 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1223 }; 1224 1225 #define HTT_TARGET_VERSION_MAJOR 3 1226 1227 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1228 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1229 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1230 1231 struct htt_t2h_version_conf_msg { 1232 __le32 version; 1233 } __packed; 1234 1235 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1236 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1237 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1238 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1239 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1240 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1241 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1242 1243 struct htt_t2h_peer_map_event { 1244 __le32 info; 1245 __le32 mac_addr_l32; 1246 __le32 info1; 1247 __le32 info2; 1248 } __packed; 1249 1250 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1251 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1252 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1253 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1254 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1255 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1256 1257 struct htt_t2h_peer_unmap_event { 1258 __le32 info; 1259 __le32 mac_addr_l32; 1260 __le32 info1; 1261 } __packed; 1262 1263 struct htt_resp_msg { 1264 union { 1265 struct htt_t2h_version_conf_msg version_msg; 1266 struct htt_t2h_peer_map_event peer_map_ev; 1267 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1268 }; 1269 } __packed; 1270 1271 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1272 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1273 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1274 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1275 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1276 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1277 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1278 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1279 1280 struct htt_t2h_vdev_txrx_stats_ind { 1281 __le32 vdev_id; 1282 __le32 rx_msdu_byte_cnt_lo; 1283 __le32 rx_msdu_byte_cnt_hi; 1284 __le32 rx_msdu_cnt_lo; 1285 __le32 rx_msdu_cnt_hi; 1286 __le32 tx_msdu_byte_cnt_lo; 1287 __le32 tx_msdu_byte_cnt_hi; 1288 __le32 tx_msdu_cnt_lo; 1289 __le32 tx_msdu_cnt_hi; 1290 __le32 tx_retry_cnt_lo; 1291 __le32 tx_retry_cnt_hi; 1292 __le32 tx_retry_byte_cnt_lo; 1293 __le32 tx_retry_byte_cnt_hi; 1294 __le32 tx_drop_cnt_lo; 1295 __le32 tx_drop_cnt_hi; 1296 __le32 tx_drop_byte_cnt_lo; 1297 __le32 tx_drop_byte_cnt_hi; 1298 __le32 msdu_ttl_cnt_lo; 1299 __le32 msdu_ttl_cnt_hi; 1300 __le32 msdu_ttl_byte_cnt_lo; 1301 __le32 msdu_ttl_byte_cnt_hi; 1302 } __packed; 1303 1304 struct htt_t2h_vdev_common_stats_tlv { 1305 __le32 soc_drop_count_lo; 1306 __le32 soc_drop_count_hi; 1307 } __packed; 1308 1309 /* ppdu stats 1310 * 1311 * @details 1312 * The following field definitions describe the format of the HTT target 1313 * to host ppdu stats indication message. 1314 * 1315 * 1316 * |31 16|15 12|11 10|9 8|7 0 | 1317 * |----------------------------------------------------------------------| 1318 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1319 * |----------------------------------------------------------------------| 1320 * | ppdu_id | 1321 * |----------------------------------------------------------------------| 1322 * | Timestamp in us | 1323 * |----------------------------------------------------------------------| 1324 * | reserved | 1325 * |----------------------------------------------------------------------| 1326 * | type-specific stats info | 1327 * | (see htt_ppdu_stats.h) | 1328 * |----------------------------------------------------------------------| 1329 * Header fields: 1330 * - MSG_TYPE 1331 * Bits 7:0 1332 * Purpose: Identifies this is a PPDU STATS indication 1333 * message. 1334 * Value: 0x1d 1335 * - mac_id 1336 * Bits 9:8 1337 * Purpose: mac_id of this ppdu_id 1338 * Value: 0-3 1339 * - pdev_id 1340 * Bits 11:10 1341 * Purpose: pdev_id of this ppdu_id 1342 * Value: 0-3 1343 * 0 (for rings at SOC level), 1344 * 1/2/3 PDEV -> 0/1/2 1345 * - payload_size 1346 * Bits 31:16 1347 * Purpose: total tlv size 1348 * Value: payload_size in bytes 1349 */ 1350 1351 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1352 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1353 1354 struct ath12k_htt_ppdu_stats_msg { 1355 __le32 info; 1356 __le32 ppdu_id; 1357 __le32 timestamp; 1358 __le32 rsvd; 1359 u8 data[]; 1360 } __packed; 1361 1362 struct htt_tlv { 1363 __le32 header; 1364 u8 value[]; 1365 } __packed; 1366 1367 #define HTT_TLV_TAG GENMASK(11, 0) 1368 #define HTT_TLV_LEN GENMASK(23, 12) 1369 1370 enum HTT_PPDU_STATS_BW { 1371 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1372 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1373 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1374 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1375 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1376 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1377 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1378 }; 1379 1380 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1381 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1382 /* bw - HTT_PPDU_STATS_BW */ 1383 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1384 1385 struct htt_ppdu_stats_common { 1386 __le32 ppdu_id; 1387 __le16 sched_cmdid; 1388 u8 ring_id; 1389 u8 num_users; 1390 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1391 __le32 chain_mask; 1392 __le32 fes_duration_us; /* frame exchange sequence */ 1393 __le32 ppdu_sch_eval_start_tstmp_us; 1394 __le32 ppdu_sch_end_tstmp_us; 1395 __le32 ppdu_start_tstmp_us; 1396 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1397 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1398 */ 1399 __le16 phy_mode; 1400 __le16 bw_mhz; 1401 } __packed; 1402 1403 enum htt_ppdu_stats_gi { 1404 HTT_PPDU_STATS_SGI_0_8_US, 1405 HTT_PPDU_STATS_SGI_0_4_US, 1406 HTT_PPDU_STATS_SGI_1_6_US, 1407 HTT_PPDU_STATS_SGI_3_2_US, 1408 }; 1409 1410 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1411 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1412 1413 enum HTT_PPDU_STATS_PPDU_TYPE { 1414 HTT_PPDU_STATS_PPDU_TYPE_SU, 1415 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1416 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1417 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1418 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1419 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1420 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1421 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1422 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1423 HTT_PPDU_STATS_PPDU_TYPE_MAX 1424 }; 1425 1426 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1427 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1428 1429 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1430 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1431 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1432 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1433 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1434 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1435 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1436 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1437 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1438 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1439 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1440 1441 #define HTT_USR_RATE_PREAMBLE(_val) \ 1442 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1443 #define HTT_USR_RATE_BW(_val) \ 1444 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1445 #define HTT_USR_RATE_NSS(_val) \ 1446 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1447 #define HTT_USR_RATE_MCS(_val) \ 1448 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1449 #define HTT_USR_RATE_GI(_val) \ 1450 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1451 #define HTT_USR_RATE_DCM(_val) \ 1452 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1453 1454 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1455 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1456 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1457 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1458 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1459 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1460 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1461 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1462 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1463 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1464 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1465 1466 struct htt_ppdu_stats_user_rate { 1467 u8 tid_num; 1468 u8 reserved0; 1469 __le16 sw_peer_id; 1470 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1471 __le16 ru_end; 1472 __le16 ru_start; 1473 __le16 resp_ru_end; 1474 __le16 resp_ru_start; 1475 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1476 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1477 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1478 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1479 } __packed; 1480 1481 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1482 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1483 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1484 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1485 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1486 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1487 1488 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1489 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1490 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1491 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1492 #define HTT_TX_INFO_RATECODE(_flags) \ 1493 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1494 #define HTT_TX_INFO_PEERID(_flags) \ 1495 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1496 1497 struct htt_tx_ppdu_stats_info { 1498 struct htt_tlv tlv_hdr; 1499 __le32 tx_success_bytes; 1500 __le32 tx_retry_bytes; 1501 __le32 tx_failed_bytes; 1502 __le32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1503 __le16 tx_success_msdus; 1504 __le16 tx_retry_msdus; 1505 __le16 tx_failed_msdus; 1506 __le16 tx_duration; /* united in us */ 1507 } __packed; 1508 1509 enum htt_ppdu_stats_usr_compln_status { 1510 HTT_PPDU_STATS_USER_STATUS_OK, 1511 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1512 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1513 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1514 HTT_PPDU_STATS_USER_STATUS_ABORT, 1515 }; 1516 1517 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1518 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1519 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1520 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1521 1522 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1523 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1524 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1525 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1526 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1527 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1528 1529 struct htt_ppdu_stats_usr_cmpltn_cmn { 1530 u8 status; 1531 u8 tid_num; 1532 __le16 sw_peer_id; 1533 /* RSSI value of last ack packet (units = dB above noise floor) */ 1534 __le32 ack_rssi; 1535 __le16 mpdu_tried; 1536 __le16 mpdu_success; 1537 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1538 } __packed; 1539 1540 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1541 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1542 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1543 1544 #define HTT_PPDU_STATS_NON_QOS_TID 16 1545 1546 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1547 __le32 ppdu_id; 1548 __le16 sw_peer_id; 1549 __le16 reserved0; 1550 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1551 __le16 current_seq; 1552 __le16 start_seq; 1553 __le32 success_bytes; 1554 } __packed; 1555 1556 struct htt_ppdu_user_stats { 1557 u16 peer_id; 1558 u16 delay_ba; 1559 u32 tlv_flags; 1560 bool is_valid_peer_id; 1561 struct htt_ppdu_stats_user_rate rate; 1562 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1563 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1564 }; 1565 1566 #define HTT_PPDU_STATS_MAX_USERS 8 1567 #define HTT_PPDU_DESC_MAX_DEPTH 16 1568 1569 struct htt_ppdu_stats { 1570 struct htt_ppdu_stats_common common; 1571 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1572 }; 1573 1574 struct htt_ppdu_stats_info { 1575 u32 tlv_bitmap; 1576 u32 ppdu_id; 1577 u32 frame_type; 1578 u32 frame_ctrl; 1579 u32 delay_ba; 1580 u32 bar_num_users; 1581 struct htt_ppdu_stats ppdu_stats; 1582 struct list_head list; 1583 }; 1584 1585 /* @brief target -> host MLO offset indiciation message 1586 * 1587 * @details 1588 * The following field definitions describe the format of the HTT target 1589 * to host mlo offset indication message. 1590 * 1591 * 1592 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1593 * |---------------------------------------------------------------------| 1594 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1595 * |---------------------------------------------------------------------| 1596 * | sync_timestamp_lo_us | 1597 * |---------------------------------------------------------------------| 1598 * | sync_timestamp_hi_us | 1599 * |---------------------------------------------------------------------| 1600 * | mlo_offset_lo | 1601 * |---------------------------------------------------------------------| 1602 * | mlo_offset_hi | 1603 * |---------------------------------------------------------------------| 1604 * | mlo_offset_clcks | 1605 * |---------------------------------------------------------------------| 1606 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1607 * |---------------------------------------------------------------------| 1608 * | rsvd3 |mlo_comp_timer | 1609 * |---------------------------------------------------------------------| 1610 * Header fields 1611 * - MSG_TYPE 1612 * Bits 7:0 1613 * Purpose: Identifies this is a MLO offset indication msg 1614 * - PDEV_ID 1615 * Bits 9:8 1616 * Purpose: Pdev of this MLO offset 1617 * - CHIP_ID 1618 * Bits 12:10 1619 * Purpose: chip_id of this MLO offset 1620 * - MAC_FREQ 1621 * Bits 28:13 1622 * - SYNC_TIMESTAMP_LO_US 1623 * Purpose: clock frequency of the mac HW block in MHz 1624 * Bits: 31:0 1625 * Purpose: lower 32 bits of the WLAN global time stamp at which 1626 * last sync interrupt was received 1627 * - SYNC_TIMESTAMP_HI_US 1628 * Bits: 31:0 1629 * Purpose: upper 32 bits of WLAN global time stamp at which 1630 * last sync interrupt was received 1631 * - MLO_OFFSET_LO 1632 * Bits: 31:0 1633 * Purpose: lower 32 bits of the MLO offset in us 1634 * - MLO_OFFSET_HI 1635 * Bits: 31:0 1636 * Purpose: upper 32 bits of the MLO offset in us 1637 * - MLO_COMP_US 1638 * Bits: 15:0 1639 * Purpose: MLO time stamp compensation applied in us 1640 * - MLO_COMP_CLCKS 1641 * Bits: 25:16 1642 * Purpose: MLO time stamp compensation applied in clock ticks 1643 * - MLO_COMP_TIMER 1644 * Bits: 21:0 1645 * Purpose: Periodic timer at which compensation is applied 1646 */ 1647 1648 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1649 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1650 1651 struct ath12k_htt_mlo_offset_msg { 1652 __le32 info; 1653 __le32 sync_timestamp_lo_us; 1654 __le32 sync_timestamp_hi_us; 1655 __le32 mlo_offset_hi; 1656 __le32 mlo_offset_lo; 1657 __le32 mlo_offset_clks; 1658 __le32 mlo_comp_clks; 1659 __le32 mlo_comp_timer; 1660 } __packed; 1661 1662 /* @brief host -> target FW extended statistics retrieve 1663 * 1664 * @details 1665 * The following field definitions describe the format of the HTT host 1666 * to target FW extended stats retrieve message. 1667 * The message specifies the type of stats the host wants to retrieve. 1668 * 1669 * |31 24|23 16|15 8|7 0| 1670 * |-----------------------------------------------------------| 1671 * | reserved | stats type | pdev_mask | msg type | 1672 * |-----------------------------------------------------------| 1673 * | config param [0] | 1674 * |-----------------------------------------------------------| 1675 * | config param [1] | 1676 * |-----------------------------------------------------------| 1677 * | config param [2] | 1678 * |-----------------------------------------------------------| 1679 * | config param [3] | 1680 * |-----------------------------------------------------------| 1681 * | reserved | 1682 * |-----------------------------------------------------------| 1683 * | cookie LSBs | 1684 * |-----------------------------------------------------------| 1685 * | cookie MSBs | 1686 * |-----------------------------------------------------------| 1687 * Header fields: 1688 * - MSG_TYPE 1689 * Bits 7:0 1690 * Purpose: identifies this is a extended stats upload request message 1691 * Value: 0x10 1692 * - PDEV_MASK 1693 * Bits 8:15 1694 * Purpose: identifies the mask of PDEVs to retrieve stats from 1695 * Value: This is a overloaded field, refer to usage and interpretation of 1696 * PDEV in interface document. 1697 * Bit 8 : Reserved for SOC stats 1698 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1699 * Indicates MACID_MASK in DBS 1700 * - STATS_TYPE 1701 * Bits 23:16 1702 * Purpose: identifies which FW statistics to upload 1703 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1704 * - Reserved 1705 * Bits 31:24 1706 * - CONFIG_PARAM [0] 1707 * Bits 31:0 1708 * Purpose: give an opaque configuration value to the specified stats type 1709 * Value: stats-type specific configuration value 1710 * Refer to htt_stats.h for interpretation for each stats sub_type 1711 * - CONFIG_PARAM [1] 1712 * Bits 31:0 1713 * Purpose: give an opaque configuration value to the specified stats type 1714 * Value: stats-type specific configuration value 1715 * Refer to htt_stats.h for interpretation for each stats sub_type 1716 * - CONFIG_PARAM [2] 1717 * Bits 31:0 1718 * Purpose: give an opaque configuration value to the specified stats type 1719 * Value: stats-type specific configuration value 1720 * Refer to htt_stats.h for interpretation for each stats sub_type 1721 * - CONFIG_PARAM [3] 1722 * Bits 31:0 1723 * Purpose: give an opaque configuration value to the specified stats type 1724 * Value: stats-type specific configuration value 1725 * Refer to htt_stats.h for interpretation for each stats sub_type 1726 * - Reserved [31:0] for future use. 1727 * - COOKIE_LSBS 1728 * Bits 31:0 1729 * Purpose: Provide a mechanism to match a target->host stats confirmation 1730 * message with its preceding host->target stats request message. 1731 * Value: LSBs of the opaque cookie specified by the host-side requestor 1732 * - COOKIE_MSBS 1733 * Bits 31:0 1734 * Purpose: Provide a mechanism to match a target->host stats confirmation 1735 * message with its preceding host->target stats request message. 1736 * Value: MSBs of the opaque cookie specified by the host-side requestor 1737 */ 1738 1739 struct htt_ext_stats_cfg_hdr { 1740 u8 msg_type; 1741 u8 pdev_mask; 1742 u8 stats_type; 1743 u8 reserved; 1744 } __packed; 1745 1746 struct htt_ext_stats_cfg_cmd { 1747 struct htt_ext_stats_cfg_hdr hdr; 1748 __le32 cfg_param0; 1749 __le32 cfg_param1; 1750 __le32 cfg_param2; 1751 __le32 cfg_param3; 1752 __le32 reserved; 1753 __le32 cookie_lsb; 1754 __le32 cookie_msb; 1755 } __packed; 1756 1757 /* htt stats config default params */ 1758 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1759 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1760 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1761 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1762 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1763 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1764 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1765 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1766 1767 /* HTT_DBG_EXT_STATS_PEER_INFO 1768 * PARAMS: 1769 * @config_param0: 1770 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1771 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1772 * [Bit31 : Bit16] sw_peer_id 1773 * @config_param1: 1774 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1775 * 0 bit htt_peer_stats_cmn_tlv 1776 * 1 bit htt_peer_details_tlv 1777 * 2 bit htt_tx_peer_rate_stats_tlv 1778 * 3 bit htt_rx_peer_rate_stats_tlv 1779 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1780 * 5 bit htt_rx_tid_stats_tlv 1781 * 6 bit htt_msdu_flow_stats_tlv 1782 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1783 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1784 * [Bit31 : Bit16] reserved 1785 */ 1786 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1787 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1788 1789 /* Used to set different configs to the specified stats type.*/ 1790 struct htt_ext_stats_cfg_params { 1791 u32 cfg0; 1792 u32 cfg1; 1793 u32 cfg2; 1794 u32 cfg3; 1795 }; 1796 1797 enum vdev_stats_offload_timer_duration { 1798 ATH12K_STATS_TIMER_DUR_500MS = 1, 1799 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1800 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1801 }; 1802 1803 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1804 { 1805 memcpy(addr, &addr_l32, 4); 1806 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1807 } 1808 1809 int ath12k_dp_service_srng(struct ath12k_base *ab, 1810 struct ath12k_ext_irq_grp *irq_grp, 1811 int budget); 1812 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1813 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif); 1814 void ath12k_dp_free(struct ath12k_base *ab); 1815 int ath12k_dp_alloc(struct ath12k_base *ab); 1816 void ath12k_dp_cc_config(struct ath12k_base *ab); 1817 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1818 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab); 1819 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1820 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1821 int mac_id, enum hal_ring_type ring_type); 1822 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1823 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1824 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1825 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1826 enum hal_ring_type type, int ring_num, 1827 int mac_id, int num_entries); 1828 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1829 struct dp_link_desc_bank *desc_bank, 1830 u32 ring_type, struct dp_srng *ring); 1831 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1832 struct dp_link_desc_bank *link_desc_banks, 1833 u32 ring_type, struct hal_srng *srng, 1834 u32 n_link_desc); 1835 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1836 u32 cookie); 1837 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1838 u32 desc_id); 1839 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab); 1840 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab); 1841 #endif 1842