1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <crypto/hash.h> 8 #include "core.h" 9 #include "dp_tx.h" 10 #include "hal_tx.h" 11 #include "hif.h" 12 #include "debug.h" 13 #include "dp_rx.h" 14 #include "peer.h" 15 #include "dp_mon.h" 16 17 enum ath12k_dp_desc_type { 18 ATH12K_DP_TX_DESC, 19 ATH12K_DP_RX_DESC, 20 }; 21 22 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab, 23 struct sk_buff *skb) 24 { 25 dev_kfree_skb_any(skb); 26 } 27 28 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr) 29 { 30 struct ath12k_base *ab = ar->ab; 31 struct ath12k_peer *peer; 32 33 /* TODO: Any other peer specific DP cleanup */ 34 35 spin_lock_bh(&ab->base_lock); 36 peer = ath12k_peer_find(ab, vdev_id, addr); 37 if (!peer) { 38 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n", 39 addr, vdev_id); 40 spin_unlock_bh(&ab->base_lock); 41 return; 42 } 43 44 if (!peer->primary_link) { 45 spin_unlock_bh(&ab->base_lock); 46 return; 47 } 48 49 ath12k_dp_rx_peer_tid_cleanup(ar, peer); 50 crypto_free_shash(peer->tfm_mmic); 51 peer->dp_setup_done = false; 52 spin_unlock_bh(&ab->base_lock); 53 } 54 55 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr) 56 { 57 struct ath12k_base *ab = ar->ab; 58 struct ath12k_peer *peer; 59 u32 reo_dest; 60 int ret = 0, tid; 61 62 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */ 63 reo_dest = ar->dp.mac_id + 1; 64 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id, 65 WMI_PEER_SET_DEFAULT_ROUTING, 66 DP_RX_HASH_ENABLE | (reo_dest << 1)); 67 68 if (ret) { 69 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n", 70 ret, addr, vdev_id); 71 return ret; 72 } 73 74 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 75 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0, 76 HAL_PN_TYPE_NONE); 77 if (ret) { 78 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n", 79 tid, ret); 80 goto peer_clean; 81 } 82 } 83 84 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id); 85 if (ret) { 86 ath12k_warn(ab, "failed to setup rx defrag context\n"); 87 goto peer_clean; 88 } 89 90 /* TODO: Setup other peer specific resource used in data path */ 91 92 return 0; 93 94 peer_clean: 95 spin_lock_bh(&ab->base_lock); 96 97 peer = ath12k_peer_find(ab, vdev_id, addr); 98 if (!peer) { 99 ath12k_warn(ab, "failed to find the peer to del rx tid\n"); 100 spin_unlock_bh(&ab->base_lock); 101 return -ENOENT; 102 } 103 104 for (; tid >= 0; tid--) 105 ath12k_dp_rx_peer_tid_delete(ar, peer, tid); 106 107 spin_unlock_bh(&ab->base_lock); 108 109 return ret; 110 } 111 112 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring) 113 { 114 if (!ring->vaddr_unaligned) 115 return; 116 117 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned, 118 ring->paddr_unaligned); 119 120 ring->vaddr_unaligned = NULL; 121 } 122 123 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask) 124 { 125 int ext_group_num; 126 u8 mask = 1 << ring_num; 127 128 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX; 129 ext_group_num++) { 130 if (mask & grp_mask[ext_group_num]) 131 return ext_group_num; 132 } 133 134 return -ENOENT; 135 } 136 137 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab, 138 enum hal_ring_type type, int ring_num) 139 { 140 const struct ath12k_hal_tcl_to_wbm_rbm_map *map; 141 const u8 *grp_mask; 142 int i; 143 144 switch (type) { 145 case HAL_WBM2SW_RELEASE: 146 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) { 147 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0]; 148 ring_num = 0; 149 } else { 150 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map; 151 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 152 if (ring_num == map[i].wbm_ring_num) { 153 ring_num = i; 154 break; 155 } 156 } 157 158 grp_mask = &ab->hw_params->ring_mask->tx[0]; 159 } 160 break; 161 case HAL_REO_EXCEPTION: 162 grp_mask = &ab->hw_params->ring_mask->rx_err[0]; 163 break; 164 case HAL_REO_DST: 165 grp_mask = &ab->hw_params->ring_mask->rx[0]; 166 break; 167 case HAL_REO_STATUS: 168 grp_mask = &ab->hw_params->ring_mask->reo_status[0]; 169 break; 170 case HAL_RXDMA_MONITOR_STATUS: 171 case HAL_RXDMA_MONITOR_DST: 172 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0]; 173 break; 174 case HAL_TX_MONITOR_DST: 175 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0]; 176 break; 177 case HAL_RXDMA_BUF: 178 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0]; 179 break; 180 case HAL_RXDMA_MONITOR_BUF: 181 case HAL_TCL_DATA: 182 case HAL_TCL_CMD: 183 case HAL_REO_CMD: 184 case HAL_SW2WBM_RELEASE: 185 case HAL_WBM_IDLE_LINK: 186 case HAL_TCL_STATUS: 187 case HAL_REO_REINJECT: 188 case HAL_CE_SRC: 189 case HAL_CE_DST: 190 case HAL_CE_DST_STATUS: 191 default: 192 return -ENOENT; 193 } 194 195 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask); 196 } 197 198 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab, 199 struct hal_srng_params *ring_params, 200 enum hal_ring_type type, int ring_num) 201 { 202 int msi_group_number, msi_data_count; 203 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi; 204 int ret; 205 206 ret = ath12k_hif_get_user_msi_vector(ab, "DP", 207 &msi_data_count, &msi_data_start, 208 &msi_irq_start); 209 if (ret) 210 return; 211 212 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type, 213 ring_num); 214 if (msi_group_number < 0) { 215 ath12k_dbg(ab, ATH12K_DBG_PCI, 216 "ring not part of an ext_group; ring_type: %d,ring_num %d", 217 type, ring_num); 218 ring_params->msi_addr = 0; 219 ring_params->msi_data = 0; 220 return; 221 } 222 223 if (msi_group_number > msi_data_count) { 224 ath12k_dbg(ab, ATH12K_DBG_PCI, 225 "multiple msi_groups share one msi, msi_group_num %d", 226 msi_group_number); 227 } 228 229 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi); 230 231 ring_params->msi_addr = addr_lo; 232 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); 233 ring_params->msi_data = (msi_group_number % msi_data_count) 234 + msi_data_start; 235 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; 236 } 237 238 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 239 enum hal_ring_type type, int ring_num, 240 int mac_id, int num_entries) 241 { 242 struct hal_srng_params params = { 0 }; 243 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type); 244 int max_entries = ath12k_hal_srng_get_max_entries(ab, type); 245 int ret; 246 247 if (max_entries < 0 || entry_sz < 0) 248 return -EINVAL; 249 250 if (num_entries > max_entries) 251 num_entries = max_entries; 252 253 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; 254 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, 255 &ring->paddr_unaligned, 256 GFP_KERNEL); 257 if (!ring->vaddr_unaligned) 258 return -ENOMEM; 259 260 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN); 261 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - 262 (unsigned long)ring->vaddr_unaligned); 263 264 params.ring_base_vaddr = ring->vaddr; 265 params.ring_base_paddr = ring->paddr; 266 params.num_entries = num_entries; 267 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id); 268 269 switch (type) { 270 case HAL_REO_DST: 271 params.intr_batch_cntr_thres_entries = 272 HAL_SRNG_INT_BATCH_THRESHOLD_RX; 273 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 274 break; 275 case HAL_RXDMA_BUF: 276 case HAL_RXDMA_MONITOR_BUF: 277 case HAL_RXDMA_MONITOR_STATUS: 278 params.low_threshold = num_entries >> 3; 279 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 280 params.intr_batch_cntr_thres_entries = 0; 281 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 282 break; 283 case HAL_TX_MONITOR_DST: 284 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3; 285 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 286 params.intr_batch_cntr_thres_entries = 0; 287 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 288 break; 289 case HAL_WBM2SW_RELEASE: 290 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) { 291 params.intr_batch_cntr_thres_entries = 292 HAL_SRNG_INT_BATCH_THRESHOLD_TX; 293 params.intr_timer_thres_us = 294 HAL_SRNG_INT_TIMER_THRESHOLD_TX; 295 break; 296 } 297 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */ 298 fallthrough; 299 case HAL_REO_EXCEPTION: 300 case HAL_REO_REINJECT: 301 case HAL_REO_CMD: 302 case HAL_REO_STATUS: 303 case HAL_TCL_DATA: 304 case HAL_TCL_CMD: 305 case HAL_TCL_STATUS: 306 case HAL_WBM_IDLE_LINK: 307 case HAL_SW2WBM_RELEASE: 308 case HAL_RXDMA_DST: 309 case HAL_RXDMA_MONITOR_DST: 310 case HAL_RXDMA_MONITOR_DESC: 311 params.intr_batch_cntr_thres_entries = 312 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; 313 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; 314 break; 315 case HAL_RXDMA_DIR_BUF: 316 break; 317 default: 318 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type); 319 return -EINVAL; 320 } 321 322 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms); 323 if (ret < 0) { 324 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", 325 ret, ring_num); 326 return ret; 327 } 328 329 ring->ring_id = ret; 330 331 return 0; 332 } 333 334 static 335 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, 336 struct ath12k_link_vif *arvif) 337 { 338 u32 bank_config = 0; 339 struct ath12k_vif *ahvif = arvif->ahvif; 340 341 /* Only valid for raw frames with HW crypto enabled. 342 * With SW crypto, mac80211 sets key per packet 343 */ 344 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 345 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags)) 346 bank_config |= 347 u32_encode_bits(ath12k_dp_tx_get_encrypt_type(ahvif->key_cipher), 348 HAL_TX_BANK_CONFIG_ENCRYPT_TYPE); 349 350 bank_config |= u32_encode_bits(ahvif->tx_encap_type, 351 HAL_TX_BANK_CONFIG_ENCAP_TYPE); 352 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) | 353 u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) | 354 u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD); 355 356 /* only valid if idx_lookup_override is not set in tcl_data_cmd */ 357 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); 358 359 bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN, 360 HAL_TX_BANK_CONFIG_ADDRX_EN) | 361 u32_encode_bits(!!(arvif->hal_addr_search_flags & 362 HAL_TX_ADDRY_EN), 363 HAL_TX_BANK_CONFIG_ADDRY_EN); 364 365 bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(ahvif->vif) ? 3 : 0, 366 HAL_TX_BANK_CONFIG_MESH_EN) | 367 u32_encode_bits(arvif->vdev_id_check_en, 368 HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN); 369 370 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID); 371 372 return bank_config; 373 } 374 375 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, 376 struct ath12k_link_vif *arvif, 377 struct ath12k_dp *dp) 378 { 379 int bank_id = DP_INVALID_BANK_ID; 380 int i; 381 u32 bank_config; 382 bool configure_register = false; 383 384 /* convert vdev params into hal_tx_bank_config */ 385 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif); 386 387 spin_lock_bh(&dp->tx_bank_lock); 388 /* TODO: implement using idr kernel framework*/ 389 for (i = 0; i < dp->num_bank_profiles; i++) { 390 if (dp->bank_profiles[i].is_configured && 391 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) { 392 bank_id = i; 393 goto inc_ref_and_return; 394 } 395 if (!dp->bank_profiles[i].is_configured || 396 !dp->bank_profiles[i].num_users) { 397 bank_id = i; 398 goto configure_and_return; 399 } 400 } 401 402 if (bank_id == DP_INVALID_BANK_ID) { 403 spin_unlock_bh(&dp->tx_bank_lock); 404 ath12k_err(ab, "unable to find TX bank!"); 405 return bank_id; 406 } 407 408 configure_and_return: 409 dp->bank_profiles[bank_id].is_configured = true; 410 dp->bank_profiles[bank_id].bank_config = bank_config; 411 configure_register = true; 412 inc_ref_and_return: 413 dp->bank_profiles[bank_id].num_users++; 414 spin_unlock_bh(&dp->tx_bank_lock); 415 416 if (configure_register) 417 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id); 418 419 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u", 420 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config, 421 dp->bank_profiles[bank_id].num_users); 422 423 return bank_id; 424 } 425 426 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id) 427 { 428 spin_lock_bh(&dp->tx_bank_lock); 429 dp->bank_profiles[bank_id].num_users--; 430 spin_unlock_bh(&dp->tx_bank_lock); 431 } 432 433 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab) 434 { 435 struct ath12k_dp *dp = &ab->dp; 436 437 kfree(dp->bank_profiles); 438 dp->bank_profiles = NULL; 439 } 440 441 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab) 442 { 443 struct ath12k_dp *dp = &ab->dp; 444 u32 num_tcl_banks = ab->hw_params->num_tcl_banks; 445 int i; 446 447 dp->num_bank_profiles = num_tcl_banks; 448 dp->bank_profiles = kmalloc_array(num_tcl_banks, 449 sizeof(struct ath12k_dp_tx_bank_profile), 450 GFP_KERNEL); 451 if (!dp->bank_profiles) 452 return -ENOMEM; 453 454 spin_lock_init(&dp->tx_bank_lock); 455 456 for (i = 0; i < num_tcl_banks; i++) { 457 dp->bank_profiles[i].is_configured = false; 458 dp->bank_profiles[i].num_users = 0; 459 } 460 461 return 0; 462 } 463 464 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab) 465 { 466 struct ath12k_dp *dp = &ab->dp; 467 int i; 468 469 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring); 470 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring); 471 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring); 472 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring); 473 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring); 474 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 475 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring); 476 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring); 477 } 478 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring); 479 } 480 481 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab) 482 { 483 struct ath12k_dp *dp = &ab->dp; 484 const struct ath12k_hal_tcl_to_wbm_rbm_map *map; 485 struct hal_srng *srng; 486 int i, ret, tx_comp_ring_num; 487 u32 ring_hash_map; 488 489 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring, 490 HAL_SW2WBM_RELEASE, 0, 0, 491 DP_WBM_RELEASE_RING_SIZE); 492 if (ret) { 493 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n", 494 ret); 495 goto err; 496 } 497 498 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 499 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map; 500 tx_comp_ring_num = map[i].wbm_ring_num; 501 502 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring, 503 HAL_TCL_DATA, i, 0, 504 DP_TCL_DATA_RING_SIZE); 505 if (ret) { 506 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n", 507 i, ret); 508 goto err; 509 } 510 511 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring, 512 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0, 513 DP_TX_COMP_RING_SIZE); 514 if (ret) { 515 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n", 516 tx_comp_ring_num, ret); 517 goto err; 518 } 519 } 520 521 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT, 522 0, 0, DP_REO_REINJECT_RING_SIZE); 523 if (ret) { 524 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n", 525 ret); 526 goto err; 527 } 528 529 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE, 530 HAL_WBM2SW_REL_ERR_RING_NUM, 0, 531 DP_RX_RELEASE_RING_SIZE); 532 if (ret) { 533 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret); 534 goto err; 535 } 536 537 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION, 538 0, 0, DP_REO_EXCEPTION_RING_SIZE); 539 if (ret) { 540 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n", 541 ret); 542 goto err; 543 } 544 545 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD, 546 0, 0, DP_REO_CMD_RING_SIZE); 547 if (ret) { 548 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret); 549 goto err; 550 } 551 552 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 553 ath12k_hal_reo_init_cmd_ring(ab, srng); 554 555 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS, 556 0, 0, DP_REO_STATUS_RING_SIZE); 557 if (ret) { 558 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret); 559 goto err; 560 } 561 562 /* When hash based routing of rx packet is enabled, 32 entries to map 563 * the hash values to the ring will be configured. Each hash entry uses 564 * four bits to map to a particular ring. The ring mapping will be 565 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5 566 * 8:SW6, 9:SW7, 10:SW8, 11:Not used. 567 */ 568 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 | 569 HAL_HASH_ROUTING_RING_SW2 << 4 | 570 HAL_HASH_ROUTING_RING_SW3 << 8 | 571 HAL_HASH_ROUTING_RING_SW4 << 12 | 572 HAL_HASH_ROUTING_RING_SW1 << 16 | 573 HAL_HASH_ROUTING_RING_SW2 << 20 | 574 HAL_HASH_ROUTING_RING_SW3 << 24 | 575 HAL_HASH_ROUTING_RING_SW4 << 28; 576 577 ath12k_hal_reo_hw_setup(ab, ring_hash_map); 578 579 return 0; 580 581 err: 582 ath12k_dp_srng_common_cleanup(ab); 583 584 return ret; 585 } 586 587 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab) 588 { 589 struct ath12k_dp *dp = &ab->dp; 590 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 591 int i; 592 593 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) { 594 if (!slist[i].vaddr) 595 continue; 596 597 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 598 slist[i].vaddr, slist[i].paddr); 599 slist[i].vaddr = NULL; 600 } 601 } 602 603 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab, 604 int size, 605 u32 n_link_desc_bank, 606 u32 n_link_desc, 607 u32 last_bank_sz) 608 { 609 struct ath12k_dp *dp = &ab->dp; 610 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks; 611 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 612 u32 n_entries_per_buf; 613 int num_scatter_buf, scatter_idx; 614 struct hal_wbm_link_desc *scatter_buf; 615 int align_bytes, n_entries; 616 dma_addr_t paddr; 617 int rem_entries; 618 int i; 619 int ret = 0; 620 u32 end_offset, cookie; 621 enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm; 622 623 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 624 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK); 625 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE); 626 627 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX) 628 return -EINVAL; 629 630 for (i = 0; i < num_scatter_buf; i++) { 631 slist[i].vaddr = dma_alloc_coherent(ab->dev, 632 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 633 &slist[i].paddr, GFP_KERNEL); 634 if (!slist[i].vaddr) { 635 ret = -ENOMEM; 636 goto err; 637 } 638 } 639 640 scatter_idx = 0; 641 scatter_buf = slist[scatter_idx].vaddr; 642 rem_entries = n_entries_per_buf; 643 644 for (i = 0; i < n_link_desc_bank; i++) { 645 align_bytes = link_desc_banks[i].vaddr - 646 link_desc_banks[i].vaddr_unaligned; 647 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) / 648 HAL_LINK_DESC_SIZE; 649 paddr = link_desc_banks[i].paddr; 650 while (n_entries) { 651 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); 652 ath12k_hal_set_link_desc_addr(scatter_buf, cookie, 653 paddr, rbm); 654 n_entries--; 655 paddr += HAL_LINK_DESC_SIZE; 656 if (rem_entries) { 657 rem_entries--; 658 scatter_buf++; 659 continue; 660 } 661 662 rem_entries = n_entries_per_buf; 663 scatter_idx++; 664 scatter_buf = slist[scatter_idx].vaddr; 665 } 666 } 667 668 end_offset = (scatter_buf - slist[scatter_idx].vaddr) * 669 sizeof(struct hal_wbm_link_desc); 670 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf, 671 n_link_desc, end_offset); 672 673 return 0; 674 675 err: 676 ath12k_dp_scatter_idle_link_desc_cleanup(ab); 677 678 return ret; 679 } 680 681 static void 682 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab, 683 struct dp_link_desc_bank *link_desc_banks) 684 { 685 int i; 686 687 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) { 688 if (link_desc_banks[i].vaddr_unaligned) { 689 dma_free_coherent(ab->dev, 690 link_desc_banks[i].size, 691 link_desc_banks[i].vaddr_unaligned, 692 link_desc_banks[i].paddr_unaligned); 693 link_desc_banks[i].vaddr_unaligned = NULL; 694 } 695 } 696 } 697 698 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab, 699 struct dp_link_desc_bank *desc_bank, 700 int n_link_desc_bank, 701 int last_bank_sz) 702 { 703 struct ath12k_dp *dp = &ab->dp; 704 int i; 705 int ret = 0; 706 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH; 707 708 for (i = 0; i < n_link_desc_bank; i++) { 709 if (i == (n_link_desc_bank - 1) && last_bank_sz) 710 desc_sz = last_bank_sz; 711 712 desc_bank[i].vaddr_unaligned = 713 dma_alloc_coherent(ab->dev, desc_sz, 714 &desc_bank[i].paddr_unaligned, 715 GFP_KERNEL); 716 if (!desc_bank[i].vaddr_unaligned) { 717 ret = -ENOMEM; 718 goto err; 719 } 720 721 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned, 722 HAL_LINK_DESC_ALIGN); 723 desc_bank[i].paddr = desc_bank[i].paddr_unaligned + 724 ((unsigned long)desc_bank[i].vaddr - 725 (unsigned long)desc_bank[i].vaddr_unaligned); 726 desc_bank[i].size = desc_sz; 727 } 728 729 return 0; 730 731 err: 732 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks); 733 734 return ret; 735 } 736 737 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 738 struct dp_link_desc_bank *desc_bank, 739 u32 ring_type, struct dp_srng *ring) 740 { 741 ath12k_dp_link_desc_bank_free(ab, desc_bank); 742 743 if (ring_type != HAL_RXDMA_MONITOR_DESC) { 744 ath12k_dp_srng_cleanup(ab, ring); 745 ath12k_dp_scatter_idle_link_desc_cleanup(ab); 746 } 747 } 748 749 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc) 750 { 751 struct ath12k_dp *dp = &ab->dp; 752 u32 n_mpdu_link_desc, n_mpdu_queue_desc; 753 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc; 754 int ret = 0; 755 756 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) / 757 HAL_NUM_MPDUS_PER_LINK_DESC; 758 759 n_mpdu_queue_desc = n_mpdu_link_desc / 760 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC; 761 762 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID * 763 DP_AVG_MSDUS_PER_FLOW) / 764 HAL_NUM_TX_MSDUS_PER_LINK_DESC; 765 766 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX * 767 DP_AVG_MSDUS_PER_MPDU) / 768 HAL_NUM_RX_MSDUS_PER_LINK_DESC; 769 770 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc + 771 n_tx_msdu_link_desc + n_rx_msdu_link_desc; 772 773 if (*n_link_desc & (*n_link_desc - 1)) 774 *n_link_desc = 1 << fls(*n_link_desc); 775 776 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring, 777 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc); 778 if (ret) { 779 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 780 return ret; 781 } 782 return ret; 783 } 784 785 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 786 struct dp_link_desc_bank *link_desc_banks, 787 u32 ring_type, struct hal_srng *srng, 788 u32 n_link_desc) 789 { 790 u32 tot_mem_sz; 791 u32 n_link_desc_bank, last_bank_sz; 792 u32 entry_sz, align_bytes, n_entries; 793 struct hal_wbm_link_desc *desc; 794 u32 paddr; 795 int i, ret; 796 u32 cookie; 797 enum hal_rx_buf_return_buf_manager rbm = ab->dp.idle_link_rbm; 798 799 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE; 800 tot_mem_sz += HAL_LINK_DESC_ALIGN; 801 802 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) { 803 n_link_desc_bank = 1; 804 last_bank_sz = tot_mem_sz; 805 } else { 806 n_link_desc_bank = tot_mem_sz / 807 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 808 HAL_LINK_DESC_ALIGN); 809 last_bank_sz = tot_mem_sz % 810 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 811 HAL_LINK_DESC_ALIGN); 812 813 if (last_bank_sz) 814 n_link_desc_bank += 1; 815 } 816 817 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX) 818 return -EINVAL; 819 820 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks, 821 n_link_desc_bank, last_bank_sz); 822 if (ret) 823 return ret; 824 825 /* Setup link desc idle list for HW internal usage */ 826 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type); 827 tot_mem_sz = entry_sz * n_link_desc; 828 829 /* Setup scatter desc list when the total memory requirement is more */ 830 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH && 831 ring_type != HAL_RXDMA_MONITOR_DESC) { 832 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz, 833 n_link_desc_bank, 834 n_link_desc, 835 last_bank_sz); 836 if (ret) { 837 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n", 838 ret); 839 goto fail_desc_bank_free; 840 } 841 842 return 0; 843 } 844 845 spin_lock_bh(&srng->lock); 846 847 ath12k_hal_srng_access_begin(ab, srng); 848 849 for (i = 0; i < n_link_desc_bank; i++) { 850 align_bytes = link_desc_banks[i].vaddr - 851 link_desc_banks[i].vaddr_unaligned; 852 n_entries = (link_desc_banks[i].size - align_bytes) / 853 HAL_LINK_DESC_SIZE; 854 paddr = link_desc_banks[i].paddr; 855 while (n_entries && 856 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) { 857 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); 858 ath12k_hal_set_link_desc_addr(desc, cookie, paddr, rbm); 859 n_entries--; 860 paddr += HAL_LINK_DESC_SIZE; 861 } 862 } 863 864 ath12k_hal_srng_access_end(ab, srng); 865 866 spin_unlock_bh(&srng->lock); 867 868 return 0; 869 870 fail_desc_bank_free: 871 ath12k_dp_link_desc_bank_free(ab, link_desc_banks); 872 873 return ret; 874 } 875 876 int ath12k_dp_service_srng(struct ath12k_base *ab, 877 struct ath12k_ext_irq_grp *irq_grp, 878 int budget) 879 { 880 struct napi_struct *napi = &irq_grp->napi; 881 int grp_id = irq_grp->grp_id; 882 int work_done = 0; 883 int i = 0, j; 884 int tot_work_done = 0; 885 enum dp_monitor_mode monitor_mode; 886 u8 ring_mask; 887 888 if (ab->hw_params->ring_mask->tx[grp_id]) { 889 i = fls(ab->hw_params->ring_mask->tx[grp_id]) - 1; 890 ath12k_dp_tx_completion_handler(ab, i); 891 } 892 893 if (ab->hw_params->ring_mask->rx_err[grp_id]) { 894 work_done = ath12k_dp_rx_process_err(ab, napi, budget); 895 budget -= work_done; 896 tot_work_done += work_done; 897 if (budget <= 0) 898 goto done; 899 } 900 901 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) { 902 work_done = ath12k_dp_rx_process_wbm_err(ab, 903 napi, 904 budget); 905 budget -= work_done; 906 tot_work_done += work_done; 907 908 if (budget <= 0) 909 goto done; 910 } 911 912 if (ab->hw_params->ring_mask->rx[grp_id]) { 913 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1; 914 work_done = ath12k_dp_rx_process(ab, i, napi, 915 budget); 916 budget -= work_done; 917 tot_work_done += work_done; 918 if (budget <= 0) 919 goto done; 920 } 921 922 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) { 923 monitor_mode = ATH12K_DP_RX_MONITOR_MODE; 924 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id]; 925 for (i = 0; i < ab->num_radios; i++) { 926 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) { 927 int id = i * ab->hw_params->num_rxdma_per_pdev + j; 928 929 if (ring_mask & BIT(id)) { 930 work_done = 931 ath12k_dp_mon_process_ring(ab, id, napi, budget, 932 monitor_mode); 933 budget -= work_done; 934 tot_work_done += work_done; 935 936 if (budget <= 0) 937 goto done; 938 } 939 } 940 } 941 } 942 943 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) { 944 monitor_mode = ATH12K_DP_TX_MONITOR_MODE; 945 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id]; 946 for (i = 0; i < ab->num_radios; i++) { 947 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) { 948 int id = i * ab->hw_params->num_rxdma_per_pdev + j; 949 950 if (ring_mask & BIT(id)) { 951 work_done = 952 ath12k_dp_mon_process_ring(ab, id, napi, budget, 953 monitor_mode); 954 budget -= work_done; 955 tot_work_done += work_done; 956 957 if (budget <= 0) 958 goto done; 959 } 960 } 961 } 962 } 963 964 if (ab->hw_params->ring_mask->reo_status[grp_id]) 965 ath12k_dp_rx_process_reo_status(ab); 966 967 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) { 968 struct ath12k_dp *dp = &ab->dp; 969 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 970 LIST_HEAD(list); 971 972 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 973 } 974 975 /* TODO: Implement handler for other interrupts */ 976 977 done: 978 return tot_work_done; 979 } 980 981 void ath12k_dp_pdev_free(struct ath12k_base *ab) 982 { 983 int i; 984 985 if (!ab->mon_reap_timer.function) 986 return; 987 988 del_timer_sync(&ab->mon_reap_timer); 989 990 for (i = 0; i < ab->num_radios; i++) 991 ath12k_dp_rx_pdev_free(ab, i); 992 } 993 994 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar) 995 { 996 struct ath12k_pdev_dp *dp = &ar->dp; 997 998 dp->mac_id = ar->pdev_idx; 999 atomic_set(&dp->num_tx_pending, 0); 1000 init_waitqueue_head(&dp->tx_empty_waitq); 1001 /* TODO: Add any RXDMA setup required per pdev */ 1002 } 1003 1004 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab) 1005 { 1006 if (test_bit(WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS, ab->wmi_ab.svc_map) && 1007 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start && 1008 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end && 1009 ab->hw_params->hal_ops->get_hal_rx_compact_ops) { 1010 return true; 1011 } 1012 return false; 1013 } 1014 1015 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab) 1016 { 1017 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 1018 /* RX TLVS compaction is supported, hence change the hal_rx_ops 1019 * to compact hal_rx_ops. 1020 */ 1021 ab->hal_rx_ops = ab->hw_params->hal_ops->get_hal_rx_compact_ops(); 1022 } 1023 ab->hal.hal_desc_sz = 1024 ab->hal_rx_ops->rx_desc_get_desc_size(); 1025 } 1026 1027 static void ath12k_dp_service_mon_ring(struct timer_list *t) 1028 { 1029 struct ath12k_base *ab = from_timer(ab, t, mon_reap_timer); 1030 int i; 1031 1032 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 1033 ath12k_dp_mon_process_ring(ab, i, NULL, DP_MON_SERVICE_BUDGET, 1034 ATH12K_DP_RX_MONITOR_MODE); 1035 1036 mod_timer(&ab->mon_reap_timer, jiffies + 1037 msecs_to_jiffies(ATH12K_MON_TIMER_INTERVAL)); 1038 } 1039 1040 static void ath12k_dp_mon_reap_timer_init(struct ath12k_base *ab) 1041 { 1042 if (ab->hw_params->rxdma1_enable) 1043 return; 1044 1045 timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0); 1046 } 1047 1048 int ath12k_dp_pdev_alloc(struct ath12k_base *ab) 1049 { 1050 struct ath12k *ar; 1051 int ret; 1052 int i; 1053 1054 ret = ath12k_dp_rx_htt_setup(ab); 1055 if (ret) 1056 goto out; 1057 1058 ath12k_dp_mon_reap_timer_init(ab); 1059 1060 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */ 1061 for (i = 0; i < ab->num_radios; i++) { 1062 ar = ab->pdevs[i].ar; 1063 ret = ath12k_dp_rx_pdev_alloc(ab, i); 1064 if (ret) { 1065 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n", 1066 i); 1067 goto err; 1068 } 1069 ret = ath12k_dp_rx_pdev_mon_attach(ar); 1070 if (ret) { 1071 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i); 1072 goto err; 1073 } 1074 } 1075 1076 return 0; 1077 err: 1078 ath12k_dp_pdev_free(ab); 1079 out: 1080 return ret; 1081 } 1082 1083 int ath12k_dp_htt_connect(struct ath12k_dp *dp) 1084 { 1085 struct ath12k_htc_svc_conn_req conn_req = {0}; 1086 struct ath12k_htc_svc_conn_resp conn_resp = {0}; 1087 int status; 1088 1089 conn_req.ep_ops.ep_tx_complete = ath12k_dp_htt_htc_tx_complete; 1090 conn_req.ep_ops.ep_rx_complete = ath12k_dp_htt_htc_t2h_msg_handler; 1091 1092 /* connect to control service */ 1093 conn_req.service_id = ATH12K_HTC_SVC_ID_HTT_DATA_MSG; 1094 1095 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req, 1096 &conn_resp); 1097 1098 if (status) 1099 return status; 1100 1101 dp->eid = conn_resp.eid; 1102 1103 return 0; 1104 } 1105 1106 static void ath12k_dp_update_vdev_search(struct ath12k_link_vif *arvif) 1107 { 1108 switch (arvif->ahvif->vdev_type) { 1109 case WMI_VDEV_TYPE_STA: 1110 /* TODO: Verify the search type and flags since ast hash 1111 * is not part of peer mapv3 1112 */ 1113 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN; 1114 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 1115 break; 1116 case WMI_VDEV_TYPE_AP: 1117 case WMI_VDEV_TYPE_IBSS: 1118 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 1119 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 1120 break; 1121 case WMI_VDEV_TYPE_MONITOR: 1122 default: 1123 return; 1124 } 1125 } 1126 1127 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif) 1128 { 1129 struct ath12k_base *ab = ar->ab; 1130 1131 arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) | 1132 u32_encode_bits(arvif->vdev_id, 1133 HTT_TCL_META_DATA_VDEV_ID) | 1134 u32_encode_bits(ar->pdev->pdev_id, 1135 HTT_TCL_META_DATA_PDEV_ID); 1136 1137 /* set HTT extension valid bit to 0 by default */ 1138 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; 1139 1140 ath12k_dp_update_vdev_search(arvif); 1141 arvif->vdev_id_check_en = true; 1142 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp); 1143 1144 /* TODO: error path for bank id failure */ 1145 if (arvif->bank_id == DP_INVALID_BANK_ID) { 1146 ath12k_err(ar->ab, "Failed to initialize DP TX Banks"); 1147 return; 1148 } 1149 } 1150 1151 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) 1152 { 1153 struct ath12k_rx_desc_info *desc_info; 1154 struct ath12k_tx_desc_info *tx_desc_info, *tmp1; 1155 struct ath12k_dp *dp = &ab->dp; 1156 struct ath12k_skb_cb *skb_cb; 1157 struct sk_buff *skb; 1158 struct ath12k *ar; 1159 int i, j; 1160 u32 pool_id, tx_spt_page; 1161 1162 if (!dp->spt_info) 1163 return; 1164 1165 /* RX Descriptor cleanup */ 1166 spin_lock_bh(&dp->rx_desc_lock); 1167 1168 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { 1169 desc_info = dp->rxbaddr[i]; 1170 1171 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1172 if (!desc_info[j].in_use) { 1173 list_del(&desc_info[j].list); 1174 continue; 1175 } 1176 1177 skb = desc_info[j].skb; 1178 if (!skb) 1179 continue; 1180 1181 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 1182 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 1183 dev_kfree_skb_any(skb); 1184 } 1185 } 1186 1187 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { 1188 if (!dp->rxbaddr[i]) 1189 continue; 1190 1191 kfree(dp->rxbaddr[i]); 1192 dp->rxbaddr[i] = NULL; 1193 } 1194 1195 spin_unlock_bh(&dp->rx_desc_lock); 1196 1197 /* TX Descriptor cleanup */ 1198 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { 1199 spin_lock_bh(&dp->tx_desc_lock[i]); 1200 1201 list_for_each_entry_safe(tx_desc_info, tmp1, &dp->tx_desc_used_list[i], 1202 list) { 1203 list_del(&tx_desc_info->list); 1204 skb = tx_desc_info->skb; 1205 1206 if (!skb) 1207 continue; 1208 1209 /* if we are unregistering, hw would've been destroyed and 1210 * ar is no longer valid. 1211 */ 1212 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) { 1213 skb_cb = ATH12K_SKB_CB(skb); 1214 ar = skb_cb->ar; 1215 1216 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 1217 wake_up(&ar->dp.tx_empty_waitq); 1218 } 1219 1220 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, 1221 skb->len, DMA_TO_DEVICE); 1222 dev_kfree_skb_any(skb); 1223 } 1224 1225 spin_unlock_bh(&dp->tx_desc_lock[i]); 1226 } 1227 1228 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { 1229 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 1230 1231 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { 1232 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; 1233 if (!dp->txbaddr[tx_spt_page]) 1234 continue; 1235 1236 kfree(dp->txbaddr[tx_spt_page]); 1237 dp->txbaddr[tx_spt_page] = NULL; 1238 } 1239 1240 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1241 } 1242 1243 /* unmap SPT pages */ 1244 for (i = 0; i < dp->num_spt_pages; i++) { 1245 if (!dp->spt_info[i].vaddr) 1246 continue; 1247 1248 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE, 1249 dp->spt_info[i].vaddr, dp->spt_info[i].paddr); 1250 dp->spt_info[i].vaddr = NULL; 1251 } 1252 1253 kfree(dp->spt_info); 1254 dp->spt_info = NULL; 1255 } 1256 1257 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab) 1258 { 1259 struct ath12k_dp *dp = &ab->dp; 1260 1261 if (!ab->hw_params->reoq_lut_support) 1262 return; 1263 1264 if (dp->reoq_lut.vaddr) { 1265 ath12k_hif_write32(ab, 1266 HAL_SEQ_WCSS_UMAC_REO_REG + 1267 HAL_REO1_QDESC_LUT_BASE0(ab), 0); 1268 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE, 1269 dp->reoq_lut.vaddr, dp->reoq_lut.paddr); 1270 dp->reoq_lut.vaddr = NULL; 1271 } 1272 1273 if (dp->ml_reoq_lut.vaddr) { 1274 ath12k_hif_write32(ab, 1275 HAL_SEQ_WCSS_UMAC_REO_REG + 1276 HAL_REO1_QDESC_LUT_BASE1(ab), 0); 1277 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE, 1278 dp->ml_reoq_lut.vaddr, dp->ml_reoq_lut.paddr); 1279 dp->ml_reoq_lut.vaddr = NULL; 1280 } 1281 } 1282 1283 void ath12k_dp_free(struct ath12k_base *ab) 1284 { 1285 struct ath12k_dp *dp = &ab->dp; 1286 int i; 1287 1288 if (!dp->ab) 1289 return; 1290 1291 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1292 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1293 1294 ath12k_dp_cc_cleanup(ab); 1295 ath12k_dp_reoq_lut_cleanup(ab); 1296 ath12k_dp_deinit_bank_profiles(ab); 1297 ath12k_dp_srng_common_cleanup(ab); 1298 1299 ath12k_dp_rx_reo_cmd_list_cleanup(ab); 1300 1301 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 1302 kfree(dp->tx_ring[i].tx_status); 1303 dp->tx_ring[i].tx_status = NULL; 1304 } 1305 1306 ath12k_dp_rx_free(ab); 1307 /* Deinit any SOC level resource */ 1308 dp->ab = NULL; 1309 } 1310 1311 void ath12k_dp_cc_config(struct ath12k_base *ab) 1312 { 1313 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; 1314 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 1315 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG; 1316 u32 val = 0; 1317 1318 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base); 1319 1320 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB, 1321 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) | 1322 u32_encode_bits(ATH12K_CC_PPT_MSB, 1323 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) | 1324 u32_encode_bits(ATH12K_CC_SPT_MSB, 1325 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) | 1326 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) | 1327 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) | 1328 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE); 1329 1330 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val); 1331 1332 /* Enable HW CC for WBM */ 1333 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base); 1334 1335 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB, 1336 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) | 1337 u32_encode_bits(ATH12K_CC_PPT_MSB, 1338 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) | 1339 u32_encode_bits(ATH12K_CC_SPT_MSB, 1340 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) | 1341 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN); 1342 1343 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val); 1344 1345 /* Enable conversion complete indication */ 1346 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2); 1347 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) | 1348 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) | 1349 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN); 1350 1351 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val); 1352 1353 /* Enable Cookie conversion for WBM2SW Rings */ 1354 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG); 1355 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) | 1356 ab->hw_params->hal_params->wbm2sw_cc_enable; 1357 1358 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val); 1359 } 1360 1361 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx) 1362 { 1363 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx; 1364 } 1365 1366 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab, 1367 u16 ppt_idx, u16 spt_idx) 1368 { 1369 struct ath12k_dp *dp = &ab->dp; 1370 1371 return dp->spt_info[ppt_idx].vaddr + spt_idx; 1372 } 1373 1374 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1375 u32 cookie) 1376 { 1377 struct ath12k_dp *dp = &ab->dp; 1378 struct ath12k_rx_desc_info **desc_addr_ptr; 1379 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx; 1380 1381 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); 1382 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT); 1383 1384 start_ppt_idx = dp->rx_ppt_base + ATH12K_RX_SPT_PAGE_OFFSET; 1385 end_ppt_idx = start_ppt_idx + ATH12K_NUM_RX_SPT_PAGES; 1386 1387 if (ppt_idx < start_ppt_idx || 1388 ppt_idx >= end_ppt_idx || 1389 spt_idx > ATH12K_MAX_SPT_ENTRIES) 1390 return NULL; 1391 1392 ppt_idx = ppt_idx - dp->rx_ppt_base; 1393 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx); 1394 1395 return *desc_addr_ptr; 1396 } 1397 1398 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1399 u32 cookie) 1400 { 1401 struct ath12k_tx_desc_info **desc_addr_ptr; 1402 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx; 1403 1404 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); 1405 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT); 1406 1407 start_ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET; 1408 end_ppt_idx = start_ppt_idx + 1409 (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES); 1410 1411 if (ppt_idx < start_ppt_idx || 1412 ppt_idx >= end_ppt_idx || 1413 spt_idx > ATH12K_MAX_SPT_ENTRIES) 1414 return NULL; 1415 1416 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx); 1417 1418 return *desc_addr_ptr; 1419 } 1420 1421 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab) 1422 { 1423 struct ath12k_dp *dp = &ab->dp; 1424 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr; 1425 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr; 1426 u32 i, j, pool_id, tx_spt_page; 1427 u32 ppt_idx, cookie_ppt_idx; 1428 1429 spin_lock_bh(&dp->rx_desc_lock); 1430 1431 /* First ATH12K_NUM_RX_SPT_PAGES of allocated SPT pages are used for RX */ 1432 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { 1433 rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs), 1434 GFP_ATOMIC); 1435 1436 if (!rx_descs) { 1437 spin_unlock_bh(&dp->rx_desc_lock); 1438 return -ENOMEM; 1439 } 1440 1441 ppt_idx = ATH12K_RX_SPT_PAGE_OFFSET + i; 1442 cookie_ppt_idx = dp->rx_ppt_base + ppt_idx; 1443 dp->rxbaddr[i] = &rx_descs[0]; 1444 1445 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1446 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(cookie_ppt_idx, j); 1447 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC; 1448 rx_descs[j].device_id = ab->device_id; 1449 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list); 1450 1451 /* Update descriptor VA in SPT */ 1452 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j); 1453 *rx_desc_addr = &rx_descs[j]; 1454 } 1455 } 1456 1457 spin_unlock_bh(&dp->rx_desc_lock); 1458 1459 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { 1460 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 1461 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { 1462 tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*tx_descs), 1463 GFP_ATOMIC); 1464 1465 if (!tx_descs) { 1466 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1467 /* Caller takes care of TX pending and RX desc cleanup */ 1468 return -ENOMEM; 1469 } 1470 1471 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; 1472 ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET + tx_spt_page; 1473 1474 dp->txbaddr[tx_spt_page] = &tx_descs[0]; 1475 1476 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1477 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j); 1478 tx_descs[j].pool_id = pool_id; 1479 list_add_tail(&tx_descs[j].list, 1480 &dp->tx_desc_free_list[pool_id]); 1481 1482 /* Update descriptor VA in SPT */ 1483 tx_desc_addr = 1484 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j); 1485 *tx_desc_addr = &tx_descs[j]; 1486 } 1487 } 1488 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1489 } 1490 return 0; 1491 } 1492 1493 static int ath12k_dp_cmem_init(struct ath12k_base *ab, 1494 struct ath12k_dp *dp, 1495 enum ath12k_dp_desc_type type) 1496 { 1497 u32 cmem_base; 1498 int i, start, end; 1499 1500 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; 1501 1502 switch (type) { 1503 case ATH12K_DP_TX_DESC: 1504 start = ATH12K_TX_SPT_PAGE_OFFSET; 1505 end = start + ATH12K_NUM_TX_SPT_PAGES; 1506 break; 1507 case ATH12K_DP_RX_DESC: 1508 cmem_base += ATH12K_PPT_ADDR_OFFSET(dp->rx_ppt_base); 1509 start = ATH12K_RX_SPT_PAGE_OFFSET; 1510 end = start + ATH12K_NUM_RX_SPT_PAGES; 1511 break; 1512 default: 1513 ath12k_err(ab, "invalid descriptor type %d in cmem init\n", type); 1514 return -EINVAL; 1515 } 1516 1517 /* Write to PPT in CMEM */ 1518 for (i = start; i < end; i++) 1519 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), 1520 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); 1521 1522 return 0; 1523 } 1524 1525 void ath12k_dp_partner_cc_init(struct ath12k_base *ab) 1526 { 1527 struct ath12k_hw_group *ag = ab->ag; 1528 int i; 1529 1530 for (i = 0; i < ag->num_devices; i++) { 1531 if (ag->ab[i] == ab) 1532 continue; 1533 1534 ath12k_dp_cmem_init(ab, &ag->ab[i]->dp, ATH12K_DP_RX_DESC); 1535 } 1536 } 1537 1538 static int ath12k_dp_cc_init(struct ath12k_base *ab) 1539 { 1540 struct ath12k_dp *dp = &ab->dp; 1541 int i, ret = 0; 1542 1543 INIT_LIST_HEAD(&dp->rx_desc_free_list); 1544 spin_lock_init(&dp->rx_desc_lock); 1545 1546 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { 1547 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]); 1548 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]); 1549 spin_lock_init(&dp->tx_desc_lock[i]); 1550 } 1551 1552 dp->num_spt_pages = ATH12K_NUM_SPT_PAGES; 1553 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES) 1554 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES; 1555 1556 dp->spt_info = kcalloc(dp->num_spt_pages, sizeof(struct ath12k_spt_info), 1557 GFP_KERNEL); 1558 1559 if (!dp->spt_info) { 1560 ath12k_warn(ab, "SPT page allocation failure"); 1561 return -ENOMEM; 1562 } 1563 1564 dp->rx_ppt_base = ab->device_id * ATH12K_NUM_RX_SPT_PAGES; 1565 1566 for (i = 0; i < dp->num_spt_pages; i++) { 1567 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev, 1568 ATH12K_PAGE_SIZE, 1569 &dp->spt_info[i].paddr, 1570 GFP_KERNEL); 1571 1572 if (!dp->spt_info[i].vaddr) { 1573 ret = -ENOMEM; 1574 goto free; 1575 } 1576 1577 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) { 1578 ath12k_warn(ab, "SPT allocated memory is not 4K aligned"); 1579 ret = -EINVAL; 1580 goto free; 1581 } 1582 } 1583 1584 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_TX_DESC); 1585 if (ret) { 1586 ath12k_warn(ab, "HW CC Tx cmem init failed %d", ret); 1587 goto free; 1588 } 1589 1590 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_RX_DESC); 1591 if (ret) { 1592 ath12k_warn(ab, "HW CC Rx cmem init failed %d", ret); 1593 goto free; 1594 } 1595 1596 ret = ath12k_dp_cc_desc_init(ab); 1597 if (ret) { 1598 ath12k_warn(ab, "HW CC desc init failed %d", ret); 1599 goto free; 1600 } 1601 1602 return 0; 1603 free: 1604 ath12k_dp_cc_cleanup(ab); 1605 return ret; 1606 } 1607 1608 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab) 1609 { 1610 struct ath12k_dp *dp = &ab->dp; 1611 1612 if (!ab->hw_params->reoq_lut_support) 1613 return 0; 1614 1615 dp->reoq_lut.vaddr = dma_alloc_coherent(ab->dev, 1616 DP_REOQ_LUT_SIZE, 1617 &dp->reoq_lut.paddr, 1618 GFP_KERNEL | __GFP_ZERO); 1619 if (!dp->reoq_lut.vaddr) { 1620 ath12k_warn(ab, "failed to allocate memory for reoq table"); 1621 return -ENOMEM; 1622 } 1623 1624 dp->ml_reoq_lut.vaddr = dma_alloc_coherent(ab->dev, 1625 DP_REOQ_LUT_SIZE, 1626 &dp->ml_reoq_lut.paddr, 1627 GFP_KERNEL | __GFP_ZERO); 1628 if (!dp->ml_reoq_lut.vaddr) { 1629 ath12k_warn(ab, "failed to allocate memory for ML reoq table"); 1630 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE, 1631 dp->reoq_lut.vaddr, dp->reoq_lut.paddr); 1632 dp->reoq_lut.vaddr = NULL; 1633 return -ENOMEM; 1634 } 1635 1636 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 1637 dp->reoq_lut.paddr); 1638 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE1(ab), 1639 dp->ml_reoq_lut.paddr >> 8); 1640 1641 return 0; 1642 } 1643 1644 static enum hal_rx_buf_return_buf_manager 1645 ath12k_dp_get_idle_link_rbm(struct ath12k_base *ab) 1646 { 1647 switch (ab->device_id) { 1648 case 0: 1649 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST; 1650 case 1: 1651 return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST; 1652 case 2: 1653 return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST; 1654 default: 1655 ath12k_warn(ab, "invalid %d device id, so choose default rbm\n", 1656 ab->device_id); 1657 WARN_ON(1); 1658 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST; 1659 } 1660 } 1661 1662 int ath12k_dp_alloc(struct ath12k_base *ab) 1663 { 1664 struct ath12k_dp *dp = &ab->dp; 1665 struct hal_srng *srng = NULL; 1666 size_t size = 0; 1667 u32 n_link_desc = 0; 1668 int ret; 1669 int i; 1670 1671 dp->ab = ab; 1672 1673 INIT_LIST_HEAD(&dp->reo_cmd_list); 1674 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); 1675 spin_lock_init(&dp->reo_cmd_lock); 1676 1677 dp->reo_cmd_cache_flush_count = 0; 1678 dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab); 1679 1680 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc); 1681 if (ret) { 1682 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 1683 return ret; 1684 } 1685 1686 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id]; 1687 1688 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks, 1689 HAL_WBM_IDLE_LINK, srng, n_link_desc); 1690 if (ret) { 1691 ath12k_warn(ab, "failed to setup link desc: %d\n", ret); 1692 return ret; 1693 } 1694 1695 ret = ath12k_dp_cc_init(ab); 1696 1697 if (ret) { 1698 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret); 1699 goto fail_link_desc_cleanup; 1700 } 1701 ret = ath12k_dp_init_bank_profiles(ab); 1702 if (ret) { 1703 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret); 1704 goto fail_hw_cc_cleanup; 1705 } 1706 1707 ret = ath12k_dp_srng_common_setup(ab); 1708 if (ret) 1709 goto fail_dp_bank_profiles_cleanup; 1710 1711 size = sizeof(struct hal_wbm_release_ring_tx) * DP_TX_COMP_RING_SIZE; 1712 1713 ret = ath12k_dp_reoq_lut_setup(ab); 1714 if (ret) { 1715 ath12k_warn(ab, "failed to setup reoq table %d\n", ret); 1716 goto fail_cmn_srng_cleanup; 1717 } 1718 1719 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 1720 dp->tx_ring[i].tcl_data_ring_id = i; 1721 1722 dp->tx_ring[i].tx_status_head = 0; 1723 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1; 1724 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL); 1725 if (!dp->tx_ring[i].tx_status) { 1726 ret = -ENOMEM; 1727 /* FIXME: The allocated tx status is not freed 1728 * properly here 1729 */ 1730 goto fail_cmn_reoq_cleanup; 1731 } 1732 } 1733 1734 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++) 1735 ath12k_hal_tx_set_dscp_tid_map(ab, i); 1736 1737 ret = ath12k_dp_rx_alloc(ab); 1738 if (ret) 1739 goto fail_dp_rx_free; 1740 1741 /* Init any SOC level resource for DP */ 1742 1743 return 0; 1744 1745 fail_dp_rx_free: 1746 ath12k_dp_rx_free(ab); 1747 1748 fail_cmn_reoq_cleanup: 1749 ath12k_dp_reoq_lut_cleanup(ab); 1750 1751 fail_cmn_srng_cleanup: 1752 ath12k_dp_srng_common_cleanup(ab); 1753 1754 fail_dp_bank_profiles_cleanup: 1755 ath12k_dp_deinit_bank_profiles(ab); 1756 1757 fail_hw_cc_cleanup: 1758 ath12k_dp_cc_cleanup(ab); 1759 1760 fail_link_desc_cleanup: 1761 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1762 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1763 1764 return ret; 1765 } 1766