1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <crypto/hash.h> 8 #include "core.h" 9 #include "dp_tx.h" 10 #include "hal_tx.h" 11 #include "hif.h" 12 #include "debug.h" 13 #include "dp_rx.h" 14 #include "peer.h" 15 #include "dp_mon.h" 16 17 enum ath12k_dp_desc_type { 18 ATH12K_DP_TX_DESC, 19 ATH12K_DP_RX_DESC, 20 }; 21 22 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab, 23 struct sk_buff *skb) 24 { 25 dev_kfree_skb_any(skb); 26 } 27 28 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr) 29 { 30 struct ath12k_base *ab = ar->ab; 31 struct ath12k_peer *peer; 32 33 /* TODO: Any other peer specific DP cleanup */ 34 35 spin_lock_bh(&ab->base_lock); 36 peer = ath12k_peer_find(ab, vdev_id, addr); 37 if (!peer) { 38 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n", 39 addr, vdev_id); 40 spin_unlock_bh(&ab->base_lock); 41 return; 42 } 43 44 if (!peer->primary_link) { 45 spin_unlock_bh(&ab->base_lock); 46 return; 47 } 48 49 ath12k_dp_rx_peer_tid_cleanup(ar, peer); 50 crypto_free_shash(peer->tfm_mmic); 51 peer->dp_setup_done = false; 52 spin_unlock_bh(&ab->base_lock); 53 } 54 55 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr) 56 { 57 struct ath12k_base *ab = ar->ab; 58 struct ath12k_peer *peer; 59 u32 reo_dest; 60 int ret = 0, tid; 61 62 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */ 63 reo_dest = ar->dp.mac_id + 1; 64 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id, 65 WMI_PEER_SET_DEFAULT_ROUTING, 66 DP_RX_HASH_ENABLE | (reo_dest << 1)); 67 68 if (ret) { 69 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n", 70 ret, addr, vdev_id); 71 return ret; 72 } 73 74 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 75 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0, 76 HAL_PN_TYPE_NONE); 77 if (ret) { 78 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n", 79 tid, ret); 80 goto peer_clean; 81 } 82 } 83 84 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id); 85 if (ret) { 86 ath12k_warn(ab, "failed to setup rx defrag context\n"); 87 tid--; 88 goto peer_clean; 89 } 90 91 /* TODO: Setup other peer specific resource used in data path */ 92 93 return 0; 94 95 peer_clean: 96 spin_lock_bh(&ab->base_lock); 97 98 peer = ath12k_peer_find(ab, vdev_id, addr); 99 if (!peer) { 100 ath12k_warn(ab, "failed to find the peer to del rx tid\n"); 101 spin_unlock_bh(&ab->base_lock); 102 return -ENOENT; 103 } 104 105 for (; tid >= 0; tid--) 106 ath12k_dp_rx_peer_tid_delete(ar, peer, tid); 107 108 spin_unlock_bh(&ab->base_lock); 109 110 return ret; 111 } 112 113 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring) 114 { 115 if (!ring->vaddr_unaligned) 116 return; 117 118 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned, 119 ring->paddr_unaligned); 120 121 ring->vaddr_unaligned = NULL; 122 } 123 124 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask) 125 { 126 int ext_group_num; 127 u8 mask = 1 << ring_num; 128 129 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX; 130 ext_group_num++) { 131 if (mask & grp_mask[ext_group_num]) 132 return ext_group_num; 133 } 134 135 return -ENOENT; 136 } 137 138 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab, 139 enum hal_ring_type type, int ring_num) 140 { 141 const struct ath12k_hal_tcl_to_wbm_rbm_map *map; 142 const u8 *grp_mask; 143 int i; 144 145 switch (type) { 146 case HAL_WBM2SW_RELEASE: 147 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) { 148 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0]; 149 ring_num = 0; 150 } else { 151 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map; 152 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 153 if (ring_num == map[i].wbm_ring_num) { 154 ring_num = i; 155 break; 156 } 157 } 158 159 grp_mask = &ab->hw_params->ring_mask->tx[0]; 160 } 161 break; 162 case HAL_REO_EXCEPTION: 163 grp_mask = &ab->hw_params->ring_mask->rx_err[0]; 164 break; 165 case HAL_REO_DST: 166 grp_mask = &ab->hw_params->ring_mask->rx[0]; 167 break; 168 case HAL_REO_STATUS: 169 grp_mask = &ab->hw_params->ring_mask->reo_status[0]; 170 break; 171 case HAL_RXDMA_MONITOR_STATUS: 172 grp_mask = &ab->hw_params->ring_mask->rx_mon_status[0]; 173 break; 174 case HAL_RXDMA_MONITOR_DST: 175 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0]; 176 break; 177 case HAL_TX_MONITOR_DST: 178 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0]; 179 break; 180 case HAL_RXDMA_BUF: 181 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0]; 182 break; 183 case HAL_RXDMA_MONITOR_BUF: 184 case HAL_TCL_DATA: 185 case HAL_TCL_CMD: 186 case HAL_REO_CMD: 187 case HAL_SW2WBM_RELEASE: 188 case HAL_WBM_IDLE_LINK: 189 case HAL_TCL_STATUS: 190 case HAL_REO_REINJECT: 191 case HAL_CE_SRC: 192 case HAL_CE_DST: 193 case HAL_CE_DST_STATUS: 194 default: 195 return -ENOENT; 196 } 197 198 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask); 199 } 200 201 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab, 202 struct hal_srng_params *ring_params, 203 enum hal_ring_type type, int ring_num) 204 { 205 int msi_group_number, msi_data_count; 206 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi; 207 int ret; 208 209 ret = ath12k_hif_get_user_msi_vector(ab, "DP", 210 &msi_data_count, &msi_data_start, 211 &msi_irq_start); 212 if (ret) 213 return; 214 215 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type, 216 ring_num); 217 if (msi_group_number < 0) { 218 ath12k_dbg(ab, ATH12K_DBG_PCI, 219 "ring not part of an ext_group; ring_type: %d,ring_num %d", 220 type, ring_num); 221 ring_params->msi_addr = 0; 222 ring_params->msi_data = 0; 223 return; 224 } 225 226 if (msi_group_number > msi_data_count) { 227 ath12k_dbg(ab, ATH12K_DBG_PCI, 228 "multiple msi_groups share one msi, msi_group_num %d", 229 msi_group_number); 230 } 231 232 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi); 233 234 ring_params->msi_addr = addr_lo; 235 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); 236 ring_params->msi_data = (msi_group_number % msi_data_count) 237 + msi_data_start; 238 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; 239 } 240 241 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 242 enum hal_ring_type type, int ring_num, 243 int mac_id, int num_entries) 244 { 245 struct hal_srng_params params = { 0 }; 246 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type); 247 int max_entries = ath12k_hal_srng_get_max_entries(ab, type); 248 int ret; 249 250 if (max_entries < 0 || entry_sz < 0) 251 return -EINVAL; 252 253 if (num_entries > max_entries) 254 num_entries = max_entries; 255 256 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; 257 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, 258 &ring->paddr_unaligned, 259 GFP_KERNEL); 260 if (!ring->vaddr_unaligned) 261 return -ENOMEM; 262 263 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN); 264 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - 265 (unsigned long)ring->vaddr_unaligned); 266 267 params.ring_base_vaddr = ring->vaddr; 268 params.ring_base_paddr = ring->paddr; 269 params.num_entries = num_entries; 270 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id); 271 272 switch (type) { 273 case HAL_REO_DST: 274 params.intr_batch_cntr_thres_entries = 275 HAL_SRNG_INT_BATCH_THRESHOLD_RX; 276 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 277 break; 278 case HAL_RXDMA_BUF: 279 case HAL_RXDMA_MONITOR_BUF: 280 params.low_threshold = num_entries >> 3; 281 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 282 params.intr_batch_cntr_thres_entries = 0; 283 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 284 break; 285 case HAL_RXDMA_MONITOR_STATUS: 286 params.low_threshold = num_entries >> 3; 287 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 288 params.intr_batch_cntr_thres_entries = 1; 289 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 290 break; 291 case HAL_TX_MONITOR_DST: 292 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3; 293 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 294 params.intr_batch_cntr_thres_entries = 0; 295 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 296 break; 297 case HAL_WBM2SW_RELEASE: 298 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) { 299 params.intr_batch_cntr_thres_entries = 300 HAL_SRNG_INT_BATCH_THRESHOLD_TX; 301 params.intr_timer_thres_us = 302 HAL_SRNG_INT_TIMER_THRESHOLD_TX; 303 break; 304 } 305 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */ 306 fallthrough; 307 case HAL_REO_EXCEPTION: 308 case HAL_REO_REINJECT: 309 case HAL_REO_CMD: 310 case HAL_REO_STATUS: 311 case HAL_TCL_DATA: 312 case HAL_TCL_CMD: 313 case HAL_TCL_STATUS: 314 case HAL_WBM_IDLE_LINK: 315 case HAL_SW2WBM_RELEASE: 316 case HAL_RXDMA_DST: 317 case HAL_RXDMA_MONITOR_DST: 318 case HAL_RXDMA_MONITOR_DESC: 319 params.intr_batch_cntr_thres_entries = 320 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; 321 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; 322 break; 323 case HAL_RXDMA_DIR_BUF: 324 break; 325 default: 326 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type); 327 return -EINVAL; 328 } 329 330 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms); 331 if (ret < 0) { 332 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", 333 ret, ring_num); 334 return ret; 335 } 336 337 ring->ring_id = ret; 338 339 return 0; 340 } 341 342 static 343 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, 344 struct ath12k_link_vif *arvif) 345 { 346 u32 bank_config = 0; 347 struct ath12k_vif *ahvif = arvif->ahvif; 348 349 /* Only valid for raw frames with HW crypto enabled. 350 * With SW crypto, mac80211 sets key per packet 351 */ 352 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 353 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags)) 354 bank_config |= 355 u32_encode_bits(ath12k_dp_tx_get_encrypt_type(ahvif->key_cipher), 356 HAL_TX_BANK_CONFIG_ENCRYPT_TYPE); 357 358 bank_config |= u32_encode_bits(ahvif->tx_encap_type, 359 HAL_TX_BANK_CONFIG_ENCAP_TYPE); 360 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) | 361 u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) | 362 u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD); 363 364 /* only valid if idx_lookup_override is not set in tcl_data_cmd */ 365 if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) 366 bank_config |= u32_encode_bits(1, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); 367 else 368 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); 369 370 bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN, 371 HAL_TX_BANK_CONFIG_ADDRX_EN) | 372 u32_encode_bits(!!(arvif->hal_addr_search_flags & 373 HAL_TX_ADDRY_EN), 374 HAL_TX_BANK_CONFIG_ADDRY_EN); 375 376 bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(ahvif->vif) ? 3 : 0, 377 HAL_TX_BANK_CONFIG_MESH_EN) | 378 u32_encode_bits(arvif->vdev_id_check_en, 379 HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN); 380 381 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID); 382 383 return bank_config; 384 } 385 386 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, 387 struct ath12k_link_vif *arvif, 388 struct ath12k_dp *dp) 389 { 390 int bank_id = DP_INVALID_BANK_ID; 391 int i; 392 u32 bank_config; 393 bool configure_register = false; 394 395 /* convert vdev params into hal_tx_bank_config */ 396 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif); 397 398 spin_lock_bh(&dp->tx_bank_lock); 399 /* TODO: implement using idr kernel framework*/ 400 for (i = 0; i < dp->num_bank_profiles; i++) { 401 if (dp->bank_profiles[i].is_configured && 402 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) { 403 bank_id = i; 404 goto inc_ref_and_return; 405 } 406 if (!dp->bank_profiles[i].is_configured || 407 !dp->bank_profiles[i].num_users) { 408 bank_id = i; 409 goto configure_and_return; 410 } 411 } 412 413 if (bank_id == DP_INVALID_BANK_ID) { 414 spin_unlock_bh(&dp->tx_bank_lock); 415 ath12k_err(ab, "unable to find TX bank!"); 416 return bank_id; 417 } 418 419 configure_and_return: 420 dp->bank_profiles[bank_id].is_configured = true; 421 dp->bank_profiles[bank_id].bank_config = bank_config; 422 configure_register = true; 423 inc_ref_and_return: 424 dp->bank_profiles[bank_id].num_users++; 425 spin_unlock_bh(&dp->tx_bank_lock); 426 427 if (configure_register) 428 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id); 429 430 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u", 431 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config, 432 dp->bank_profiles[bank_id].num_users); 433 434 return bank_id; 435 } 436 437 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id) 438 { 439 spin_lock_bh(&dp->tx_bank_lock); 440 dp->bank_profiles[bank_id].num_users--; 441 spin_unlock_bh(&dp->tx_bank_lock); 442 } 443 444 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab) 445 { 446 struct ath12k_dp *dp = &ab->dp; 447 448 kfree(dp->bank_profiles); 449 dp->bank_profiles = NULL; 450 } 451 452 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab) 453 { 454 struct ath12k_dp *dp = &ab->dp; 455 u32 num_tcl_banks = ab->hw_params->num_tcl_banks; 456 int i; 457 458 dp->num_bank_profiles = num_tcl_banks; 459 dp->bank_profiles = kmalloc_array(num_tcl_banks, 460 sizeof(struct ath12k_dp_tx_bank_profile), 461 GFP_KERNEL); 462 if (!dp->bank_profiles) 463 return -ENOMEM; 464 465 spin_lock_init(&dp->tx_bank_lock); 466 467 for (i = 0; i < num_tcl_banks; i++) { 468 dp->bank_profiles[i].is_configured = false; 469 dp->bank_profiles[i].num_users = 0; 470 } 471 472 return 0; 473 } 474 475 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab) 476 { 477 struct ath12k_dp *dp = &ab->dp; 478 int i; 479 480 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring); 481 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring); 482 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring); 483 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring); 484 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring); 485 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 486 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring); 487 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring); 488 } 489 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring); 490 } 491 492 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab) 493 { 494 struct ath12k_dp *dp = &ab->dp; 495 const struct ath12k_hal_tcl_to_wbm_rbm_map *map; 496 struct hal_srng *srng; 497 int i, ret, tx_comp_ring_num; 498 u32 ring_hash_map; 499 500 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring, 501 HAL_SW2WBM_RELEASE, 0, 0, 502 DP_WBM_RELEASE_RING_SIZE); 503 if (ret) { 504 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n", 505 ret); 506 goto err; 507 } 508 509 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 510 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map; 511 tx_comp_ring_num = map[i].wbm_ring_num; 512 513 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring, 514 HAL_TCL_DATA, i, 0, 515 DP_TCL_DATA_RING_SIZE); 516 if (ret) { 517 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n", 518 i, ret); 519 goto err; 520 } 521 522 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring, 523 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0, 524 DP_TX_COMP_RING_SIZE); 525 if (ret) { 526 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n", 527 tx_comp_ring_num, ret); 528 goto err; 529 } 530 } 531 532 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT, 533 0, 0, DP_REO_REINJECT_RING_SIZE); 534 if (ret) { 535 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n", 536 ret); 537 goto err; 538 } 539 540 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE, 541 HAL_WBM2SW_REL_ERR_RING_NUM, 0, 542 DP_RX_RELEASE_RING_SIZE); 543 if (ret) { 544 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret); 545 goto err; 546 } 547 548 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION, 549 0, 0, DP_REO_EXCEPTION_RING_SIZE); 550 if (ret) { 551 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n", 552 ret); 553 goto err; 554 } 555 556 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD, 557 0, 0, DP_REO_CMD_RING_SIZE); 558 if (ret) { 559 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret); 560 goto err; 561 } 562 563 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 564 ath12k_hal_reo_init_cmd_ring(ab, srng); 565 566 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS, 567 0, 0, DP_REO_STATUS_RING_SIZE); 568 if (ret) { 569 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret); 570 goto err; 571 } 572 573 /* When hash based routing of rx packet is enabled, 32 entries to map 574 * the hash values to the ring will be configured. Each hash entry uses 575 * four bits to map to a particular ring. The ring mapping will be 576 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5 577 * 8:SW6, 9:SW7, 10:SW8, 11:Not used. 578 */ 579 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 | 580 HAL_HASH_ROUTING_RING_SW2 << 4 | 581 HAL_HASH_ROUTING_RING_SW3 << 8 | 582 HAL_HASH_ROUTING_RING_SW4 << 12 | 583 HAL_HASH_ROUTING_RING_SW1 << 16 | 584 HAL_HASH_ROUTING_RING_SW2 << 20 | 585 HAL_HASH_ROUTING_RING_SW3 << 24 | 586 HAL_HASH_ROUTING_RING_SW4 << 28; 587 588 ath12k_hal_reo_hw_setup(ab, ring_hash_map); 589 590 return 0; 591 592 err: 593 ath12k_dp_srng_common_cleanup(ab); 594 595 return ret; 596 } 597 598 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab) 599 { 600 struct ath12k_dp *dp = &ab->dp; 601 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 602 int i; 603 604 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) { 605 if (!slist[i].vaddr) 606 continue; 607 608 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 609 slist[i].vaddr, slist[i].paddr); 610 slist[i].vaddr = NULL; 611 } 612 } 613 614 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab, 615 int size, 616 u32 n_link_desc_bank, 617 u32 n_link_desc, 618 u32 last_bank_sz) 619 { 620 struct ath12k_dp *dp = &ab->dp; 621 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks; 622 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 623 u32 n_entries_per_buf; 624 int num_scatter_buf, scatter_idx; 625 struct hal_wbm_link_desc *scatter_buf; 626 int align_bytes, n_entries; 627 dma_addr_t paddr; 628 int rem_entries; 629 int i; 630 int ret = 0; 631 u32 end_offset, cookie; 632 enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm; 633 634 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 635 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK); 636 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE); 637 638 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX) 639 return -EINVAL; 640 641 for (i = 0; i < num_scatter_buf; i++) { 642 slist[i].vaddr = dma_alloc_coherent(ab->dev, 643 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 644 &slist[i].paddr, GFP_KERNEL); 645 if (!slist[i].vaddr) { 646 ret = -ENOMEM; 647 goto err; 648 } 649 } 650 651 scatter_idx = 0; 652 scatter_buf = slist[scatter_idx].vaddr; 653 rem_entries = n_entries_per_buf; 654 655 for (i = 0; i < n_link_desc_bank; i++) { 656 align_bytes = link_desc_banks[i].vaddr - 657 link_desc_banks[i].vaddr_unaligned; 658 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) / 659 HAL_LINK_DESC_SIZE; 660 paddr = link_desc_banks[i].paddr; 661 while (n_entries) { 662 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); 663 ath12k_hal_set_link_desc_addr(scatter_buf, cookie, 664 paddr, rbm); 665 n_entries--; 666 paddr += HAL_LINK_DESC_SIZE; 667 if (rem_entries) { 668 rem_entries--; 669 scatter_buf++; 670 continue; 671 } 672 673 rem_entries = n_entries_per_buf; 674 scatter_idx++; 675 scatter_buf = slist[scatter_idx].vaddr; 676 } 677 } 678 679 end_offset = (scatter_buf - slist[scatter_idx].vaddr) * 680 sizeof(struct hal_wbm_link_desc); 681 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf, 682 n_link_desc, end_offset); 683 684 return 0; 685 686 err: 687 ath12k_dp_scatter_idle_link_desc_cleanup(ab); 688 689 return ret; 690 } 691 692 static void 693 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab, 694 struct dp_link_desc_bank *link_desc_banks) 695 { 696 int i; 697 698 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) { 699 if (link_desc_banks[i].vaddr_unaligned) { 700 dma_free_coherent(ab->dev, 701 link_desc_banks[i].size, 702 link_desc_banks[i].vaddr_unaligned, 703 link_desc_banks[i].paddr_unaligned); 704 link_desc_banks[i].vaddr_unaligned = NULL; 705 } 706 } 707 } 708 709 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab, 710 struct dp_link_desc_bank *desc_bank, 711 int n_link_desc_bank, 712 int last_bank_sz) 713 { 714 struct ath12k_dp *dp = &ab->dp; 715 int i; 716 int ret = 0; 717 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH; 718 719 for (i = 0; i < n_link_desc_bank; i++) { 720 if (i == (n_link_desc_bank - 1) && last_bank_sz) 721 desc_sz = last_bank_sz; 722 723 desc_bank[i].vaddr_unaligned = 724 dma_alloc_coherent(ab->dev, desc_sz, 725 &desc_bank[i].paddr_unaligned, 726 GFP_KERNEL); 727 if (!desc_bank[i].vaddr_unaligned) { 728 ret = -ENOMEM; 729 goto err; 730 } 731 732 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned, 733 HAL_LINK_DESC_ALIGN); 734 desc_bank[i].paddr = desc_bank[i].paddr_unaligned + 735 ((unsigned long)desc_bank[i].vaddr - 736 (unsigned long)desc_bank[i].vaddr_unaligned); 737 desc_bank[i].size = desc_sz; 738 } 739 740 return 0; 741 742 err: 743 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks); 744 745 return ret; 746 } 747 748 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 749 struct dp_link_desc_bank *desc_bank, 750 u32 ring_type, struct dp_srng *ring) 751 { 752 ath12k_dp_link_desc_bank_free(ab, desc_bank); 753 754 if (ring_type != HAL_RXDMA_MONITOR_DESC) { 755 ath12k_dp_srng_cleanup(ab, ring); 756 ath12k_dp_scatter_idle_link_desc_cleanup(ab); 757 } 758 } 759 760 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc) 761 { 762 struct ath12k_dp *dp = &ab->dp; 763 u32 n_mpdu_link_desc, n_mpdu_queue_desc; 764 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc; 765 int ret = 0; 766 767 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) / 768 HAL_NUM_MPDUS_PER_LINK_DESC; 769 770 n_mpdu_queue_desc = n_mpdu_link_desc / 771 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC; 772 773 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID * 774 DP_AVG_MSDUS_PER_FLOW) / 775 HAL_NUM_TX_MSDUS_PER_LINK_DESC; 776 777 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX * 778 DP_AVG_MSDUS_PER_MPDU) / 779 HAL_NUM_RX_MSDUS_PER_LINK_DESC; 780 781 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc + 782 n_tx_msdu_link_desc + n_rx_msdu_link_desc; 783 784 if (*n_link_desc & (*n_link_desc - 1)) 785 *n_link_desc = 1 << fls(*n_link_desc); 786 787 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring, 788 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc); 789 if (ret) { 790 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 791 return ret; 792 } 793 return ret; 794 } 795 796 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 797 struct dp_link_desc_bank *link_desc_banks, 798 u32 ring_type, struct hal_srng *srng, 799 u32 n_link_desc) 800 { 801 u32 tot_mem_sz; 802 u32 n_link_desc_bank, last_bank_sz; 803 u32 entry_sz, align_bytes, n_entries; 804 struct hal_wbm_link_desc *desc; 805 u32 paddr; 806 int i, ret; 807 u32 cookie; 808 enum hal_rx_buf_return_buf_manager rbm = ab->dp.idle_link_rbm; 809 810 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE; 811 tot_mem_sz += HAL_LINK_DESC_ALIGN; 812 813 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) { 814 n_link_desc_bank = 1; 815 last_bank_sz = tot_mem_sz; 816 } else { 817 n_link_desc_bank = tot_mem_sz / 818 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 819 HAL_LINK_DESC_ALIGN); 820 last_bank_sz = tot_mem_sz % 821 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 822 HAL_LINK_DESC_ALIGN); 823 824 if (last_bank_sz) 825 n_link_desc_bank += 1; 826 } 827 828 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX) 829 return -EINVAL; 830 831 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks, 832 n_link_desc_bank, last_bank_sz); 833 if (ret) 834 return ret; 835 836 /* Setup link desc idle list for HW internal usage */ 837 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type); 838 tot_mem_sz = entry_sz * n_link_desc; 839 840 /* Setup scatter desc list when the total memory requirement is more */ 841 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH && 842 ring_type != HAL_RXDMA_MONITOR_DESC) { 843 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz, 844 n_link_desc_bank, 845 n_link_desc, 846 last_bank_sz); 847 if (ret) { 848 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n", 849 ret); 850 goto fail_desc_bank_free; 851 } 852 853 return 0; 854 } 855 856 spin_lock_bh(&srng->lock); 857 858 ath12k_hal_srng_access_begin(ab, srng); 859 860 for (i = 0; i < n_link_desc_bank; i++) { 861 align_bytes = link_desc_banks[i].vaddr - 862 link_desc_banks[i].vaddr_unaligned; 863 n_entries = (link_desc_banks[i].size - align_bytes) / 864 HAL_LINK_DESC_SIZE; 865 paddr = link_desc_banks[i].paddr; 866 while (n_entries && 867 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) { 868 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); 869 ath12k_hal_set_link_desc_addr(desc, cookie, paddr, rbm); 870 n_entries--; 871 paddr += HAL_LINK_DESC_SIZE; 872 } 873 } 874 875 ath12k_hal_srng_access_end(ab, srng); 876 877 spin_unlock_bh(&srng->lock); 878 879 return 0; 880 881 fail_desc_bank_free: 882 ath12k_dp_link_desc_bank_free(ab, link_desc_banks); 883 884 return ret; 885 } 886 887 int ath12k_dp_service_srng(struct ath12k_base *ab, 888 struct ath12k_ext_irq_grp *irq_grp, 889 int budget) 890 { 891 struct napi_struct *napi = &irq_grp->napi; 892 int grp_id = irq_grp->grp_id; 893 int work_done = 0; 894 int i = 0, j; 895 int tot_work_done = 0; 896 enum dp_monitor_mode monitor_mode; 897 u8 ring_mask; 898 899 if (ab->hw_params->ring_mask->tx[grp_id]) { 900 i = fls(ab->hw_params->ring_mask->tx[grp_id]) - 1; 901 ath12k_dp_tx_completion_handler(ab, i); 902 } 903 904 if (ab->hw_params->ring_mask->rx_err[grp_id]) { 905 work_done = ath12k_dp_rx_process_err(ab, napi, budget); 906 budget -= work_done; 907 tot_work_done += work_done; 908 if (budget <= 0) 909 goto done; 910 } 911 912 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) { 913 work_done = ath12k_dp_rx_process_wbm_err(ab, 914 napi, 915 budget); 916 budget -= work_done; 917 tot_work_done += work_done; 918 919 if (budget <= 0) 920 goto done; 921 } 922 923 if (ab->hw_params->ring_mask->rx[grp_id]) { 924 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1; 925 work_done = ath12k_dp_rx_process(ab, i, napi, 926 budget); 927 budget -= work_done; 928 tot_work_done += work_done; 929 if (budget <= 0) 930 goto done; 931 } 932 933 if (ab->hw_params->ring_mask->rx_mon_status[grp_id]) { 934 ring_mask = ab->hw_params->ring_mask->rx_mon_status[grp_id]; 935 for (i = 0; i < ab->num_radios; i++) { 936 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) { 937 int id = i * ab->hw_params->num_rxdma_per_pdev + j; 938 939 if (ring_mask & BIT(id)) { 940 work_done = 941 ath12k_dp_mon_process_ring(ab, id, napi, budget, 942 0); 943 budget -= work_done; 944 tot_work_done += work_done; 945 if (budget <= 0) 946 goto done; 947 } 948 } 949 } 950 } 951 952 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) { 953 monitor_mode = ATH12K_DP_RX_MONITOR_MODE; 954 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id]; 955 for (i = 0; i < ab->num_radios; i++) { 956 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) { 957 int id = i * ab->hw_params->num_rxdma_per_pdev + j; 958 959 if (ring_mask & BIT(id)) { 960 work_done = 961 ath12k_dp_mon_process_ring(ab, id, napi, budget, 962 monitor_mode); 963 budget -= work_done; 964 tot_work_done += work_done; 965 966 if (budget <= 0) 967 goto done; 968 } 969 } 970 } 971 } 972 973 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) { 974 monitor_mode = ATH12K_DP_TX_MONITOR_MODE; 975 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id]; 976 for (i = 0; i < ab->num_radios; i++) { 977 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) { 978 int id = i * ab->hw_params->num_rxdma_per_pdev + j; 979 980 if (ring_mask & BIT(id)) { 981 work_done = 982 ath12k_dp_mon_process_ring(ab, id, napi, budget, 983 monitor_mode); 984 budget -= work_done; 985 tot_work_done += work_done; 986 987 if (budget <= 0) 988 goto done; 989 } 990 } 991 } 992 } 993 994 if (ab->hw_params->ring_mask->reo_status[grp_id]) 995 ath12k_dp_rx_process_reo_status(ab); 996 997 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) { 998 struct ath12k_dp *dp = &ab->dp; 999 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 1000 LIST_HEAD(list); 1001 1002 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); 1003 } 1004 1005 /* TODO: Implement handler for other interrupts */ 1006 1007 done: 1008 return tot_work_done; 1009 } 1010 1011 void ath12k_dp_pdev_free(struct ath12k_base *ab) 1012 { 1013 int i; 1014 1015 for (i = 0; i < ab->num_radios; i++) 1016 ath12k_dp_rx_pdev_free(ab, i); 1017 } 1018 1019 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar) 1020 { 1021 struct ath12k_pdev_dp *dp = &ar->dp; 1022 1023 dp->mac_id = ar->pdev_idx; 1024 atomic_set(&dp->num_tx_pending, 0); 1025 init_waitqueue_head(&dp->tx_empty_waitq); 1026 /* TODO: Add any RXDMA setup required per pdev */ 1027 } 1028 1029 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab) 1030 { 1031 if (test_bit(WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS, ab->wmi_ab.svc_map) && 1032 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start && 1033 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end && 1034 ab->hw_params->hal_ops->get_hal_rx_compact_ops) { 1035 return true; 1036 } 1037 return false; 1038 } 1039 1040 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab) 1041 { 1042 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) { 1043 /* RX TLVS compaction is supported, hence change the hal_rx_ops 1044 * to compact hal_rx_ops. 1045 */ 1046 ab->hal_rx_ops = ab->hw_params->hal_ops->get_hal_rx_compact_ops(); 1047 } 1048 ab->hal.hal_desc_sz = 1049 ab->hal_rx_ops->rx_desc_get_desc_size(); 1050 } 1051 1052 int ath12k_dp_pdev_alloc(struct ath12k_base *ab) 1053 { 1054 struct ath12k *ar; 1055 int ret; 1056 int i; 1057 1058 ret = ath12k_dp_rx_htt_setup(ab); 1059 if (ret) 1060 goto out; 1061 1062 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */ 1063 for (i = 0; i < ab->num_radios; i++) { 1064 ar = ab->pdevs[i].ar; 1065 ret = ath12k_dp_rx_pdev_alloc(ab, i); 1066 if (ret) { 1067 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n", 1068 i); 1069 goto err; 1070 } 1071 ret = ath12k_dp_rx_pdev_mon_attach(ar); 1072 if (ret) { 1073 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i); 1074 goto err; 1075 } 1076 } 1077 1078 return 0; 1079 err: 1080 ath12k_dp_pdev_free(ab); 1081 out: 1082 return ret; 1083 } 1084 1085 int ath12k_dp_htt_connect(struct ath12k_dp *dp) 1086 { 1087 struct ath12k_htc_svc_conn_req conn_req = {0}; 1088 struct ath12k_htc_svc_conn_resp conn_resp = {0}; 1089 int status; 1090 1091 conn_req.ep_ops.ep_tx_complete = ath12k_dp_htt_htc_tx_complete; 1092 conn_req.ep_ops.ep_rx_complete = ath12k_dp_htt_htc_t2h_msg_handler; 1093 1094 /* connect to control service */ 1095 conn_req.service_id = ATH12K_HTC_SVC_ID_HTT_DATA_MSG; 1096 1097 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req, 1098 &conn_resp); 1099 1100 if (status) 1101 return status; 1102 1103 dp->eid = conn_resp.eid; 1104 1105 return 0; 1106 } 1107 1108 static void ath12k_dp_update_vdev_search(struct ath12k_link_vif *arvif) 1109 { 1110 switch (arvif->ahvif->vdev_type) { 1111 case WMI_VDEV_TYPE_STA: 1112 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN; 1113 arvif->search_type = HAL_TX_ADDR_SEARCH_INDEX; 1114 break; 1115 case WMI_VDEV_TYPE_AP: 1116 case WMI_VDEV_TYPE_IBSS: 1117 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 1118 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 1119 break; 1120 case WMI_VDEV_TYPE_MONITOR: 1121 default: 1122 return; 1123 } 1124 } 1125 1126 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif) 1127 { 1128 struct ath12k_base *ab = ar->ab; 1129 1130 arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) | 1131 u32_encode_bits(arvif->vdev_id, 1132 HTT_TCL_META_DATA_VDEV_ID) | 1133 u32_encode_bits(ar->pdev->pdev_id, 1134 HTT_TCL_META_DATA_PDEV_ID); 1135 1136 /* set HTT extension valid bit to 0 by default */ 1137 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; 1138 1139 ath12k_dp_update_vdev_search(arvif); 1140 arvif->vdev_id_check_en = true; 1141 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp); 1142 1143 /* TODO: error path for bank id failure */ 1144 if (arvif->bank_id == DP_INVALID_BANK_ID) { 1145 ath12k_err(ar->ab, "Failed to initialize DP TX Banks"); 1146 return; 1147 } 1148 } 1149 1150 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) 1151 { 1152 struct ath12k_rx_desc_info *desc_info; 1153 struct ath12k_tx_desc_info *tx_desc_info, *tmp1; 1154 struct ath12k_dp *dp = &ab->dp; 1155 struct ath12k_skb_cb *skb_cb; 1156 struct sk_buff *skb; 1157 struct ath12k *ar; 1158 int i, j; 1159 u32 pool_id, tx_spt_page; 1160 1161 if (!dp->spt_info) 1162 return; 1163 1164 /* RX Descriptor cleanup */ 1165 spin_lock_bh(&dp->rx_desc_lock); 1166 1167 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { 1168 desc_info = dp->rxbaddr[i]; 1169 1170 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1171 if (!desc_info[j].in_use) { 1172 list_del(&desc_info[j].list); 1173 continue; 1174 } 1175 1176 skb = desc_info[j].skb; 1177 if (!skb) 1178 continue; 1179 1180 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 1181 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 1182 dev_kfree_skb_any(skb); 1183 } 1184 } 1185 1186 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { 1187 if (!dp->rxbaddr[i]) 1188 continue; 1189 1190 kfree(dp->rxbaddr[i]); 1191 dp->rxbaddr[i] = NULL; 1192 } 1193 1194 spin_unlock_bh(&dp->rx_desc_lock); 1195 1196 /* TX Descriptor cleanup */ 1197 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { 1198 spin_lock_bh(&dp->tx_desc_lock[i]); 1199 1200 list_for_each_entry_safe(tx_desc_info, tmp1, &dp->tx_desc_used_list[i], 1201 list) { 1202 list_del(&tx_desc_info->list); 1203 skb = tx_desc_info->skb; 1204 1205 if (!skb) 1206 continue; 1207 1208 skb_cb = ATH12K_SKB_CB(skb); 1209 if (skb_cb->paddr_ext_desc) { 1210 dma_unmap_single(ab->dev, 1211 skb_cb->paddr_ext_desc, 1212 tx_desc_info->skb_ext_desc->len, 1213 DMA_TO_DEVICE); 1214 dev_kfree_skb_any(tx_desc_info->skb_ext_desc); 1215 } 1216 1217 /* if we are unregistering, hw would've been destroyed and 1218 * ar is no longer valid. 1219 */ 1220 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) { 1221 ar = skb_cb->ar; 1222 1223 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 1224 wake_up(&ar->dp.tx_empty_waitq); 1225 } 1226 1227 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, 1228 skb->len, DMA_TO_DEVICE); 1229 dev_kfree_skb_any(skb); 1230 } 1231 1232 spin_unlock_bh(&dp->tx_desc_lock[i]); 1233 } 1234 1235 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { 1236 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 1237 1238 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { 1239 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; 1240 if (!dp->txbaddr[tx_spt_page]) 1241 continue; 1242 1243 kfree(dp->txbaddr[tx_spt_page]); 1244 dp->txbaddr[tx_spt_page] = NULL; 1245 } 1246 1247 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1248 } 1249 1250 /* unmap SPT pages */ 1251 for (i = 0; i < dp->num_spt_pages; i++) { 1252 if (!dp->spt_info[i].vaddr) 1253 continue; 1254 1255 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE, 1256 dp->spt_info[i].vaddr, dp->spt_info[i].paddr); 1257 dp->spt_info[i].vaddr = NULL; 1258 } 1259 1260 kfree(dp->spt_info); 1261 dp->spt_info = NULL; 1262 } 1263 1264 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab) 1265 { 1266 struct ath12k_dp *dp = &ab->dp; 1267 1268 if (!ab->hw_params->reoq_lut_support) 1269 return; 1270 1271 if (dp->reoq_lut.vaddr_unaligned) { 1272 ath12k_hif_write32(ab, 1273 HAL_SEQ_WCSS_UMAC_REO_REG + 1274 HAL_REO1_QDESC_LUT_BASE0(ab), 0); 1275 dma_free_coherent(ab->dev, dp->reoq_lut.size, 1276 dp->reoq_lut.vaddr_unaligned, 1277 dp->reoq_lut.paddr_unaligned); 1278 dp->reoq_lut.vaddr_unaligned = NULL; 1279 } 1280 1281 if (dp->ml_reoq_lut.vaddr_unaligned) { 1282 ath12k_hif_write32(ab, 1283 HAL_SEQ_WCSS_UMAC_REO_REG + 1284 HAL_REO1_QDESC_LUT_BASE1(ab), 0); 1285 dma_free_coherent(ab->dev, dp->ml_reoq_lut.size, 1286 dp->ml_reoq_lut.vaddr_unaligned, 1287 dp->ml_reoq_lut.paddr_unaligned); 1288 dp->ml_reoq_lut.vaddr_unaligned = NULL; 1289 } 1290 } 1291 1292 void ath12k_dp_free(struct ath12k_base *ab) 1293 { 1294 struct ath12k_dp *dp = &ab->dp; 1295 int i; 1296 1297 if (!dp->ab) 1298 return; 1299 1300 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1301 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1302 1303 ath12k_dp_cc_cleanup(ab); 1304 ath12k_dp_reoq_lut_cleanup(ab); 1305 ath12k_dp_deinit_bank_profiles(ab); 1306 ath12k_dp_srng_common_cleanup(ab); 1307 1308 ath12k_dp_rx_reo_cmd_list_cleanup(ab); 1309 1310 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 1311 kfree(dp->tx_ring[i].tx_status); 1312 dp->tx_ring[i].tx_status = NULL; 1313 } 1314 1315 ath12k_dp_rx_free(ab); 1316 /* Deinit any SOC level resource */ 1317 dp->ab = NULL; 1318 } 1319 1320 void ath12k_dp_cc_config(struct ath12k_base *ab) 1321 { 1322 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; 1323 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 1324 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG; 1325 u32 val = 0; 1326 1327 if (ath12k_ftm_mode) 1328 return; 1329 1330 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base); 1331 1332 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB, 1333 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) | 1334 u32_encode_bits(ATH12K_CC_PPT_MSB, 1335 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) | 1336 u32_encode_bits(ATH12K_CC_SPT_MSB, 1337 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) | 1338 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) | 1339 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) | 1340 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE); 1341 1342 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val); 1343 1344 /* Enable HW CC for WBM */ 1345 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base); 1346 1347 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB, 1348 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) | 1349 u32_encode_bits(ATH12K_CC_PPT_MSB, 1350 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) | 1351 u32_encode_bits(ATH12K_CC_SPT_MSB, 1352 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) | 1353 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN); 1354 1355 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val); 1356 1357 /* Enable conversion complete indication */ 1358 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2); 1359 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) | 1360 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) | 1361 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN); 1362 1363 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val); 1364 1365 /* Enable Cookie conversion for WBM2SW Rings */ 1366 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG); 1367 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) | 1368 ab->hw_params->hal_params->wbm2sw_cc_enable; 1369 1370 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val); 1371 } 1372 1373 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx) 1374 { 1375 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx; 1376 } 1377 1378 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab, 1379 u16 ppt_idx, u16 spt_idx) 1380 { 1381 struct ath12k_dp *dp = &ab->dp; 1382 1383 return dp->spt_info[ppt_idx].vaddr + spt_idx; 1384 } 1385 1386 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1387 u32 cookie) 1388 { 1389 struct ath12k_dp *dp = &ab->dp; 1390 struct ath12k_rx_desc_info **desc_addr_ptr; 1391 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx; 1392 1393 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); 1394 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT); 1395 1396 start_ppt_idx = dp->rx_ppt_base + ATH12K_RX_SPT_PAGE_OFFSET; 1397 end_ppt_idx = start_ppt_idx + ATH12K_NUM_RX_SPT_PAGES; 1398 1399 if (ppt_idx < start_ppt_idx || 1400 ppt_idx >= end_ppt_idx || 1401 spt_idx > ATH12K_MAX_SPT_ENTRIES) 1402 return NULL; 1403 1404 ppt_idx = ppt_idx - dp->rx_ppt_base; 1405 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx); 1406 1407 return *desc_addr_ptr; 1408 } 1409 1410 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1411 u32 cookie) 1412 { 1413 struct ath12k_tx_desc_info **desc_addr_ptr; 1414 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx; 1415 1416 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); 1417 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT); 1418 1419 start_ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET; 1420 end_ppt_idx = start_ppt_idx + 1421 (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES); 1422 1423 if (ppt_idx < start_ppt_idx || 1424 ppt_idx >= end_ppt_idx || 1425 spt_idx > ATH12K_MAX_SPT_ENTRIES) 1426 return NULL; 1427 1428 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx); 1429 1430 return *desc_addr_ptr; 1431 } 1432 1433 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab) 1434 { 1435 struct ath12k_dp *dp = &ab->dp; 1436 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr; 1437 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr; 1438 u32 i, j, pool_id, tx_spt_page; 1439 u32 ppt_idx, cookie_ppt_idx; 1440 1441 spin_lock_bh(&dp->rx_desc_lock); 1442 1443 /* First ATH12K_NUM_RX_SPT_PAGES of allocated SPT pages are used for RX */ 1444 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { 1445 rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs), 1446 GFP_ATOMIC); 1447 1448 if (!rx_descs) { 1449 spin_unlock_bh(&dp->rx_desc_lock); 1450 return -ENOMEM; 1451 } 1452 1453 ppt_idx = ATH12K_RX_SPT_PAGE_OFFSET + i; 1454 cookie_ppt_idx = dp->rx_ppt_base + ppt_idx; 1455 dp->rxbaddr[i] = &rx_descs[0]; 1456 1457 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1458 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(cookie_ppt_idx, j); 1459 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC; 1460 rx_descs[j].device_id = ab->device_id; 1461 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list); 1462 1463 /* Update descriptor VA in SPT */ 1464 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j); 1465 *rx_desc_addr = &rx_descs[j]; 1466 } 1467 } 1468 1469 spin_unlock_bh(&dp->rx_desc_lock); 1470 1471 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { 1472 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 1473 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { 1474 tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*tx_descs), 1475 GFP_ATOMIC); 1476 1477 if (!tx_descs) { 1478 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1479 /* Caller takes care of TX pending and RX desc cleanup */ 1480 return -ENOMEM; 1481 } 1482 1483 tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; 1484 ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET + tx_spt_page; 1485 1486 dp->txbaddr[tx_spt_page] = &tx_descs[0]; 1487 1488 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1489 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j); 1490 tx_descs[j].pool_id = pool_id; 1491 list_add_tail(&tx_descs[j].list, 1492 &dp->tx_desc_free_list[pool_id]); 1493 1494 /* Update descriptor VA in SPT */ 1495 tx_desc_addr = 1496 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j); 1497 *tx_desc_addr = &tx_descs[j]; 1498 } 1499 } 1500 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1501 } 1502 return 0; 1503 } 1504 1505 static int ath12k_dp_cmem_init(struct ath12k_base *ab, 1506 struct ath12k_dp *dp, 1507 enum ath12k_dp_desc_type type) 1508 { 1509 u32 cmem_base; 1510 int i, start, end; 1511 1512 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; 1513 1514 switch (type) { 1515 case ATH12K_DP_TX_DESC: 1516 start = ATH12K_TX_SPT_PAGE_OFFSET; 1517 end = start + ATH12K_NUM_TX_SPT_PAGES; 1518 break; 1519 case ATH12K_DP_RX_DESC: 1520 cmem_base += ATH12K_PPT_ADDR_OFFSET(dp->rx_ppt_base); 1521 start = ATH12K_RX_SPT_PAGE_OFFSET; 1522 end = start + ATH12K_NUM_RX_SPT_PAGES; 1523 break; 1524 default: 1525 ath12k_err(ab, "invalid descriptor type %d in cmem init\n", type); 1526 return -EINVAL; 1527 } 1528 1529 /* Write to PPT in CMEM */ 1530 for (i = start; i < end; i++) 1531 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), 1532 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); 1533 1534 return 0; 1535 } 1536 1537 void ath12k_dp_partner_cc_init(struct ath12k_base *ab) 1538 { 1539 struct ath12k_hw_group *ag = ab->ag; 1540 int i; 1541 1542 for (i = 0; i < ag->num_devices; i++) { 1543 if (ag->ab[i] == ab) 1544 continue; 1545 1546 ath12k_dp_cmem_init(ab, &ag->ab[i]->dp, ATH12K_DP_RX_DESC); 1547 } 1548 } 1549 1550 static int ath12k_dp_cc_init(struct ath12k_base *ab) 1551 { 1552 struct ath12k_dp *dp = &ab->dp; 1553 int i, ret = 0; 1554 1555 INIT_LIST_HEAD(&dp->rx_desc_free_list); 1556 spin_lock_init(&dp->rx_desc_lock); 1557 1558 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { 1559 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]); 1560 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]); 1561 spin_lock_init(&dp->tx_desc_lock[i]); 1562 } 1563 1564 dp->num_spt_pages = ATH12K_NUM_SPT_PAGES; 1565 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES) 1566 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES; 1567 1568 dp->spt_info = kcalloc(dp->num_spt_pages, sizeof(struct ath12k_spt_info), 1569 GFP_KERNEL); 1570 1571 if (!dp->spt_info) { 1572 ath12k_warn(ab, "SPT page allocation failure"); 1573 return -ENOMEM; 1574 } 1575 1576 dp->rx_ppt_base = ab->device_id * ATH12K_NUM_RX_SPT_PAGES; 1577 1578 for (i = 0; i < dp->num_spt_pages; i++) { 1579 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev, 1580 ATH12K_PAGE_SIZE, 1581 &dp->spt_info[i].paddr, 1582 GFP_KERNEL); 1583 1584 if (!dp->spt_info[i].vaddr) { 1585 ret = -ENOMEM; 1586 goto free; 1587 } 1588 1589 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) { 1590 ath12k_warn(ab, "SPT allocated memory is not 4K aligned"); 1591 ret = -EINVAL; 1592 goto free; 1593 } 1594 } 1595 1596 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_TX_DESC); 1597 if (ret) { 1598 ath12k_warn(ab, "HW CC Tx cmem init failed %d", ret); 1599 goto free; 1600 } 1601 1602 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_RX_DESC); 1603 if (ret) { 1604 ath12k_warn(ab, "HW CC Rx cmem init failed %d", ret); 1605 goto free; 1606 } 1607 1608 ret = ath12k_dp_cc_desc_init(ab); 1609 if (ret) { 1610 ath12k_warn(ab, "HW CC desc init failed %d", ret); 1611 goto free; 1612 } 1613 1614 return 0; 1615 free: 1616 ath12k_dp_cc_cleanup(ab); 1617 return ret; 1618 } 1619 1620 static int ath12k_dp_alloc_reoq_lut(struct ath12k_base *ab, 1621 struct ath12k_reo_q_addr_lut *lut) 1622 { 1623 lut->size = DP_REOQ_LUT_SIZE + HAL_REO_QLUT_ADDR_ALIGN - 1; 1624 lut->vaddr_unaligned = dma_alloc_coherent(ab->dev, lut->size, 1625 &lut->paddr_unaligned, 1626 GFP_KERNEL | __GFP_ZERO); 1627 if (!lut->vaddr_unaligned) 1628 return -ENOMEM; 1629 1630 lut->vaddr = PTR_ALIGN(lut->vaddr_unaligned, HAL_REO_QLUT_ADDR_ALIGN); 1631 lut->paddr = lut->paddr_unaligned + 1632 ((unsigned long)lut->vaddr - (unsigned long)lut->vaddr_unaligned); 1633 return 0; 1634 } 1635 1636 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab) 1637 { 1638 struct ath12k_dp *dp = &ab->dp; 1639 u32 val; 1640 int ret; 1641 1642 if (!ab->hw_params->reoq_lut_support) 1643 return 0; 1644 1645 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->reoq_lut); 1646 if (ret) { 1647 ath12k_warn(ab, "failed to allocate memory for reoq table"); 1648 return ret; 1649 } 1650 1651 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->ml_reoq_lut); 1652 if (ret) { 1653 ath12k_warn(ab, "failed to allocate memory for ML reoq table"); 1654 dma_free_coherent(ab->dev, dp->reoq_lut.size, 1655 dp->reoq_lut.vaddr_unaligned, 1656 dp->reoq_lut.paddr_unaligned); 1657 dp->reoq_lut.vaddr_unaligned = NULL; 1658 return ret; 1659 } 1660 1661 /* Bits in the register have address [39:8] LUT base address to be 1662 * allocated such that LSBs are assumed to be zero. Also, current 1663 * design supports paddr up to 4 GB max hence it fits in 32 bit 1664 * register only 1665 */ 1666 1667 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 1668 dp->reoq_lut.paddr >> 8); 1669 1670 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE1(ab), 1671 dp->ml_reoq_lut.paddr >> 8); 1672 1673 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(ab)); 1674 1675 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(ab), 1676 val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE); 1677 1678 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(ab), 1679 HAL_REO_QDESC_MAX_PEERID); 1680 1681 return 0; 1682 } 1683 1684 static enum hal_rx_buf_return_buf_manager 1685 ath12k_dp_get_idle_link_rbm(struct ath12k_base *ab) 1686 { 1687 switch (ab->device_id) { 1688 case 0: 1689 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST; 1690 case 1: 1691 return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST; 1692 case 2: 1693 return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST; 1694 default: 1695 ath12k_warn(ab, "invalid %d device id, so choose default rbm\n", 1696 ab->device_id); 1697 WARN_ON(1); 1698 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST; 1699 } 1700 } 1701 1702 int ath12k_dp_alloc(struct ath12k_base *ab) 1703 { 1704 struct ath12k_dp *dp = &ab->dp; 1705 struct hal_srng *srng = NULL; 1706 size_t size = 0; 1707 u32 n_link_desc = 0; 1708 int ret; 1709 int i; 1710 1711 dp->ab = ab; 1712 1713 INIT_LIST_HEAD(&dp->reo_cmd_list); 1714 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); 1715 spin_lock_init(&dp->reo_cmd_lock); 1716 1717 dp->reo_cmd_cache_flush_count = 0; 1718 dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab); 1719 1720 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc); 1721 if (ret) { 1722 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 1723 return ret; 1724 } 1725 1726 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id]; 1727 1728 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks, 1729 HAL_WBM_IDLE_LINK, srng, n_link_desc); 1730 if (ret) { 1731 ath12k_warn(ab, "failed to setup link desc: %d\n", ret); 1732 return ret; 1733 } 1734 1735 ret = ath12k_dp_cc_init(ab); 1736 1737 if (ret) { 1738 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret); 1739 goto fail_link_desc_cleanup; 1740 } 1741 ret = ath12k_dp_init_bank_profiles(ab); 1742 if (ret) { 1743 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret); 1744 goto fail_hw_cc_cleanup; 1745 } 1746 1747 ret = ath12k_dp_srng_common_setup(ab); 1748 if (ret) 1749 goto fail_dp_bank_profiles_cleanup; 1750 1751 size = sizeof(struct hal_wbm_release_ring_tx) * DP_TX_COMP_RING_SIZE; 1752 1753 ret = ath12k_dp_reoq_lut_setup(ab); 1754 if (ret) { 1755 ath12k_warn(ab, "failed to setup reoq table %d\n", ret); 1756 goto fail_cmn_srng_cleanup; 1757 } 1758 1759 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 1760 dp->tx_ring[i].tcl_data_ring_id = i; 1761 1762 dp->tx_ring[i].tx_status_head = 0; 1763 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1; 1764 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL); 1765 if (!dp->tx_ring[i].tx_status) { 1766 ret = -ENOMEM; 1767 /* FIXME: The allocated tx status is not freed 1768 * properly here 1769 */ 1770 goto fail_cmn_reoq_cleanup; 1771 } 1772 } 1773 1774 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++) 1775 ath12k_hal_tx_set_dscp_tid_map(ab, i); 1776 1777 ret = ath12k_dp_rx_alloc(ab); 1778 if (ret) 1779 goto fail_dp_rx_free; 1780 1781 /* Init any SOC level resource for DP */ 1782 1783 return 0; 1784 1785 fail_dp_rx_free: 1786 ath12k_dp_rx_free(ab); 1787 1788 fail_cmn_reoq_cleanup: 1789 ath12k_dp_reoq_lut_cleanup(ab); 1790 1791 fail_cmn_srng_cleanup: 1792 ath12k_dp_srng_common_cleanup(ab); 1793 1794 fail_dp_bank_profiles_cleanup: 1795 ath12k_dp_deinit_bank_profiles(ab); 1796 1797 fail_hw_cc_cleanup: 1798 ath12k_dp_cc_cleanup(ab); 1799 1800 fail_link_desc_cleanup: 1801 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1802 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1803 1804 return ret; 1805 } 1806