1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) 11 #define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 12 #define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 13 #define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 14 #define ATH12K_HTT_STATS_SUBTYPE_MAX 16 15 #define ATH12K_HTT_MAX_STRING_LEN 256 16 17 #define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f) 18 #define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f) 19 #define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \ 20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx)) 21 #define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \ 22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx)) 23 24 void ath12k_debugfs_htt_stats_register(struct ath12k *ar); 25 26 #ifdef CONFIG_ATH12K_DEBUGFS 27 void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 28 struct sk_buff *skb); 29 #else /* CONFIG_ATH12K_DEBUGFS */ 30 static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 31 struct sk_buff *skb) 32 { 33 } 34 #endif 35 36 /** 37 * DOC: target -> host extended statistics upload 38 * 39 * The following field definitions describe the format of the HTT 40 * target to host stats upload confirmation message. 41 * The message contains a cookie echoed from the HTT host->target stats 42 * upload request, which identifies which request the confirmation is 43 * for, and a single stats can span over multiple HTT stats indication 44 * due to the HTT message size limitation so every HTT ext stats 45 * indication will have tag-length-value stats information elements. 46 * The tag-length header for each HTT stats IND message also includes a 47 * status field, to indicate whether the request for the stat type in 48 * question was fully met, partially met, unable to be met, or invalid 49 * (if the stat type in question is disabled in the target). 50 * A Done bit 1's indicate the end of the of stats info elements. 51 * 52 * 53 * |31 16|15 12|11|10 8|7 5|4 0| 54 * |--------------------------------------------------------------| 55 * | reserved | msg type | 56 * |--------------------------------------------------------------| 57 * | cookie LSBs | 58 * |--------------------------------------------------------------| 59 * | cookie MSBs | 60 * |--------------------------------------------------------------| 61 * | stats entry length | rsvd | D| S | stat type | 62 * |--------------------------------------------------------------| 63 * | type-specific stats info | 64 * | (see debugfs_htt_stats.h) | 65 * |--------------------------------------------------------------| 66 * Header fields: 67 * - MSG_TYPE 68 * Bits 7:0 69 * Purpose: Identifies this is a extended statistics upload confirmation 70 * message. 71 * Value: 0x1c 72 * - COOKIE_LSBS 73 * Bits 31:0 74 * Purpose: Provide a mechanism to match a target->host stats confirmation 75 * message with its preceding host->target stats request message. 76 * Value: MSBs of the opaque cookie specified by the host-side requestor 77 * - COOKIE_MSBS 78 * Bits 31:0 79 * Purpose: Provide a mechanism to match a target->host stats confirmation 80 * message with its preceding host->target stats request message. 81 * Value: MSBs of the opaque cookie specified by the host-side requestor 82 * 83 * Stats Information Element tag-length header fields: 84 * - STAT_TYPE 85 * Bits 7:0 86 * Purpose: identifies the type of statistics info held in the 87 * following information element 88 * Value: ath12k_dbg_htt_ext_stats_type 89 * - STATUS 90 * Bits 10:8 91 * Purpose: indicate whether the requested stats are present 92 * Value: 93 * 0 -> The requested stats have been delivered in full 94 * 1 -> The requested stats have been delivered in part 95 * 2 -> The requested stats could not be delivered (error case) 96 * 3 -> The requested stat type is either not recognized (invalid) 97 * - DONE 98 * Bits 11 99 * Purpose: 100 * Indicates the completion of the stats entry, this will be the last 101 * stats conf HTT segment for the requested stats type. 102 * Value: 103 * 0 -> the stats retrieval is ongoing 104 * 1 -> the stats retrieval is complete 105 * - LENGTH 106 * Bits 31:16 107 * Purpose: indicate the stats information size 108 * Value: This field specifies the number of bytes of stats information 109 * that follows the element tag-length header. 110 * It is expected but not required that this length is a multiple of 111 * 4 bytes. 112 */ 113 114 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 115 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 116 117 struct ath12k_htt_extd_stats_msg { 118 __le32 info0; 119 __le64 cookie; 120 __le32 info1; 121 u8 data[]; 122 } __packed; 123 124 /* htt_dbg_ext_stats_type */ 125 enum ath12k_dbg_htt_ext_stats_type { 126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0, 127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, 128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, 129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, 130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, 131 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8, 132 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12, 133 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15, 134 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16, 135 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17, 136 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19, 137 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 138 ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36, 139 ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 140 ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38, 141 ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40, 142 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45, 143 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49, 144 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51, 145 ATH12K_DGB_HTT_EXT_STATS_PDEV_MBSSID_CTRL_FRAME = 54, 146 147 /* keep this last */ 148 ATH12K_DBG_HTT_NUM_EXT_STATS, 149 }; 150 151 enum ath12k_dbg_htt_tlv_tag { 152 HTT_STATS_TX_PDEV_CMN_TAG = 0, 153 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 154 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 155 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 156 HTT_STATS_STRING_TAG = 5, 157 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 158 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 159 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 160 HTT_STATS_TX_TQM_CMN_TAG = 14, 161 HTT_STATS_TX_TQM_PDEV_TAG = 15, 162 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 163 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 164 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 165 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 166 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 167 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 168 HTT_STATS_TX_DE_CMN_TAG = 23, 169 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 170 HTT_STATS_SFM_CMN_TAG = 26, 171 HTT_STATS_SRING_STATS_TAG = 27, 172 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 173 HTT_STATS_TX_SCHED_CMN_TAG = 37, 174 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 175 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 176 HTT_STATS_SFM_CLIENT_TAG = 42, 177 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 178 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 179 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 180 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 181 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 182 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 183 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 184 HTT_STATS_HW_INTR_MISC_TAG = 54, 185 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 186 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 187 HTT_STATS_WHAL_TX_TAG = 66, 188 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 189 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 190 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 191 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 192 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 193 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 194 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 195 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 196 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 197 HTT_STATS_HW_WAR_TAG = 89, 198 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, 199 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, 200 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, 201 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, 202 HTT_STATS_DLPAGER_STATS_TAG = 120, 203 HTT_STATS_PHY_COUNTERS_TAG = 121, 204 HTT_STATS_PHY_STATS_TAG = 122, 205 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, 206 HTT_STATS_PHY_RESET_STATS_TAG = 124, 207 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, 208 HTT_STATS_PER_RATE_STATS_TAG = 128, 209 HTT_STATS_MU_PPDU_DIST_TAG = 129, 210 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, 211 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, 212 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, 213 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, 214 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, 215 HTT_STATS_DMAC_RESET_STATS_TAG = 155, 216 HTT_STATS_PHY_TPC_STATS_TAG = 157, 217 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, 218 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, 219 220 HTT_STATS_MAX_TAG, 221 }; 222 223 #define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0) 224 225 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 226 #define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 227 228 /* MU MIMO distribution stats is a 2-dimensional array 229 * with dimension one denoting stats for nr4[0] or nr8[1] 230 */ 231 #define ATH12K_HTT_STATS_NUM_NR_BINS 2 232 #define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 233 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 234 #define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9 235 #define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \ 236 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS) 237 #define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \ 238 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 239 240 enum ath12k_htt_tx_pdev_underrun_enum { 241 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 242 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 243 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 244 HTT_TX_PDEV_MAX_URRN_STATS = 3, 245 }; 246 247 enum ath12k_htt_stats_reset_cfg_param_alloc_pos { 248 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1, 249 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES, 250 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES, 251 }; 252 253 struct debug_htt_stats_req { 254 bool done; 255 bool override_cfg_param; 256 u8 pdev_id; 257 enum ath12k_dbg_htt_ext_stats_type type; 258 u32 cfg_param[4]; 259 u8 peer_addr[ETH_ALEN]; 260 struct completion htt_stats_rcvd; 261 u32 buf_len; 262 u8 buf[]; 263 }; 264 265 struct ath12k_htt_tx_pdev_stats_cmn_tlv { 266 __le32 mac_id__word; 267 __le32 hw_queued; 268 __le32 hw_reaped; 269 __le32 underrun; 270 __le32 hw_paused; 271 __le32 hw_flush; 272 __le32 hw_filt; 273 __le32 tx_abort; 274 __le32 mpdu_requed; 275 __le32 tx_xretry; 276 __le32 data_rc; 277 __le32 mpdu_dropped_xretry; 278 __le32 illgl_rate_phy_err; 279 __le32 cont_xretry; 280 __le32 tx_timeout; 281 __le32 pdev_resets; 282 __le32 phy_underrun; 283 __le32 txop_ovf; 284 __le32 seq_posted; 285 __le32 seq_failed_queueing; 286 __le32 seq_completed; 287 __le32 seq_restarted; 288 __le32 mu_seq_posted; 289 __le32 seq_switch_hw_paused; 290 __le32 next_seq_posted_dsr; 291 __le32 seq_posted_isr; 292 __le32 seq_ctrl_cached; 293 __le32 mpdu_count_tqm; 294 __le32 msdu_count_tqm; 295 __le32 mpdu_removed_tqm; 296 __le32 msdu_removed_tqm; 297 __le32 mpdus_sw_flush; 298 __le32 mpdus_hw_filter; 299 __le32 mpdus_truncated; 300 __le32 mpdus_ack_failed; 301 __le32 mpdus_expired; 302 __le32 mpdus_seq_hw_retry; 303 __le32 ack_tlv_proc; 304 __le32 coex_abort_mpdu_cnt_valid; 305 __le32 coex_abort_mpdu_cnt; 306 __le32 num_total_ppdus_tried_ota; 307 __le32 num_data_ppdus_tried_ota; 308 __le32 local_ctrl_mgmt_enqued; 309 __le32 local_ctrl_mgmt_freed; 310 __le32 local_data_enqued; 311 __le32 local_data_freed; 312 __le32 mpdu_tried; 313 __le32 isr_wait_seq_posted; 314 315 __le32 tx_active_dur_us_low; 316 __le32 tx_active_dur_us_high; 317 __le32 remove_mpdus_max_retries; 318 __le32 comp_delivered; 319 __le32 ppdu_ok; 320 __le32 self_triggers; 321 __le32 tx_time_dur_data; 322 __le32 seq_qdepth_repost_stop; 323 __le32 mu_seq_min_msdu_repost_stop; 324 __le32 seq_min_msdu_repost_stop; 325 __le32 seq_txop_repost_stop; 326 __le32 next_seq_cancel; 327 __le32 fes_offsets_err_cnt; 328 __le32 num_mu_peer_blacklisted; 329 __le32 mu_ofdma_seq_posted; 330 __le32 ul_mumimo_seq_posted; 331 __le32 ul_ofdma_seq_posted; 332 333 __le32 thermal_suspend_cnt; 334 __le32 dfs_suspend_cnt; 335 __le32 tx_abort_suspend_cnt; 336 __le32 tgt_specific_opaque_txq_suspend_info; 337 __le32 last_suspend_reason; 338 } __packed; 339 340 struct ath12k_htt_tx_pdev_stats_urrn_tlv { 341 DECLARE_FLEX_ARRAY(__le32, urrn_stats); 342 } __packed; 343 344 struct ath12k_htt_tx_pdev_stats_flush_tlv { 345 DECLARE_FLEX_ARRAY(__le32, flush_errs); 346 } __packed; 347 348 struct ath12k_htt_tx_pdev_stats_phy_err_tlv { 349 DECLARE_FLEX_ARRAY(__le32, phy_errs); 350 } __packed; 351 352 struct ath12k_htt_tx_pdev_stats_sifs_tlv { 353 DECLARE_FLEX_ARRAY(__le32, sifs_status); 354 } __packed; 355 356 struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv { 357 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 358 } __packed; 359 360 struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv { 361 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status); 362 } __packed; 363 364 enum ath12k_htt_stats_hw_mode { 365 ATH12K_HTT_STATS_HWMODE_AC = 0, 366 ATH12K_HTT_STATS_HWMODE_AX = 1, 367 ATH12K_HTT_STATS_HWMODE_BE = 2, 368 }; 369 370 struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv { 371 __le32 hw_mode; 372 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS]; 373 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 374 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS]; 375 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 376 } __packed; 377 378 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 379 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 380 381 #define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 382 383 struct ath12k_htt_stats_tx_sched_cmn_tlv { 384 __le32 mac_id__word; 385 __le32 current_timestamp; 386 } __packed; 387 388 struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv { 389 __le32 mac_id__word; 390 __le32 sched_policy; 391 __le32 last_sched_cmd_posted_timestamp; 392 __le32 last_sched_cmd_compl_timestamp; 393 __le32 sched_2_tac_lwm_count; 394 __le32 sched_2_tac_ring_full; 395 __le32 sched_cmd_post_failure; 396 __le32 num_active_tids; 397 __le32 num_ps_schedules; 398 __le32 sched_cmds_pending; 399 __le32 num_tid_register; 400 __le32 num_tid_unregister; 401 __le32 num_qstats_queried; 402 __le32 qstats_update_pending; 403 __le32 last_qstats_query_timestamp; 404 __le32 num_tqm_cmdq_full; 405 __le32 num_de_sched_algo_trigger; 406 __le32 num_rt_sched_algo_trigger; 407 __le32 num_tqm_sched_algo_trigger; 408 __le32 notify_sched; 409 __le32 dur_based_sendn_term; 410 __le32 su_notify2_sched; 411 __le32 su_optimal_queued_msdus_sched; 412 __le32 su_delay_timeout_sched; 413 __le32 su_min_txtime_sched_delay; 414 __le32 su_no_delay; 415 __le32 num_supercycles; 416 __le32 num_subcycles_with_sort; 417 __le32 num_subcycles_no_sort; 418 } __packed; 419 420 struct ath12k_htt_sched_txq_cmd_posted_tlv { 421 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted); 422 } __packed; 423 424 struct ath12k_htt_sched_txq_cmd_reaped_tlv { 425 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped); 426 } __packed; 427 428 struct ath12k_htt_sched_txq_sched_order_su_tlv { 429 DECLARE_FLEX_ARRAY(__le32, sched_order_su); 430 } __packed; 431 432 struct ath12k_htt_sched_txq_sched_ineligibility_tlv { 433 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility); 434 } __packed; 435 436 enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum { 437 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, 438 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, 439 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, 440 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, 441 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, 442 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, 443 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, 444 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 445 }; 446 447 struct ath12k_htt_sched_txq_supercycle_triggers_tlv { 448 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers); 449 } __packed; 450 451 struct ath12k_htt_hw_stats_pdev_errs_tlv { 452 __le32 mac_id__word; 453 __le32 tx_abort; 454 __le32 tx_abort_fail_count; 455 __le32 rx_abort; 456 __le32 rx_abort_fail_count; 457 __le32 warm_reset; 458 __le32 cold_reset; 459 __le32 tx_flush; 460 __le32 tx_glb_reset; 461 __le32 tx_txq_reset; 462 __le32 rx_timeout_reset; 463 __le32 mac_cold_reset_restore_cal; 464 __le32 mac_cold_reset; 465 __le32 mac_warm_reset; 466 __le32 mac_only_reset; 467 __le32 phy_warm_reset; 468 __le32 phy_warm_reset_ucode_trig; 469 __le32 mac_warm_reset_restore_cal; 470 __le32 mac_sfm_reset; 471 __le32 phy_warm_reset_m3_ssr; 472 __le32 phy_warm_reset_reason_phy_m3; 473 __le32 phy_warm_reset_reason_tx_hw_stuck; 474 __le32 phy_warm_reset_reason_num_rx_frame_stuck; 475 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy; 476 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng; 477 __le32 phy_warm_reset_reason_mac_conv_phy_reset; 478 __le32 wal_rx_recovery_rst_mac_hang_cnt; 479 __le32 wal_rx_recovery_rst_known_sig_cnt; 480 __le32 wal_rx_recovery_rst_no_rx_cnt; 481 __le32 wal_rx_recovery_rst_no_rx_consec_cnt; 482 __le32 wal_rx_recovery_rst_rx_busy_cnt; 483 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt; 484 __le32 rx_flush_cnt; 485 __le32 phy_warm_reset_reason_tx_exp_cca_stuck; 486 __le32 phy_warm_reset_reason_tx_consec_flsh_war; 487 __le32 phy_warm_reset_reason_tx_hwsch_reset_war; 488 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war; 489 __le32 fw_rx_rings_reset; 490 __le32 rx_dest_drain_rx_descs_leak_prevented; 491 __le32 rx_dest_drain_rx_descs_saved_cnt; 492 __le32 rx_dest_drain_rxdma2reo_leak_detected; 493 __le32 rx_dest_drain_rxdma2fw_leak_detected; 494 __le32 rx_dest_drain_rxdma2wbm_leak_detected; 495 __le32 rx_dest_drain_rxdma1_2sw_leak_detected; 496 __le32 rx_dest_drain_rx_drain_ok_mac_idle; 497 __le32 rx_dest_drain_ok_mac_not_idle; 498 __le32 rx_dest_drain_prerequisite_invld; 499 __le32 rx_dest_drain_skip_non_lmac_reset; 500 __le32 rx_dest_drain_hw_fifo_notempty_post_wait; 501 } __packed; 502 503 #define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8 504 struct ath12k_htt_hw_stats_intr_misc_tlv { 505 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN]; 506 __le32 mask; 507 __le32 count; 508 } __packed; 509 510 struct ath12k_htt_hw_stats_whal_tx_tlv { 511 __le32 mac_id__word; 512 __le32 last_unpause_ppdu_id; 513 __le32 hwsch_unpause_wait_tqm_write; 514 __le32 hwsch_dummy_tlv_skipped; 515 __le32 hwsch_misaligned_offset_received; 516 __le32 hwsch_reset_count; 517 __le32 hwsch_dev_reset_war; 518 __le32 hwsch_delayed_pause; 519 __le32 hwsch_long_delayed_pause; 520 __le32 sch_rx_ppdu_no_response; 521 __le32 sch_selfgen_response; 522 __le32 sch_rx_sifs_resp_trigger; 523 } __packed; 524 525 struct ath12k_htt_hw_war_stats_tlv { 526 __le32 mac_id__word; 527 DECLARE_FLEX_ARRAY(__le32, hw_wars); 528 } __packed; 529 530 struct ath12k_htt_tx_tqm_cmn_stats_tlv { 531 __le32 mac_id__word; 532 __le32 max_cmdq_id; 533 __le32 list_mpdu_cnt_hist_intvl; 534 __le32 add_msdu; 535 __le32 q_empty; 536 __le32 q_not_empty; 537 __le32 drop_notification; 538 __le32 desc_threshold; 539 __le32 hwsch_tqm_invalid_status; 540 __le32 missed_tqm_gen_mpdus; 541 __le32 tqm_active_tids; 542 __le32 tqm_inactive_tids; 543 __le32 tqm_active_msduq_flows; 544 __le32 msduq_timestamp_updates; 545 __le32 msduq_updates_mpdu_head_info_cmd; 546 __le32 msduq_updates_emp_to_nonemp_status; 547 __le32 get_mpdu_head_info_cmds_by_query; 548 __le32 get_mpdu_head_info_cmds_by_tac; 549 __le32 gen_mpdu_cmds_by_query; 550 __le32 high_prio_q_not_empty; 551 } __packed; 552 553 struct ath12k_htt_tx_tqm_error_stats_tlv { 554 __le32 q_empty_failure; 555 __le32 q_not_empty_failure; 556 __le32 add_msdu_failure; 557 __le32 tqm_cache_ctl_err; 558 __le32 tqm_soft_reset; 559 __le32 tqm_reset_num_in_use_link_descs; 560 __le32 tqm_reset_num_lost_link_descs; 561 __le32 tqm_reset_num_lost_host_tx_buf_cnt; 562 __le32 tqm_reset_num_in_use_internal_tqm; 563 __le32 tqm_reset_num_in_use_idle_link_rng; 564 __le32 tqm_reset_time_to_tqm_hang_delta_ms; 565 __le32 tqm_reset_recovery_time_ms; 566 __le32 tqm_reset_num_peers_hdl; 567 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt; 568 __le32 tqm_reset_cumm_dirty_hw_msduq_proc; 569 __le32 tqm_reset_flush_cache_cmd_su_cnt; 570 __le32 tqm_reset_flush_cache_cmd_other_cnt; 571 __le32 tqm_reset_flush_cache_cmd_trig_type; 572 __le32 tqm_reset_flush_cache_cmd_trig_cfg; 573 __le32 tqm_reset_flush_cmd_skp_status_null; 574 } __packed; 575 576 struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv { 577 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason); 578 } __packed; 579 580 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 581 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 582 583 struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv { 584 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason); 585 } __packed; 586 587 struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv { 588 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist); 589 } __packed; 590 591 struct ath12k_htt_tx_tqm_pdev_stats_tlv { 592 __le32 msdu_count; 593 __le32 mpdu_count; 594 __le32 remove_msdu; 595 __le32 remove_mpdu; 596 __le32 remove_msdu_ttl; 597 __le32 send_bar; 598 __le32 bar_sync; 599 __le32 notify_mpdu; 600 __le32 sync_cmd; 601 __le32 write_cmd; 602 __le32 hwsch_trigger; 603 __le32 ack_tlv_proc; 604 __le32 gen_mpdu_cmd; 605 __le32 gen_list_cmd; 606 __le32 remove_mpdu_cmd; 607 __le32 remove_mpdu_tried_cmd; 608 __le32 mpdu_queue_stats_cmd; 609 __le32 mpdu_head_info_cmd; 610 __le32 msdu_flow_stats_cmd; 611 __le32 remove_msdu_cmd; 612 __le32 remove_msdu_ttl_cmd; 613 __le32 flush_cache_cmd; 614 __le32 update_mpduq_cmd; 615 __le32 enqueue; 616 __le32 enqueue_notify; 617 __le32 notify_mpdu_at_head; 618 __le32 notify_mpdu_state_valid; 619 __le32 sched_udp_notify1; 620 __le32 sched_udp_notify2; 621 __le32 sched_nonudp_notify1; 622 __le32 sched_nonudp_notify2; 623 } __packed; 624 625 struct ath12k_htt_tx_de_cmn_stats_tlv { 626 __le32 mac_id__word; 627 __le32 tcl2fw_entry_count; 628 __le32 not_to_fw; 629 __le32 invalid_pdev_vdev_peer; 630 __le32 tcl_res_invalid_addrx; 631 __le32 wbm2fw_entry_count; 632 __le32 invalid_pdev; 633 __le32 tcl_res_addrx_timeout; 634 __le32 invalid_vdev; 635 __le32 invalid_tcl_exp_frame_desc; 636 __le32 vdev_id_mismatch_cnt; 637 } __packed; 638 639 struct ath12k_htt_tx_de_eapol_packets_stats_tlv { 640 __le32 m1_packets; 641 __le32 m2_packets; 642 __le32 m3_packets; 643 __le32 m4_packets; 644 __le32 g1_packets; 645 __le32 g2_packets; 646 __le32 rc4_packets; 647 __le32 eap_packets; 648 __le32 eapol_start_packets; 649 __le32 eapol_logoff_packets; 650 __le32 eapol_encap_asf_packets; 651 } __packed; 652 653 struct ath12k_htt_tx_de_classify_stats_tlv { 654 __le32 arp_packets; 655 __le32 igmp_packets; 656 __le32 dhcp_packets; 657 __le32 host_inspected; 658 __le32 htt_included; 659 __le32 htt_valid_mcs; 660 __le32 htt_valid_nss; 661 __le32 htt_valid_preamble_type; 662 __le32 htt_valid_chainmask; 663 __le32 htt_valid_guard_interval; 664 __le32 htt_valid_retries; 665 __le32 htt_valid_bw_info; 666 __le32 htt_valid_power; 667 __le32 htt_valid_key_flags; 668 __le32 htt_valid_no_encryption; 669 __le32 fse_entry_count; 670 __le32 fse_priority_be; 671 __le32 fse_priority_high; 672 __le32 fse_priority_low; 673 __le32 fse_traffic_ptrn_be; 674 __le32 fse_traffic_ptrn_over_sub; 675 __le32 fse_traffic_ptrn_bursty; 676 __le32 fse_traffic_ptrn_interactive; 677 __le32 fse_traffic_ptrn_periodic; 678 __le32 fse_hwqueue_alloc; 679 __le32 fse_hwqueue_created; 680 __le32 fse_hwqueue_send_to_host; 681 __le32 mcast_entry; 682 __le32 bcast_entry; 683 __le32 htt_update_peer_cache; 684 __le32 htt_learning_frame; 685 __le32 fse_invalid_peer; 686 __le32 mec_notify; 687 } __packed; 688 689 struct ath12k_htt_tx_de_classify_failed_stats_tlv { 690 __le32 ap_bss_peer_not_found; 691 __le32 ap_bcast_mcast_no_peer; 692 __le32 sta_delete_in_progress; 693 __le32 ibss_no_bss_peer; 694 __le32 invalid_vdev_type; 695 __le32 invalid_ast_peer_entry; 696 __le32 peer_entry_invalid; 697 __le32 ethertype_not_ip; 698 __le32 eapol_lookup_failed; 699 __le32 qpeer_not_allow_data; 700 __le32 fse_tid_override; 701 __le32 ipv6_jumbogram_zero_length; 702 __le32 qos_to_non_qos_in_prog; 703 __le32 ap_bcast_mcast_eapol; 704 __le32 unicast_on_ap_bss_peer; 705 __le32 ap_vdev_invalid; 706 __le32 incomplete_llc; 707 __le32 eapol_duplicate_m3; 708 __le32 eapol_duplicate_m4; 709 } __packed; 710 711 struct ath12k_htt_tx_de_classify_status_stats_tlv { 712 __le32 eok; 713 __le32 classify_done; 714 __le32 lookup_failed; 715 __le32 send_host_dhcp; 716 __le32 send_host_mcast; 717 __le32 send_host_unknown_dest; 718 __le32 send_host; 719 __le32 status_invalid; 720 } __packed; 721 722 struct ath12k_htt_tx_de_enqueue_packets_stats_tlv { 723 __le32 enqueued_pkts; 724 __le32 to_tqm; 725 __le32 to_tqm_bypass; 726 } __packed; 727 728 struct ath12k_htt_tx_de_enqueue_discard_stats_tlv { 729 __le32 discarded_pkts; 730 __le32 local_frames; 731 __le32 is_ext_msdu; 732 } __packed; 733 734 struct ath12k_htt_tx_de_compl_stats_tlv { 735 __le32 tcl_dummy_frame; 736 __le32 tqm_dummy_frame; 737 __le32 tqm_notify_frame; 738 __le32 fw2wbm_enq; 739 __le32 tqm_bypass_frame; 740 } __packed; 741 742 enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats { 743 ATH12K_HTT_TX_MUMIMO_GRP_VALID, 744 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 745 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 746 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 747 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 748 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 749 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 750 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 751 ATH12K_HTT_TX_MUMIMO_GRP_INVALID, 752 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 753 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 754 }; 755 756 #define ATH12K_HTT_NUM_AC_WMM 0x4 757 #define ATH12K_HTT_MAX_NUM_SBT_INTR 4 758 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 759 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 760 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 761 #define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7 762 #define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74 763 #define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8 764 #define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8 765 #define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 766 767 #define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \ 768 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 769 #define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 770 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE) 771 772 struct ath12k_htt_tx_selfgen_cmn_stats_tlv { 773 __le32 mac_id__word; 774 __le32 su_bar; 775 __le32 rts; 776 __le32 cts2self; 777 __le32 qos_null; 778 __le32 delayed_bar_1; 779 __le32 delayed_bar_2; 780 __le32 delayed_bar_3; 781 __le32 delayed_bar_4; 782 __le32 delayed_bar_5; 783 __le32 delayed_bar_6; 784 __le32 delayed_bar_7; 785 } __packed; 786 787 struct ath12k_htt_tx_selfgen_ac_stats_tlv { 788 __le32 ac_su_ndpa; 789 __le32 ac_su_ndp; 790 __le32 ac_mu_mimo_ndpa; 791 __le32 ac_mu_mimo_ndp; 792 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1]; 793 } __packed; 794 795 struct ath12k_htt_tx_selfgen_ax_stats_tlv { 796 __le32 ax_su_ndpa; 797 __le32 ax_su_ndp; 798 __le32 ax_mu_mimo_ndpa; 799 __le32 ax_mu_mimo_ndp; 800 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 801 __le32 ax_basic_trigger; 802 __le32 ax_bsr_trigger; 803 __le32 ax_mu_bar_trigger; 804 __le32 ax_mu_rts_trigger; 805 __le32 ax_ulmumimo_trigger; 806 } __packed; 807 808 struct ath12k_htt_tx_selfgen_be_stats_tlv { 809 __le32 be_su_ndpa; 810 __le32 be_su_ndp; 811 __le32 be_mu_mimo_ndpa; 812 __le32 be_mu_mimo_ndp; 813 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 814 __le32 be_basic_trigger; 815 __le32 be_bsr_trigger; 816 __le32 be_mu_bar_trigger; 817 __le32 be_mu_rts_trigger; 818 __le32 be_ulmumimo_trigger; 819 __le32 be_su_ndpa_queued; 820 __le32 be_su_ndp_queued; 821 __le32 be_mu_mimo_ndpa_queued; 822 __le32 be_mu_mimo_ndp_queued; 823 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 824 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 825 } __packed; 826 827 struct ath12k_htt_tx_selfgen_ac_err_stats_tlv { 828 __le32 ac_su_ndp_err; 829 __le32 ac_su_ndpa_err; 830 __le32 ac_mu_mimo_ndpa_err; 831 __le32 ac_mu_mimo_ndp_err; 832 __le32 ac_mu_mimo_brp1_err; 833 __le32 ac_mu_mimo_brp2_err; 834 __le32 ac_mu_mimo_brp3_err; 835 } __packed; 836 837 struct ath12k_htt_tx_selfgen_ax_err_stats_tlv { 838 __le32 ax_su_ndp_err; 839 __le32 ax_su_ndpa_err; 840 __le32 ax_mu_mimo_ndpa_err; 841 __le32 ax_mu_mimo_ndp_err; 842 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 843 __le32 ax_basic_trigger_err; 844 __le32 ax_bsr_trigger_err; 845 __le32 ax_mu_bar_trigger_err; 846 __le32 ax_mu_rts_trigger_err; 847 __le32 ax_ulmumimo_trigger_err; 848 } __packed; 849 850 struct ath12k_htt_tx_selfgen_be_err_stats_tlv { 851 __le32 be_su_ndp_err; 852 __le32 be_su_ndpa_err; 853 __le32 be_mu_mimo_ndpa_err; 854 __le32 be_mu_mimo_ndp_err; 855 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 856 __le32 be_basic_trigger_err; 857 __le32 be_bsr_trigger_err; 858 __le32 be_mu_bar_trigger_err; 859 __le32 be_mu_rts_trigger_err; 860 __le32 be_ulmumimo_trigger_err; 861 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 862 __le32 be_su_ndpa_flushed; 863 __le32 be_su_ndp_flushed; 864 __le32 be_mu_mimo_ndpa_flushed; 865 __le32 be_mu_mimo_ndp_flushed; 866 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 867 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 868 } __packed; 869 870 enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats { 871 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 872 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 873 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 874 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 875 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 876 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 877 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 878 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 879 880 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS 881 }; 882 883 struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv { 884 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 885 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 886 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 887 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 888 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 889 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 890 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 891 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 892 } __packed; 893 894 struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv { 895 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 896 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 897 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 898 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 899 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 900 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 901 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 902 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 903 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 904 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 905 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 906 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 907 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 908 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 909 } __packed; 910 911 struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv { 912 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 913 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 914 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 915 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 916 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 917 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 918 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 919 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 920 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 921 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 922 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 923 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 924 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 925 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 926 } __packed; 927 928 struct ath12k_htt_stats_string_tlv { 929 DECLARE_FLEX_ARRAY(__le32, data); 930 } __packed; 931 932 #define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 933 #define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8) 934 #define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16) 935 #define ATH12K_HTT_SRING_STATS_EP BIT(24) 936 #define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 937 #define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 938 #define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 939 #define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 940 #define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 941 #define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 942 #define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 943 #define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 944 945 struct ath12k_htt_sring_stats_tlv { 946 __le32 mac_id__ring_id__arena__ep; 947 __le32 base_addr_lsb; 948 __le32 base_addr_msb; 949 __le32 ring_size; 950 __le32 elem_size; 951 __le32 num_avail_words__num_valid_words; 952 __le32 head_ptr__tail_ptr; 953 __le32 consumer_empty__producer_full; 954 __le32 prefetch_count__internal_tail_ptr; 955 } __packed; 956 957 struct ath12k_htt_sfm_cmn_tlv { 958 __le32 mac_id__word; 959 __le32 buf_total; 960 __le32 mem_empty; 961 __le32 deallocate_bufs; 962 __le32 num_records; 963 } __packed; 964 965 struct ath12k_htt_sfm_client_tlv { 966 __le32 client_id; 967 __le32 buf_min; 968 __le32 buf_max; 969 __le32 buf_busy; 970 __le32 buf_alloc; 971 __le32 buf_avail; 972 __le32 num_users; 973 } __packed; 974 975 struct ath12k_htt_sfm_client_user_tlv { 976 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n); 977 } __packed; 978 979 struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv { 980 __le32 mu_mimo_sch_posted; 981 __le32 mu_mimo_sch_failed; 982 __le32 mu_mimo_ppdu_posted; 983 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 984 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 985 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 986 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 987 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 988 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 989 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 990 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 991 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 992 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 993 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 994 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 995 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 996 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 997 } __packed; 998 999 struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv { 1000 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1001 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1002 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1003 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1004 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 1005 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1006 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1007 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1008 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1009 } __packed; 1010 1011 enum ath12k_htt_stats_tx_sched_modes { 1012 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0, 1013 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX, 1014 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX, 1015 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE, 1016 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 1017 }; 1018 1019 struct ath12k_htt_tx_pdev_mpdu_stats_tlv { 1020 __le32 mpdus_queued_usr; 1021 __le32 mpdus_tried_usr; 1022 __le32 mpdus_failed_usr; 1023 __le32 mpdus_requeued_usr; 1024 __le32 err_no_ba_usr; 1025 __le32 mpdu_underrun_usr; 1026 __le32 ampdu_underrun_usr; 1027 __le32 user_index; 1028 __le32 tx_sched_mode; 1029 } __packed; 1030 1031 struct ath12k_htt_pdev_stats_cca_counters_tlv { 1032 __le32 tx_frame_usec; 1033 __le32 rx_frame_usec; 1034 __le32 rx_clear_usec; 1035 __le32 my_rx_frame_usec; 1036 __le32 usec_cnt; 1037 __le32 med_rx_idle_usec; 1038 __le32 med_tx_idle_global_usec; 1039 __le32 cca_obss_usec; 1040 } __packed; 1041 1042 struct ath12k_htt_pdev_cca_stats_hist_v1_tlv { 1043 __le32 chan_num; 1044 __le32 num_records; 1045 __le32 valid_cca_counters_bitmap; 1046 __le32 collection_interval; 1047 } __packed; 1048 1049 struct ath12k_htt_pdev_obss_pd_stats_tlv { 1050 __le32 num_obss_tx_ppdu_success; 1051 __le32 num_obss_tx_ppdu_failure; 1052 __le32 num_sr_tx_transmissions; 1053 __le32 num_spatial_reuse_opportunities; 1054 __le32 num_non_srg_opportunities; 1055 __le32 num_non_srg_ppdu_tried; 1056 __le32 num_non_srg_ppdu_success; 1057 __le32 num_srg_opportunities; 1058 __le32 num_srg_ppdu_tried; 1059 __le32 num_srg_ppdu_success; 1060 __le32 num_psr_opportunities; 1061 __le32 num_psr_ppdu_tried; 1062 __le32 num_psr_ppdu_success; 1063 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1064 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM]; 1065 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1066 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1067 __le32 num_obss_min_dur_check_flush_cnt; 1068 __le32 num_sr_ppdu_abort_flush_cnt; 1069 } __packed; 1070 1071 enum ath12k_htt_stats_page_lock_state { 1072 ATH12K_HTT_STATS_PAGE_LOCKED = 0, 1073 ATH12K_HTT_STATS_PAGE_UNLOCKED = 1, 1074 ATH12K_NUM_PG_LOCK_STATE 1075 }; 1076 1077 #define ATH12K_PAGER_MAX 10 1078 1079 #define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0) 1080 #define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8) 1081 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0) 1082 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16) 1083 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0) 1084 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16) 1085 1086 struct ath12k_htt_pgs_info { 1087 __le32 page_num; 1088 __le32 num_pgs; 1089 __le32 ts_lsb; 1090 __le32 ts_msb; 1091 } __packed; 1092 1093 struct ath12k_htt_dl_pager_stats_tlv { 1094 __le32 info0; 1095 __le32 info1; 1096 __le32 info2; 1097 struct ath12k_htt_pgs_info pgs_info[ATH12K_NUM_PG_LOCK_STATE][ATH12K_PAGER_MAX]; 1098 } __packed; 1099 1100 #define ATH12K_HTT_STATS_MAX_CHAINS 8 1101 #define ATH12K_HTT_MAX_RX_PKT_CNT 8 1102 #define ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1103 #define ATH12K_HTT_MAX_PER_BLK_ERR_CNT 20 1104 #define ATH12K_HTT_MAX_RX_OTA_ERR_CNT 14 1105 #define ATH12K_HTT_MAX_CH_PWR_INFO_SIZE 16 1106 1107 struct ath12k_htt_phy_stats_tlv { 1108 a_sle32 nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1109 __le32 false_radar_cnt; 1110 __le32 radar_cs_cnt; 1111 a_sle32 ani_level; 1112 __le32 fw_run_time; 1113 a_sle32 runtime_nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1114 } __packed; 1115 1116 struct ath12k_htt_phy_counters_tlv { 1117 __le32 rx_ofdma_timing_err_cnt; 1118 __le32 rx_cck_fail_cnt; 1119 __le32 mactx_abort_cnt; 1120 __le32 macrx_abort_cnt; 1121 __le32 phytx_abort_cnt; 1122 __le32 phyrx_abort_cnt; 1123 __le32 phyrx_defer_abort_cnt; 1124 __le32 rx_gain_adj_lstf_event_cnt; 1125 __le32 rx_gain_adj_non_legacy_cnt; 1126 __le32 rx_pkt_cnt[ATH12K_HTT_MAX_RX_PKT_CNT]; 1127 __le32 rx_pkt_crc_pass_cnt[ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1128 __le32 per_blk_err_cnt[ATH12K_HTT_MAX_PER_BLK_ERR_CNT]; 1129 __le32 rx_ota_err_cnt[ATH12K_HTT_MAX_RX_OTA_ERR_CNT]; 1130 } __packed; 1131 1132 struct ath12k_htt_phy_reset_stats_tlv { 1133 __le32 pdev_id; 1134 __le32 chan_mhz; 1135 __le32 chan_band_center_freq1; 1136 __le32 chan_band_center_freq2; 1137 __le32 chan_phy_mode; 1138 __le32 chan_flags; 1139 __le32 chan_num; 1140 __le32 reset_cause; 1141 __le32 prev_reset_cause; 1142 __le32 phy_warm_reset_src; 1143 __le32 rx_gain_tbl_mode; 1144 __le32 xbar_val; 1145 __le32 force_calibration; 1146 __le32 phyrf_mode; 1147 __le32 phy_homechan; 1148 __le32 phy_tx_ch_mask; 1149 __le32 phy_rx_ch_mask; 1150 __le32 phybb_ini_mask; 1151 __le32 phyrf_ini_mask; 1152 __le32 phy_dfs_en_mask; 1153 __le32 phy_sscan_en_mask; 1154 __le32 phy_synth_sel_mask; 1155 __le32 phy_adfs_freq; 1156 __le32 cck_fir_settings; 1157 __le32 phy_dyn_pri_chan; 1158 __le32 cca_thresh; 1159 __le32 dyn_cca_status; 1160 __le32 rxdesense_thresh_hw; 1161 __le32 rxdesense_thresh_sw; 1162 } __packed; 1163 1164 struct ath12k_htt_phy_reset_counters_tlv { 1165 __le32 pdev_id; 1166 __le32 cf_active_low_fail_cnt; 1167 __le32 cf_active_low_pass_cnt; 1168 __le32 phy_off_through_vreg_cnt; 1169 __le32 force_calibration_cnt; 1170 __le32 rf_mode_switch_phy_off_cnt; 1171 __le32 temperature_recal_cnt; 1172 } __packed; 1173 1174 struct ath12k_htt_phy_tpc_stats_tlv { 1175 __le32 pdev_id; 1176 __le32 tx_power_scale; 1177 __le32 tx_power_scale_db; 1178 __le32 min_negative_tx_power; 1179 __le32 reg_ctl_domain; 1180 __le32 max_reg_allowed_power[ATH12K_HTT_STATS_MAX_CHAINS]; 1181 __le32 max_reg_allowed_power_6ghz[ATH12K_HTT_STATS_MAX_CHAINS]; 1182 __le32 twice_max_rd_power; 1183 __le32 max_tx_power; 1184 __le32 home_max_tx_power; 1185 __le32 psd_power; 1186 __le32 eirp_power; 1187 __le32 power_type_6ghz; 1188 __le32 sub_band_cfreq[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1189 __le32 sub_band_txpower[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1190 } __packed; 1191 1192 struct ath12k_htt_t2h_soc_txrx_stats_common_tlv { 1193 __le32 inv_peers_msdu_drop_count_hi; 1194 __le32 inv_peers_msdu_drop_count_lo; 1195 } __packed; 1196 1197 struct ath12k_htt_dmac_reset_stats_tlv { 1198 __le32 reset_count; 1199 __le32 reset_time_lo_ms; 1200 __le32 reset_time_hi_ms; 1201 __le32 disengage_time_lo_ms; 1202 __le32 disengage_time_hi_ms; 1203 __le32 engage_time_lo_ms; 1204 __le32 engage_time_hi_ms; 1205 __le32 disengage_count; 1206 __le32 engage_count; 1207 __le32 drain_dest_ring_mask; 1208 } __packed; 1209 1210 struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv { 1211 __le32 mac_id__word; 1212 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1213 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1214 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM]; 1215 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1216 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1217 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1218 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1219 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM]; 1220 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM]; 1221 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM]; 1222 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM]; 1223 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM]; 1224 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM]; 1225 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM]; 1226 } __packed; 1227 1228 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS 4 1229 #define ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS 8 1230 #define ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS 14 1231 1232 enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE { 1233 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26, 1234 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52, 1235 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26, 1236 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106, 1237 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26, 1238 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242, 1239 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484, 1240 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242, 1241 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996, 1242 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484, 1243 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 1244 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2, 1245 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 1246 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3, 1247 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 1248 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4, 1249 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS, 1250 }; 1251 1252 enum ATH12K_HTT_RC_MODE { 1253 ATH12K_HTT_RC_MODE_SU_OL, 1254 ATH12K_HTT_RC_MODE_SU_BF, 1255 ATH12K_HTT_RC_MODE_MU1_INTF, 1256 ATH12K_HTT_RC_MODE_MU2_INTF, 1257 ATH12K_HTT_RC_MODE_MU3_INTF, 1258 ATH12K_HTT_RC_MODE_MU4_INTF, 1259 ATH12K_HTT_RC_MODE_MU5_INTF, 1260 ATH12K_HTT_RC_MODE_MU6_INTF, 1261 ATH12K_HTT_RC_MODE_MU7_INTF, 1262 ATH12K_HTT_RC_MODE_2D_COUNT 1263 }; 1264 1265 enum ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE { 1266 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_26, 1267 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_52, 1268 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_106, 1269 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_242, 1270 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_484, 1271 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996, 1272 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996x2, 1273 ATH12K_HTT_TX_RX_PDEV_STATS_NUM_AX_RU_SIZE_CNTRS 1274 }; 1275 1276 enum ath12k_htt_stats_rc_mode { 1277 ATH12K_HTT_STATS_RC_MODE_DLSU = 0, 1278 ATH12K_HTT_STATS_RC_MODE_DLMUMIMO = 1, 1279 ATH12K_HTT_STATS_RC_MODE_DLOFDMA = 2, 1280 ATH12K_HTT_STATS_RC_MODE_ULMUMIMO = 3, 1281 ATH12K_HTT_STATS_RC_MODE_ULOFDMA = 4, 1282 }; 1283 1284 enum ath12k_htt_stats_ru_type { 1285 ATH12K_HTT_STATS_RU_TYPE_INVALID, 1286 ATH12K_HTT_STATS_RU_TYPE_SINGLE_RU_ONLY, 1287 ATH12K_HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU, 1288 }; 1289 1290 struct ath12k_htt_tx_rate_stats { 1291 __le32 ppdus_tried; 1292 __le32 ppdus_ack_failed; 1293 __le32 mpdus_tried; 1294 __le32 mpdus_failed; 1295 } __packed; 1296 1297 struct ath12k_htt_tx_per_rate_stats_tlv { 1298 __le32 rc_mode; 1299 __le32 last_probed_mcs; 1300 __le32 last_probed_nss; 1301 __le32 last_probed_bw; 1302 struct ath12k_htt_tx_rate_stats per_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS]; 1303 struct ath12k_htt_tx_rate_stats per_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1304 struct ath12k_htt_tx_rate_stats per_mcs[ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS]; 1305 struct ath12k_htt_tx_rate_stats per_bw320; 1306 __le32 probe_cnt[ATH12K_HTT_RC_MODE_2D_COUNT]; 1307 __le32 ru_type; 1308 struct ath12k_htt_tx_rate_stats ru[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1309 } __packed; 1310 1311 #define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16 1312 #define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5 1313 #define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4 1314 #define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4 1315 1316 struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv { 1317 __le32 mac_id__word; 1318 __le32 be_ofdma_tx_ldpc; 1319 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1320 __le32 be_ofdma_tx_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1321 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS]; 1322 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1323 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1324 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS]; 1325 } __packed; 1326 1327 struct ath12k_htt_pdev_mbssid_ctrl_frame_tlv { 1328 __le32 mac_id__word; 1329 __le32 basic_trigger_across_bss; 1330 __le32 basic_trigger_within_bss; 1331 __le32 bsr_trigger_across_bss; 1332 __le32 bsr_trigger_within_bss; 1333 __le32 mu_rts_across_bss; 1334 __le32 mu_rts_within_bss; 1335 __le32 ul_mumimo_trigger_across_bss; 1336 __le32 ul_mumimo_trigger_within_bss; 1337 } __packed; 1338 1339 #endif 1340