1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #include "dp_htt.h" 11 12 #define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) 13 #define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 14 #define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 15 #define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 16 #define ATH12K_HTT_STATS_SUBTYPE_MAX 16 17 #define ATH12K_HTT_MAX_STRING_LEN 256 18 19 #define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f) 20 #define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f) 21 #define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \ 22 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx)) 23 #define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \ 24 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx)) 25 26 void ath12k_debugfs_htt_stats_register(struct ath12k *ar); 27 28 #ifdef CONFIG_ATH12K_DEBUGFS 29 void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 30 struct sk_buff *skb); 31 #else /* CONFIG_ATH12K_DEBUGFS */ 32 static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 33 struct sk_buff *skb) 34 { 35 } 36 #endif 37 38 /** 39 * DOC: target -> host extended statistics upload 40 * 41 * The following field definitions describe the format of the HTT 42 * target to host stats upload confirmation message. 43 * The message contains a cookie echoed from the HTT host->target stats 44 * upload request, which identifies which request the confirmation is 45 * for, and a single stats can span over multiple HTT stats indication 46 * due to the HTT message size limitation so every HTT ext stats 47 * indication will have tag-length-value stats information elements. 48 * The tag-length header for each HTT stats IND message also includes a 49 * status field, to indicate whether the request for the stat type in 50 * question was fully met, partially met, unable to be met, or invalid 51 * (if the stat type in question is disabled in the target). 52 * A Done bit 1's indicate the end of the of stats info elements. 53 * 54 * 55 * |31 16|15 12|11|10 8|7 5|4 0| 56 * |--------------------------------------------------------------| 57 * | reserved | msg type | 58 * |--------------------------------------------------------------| 59 * | cookie LSBs | 60 * |--------------------------------------------------------------| 61 * | cookie MSBs | 62 * |--------------------------------------------------------------| 63 * | stats entry length | rsvd | D| S | stat type | 64 * |--------------------------------------------------------------| 65 * | type-specific stats info | 66 * | (see debugfs_htt_stats.h) | 67 * |--------------------------------------------------------------| 68 * Header fields: 69 * - MSG_TYPE 70 * Bits 7:0 71 * Purpose: Identifies this is a extended statistics upload confirmation 72 * message. 73 * Value: 0x1c 74 * - COOKIE_LSBS 75 * Bits 31:0 76 * Purpose: Provide a mechanism to match a target->host stats confirmation 77 * message with its preceding host->target stats request message. 78 * Value: MSBs of the opaque cookie specified by the host-side requestor 79 * - COOKIE_MSBS 80 * Bits 31:0 81 * Purpose: Provide a mechanism to match a target->host stats confirmation 82 * message with its preceding host->target stats request message. 83 * Value: MSBs of the opaque cookie specified by the host-side requestor 84 * 85 * Stats Information Element tag-length header fields: 86 * - STAT_TYPE 87 * Bits 7:0 88 * Purpose: identifies the type of statistics info held in the 89 * following information element 90 * Value: ath12k_dbg_htt_ext_stats_type 91 * - STATUS 92 * Bits 10:8 93 * Purpose: indicate whether the requested stats are present 94 * Value: 95 * 0 -> The requested stats have been delivered in full 96 * 1 -> The requested stats have been delivered in part 97 * 2 -> The requested stats could not be delivered (error case) 98 * 3 -> The requested stat type is either not recognized (invalid) 99 * - DONE 100 * Bits 11 101 * Purpose: 102 * Indicates the completion of the stats entry, this will be the last 103 * stats conf HTT segment for the requested stats type. 104 * Value: 105 * 0 -> the stats retrieval is ongoing 106 * 1 -> the stats retrieval is complete 107 * - LENGTH 108 * Bits 31:16 109 * Purpose: indicate the stats information size 110 * Value: This field specifies the number of bytes of stats information 111 * that follows the element tag-length header. 112 * It is expected but not required that this length is a multiple of 113 * 4 bytes. 114 */ 115 116 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 117 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 118 119 struct ath12k_htt_extd_stats_msg { 120 __le32 info0; 121 __le64 cookie; 122 __le32 info1; 123 u8 data[]; 124 } __packed; 125 126 /* htt_dbg_ext_stats_type */ 127 enum ath12k_dbg_htt_ext_stats_type { 128 ATH12K_DBG_HTT_EXT_STATS_RESET = 0, 129 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, 130 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX = 2, 131 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_HWQ = 3, 132 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, 133 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, 134 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, 135 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8, 136 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9, 137 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10, 138 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12, 139 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15, 140 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16, 141 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17, 142 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19, 143 ATH12K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22, 144 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 145 ATH12K_DBG_HTT_EXT_STATS_LATENCY_PROF_STATS = 25, 146 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_TRIG_STATS = 26, 147 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, 148 ATH12K_DBG_HTT_EXT_STATS_FSE_RX = 28, 149 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE_EXT = 30, 150 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE_TXBF = 31, 151 ATH12K_DBG_HTT_EXT_STATS_TXBF_OFDMA = 32, 152 ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36, 153 ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 154 ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38, 155 ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40, 156 ATH12K_DBG_HTT_EXT_AST_ENTRIES = 41, 157 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45, 158 ATH12K_DBG_HTT_DBG_PDEV_PUNCTURE_STATS = 46, 159 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49, 160 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51, 161 ATH12K_DGB_HTT_EXT_STATS_PDEV_MBSSID_CTRL_FRAME = 54, 162 ATH12K_DBG_HTT_PDEV_TDMA_STATS = 57, 163 ATH12K_DBG_HTT_MLO_SCHED_STATS = 63, 164 ATH12K_DBG_HTT_PDEV_MLO_IPC_STATS = 64, 165 ATH12K_DBG_HTT_EXT_PDEV_RTT_RESP_STATS = 65, 166 ATH12K_DBG_HTT_EXT_PDEV_RTT_INITIATOR_STATS = 66, 167 ATH12K_DBG_HTT_EXT_CHAN_SWITCH_STATS = 76, 168 169 /* keep this last */ 170 ATH12K_DBG_HTT_NUM_EXT_STATS, 171 }; 172 173 enum ath12k_dbg_htt_tlv_tag { 174 HTT_STATS_TX_PDEV_CMN_TAG = 0, 175 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 176 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 177 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 178 HTT_STATS_STRING_TAG = 5, 179 HTT_STATS_TX_HWQ_CMN_TAG = 6, 180 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 181 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 182 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 183 HTT_STATS_TX_TQM_CMN_TAG = 14, 184 HTT_STATS_TX_TQM_PDEV_TAG = 15, 185 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 186 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 187 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 188 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 189 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 190 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 191 HTT_STATS_TX_DE_CMN_TAG = 23, 192 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 193 HTT_STATS_SFM_CMN_TAG = 26, 194 HTT_STATS_SRING_STATS_TAG = 27, 195 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, 196 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 197 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 198 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 199 HTT_STATS_TX_SCHED_CMN_TAG = 37, 200 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 201 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 202 HTT_STATS_SFM_CLIENT_TAG = 42, 203 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 204 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 205 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 206 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 207 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 208 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 209 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 210 HTT_STATS_HW_INTR_MISC_TAG = 54, 211 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 212 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 213 HTT_STATS_WHAL_TX_TAG = 66, 214 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 215 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 216 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 217 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 218 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 219 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 220 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 221 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 222 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 223 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 224 HTT_STATS_HW_WAR_TAG = 89, 225 HTT_STATS_LATENCY_PROF_STATS_TAG = 91, 226 HTT_STATS_LATENCY_CTX_TAG = 92, 227 HTT_STATS_LATENCY_CNT_TAG = 93, 228 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, 229 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, 230 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, 231 HTT_STATS_RX_FSE_STATS_TAG = 98, 232 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, 233 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, 234 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, 235 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 236 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, 237 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, 238 HTT_STATS_DLPAGER_STATS_TAG = 120, 239 HTT_STATS_PHY_COUNTERS_TAG = 121, 240 HTT_STATS_PHY_STATS_TAG = 122, 241 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, 242 HTT_STATS_PHY_RESET_STATS_TAG = 124, 243 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, 244 HTT_STATS_PER_RATE_STATS_TAG = 128, 245 HTT_STATS_MU_PPDU_DIST_TAG = 129, 246 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, 247 HTT_STATS_AST_ENTRY_TAG = 132, 248 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, 249 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, 250 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, 251 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, 252 HTT_STATS_TX_PDEV_HISTOGRAM_STATS_TAG = 144, 253 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, 254 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, 255 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, 256 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, 257 HTT_STATS_DMAC_RESET_STATS_TAG = 155, 258 HTT_STATS_PHY_TPC_STATS_TAG = 157, 259 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, 260 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, 261 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, 262 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, 263 HTT_STATS_PDEV_TDMA_TAG = 187, 264 HTT_STATS_MLO_SCHED_STATS_TAG = 190, 265 HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, 266 HTT_STATS_PDEV_RTT_RESP_STATS_TAG = 194, 267 HTT_STATS_PDEV_RTT_INIT_STATS_TAG = 195, 268 HTT_STATS_PDEV_RTT_HW_STATS_TAG = 196, 269 HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG = 197, 270 HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG = 198, 271 HTT_STATS_CHAN_SWITCH_STATS_TAG = 213, 272 273 HTT_STATS_MAX_TAG, 274 }; 275 276 #define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0) 277 278 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 279 #define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 280 281 /* MU MIMO distribution stats is a 2-dimensional array 282 * with dimension one denoting stats for nr4[0] or nr8[1] 283 */ 284 #define ATH12K_HTT_STATS_NUM_NR_BINS 2 285 #define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 286 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 287 #define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9 288 #define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \ 289 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS) 290 #define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \ 291 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 292 293 enum ath12k_htt_tx_pdev_underrun_enum { 294 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 295 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 296 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 297 HTT_TX_PDEV_MAX_URRN_STATS = 3, 298 }; 299 300 enum ath12k_htt_stats_reset_cfg_param_alloc_pos { 301 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1, 302 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES, 303 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES, 304 }; 305 306 struct debug_htt_stats_req { 307 bool done; 308 bool override_cfg_param; 309 u8 pdev_id; 310 enum ath12k_dbg_htt_ext_stats_type type; 311 u32 cfg_param[4]; 312 u8 peer_addr[ETH_ALEN]; 313 struct completion htt_stats_rcvd; 314 u32 buf_len; 315 u8 buf[]; 316 }; 317 318 struct ath12k_htt_tx_pdev_stats_cmn_tlv { 319 __le32 mac_id__word; 320 __le32 hw_queued; 321 __le32 hw_reaped; 322 __le32 underrun; 323 __le32 hw_paused; 324 __le32 hw_flush; 325 __le32 hw_filt; 326 __le32 tx_abort; 327 __le32 mpdu_requed; 328 __le32 tx_xretry; 329 __le32 data_rc; 330 __le32 mpdu_dropped_xretry; 331 __le32 illgl_rate_phy_err; 332 __le32 cont_xretry; 333 __le32 tx_timeout; 334 __le32 pdev_resets; 335 __le32 phy_underrun; 336 __le32 txop_ovf; 337 __le32 seq_posted; 338 __le32 seq_failed_queueing; 339 __le32 seq_completed; 340 __le32 seq_restarted; 341 __le32 mu_seq_posted; 342 __le32 seq_switch_hw_paused; 343 __le32 next_seq_posted_dsr; 344 __le32 seq_posted_isr; 345 __le32 seq_ctrl_cached; 346 __le32 mpdu_count_tqm; 347 __le32 msdu_count_tqm; 348 __le32 mpdu_removed_tqm; 349 __le32 msdu_removed_tqm; 350 __le32 mpdus_sw_flush; 351 __le32 mpdus_hw_filter; 352 __le32 mpdus_truncated; 353 __le32 mpdus_ack_failed; 354 __le32 mpdus_expired; 355 __le32 mpdus_seq_hw_retry; 356 __le32 ack_tlv_proc; 357 __le32 coex_abort_mpdu_cnt_valid; 358 __le32 coex_abort_mpdu_cnt; 359 __le32 num_total_ppdus_tried_ota; 360 __le32 num_data_ppdus_tried_ota; 361 __le32 local_ctrl_mgmt_enqued; 362 __le32 local_ctrl_mgmt_freed; 363 __le32 local_data_enqued; 364 __le32 local_data_freed; 365 __le32 mpdu_tried; 366 __le32 isr_wait_seq_posted; 367 368 __le32 tx_active_dur_us_low; 369 __le32 tx_active_dur_us_high; 370 __le32 remove_mpdus_max_retries; 371 __le32 comp_delivered; 372 __le32 ppdu_ok; 373 __le32 self_triggers; 374 __le32 tx_time_dur_data; 375 __le32 seq_qdepth_repost_stop; 376 __le32 mu_seq_min_msdu_repost_stop; 377 __le32 seq_min_msdu_repost_stop; 378 __le32 seq_txop_repost_stop; 379 __le32 next_seq_cancel; 380 __le32 fes_offsets_err_cnt; 381 __le32 num_mu_peer_blacklisted; 382 __le32 mu_ofdma_seq_posted; 383 __le32 ul_mumimo_seq_posted; 384 __le32 ul_ofdma_seq_posted; 385 386 __le32 thermal_suspend_cnt; 387 __le32 dfs_suspend_cnt; 388 __le32 tx_abort_suspend_cnt; 389 __le32 tgt_specific_opaque_txq_suspend_info; 390 __le32 last_suspend_reason; 391 } __packed; 392 393 struct ath12k_htt_tx_pdev_stats_urrn_tlv { 394 DECLARE_FLEX_ARRAY(__le32, urrn_stats); 395 } __packed; 396 397 struct ath12k_htt_tx_pdev_stats_flush_tlv { 398 DECLARE_FLEX_ARRAY(__le32, flush_errs); 399 } __packed; 400 401 struct ath12k_htt_tx_pdev_stats_phy_err_tlv { 402 DECLARE_FLEX_ARRAY(__le32, phy_errs); 403 } __packed; 404 405 struct ath12k_htt_tx_pdev_stats_sifs_tlv { 406 DECLARE_FLEX_ARRAY(__le32, sifs_status); 407 } __packed; 408 409 struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv { 410 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 411 } __packed; 412 413 struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv { 414 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status); 415 } __packed; 416 417 enum ath12k_htt_stats_hw_mode { 418 ATH12K_HTT_STATS_HWMODE_AC = 0, 419 ATH12K_HTT_STATS_HWMODE_AX = 1, 420 ATH12K_HTT_STATS_HWMODE_BE = 2, 421 }; 422 423 struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv { 424 __le32 hw_mode; 425 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS]; 426 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 427 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS]; 428 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 429 } __packed; 430 431 #define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 432 #define ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 433 #define ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 434 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 435 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 436 #define ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES 7 437 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 438 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 439 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LTF 4 440 #define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 441 #define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 442 #define ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 443 #define ATH12K_HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 444 445 #define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ 446 (ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ 447 ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ 448 ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) 449 450 struct ath12k_htt_tx_pdev_rate_stats_tlv { 451 __le32 mac_id_word; 452 __le32 tx_ldpc; 453 __le32 rts_cnt; 454 __le32 ack_rssi; 455 __le32 tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 456 __le32 tx_su_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 457 __le32 tx_mu_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 458 __le32 tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 459 __le32 tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 460 __le32 tx_stbc[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 461 __le32 tx_pream[ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 462 __le32 tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 463 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 464 __le32 tx_dcm[ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 465 __le32 rts_success; 466 __le32 tx_legacy_cck_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 467 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 468 __le32 ac_mu_mimo_tx_ldpc; 469 __le32 ax_mu_mimo_tx_ldpc; 470 __le32 ofdma_tx_ldpc; 471 __le32 tx_he_ltf[ATH12K_HTT_TX_PDEV_STATS_NUM_LTF]; 472 __le32 ac_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 473 __le32 ax_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 474 __le32 ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 475 __le32 ac_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 476 __le32 ax_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 477 __le32 ofdma_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 478 __le32 ac_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 479 __le32 ax_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 480 __le32 ofdma_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 481 __le32 ac_mu_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 482 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 483 __le32 ax_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 484 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 485 __le32 ofdma_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 486 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 487 __le32 trigger_type_11ax[ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; 488 __le32 tx_11ax_su_ext; 489 __le32 tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 490 __le32 tx_stbc_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 491 __le32 tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 492 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 493 __le32 ax_mu_mimo_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 494 __le32 ofdma_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 495 __le32 ax_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 496 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 497 __le32 ofd_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 498 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 499 __le32 tx_mcs_ext_2[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 500 __le32 tx_bw_320mhz; 501 } __packed; 502 503 struct ath12k_htt_tx_histogram_stats_tlv { 504 __le32 rate_retry_mcs_drop_cnt; 505 __le32 mcs_drop_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; 506 __le32 per_histogram_cnt[ATH12K_HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; 507 __le32 low_latency_rate_cnt; 508 __le32 su_burst_rate_drop_cnt; 509 __le32 su_burst_rate_drop_fail_cnt; 510 } __packed; 511 512 #define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 513 #define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 514 #define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 515 #define ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 516 #define ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 517 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 518 #define ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 519 #define ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES 7 520 #define ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 521 #define ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS 16 522 #define ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 523 #define ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 524 #define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 525 526 struct ath12k_htt_rx_pdev_rate_stats_tlv { 527 __le32 mac_id_word; 528 __le32 nsts; 529 __le32 rx_ldpc; 530 __le32 rts_cnt; 531 __le32 rssi_mgmt; 532 __le32 rssi_data; 533 __le32 rssi_comb; 534 __le32 rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 535 __le32 rx_nss[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 536 __le32 rx_dcm[ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 537 __le32 rx_stbc[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 538 __le32 rx_bw[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 539 __le32 rx_pream[ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 540 u8 rssi_chain_in_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 541 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 542 __le32 rx_gi[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 543 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 544 __le32 rssi_in_dbm; 545 __le32 rx_11ax_su_ext; 546 __le32 rx_11ac_mumimo; 547 __le32 rx_11ax_mumimo; 548 __le32 rx_11ax_ofdma; 549 __le32 txbf; 550 __le32 rx_legacy_cck_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 551 __le32 rx_legacy_ofdm_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 552 __le32 rx_active_dur_us_low; 553 __le32 rx_active_dur_us_high; 554 __le32 rx_11ax_ul_ofdma; 555 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 556 __le32 ul_ofdma_rx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 557 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 558 __le32 ul_ofdma_rx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 559 __le32 ul_ofdma_rx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 560 __le32 ul_ofdma_rx_stbc; 561 __le32 ul_ofdma_rx_ldpc; 562 __le32 rx_ulofdma_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 563 __le32 rx_ulofdma_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 564 __le32 rx_ulofdma_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 565 __le32 rx_ulofdma_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 566 __le32 nss_count; 567 __le32 pilot_count; 568 __le32 rx_pil_evm_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 569 [ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS]; 570 __le32 rx_pilot_evm_db_mean[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 571 s8 rx_ul_fd_rssi[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 572 [ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 573 __le32 per_chain_rssi_pkt_type; 574 s8 rx_per_chain_rssi_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 575 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 576 __le32 rx_su_ndpa; 577 __le32 rx_11ax_su_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 578 __le32 rx_mu_ndpa; 579 __le32 rx_11ax_mu_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 580 __le32 rx_br_poll; 581 __le32 rx_11ax_dl_ofdma_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 582 __le32 rx_11ax_dl_ofdma_ru[ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 583 __le32 rx_ulmumimo_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 584 __le32 rx_ulmumimo_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 585 __le32 rx_ulmumimo_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 586 __le32 rx_ulmumimo_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 587 __le32 rx_ulofdma_non_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 588 __le32 rx_ulofdma_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 589 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 590 } __packed; 591 592 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 593 #define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 594 #define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 595 #define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5 596 #define ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS 5 597 598 struct ath12k_htt_rx_pdev_rate_ext_stats_tlv { 599 u8 rssi_chain_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 600 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 601 s8 rx_per_chain_rssi_ext_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 602 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 603 __le32 rssi_mcast_in_dbm; 604 __le32 rssi_mgmt_in_dbm; 605 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 606 __le32 rx_stbc_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 607 __le32 rx_gi_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 608 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 609 __le32 ul_ofdma_rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 610 __le32 ul_ofdma_rx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 611 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 612 __le32 rx_11ax_su_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 613 __le32 rx_11ax_mu_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 614 __le32 rx_11ax_dl_ofdma_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 615 __le32 rx_mcs_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 616 __le32 rx_bw_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS]; 617 __le32 rx_gi_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 618 [ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 619 __le32 rx_su_punctured_mode[ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 620 } __packed; 621 622 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 623 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 624 625 #define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 626 627 struct ath12k_htt_stats_tx_sched_cmn_tlv { 628 __le32 mac_id__word; 629 __le32 current_timestamp; 630 } __packed; 631 632 struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv { 633 __le32 mac_id__word; 634 __le32 sched_policy; 635 __le32 last_sched_cmd_posted_timestamp; 636 __le32 last_sched_cmd_compl_timestamp; 637 __le32 sched_2_tac_lwm_count; 638 __le32 sched_2_tac_ring_full; 639 __le32 sched_cmd_post_failure; 640 __le32 num_active_tids; 641 __le32 num_ps_schedules; 642 __le32 sched_cmds_pending; 643 __le32 num_tid_register; 644 __le32 num_tid_unregister; 645 __le32 num_qstats_queried; 646 __le32 qstats_update_pending; 647 __le32 last_qstats_query_timestamp; 648 __le32 num_tqm_cmdq_full; 649 __le32 num_de_sched_algo_trigger; 650 __le32 num_rt_sched_algo_trigger; 651 __le32 num_tqm_sched_algo_trigger; 652 __le32 notify_sched; 653 __le32 dur_based_sendn_term; 654 __le32 su_notify2_sched; 655 __le32 su_optimal_queued_msdus_sched; 656 __le32 su_delay_timeout_sched; 657 __le32 su_min_txtime_sched_delay; 658 __le32 su_no_delay; 659 __le32 num_supercycles; 660 __le32 num_subcycles_with_sort; 661 __le32 num_subcycles_no_sort; 662 } __packed; 663 664 struct ath12k_htt_sched_txq_cmd_posted_tlv { 665 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted); 666 } __packed; 667 668 struct ath12k_htt_sched_txq_cmd_reaped_tlv { 669 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped); 670 } __packed; 671 672 struct ath12k_htt_sched_txq_sched_order_su_tlv { 673 DECLARE_FLEX_ARRAY(__le32, sched_order_su); 674 } __packed; 675 676 struct ath12k_htt_sched_txq_sched_ineligibility_tlv { 677 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility); 678 } __packed; 679 680 enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum { 681 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, 682 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, 683 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, 684 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, 685 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, 686 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, 687 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, 688 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 689 }; 690 691 struct ath12k_htt_sched_txq_supercycle_triggers_tlv { 692 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers); 693 } __packed; 694 695 struct ath12k_htt_hw_stats_pdev_errs_tlv { 696 __le32 mac_id__word; 697 __le32 tx_abort; 698 __le32 tx_abort_fail_count; 699 __le32 rx_abort; 700 __le32 rx_abort_fail_count; 701 __le32 warm_reset; 702 __le32 cold_reset; 703 __le32 tx_flush; 704 __le32 tx_glb_reset; 705 __le32 tx_txq_reset; 706 __le32 rx_timeout_reset; 707 __le32 mac_cold_reset_restore_cal; 708 __le32 mac_cold_reset; 709 __le32 mac_warm_reset; 710 __le32 mac_only_reset; 711 __le32 phy_warm_reset; 712 __le32 phy_warm_reset_ucode_trig; 713 __le32 mac_warm_reset_restore_cal; 714 __le32 mac_sfm_reset; 715 __le32 phy_warm_reset_m3_ssr; 716 __le32 phy_warm_reset_reason_phy_m3; 717 __le32 phy_warm_reset_reason_tx_hw_stuck; 718 __le32 phy_warm_reset_reason_num_rx_frame_stuck; 719 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy; 720 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng; 721 __le32 phy_warm_reset_reason_mac_conv_phy_reset; 722 __le32 wal_rx_recovery_rst_mac_hang_cnt; 723 __le32 wal_rx_recovery_rst_known_sig_cnt; 724 __le32 wal_rx_recovery_rst_no_rx_cnt; 725 __le32 wal_rx_recovery_rst_no_rx_consec_cnt; 726 __le32 wal_rx_recovery_rst_rx_busy_cnt; 727 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt; 728 __le32 rx_flush_cnt; 729 __le32 phy_warm_reset_reason_tx_exp_cca_stuck; 730 __le32 phy_warm_reset_reason_tx_consec_flsh_war; 731 __le32 phy_warm_reset_reason_tx_hwsch_reset_war; 732 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war; 733 __le32 fw_rx_rings_reset; 734 __le32 rx_dest_drain_rx_descs_leak_prevented; 735 __le32 rx_dest_drain_rx_descs_saved_cnt; 736 __le32 rx_dest_drain_rxdma2reo_leak_detected; 737 __le32 rx_dest_drain_rxdma2fw_leak_detected; 738 __le32 rx_dest_drain_rxdma2wbm_leak_detected; 739 __le32 rx_dest_drain_rxdma1_2sw_leak_detected; 740 __le32 rx_dest_drain_rx_drain_ok_mac_idle; 741 __le32 rx_dest_drain_ok_mac_not_idle; 742 __le32 rx_dest_drain_prerequisite_invld; 743 __le32 rx_dest_drain_skip_non_lmac_reset; 744 __le32 rx_dest_drain_hw_fifo_notempty_post_wait; 745 } __packed; 746 747 #define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8 748 struct ath12k_htt_hw_stats_intr_misc_tlv { 749 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN]; 750 __le32 mask; 751 __le32 count; 752 } __packed; 753 754 struct ath12k_htt_hw_stats_whal_tx_tlv { 755 __le32 mac_id__word; 756 __le32 last_unpause_ppdu_id; 757 __le32 hwsch_unpause_wait_tqm_write; 758 __le32 hwsch_dummy_tlv_skipped; 759 __le32 hwsch_misaligned_offset_received; 760 __le32 hwsch_reset_count; 761 __le32 hwsch_dev_reset_war; 762 __le32 hwsch_delayed_pause; 763 __le32 hwsch_long_delayed_pause; 764 __le32 sch_rx_ppdu_no_response; 765 __le32 sch_selfgen_response; 766 __le32 sch_rx_sifs_resp_trigger; 767 } __packed; 768 769 struct ath12k_htt_hw_war_stats_tlv { 770 __le32 mac_id__word; 771 DECLARE_FLEX_ARRAY(__le32, hw_wars); 772 } __packed; 773 774 struct ath12k_htt_tx_tqm_cmn_stats_tlv { 775 __le32 mac_id__word; 776 __le32 max_cmdq_id; 777 __le32 list_mpdu_cnt_hist_intvl; 778 __le32 add_msdu; 779 __le32 q_empty; 780 __le32 q_not_empty; 781 __le32 drop_notification; 782 __le32 desc_threshold; 783 __le32 hwsch_tqm_invalid_status; 784 __le32 missed_tqm_gen_mpdus; 785 __le32 tqm_active_tids; 786 __le32 tqm_inactive_tids; 787 __le32 tqm_active_msduq_flows; 788 __le32 msduq_timestamp_updates; 789 __le32 msduq_updates_mpdu_head_info_cmd; 790 __le32 msduq_updates_emp_to_nonemp_status; 791 __le32 get_mpdu_head_info_cmds_by_query; 792 __le32 get_mpdu_head_info_cmds_by_tac; 793 __le32 gen_mpdu_cmds_by_query; 794 __le32 high_prio_q_not_empty; 795 } __packed; 796 797 struct ath12k_htt_tx_tqm_error_stats_tlv { 798 __le32 q_empty_failure; 799 __le32 q_not_empty_failure; 800 __le32 add_msdu_failure; 801 __le32 tqm_cache_ctl_err; 802 __le32 tqm_soft_reset; 803 __le32 tqm_reset_num_in_use_link_descs; 804 __le32 tqm_reset_num_lost_link_descs; 805 __le32 tqm_reset_num_lost_host_tx_buf_cnt; 806 __le32 tqm_reset_num_in_use_internal_tqm; 807 __le32 tqm_reset_num_in_use_idle_link_rng; 808 __le32 tqm_reset_time_to_tqm_hang_delta_ms; 809 __le32 tqm_reset_recovery_time_ms; 810 __le32 tqm_reset_num_peers_hdl; 811 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt; 812 __le32 tqm_reset_cumm_dirty_hw_msduq_proc; 813 __le32 tqm_reset_flush_cache_cmd_su_cnt; 814 __le32 tqm_reset_flush_cache_cmd_other_cnt; 815 __le32 tqm_reset_flush_cache_cmd_trig_type; 816 __le32 tqm_reset_flush_cache_cmd_trig_cfg; 817 __le32 tqm_reset_flush_cmd_skp_status_null; 818 } __packed; 819 820 struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv { 821 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason); 822 } __packed; 823 824 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 825 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 826 827 struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv { 828 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason); 829 } __packed; 830 831 struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv { 832 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist); 833 } __packed; 834 835 struct ath12k_htt_tx_tqm_pdev_stats_tlv { 836 __le32 msdu_count; 837 __le32 mpdu_count; 838 __le32 remove_msdu; 839 __le32 remove_mpdu; 840 __le32 remove_msdu_ttl; 841 __le32 send_bar; 842 __le32 bar_sync; 843 __le32 notify_mpdu; 844 __le32 sync_cmd; 845 __le32 write_cmd; 846 __le32 hwsch_trigger; 847 __le32 ack_tlv_proc; 848 __le32 gen_mpdu_cmd; 849 __le32 gen_list_cmd; 850 __le32 remove_mpdu_cmd; 851 __le32 remove_mpdu_tried_cmd; 852 __le32 mpdu_queue_stats_cmd; 853 __le32 mpdu_head_info_cmd; 854 __le32 msdu_flow_stats_cmd; 855 __le32 remove_msdu_cmd; 856 __le32 remove_msdu_ttl_cmd; 857 __le32 flush_cache_cmd; 858 __le32 update_mpduq_cmd; 859 __le32 enqueue; 860 __le32 enqueue_notify; 861 __le32 notify_mpdu_at_head; 862 __le32 notify_mpdu_state_valid; 863 __le32 sched_udp_notify1; 864 __le32 sched_udp_notify2; 865 __le32 sched_nonudp_notify1; 866 __le32 sched_nonudp_notify2; 867 } __packed; 868 869 struct ath12k_htt_tx_de_cmn_stats_tlv { 870 __le32 mac_id__word; 871 __le32 tcl2fw_entry_count; 872 __le32 not_to_fw; 873 __le32 invalid_pdev_vdev_peer; 874 __le32 tcl_res_invalid_addrx; 875 __le32 wbm2fw_entry_count; 876 __le32 invalid_pdev; 877 __le32 tcl_res_addrx_timeout; 878 __le32 invalid_vdev; 879 __le32 invalid_tcl_exp_frame_desc; 880 __le32 vdev_id_mismatch_cnt; 881 } __packed; 882 883 struct ath12k_htt_tx_de_eapol_packets_stats_tlv { 884 __le32 m1_packets; 885 __le32 m2_packets; 886 __le32 m3_packets; 887 __le32 m4_packets; 888 __le32 g1_packets; 889 __le32 g2_packets; 890 __le32 rc4_packets; 891 __le32 eap_packets; 892 __le32 eapol_start_packets; 893 __le32 eapol_logoff_packets; 894 __le32 eapol_encap_asf_packets; 895 } __packed; 896 897 struct ath12k_htt_tx_de_classify_stats_tlv { 898 __le32 arp_packets; 899 __le32 igmp_packets; 900 __le32 dhcp_packets; 901 __le32 host_inspected; 902 __le32 htt_included; 903 __le32 htt_valid_mcs; 904 __le32 htt_valid_nss; 905 __le32 htt_valid_preamble_type; 906 __le32 htt_valid_chainmask; 907 __le32 htt_valid_guard_interval; 908 __le32 htt_valid_retries; 909 __le32 htt_valid_bw_info; 910 __le32 htt_valid_power; 911 __le32 htt_valid_key_flags; 912 __le32 htt_valid_no_encryption; 913 __le32 fse_entry_count; 914 __le32 fse_priority_be; 915 __le32 fse_priority_high; 916 __le32 fse_priority_low; 917 __le32 fse_traffic_ptrn_be; 918 __le32 fse_traffic_ptrn_over_sub; 919 __le32 fse_traffic_ptrn_bursty; 920 __le32 fse_traffic_ptrn_interactive; 921 __le32 fse_traffic_ptrn_periodic; 922 __le32 fse_hwqueue_alloc; 923 __le32 fse_hwqueue_created; 924 __le32 fse_hwqueue_send_to_host; 925 __le32 mcast_entry; 926 __le32 bcast_entry; 927 __le32 htt_update_peer_cache; 928 __le32 htt_learning_frame; 929 __le32 fse_invalid_peer; 930 __le32 mec_notify; 931 } __packed; 932 933 struct ath12k_htt_tx_de_classify_failed_stats_tlv { 934 __le32 ap_bss_peer_not_found; 935 __le32 ap_bcast_mcast_no_peer; 936 __le32 sta_delete_in_progress; 937 __le32 ibss_no_bss_peer; 938 __le32 invalid_vdev_type; 939 __le32 invalid_ast_peer_entry; 940 __le32 peer_entry_invalid; 941 __le32 ethertype_not_ip; 942 __le32 eapol_lookup_failed; 943 __le32 qpeer_not_allow_data; 944 __le32 fse_tid_override; 945 __le32 ipv6_jumbogram_zero_length; 946 __le32 qos_to_non_qos_in_prog; 947 __le32 ap_bcast_mcast_eapol; 948 __le32 unicast_on_ap_bss_peer; 949 __le32 ap_vdev_invalid; 950 __le32 incomplete_llc; 951 __le32 eapol_duplicate_m3; 952 __le32 eapol_duplicate_m4; 953 } __packed; 954 955 struct ath12k_htt_tx_de_classify_status_stats_tlv { 956 __le32 eok; 957 __le32 classify_done; 958 __le32 lookup_failed; 959 __le32 send_host_dhcp; 960 __le32 send_host_mcast; 961 __le32 send_host_unknown_dest; 962 __le32 send_host; 963 __le32 status_invalid; 964 } __packed; 965 966 struct ath12k_htt_tx_de_enqueue_packets_stats_tlv { 967 __le32 enqueued_pkts; 968 __le32 to_tqm; 969 __le32 to_tqm_bypass; 970 } __packed; 971 972 struct ath12k_htt_tx_de_enqueue_discard_stats_tlv { 973 __le32 discarded_pkts; 974 __le32 local_frames; 975 __le32 is_ext_msdu; 976 } __packed; 977 978 struct ath12k_htt_tx_de_compl_stats_tlv { 979 __le32 tcl_dummy_frame; 980 __le32 tqm_dummy_frame; 981 __le32 tqm_notify_frame; 982 __le32 fw2wbm_enq; 983 __le32 tqm_bypass_frame; 984 } __packed; 985 986 enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats { 987 ATH12K_HTT_TX_MUMIMO_GRP_VALID, 988 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 989 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 990 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 991 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 992 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 993 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 994 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 995 ATH12K_HTT_TX_MUMIMO_GRP_INVALID, 996 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 997 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 998 }; 999 1000 #define ATH12K_HTT_NUM_AC_WMM 0x4 1001 #define ATH12K_HTT_MAX_NUM_SBT_INTR 4 1002 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 1003 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 1004 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 1005 #define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7 1006 #define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74 1007 #define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8 1008 #define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8 1009 #define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 1010 1011 #define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \ 1012 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 1013 #define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 1014 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE) 1015 1016 struct ath12k_htt_tx_selfgen_cmn_stats_tlv { 1017 __le32 mac_id__word; 1018 __le32 su_bar; 1019 __le32 rts; 1020 __le32 cts2self; 1021 __le32 qos_null; 1022 __le32 delayed_bar_1; 1023 __le32 delayed_bar_2; 1024 __le32 delayed_bar_3; 1025 __le32 delayed_bar_4; 1026 __le32 delayed_bar_5; 1027 __le32 delayed_bar_6; 1028 __le32 delayed_bar_7; 1029 } __packed; 1030 1031 struct ath12k_htt_tx_selfgen_ac_stats_tlv { 1032 __le32 ac_su_ndpa; 1033 __le32 ac_su_ndp; 1034 __le32 ac_mu_mimo_ndpa; 1035 __le32 ac_mu_mimo_ndp; 1036 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1]; 1037 } __packed; 1038 1039 struct ath12k_htt_tx_selfgen_ax_stats_tlv { 1040 __le32 ax_su_ndpa; 1041 __le32 ax_su_ndp; 1042 __le32 ax_mu_mimo_ndpa; 1043 __le32 ax_mu_mimo_ndp; 1044 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 1045 __le32 ax_basic_trigger; 1046 __le32 ax_bsr_trigger; 1047 __le32 ax_mu_bar_trigger; 1048 __le32 ax_mu_rts_trigger; 1049 __le32 ax_ulmumimo_trigger; 1050 } __packed; 1051 1052 struct ath12k_htt_tx_selfgen_be_stats_tlv { 1053 __le32 be_su_ndpa; 1054 __le32 be_su_ndp; 1055 __le32 be_mu_mimo_ndpa; 1056 __le32 be_mu_mimo_ndp; 1057 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1058 __le32 be_basic_trigger; 1059 __le32 be_bsr_trigger; 1060 __le32 be_mu_bar_trigger; 1061 __le32 be_mu_rts_trigger; 1062 __le32 be_ulmumimo_trigger; 1063 __le32 be_su_ndpa_queued; 1064 __le32 be_su_ndp_queued; 1065 __le32 be_mu_mimo_ndpa_queued; 1066 __le32 be_mu_mimo_ndp_queued; 1067 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1068 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1069 } __packed; 1070 1071 struct ath12k_htt_tx_selfgen_ac_err_stats_tlv { 1072 __le32 ac_su_ndp_err; 1073 __le32 ac_su_ndpa_err; 1074 __le32 ac_mu_mimo_ndpa_err; 1075 __le32 ac_mu_mimo_ndp_err; 1076 __le32 ac_mu_mimo_brp1_err; 1077 __le32 ac_mu_mimo_brp2_err; 1078 __le32 ac_mu_mimo_brp3_err; 1079 } __packed; 1080 1081 struct ath12k_htt_tx_selfgen_ax_err_stats_tlv { 1082 __le32 ax_su_ndp_err; 1083 __le32 ax_su_ndpa_err; 1084 __le32 ax_mu_mimo_ndpa_err; 1085 __le32 ax_mu_mimo_ndp_err; 1086 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 1087 __le32 ax_basic_trigger_err; 1088 __le32 ax_bsr_trigger_err; 1089 __le32 ax_mu_bar_trigger_err; 1090 __le32 ax_mu_rts_trigger_err; 1091 __le32 ax_ulmumimo_trigger_err; 1092 } __packed; 1093 1094 struct ath12k_htt_tx_selfgen_be_err_stats_tlv { 1095 __le32 be_su_ndp_err; 1096 __le32 be_su_ndpa_err; 1097 __le32 be_mu_mimo_ndpa_err; 1098 __le32 be_mu_mimo_ndp_err; 1099 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1100 __le32 be_basic_trigger_err; 1101 __le32 be_bsr_trigger_err; 1102 __le32 be_mu_bar_trigger_err; 1103 __le32 be_mu_rts_trigger_err; 1104 __le32 be_ulmumimo_trigger_err; 1105 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1106 __le32 be_su_ndpa_flushed; 1107 __le32 be_su_ndp_flushed; 1108 __le32 be_mu_mimo_ndpa_flushed; 1109 __le32 be_mu_mimo_ndp_flushed; 1110 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1111 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1112 } __packed; 1113 1114 enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats { 1115 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 1116 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 1117 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 1118 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 1119 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 1120 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 1121 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 1122 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 1123 1124 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS 1125 }; 1126 1127 struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv { 1128 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1129 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1130 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1131 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1132 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1133 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1134 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1135 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1136 } __packed; 1137 1138 struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv { 1139 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1140 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1141 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1142 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1143 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1144 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1145 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1146 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1147 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1148 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1149 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1150 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1151 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1152 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1153 } __packed; 1154 1155 struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv { 1156 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1157 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1158 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1159 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1160 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1161 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1162 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1163 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1164 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1165 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1166 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1167 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1168 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1169 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1170 } __packed; 1171 1172 struct ath12k_htt_stats_string_tlv { 1173 DECLARE_FLEX_ARRAY(__le32, data); 1174 } __packed; 1175 1176 #define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 1177 #define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8) 1178 #define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16) 1179 #define ATH12K_HTT_SRING_STATS_EP BIT(24) 1180 #define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 1181 #define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 1182 #define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 1183 #define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 1184 #define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 1185 #define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 1186 #define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 1187 #define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 1188 1189 struct ath12k_htt_sring_stats_tlv { 1190 __le32 mac_id__ring_id__arena__ep; 1191 __le32 base_addr_lsb; 1192 __le32 base_addr_msb; 1193 __le32 ring_size; 1194 __le32 elem_size; 1195 __le32 num_avail_words__num_valid_words; 1196 __le32 head_ptr__tail_ptr; 1197 __le32 consumer_empty__producer_full; 1198 __le32 prefetch_count__internal_tail_ptr; 1199 } __packed; 1200 1201 struct ath12k_htt_sfm_cmn_tlv { 1202 __le32 mac_id__word; 1203 __le32 buf_total; 1204 __le32 mem_empty; 1205 __le32 deallocate_bufs; 1206 __le32 num_records; 1207 } __packed; 1208 1209 struct ath12k_htt_sfm_client_tlv { 1210 __le32 client_id; 1211 __le32 buf_min; 1212 __le32 buf_max; 1213 __le32 buf_busy; 1214 __le32 buf_alloc; 1215 __le32 buf_avail; 1216 __le32 num_users; 1217 } __packed; 1218 1219 struct ath12k_htt_sfm_client_user_tlv { 1220 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n); 1221 } __packed; 1222 1223 struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv { 1224 __le32 mu_mimo_sch_posted; 1225 __le32 mu_mimo_sch_failed; 1226 __le32 mu_mimo_ppdu_posted; 1227 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1228 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1229 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1230 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1231 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1232 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1233 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1234 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1235 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1236 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1237 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1238 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1239 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1240 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1241 } __packed; 1242 1243 struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv { 1244 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1245 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1246 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1247 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1248 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 1249 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1250 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1251 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1252 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1253 } __packed; 1254 1255 enum ath12k_htt_stats_tx_sched_modes { 1256 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0, 1257 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX, 1258 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX, 1259 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE, 1260 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 1261 }; 1262 1263 struct ath12k_htt_tx_pdev_mpdu_stats_tlv { 1264 __le32 mpdus_queued_usr; 1265 __le32 mpdus_tried_usr; 1266 __le32 mpdus_failed_usr; 1267 __le32 mpdus_requeued_usr; 1268 __le32 err_no_ba_usr; 1269 __le32 mpdu_underrun_usr; 1270 __le32 ampdu_underrun_usr; 1271 __le32 user_index; 1272 __le32 tx_sched_mode; 1273 } __packed; 1274 1275 struct ath12k_htt_pdev_stats_cca_counters_tlv { 1276 __le32 tx_frame_usec; 1277 __le32 rx_frame_usec; 1278 __le32 rx_clear_usec; 1279 __le32 my_rx_frame_usec; 1280 __le32 usec_cnt; 1281 __le32 med_rx_idle_usec; 1282 __le32 med_tx_idle_global_usec; 1283 __le32 cca_obss_usec; 1284 } __packed; 1285 1286 struct ath12k_htt_pdev_cca_stats_hist_v1_tlv { 1287 __le32 chan_num; 1288 __le32 num_records; 1289 __le32 valid_cca_counters_bitmap; 1290 __le32 collection_interval; 1291 } __packed; 1292 1293 #define ATH12K_HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 1294 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 1295 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 1296 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 1297 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1298 #define ATH12K_HTT_TX_NUM_MCS_CNTRS 12 1299 #define ATH12K_HTT_TX_NUM_EXTRA_MCS_CNTRS 2 1300 1301 #define ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1302 (ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1303 ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS) 1304 1305 enum ath12k_htt_txbf_sound_steer_modes { 1306 ATH12K_HTT_IMPL_STEER_STATS = 0, 1307 ATH12K_HTT_EXPL_SUSIFS_STEER_STATS = 1, 1308 ATH12K_HTT_EXPL_SURBO_STEER_STATS = 2, 1309 ATH12K_HTT_EXPL_MUSIFS_STEER_STATS = 3, 1310 ATH12K_HTT_EXPL_MURBO_STEER_STATS = 4, 1311 ATH12K_HTT_TXBF_MAX_NUM_OF_MODES = 5 1312 }; 1313 1314 enum ath12k_htt_stats_sounding_tx_mode { 1315 ATH12K_HTT_TX_AC_SOUNDING_MODE = 0, 1316 ATH12K_HTT_TX_AX_SOUNDING_MODE = 1, 1317 ATH12K_HTT_TX_BE_SOUNDING_MODE = 2, 1318 ATH12K_HTT_TX_CMN_SOUNDING_MODE = 3, 1319 }; 1320 1321 struct ath12k_htt_tx_sounding_stats_tlv { 1322 __le32 tx_sounding_mode; 1323 __le32 cbf_20[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1324 __le32 cbf_40[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1325 __le32 cbf_80[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1326 __le32 cbf_160[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1327 __le32 sounding[ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1328 __le32 cv_nc_mismatch_err; 1329 __le32 cv_fcs_err; 1330 __le32 cv_frag_idx_mismatch; 1331 __le32 cv_invalid_peer_id; 1332 __le32 cv_no_txbf_setup; 1333 __le32 cv_expiry_in_update; 1334 __le32 cv_pkt_bw_exceed; 1335 __le32 cv_dma_not_done_err; 1336 __le32 cv_update_failed; 1337 __le32 cv_total_query; 1338 __le32 cv_total_pattern_query; 1339 __le32 cv_total_bw_query; 1340 __le32 cv_invalid_bw_coding; 1341 __le32 cv_forced_sounding; 1342 __le32 cv_standalone_sounding; 1343 __le32 cv_nc_mismatch; 1344 __le32 cv_fb_type_mismatch; 1345 __le32 cv_ofdma_bw_mismatch; 1346 __le32 cv_bw_mismatch; 1347 __le32 cv_pattern_mismatch; 1348 __le32 cv_preamble_mismatch; 1349 __le32 cv_nr_mismatch; 1350 __le32 cv_in_use_cnt_exceeded; 1351 __le32 cv_found; 1352 __le32 cv_not_found; 1353 __le32 sounding_320[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1354 __le32 cbf_320[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1355 __le32 cv_ntbr_sounding; 1356 __le32 cv_found_upload_in_progress; 1357 __le32 cv_expired_during_query; 1358 __le32 cv_dma_timeout_error; 1359 __le32 cv_buf_ibf_uploads; 1360 __le32 cv_buf_ebf_uploads; 1361 __le32 cv_buf_received; 1362 __le32 cv_buf_fed_back; 1363 __le32 cv_total_query_ibf; 1364 __le32 cv_found_ibf; 1365 __le32 cv_not_found_ibf; 1366 __le32 cv_expired_during_query_ibf; 1367 } __packed; 1368 1369 struct ath12k_htt_pdev_obss_pd_stats_tlv { 1370 __le32 num_obss_tx_ppdu_success; 1371 __le32 num_obss_tx_ppdu_failure; 1372 __le32 num_sr_tx_transmissions; 1373 __le32 num_spatial_reuse_opportunities; 1374 __le32 num_non_srg_opportunities; 1375 __le32 num_non_srg_ppdu_tried; 1376 __le32 num_non_srg_ppdu_success; 1377 __le32 num_srg_opportunities; 1378 __le32 num_srg_ppdu_tried; 1379 __le32 num_srg_ppdu_success; 1380 __le32 num_psr_opportunities; 1381 __le32 num_psr_ppdu_tried; 1382 __le32 num_psr_ppdu_success; 1383 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1384 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM]; 1385 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1386 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1387 __le32 num_obss_min_dur_check_flush_cnt; 1388 __le32 num_sr_ppdu_abort_flush_cnt; 1389 } __packed; 1390 1391 #define ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 1392 #define ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST 3 1393 #define ATH12K_HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 1394 1395 struct ath12k_htt_latency_prof_stats_tlv { 1396 __le32 print_header; 1397 s8 latency_prof_name[ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 1398 __le32 cnt; 1399 __le32 min; 1400 __le32 max; 1401 __le32 last; 1402 __le32 tot; 1403 __le32 avg; 1404 __le32 hist_intvl; 1405 __le32 hist[ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST]; 1406 } __packed; 1407 1408 struct ath12k_htt_latency_prof_ctx_tlv { 1409 __le32 duration; 1410 __le32 tx_msdu_cnt; 1411 __le32 tx_mpdu_cnt; 1412 __le32 tx_ppdu_cnt; 1413 __le32 rx_msdu_cnt; 1414 __le32 rx_mpdu_cnt; 1415 } __packed; 1416 1417 struct ath12k_htt_latency_prof_cnt_tlv { 1418 __le32 prof_enable_cnt; 1419 } __packed; 1420 1421 #define ATH12K_HTT_RX_NUM_MCS_CNTRS 12 1422 #define ATH12K_HTT_RX_NUM_GI_CNTRS 4 1423 #define ATH12K_HTT_RX_NUM_SPATIAL_STREAMS 8 1424 #define ATH12K_HTT_RX_NUM_BW_CNTRS 4 1425 #define ATH12K_HTT_RX_NUM_RU_SIZE_CNTRS 6 1426 #define ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS 7 1427 #define ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 1428 #define ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES 2 1429 #define ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS 2 1430 1431 enum ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE { 1432 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_26, 1433 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_52, 1434 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_106, 1435 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_242, 1436 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_484, 1437 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996, 1438 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996x2, 1439 ATH12K_HTT_TX_RX_PDEV_STATS_NUM_AX_RU_SIZE_CNTRS, 1440 }; 1441 1442 struct ath12k_htt_rx_pdev_ul_ofdma_user_stats_tlv { 1443 __le32 user_index; 1444 __le32 rx_ulofdma_non_data_ppdu; 1445 __le32 rx_ulofdma_data_ppdu; 1446 __le32 rx_ulofdma_mpdu_ok; 1447 __le32 rx_ulofdma_mpdu_fail; 1448 __le32 rx_ulofdma_non_data_nusers; 1449 __le32 rx_ulofdma_data_nusers; 1450 } __packed; 1451 1452 struct ath12k_htt_rx_pdev_ul_trigger_stats_tlv { 1453 __le32 mac_id__word; 1454 __le32 rx_11ax_ul_ofdma; 1455 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1456 __le32 ul_ofdma_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1457 __le32 ul_ofdma_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1458 __le32 ul_ofdma_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS]; 1459 __le32 ul_ofdma_rx_stbc; 1460 __le32 ul_ofdma_rx_ldpc; 1461 __le32 data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS]; 1462 __le32 non_data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS]; 1463 __le32 uplink_sta_aid[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1464 __le32 uplink_sta_target_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1465 __le32 uplink_sta_fd_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1466 __le32 uplink_sta_power_headroom[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1467 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1468 __le32 ul_ofdma_bsc_trig_rx_qos_null_only; 1469 } __packed; 1470 1471 #define ATH12K_HTT_TX_UL_MUMIMO_USER_STATS 8 1472 1473 struct ath12k_htt_rx_ul_mumimo_trig_stats_tlv { 1474 __le32 mac_id__word; 1475 __le32 rx_11ax_ul_mumimo; 1476 __le32 ul_mumimo_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1477 __le32 ul_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1478 __le32 ul_mumimo_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1479 __le32 ul_mumimo_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS]; 1480 __le32 ul_mumimo_rx_stbc; 1481 __le32 ul_mumimo_rx_ldpc; 1482 __le32 ul_mumimo_rx_mcs_ext[ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS]; 1483 __le32 ul_gi_ext[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS]; 1484 s8 ul_rssi[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1485 s8 tgt_rssi[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1486 s8 fd[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1487 s8 db[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1488 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1489 __le32 mumimo_bsc_trig_rx_qos_null_only; 1490 } __packed; 1491 1492 #define ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX 10 1493 #define ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX 10 1494 #define ATH12K_HTT_RX_NUM_SQUARE_INDEX 6 1495 #define ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX 4 1496 #define ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX 4 1497 1498 struct ath12k_htt_rx_fse_stats_tlv { 1499 __le32 fse_enable_cnt; 1500 __le32 fse_disable_cnt; 1501 __le32 fse_cache_invalidate_entry_cnt; 1502 __le32 fse_full_cache_invalidate_cnt; 1503 __le32 fse_num_cache_hits_cnt; 1504 __le32 fse_num_searches_cnt; 1505 __le32 fse_cache_occupancy_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX]; 1506 __le32 fse_cache_occupancy_curr_cnt[ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX]; 1507 __le32 fse_search_stat_square_cnt[ATH12K_HTT_RX_NUM_SQUARE_INDEX]; 1508 __le32 fse_search_stat_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX]; 1509 __le32 fse_search_stat_pending_cnt[ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX]; 1510 } __packed; 1511 1512 #define ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS 14 1513 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1514 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1515 #define ATH12K_HTT_TXBF_NUM_BW_CNTRS 5 1516 #define ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES 2 1517 1518 struct ath12k_htt_pdev_txrate_txbf_stats_tlv { 1519 __le32 tx_su_txbf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1520 __le32 tx_su_ibf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1521 __le32 tx_su_ol_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1522 __le32 tx_su_txbf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1523 __le32 tx_su_ibf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1524 __le32 tx_su_ol_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1525 __le32 tx_su_txbf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1526 __le32 tx_su_ibf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1527 __le32 tx_su_ol_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1528 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1529 __le32 txbf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1530 __le32 ibf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1531 __le32 ol[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1532 __le32 txbf_flag_set_mu_mode; 1533 __le32 txbf_flag_set_final_status; 1534 __le32 txbf_flag_not_set_verified_txbf_mode; 1535 __le32 txbf_flag_not_set_disable_p2p_access; 1536 __le32 txbf_flag_not_set_max_nss_in_he160; 1537 __le32 txbf_flag_not_set_disable_uldlofdma; 1538 __le32 txbf_flag_not_set_mcs_threshold_val; 1539 __le32 txbf_flag_not_set_final_status; 1540 } __packed; 1541 1542 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t { 1543 __le32 ax_ofdma_ndpa_queued; 1544 __le32 ax_ofdma_ndpa_tried; 1545 __le32 ax_ofdma_ndpa_flush; 1546 __le32 ax_ofdma_ndpa_err; 1547 } __packed; 1548 1549 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_tlv { 1550 __le32 num_elems_ax_ndpa_arr; 1551 __le32 arr_elem_size_ax_ndpa; 1552 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa); 1553 } __packed; 1554 1555 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t { 1556 __le32 ax_ofdma_ndp_queued; 1557 __le32 ax_ofdma_ndp_tried; 1558 __le32 ax_ofdma_ndp_flush; 1559 __le32 ax_ofdma_ndp_err; 1560 } __packed; 1561 1562 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_tlv { 1563 __le32 num_elems_ax_ndp_arr; 1564 __le32 arr_elem_size_ax_ndp; 1565 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp); 1566 } __packed; 1567 1568 struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t { 1569 __le32 ax_ofdma_brp_queued; 1570 __le32 ax_ofdma_brp_tried; 1571 __le32 ax_ofdma_brp_flushed; 1572 __le32 ax_ofdma_brp_err; 1573 __le32 ax_ofdma_num_cbf_rcvd; 1574 } __packed; 1575 1576 struct ath12k_htt_txbf_ofdma_ax_brp_stats_tlv { 1577 __le32 num_elems_ax_brp_arr; 1578 __le32 arr_elem_size_ax_brp; 1579 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp); 1580 } __packed; 1581 1582 struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t { 1583 __le32 num_ppdu_steer; 1584 __le32 num_ppdu_ol; 1585 __le32 num_usr_prefetch; 1586 __le32 num_usr_sound; 1587 __le32 num_usr_force_sound; 1588 } __packed; 1589 1590 struct ath12k_htt_txbf_ofdma_ax_steer_stats_tlv { 1591 __le32 num_elems_ax_steer_arr; 1592 __le32 arr_elem_size_ax_steer; 1593 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer); 1594 } __packed; 1595 1596 struct ath12k_htt_txbf_ofdma_ax_steer_mpdu_stats_tlv { 1597 __le32 ax_ofdma_rbo_steer_mpdus_tried; 1598 __le32 ax_ofdma_rbo_steer_mpdus_failed; 1599 __le32 ax_ofdma_sifs_steer_mpdus_tried; 1600 __le32 ax_ofdma_sifs_steer_mpdus_failed; 1601 } __packed; 1602 1603 enum ath12k_htt_stats_page_lock_state { 1604 ATH12K_HTT_STATS_PAGE_LOCKED = 0, 1605 ATH12K_HTT_STATS_PAGE_UNLOCKED = 1, 1606 ATH12K_NUM_PG_LOCK_STATE 1607 }; 1608 1609 #define ATH12K_PAGER_MAX 10 1610 1611 #define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0) 1612 #define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8) 1613 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0) 1614 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16) 1615 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0) 1616 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16) 1617 1618 struct ath12k_htt_pgs_info { 1619 __le32 page_num; 1620 __le32 num_pgs; 1621 __le32 ts_lsb; 1622 __le32 ts_msb; 1623 } __packed; 1624 1625 struct ath12k_htt_dl_pager_stats_tlv { 1626 __le32 info0; 1627 __le32 info1; 1628 __le32 info2; 1629 struct ath12k_htt_pgs_info pgs_info[ATH12K_NUM_PG_LOCK_STATE][ATH12K_PAGER_MAX]; 1630 } __packed; 1631 1632 #define ATH12K_HTT_STATS_MAX_CHAINS 8 1633 #define ATH12K_HTT_MAX_RX_PKT_CNT 8 1634 #define ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1635 #define ATH12K_HTT_MAX_PER_BLK_ERR_CNT 20 1636 #define ATH12K_HTT_MAX_RX_OTA_ERR_CNT 14 1637 #define ATH12K_HTT_MAX_CH_PWR_INFO_SIZE 16 1638 1639 struct ath12k_htt_phy_stats_tlv { 1640 a_sle32 nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1641 __le32 false_radar_cnt; 1642 __le32 radar_cs_cnt; 1643 a_sle32 ani_level; 1644 __le32 fw_run_time; 1645 a_sle32 runtime_nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1646 } __packed; 1647 1648 struct ath12k_htt_phy_counters_tlv { 1649 __le32 rx_ofdma_timing_err_cnt; 1650 __le32 rx_cck_fail_cnt; 1651 __le32 mactx_abort_cnt; 1652 __le32 macrx_abort_cnt; 1653 __le32 phytx_abort_cnt; 1654 __le32 phyrx_abort_cnt; 1655 __le32 phyrx_defer_abort_cnt; 1656 __le32 rx_gain_adj_lstf_event_cnt; 1657 __le32 rx_gain_adj_non_legacy_cnt; 1658 __le32 rx_pkt_cnt[ATH12K_HTT_MAX_RX_PKT_CNT]; 1659 __le32 rx_pkt_crc_pass_cnt[ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1660 __le32 per_blk_err_cnt[ATH12K_HTT_MAX_PER_BLK_ERR_CNT]; 1661 __le32 rx_ota_err_cnt[ATH12K_HTT_MAX_RX_OTA_ERR_CNT]; 1662 } __packed; 1663 1664 struct ath12k_htt_phy_reset_stats_tlv { 1665 __le32 pdev_id; 1666 __le32 chan_mhz; 1667 __le32 chan_band_center_freq1; 1668 __le32 chan_band_center_freq2; 1669 __le32 chan_phy_mode; 1670 __le32 chan_flags; 1671 __le32 chan_num; 1672 __le32 reset_cause; 1673 __le32 prev_reset_cause; 1674 __le32 phy_warm_reset_src; 1675 __le32 rx_gain_tbl_mode; 1676 __le32 xbar_val; 1677 __le32 force_calibration; 1678 __le32 phyrf_mode; 1679 __le32 phy_homechan; 1680 __le32 phy_tx_ch_mask; 1681 __le32 phy_rx_ch_mask; 1682 __le32 phybb_ini_mask; 1683 __le32 phyrf_ini_mask; 1684 __le32 phy_dfs_en_mask; 1685 __le32 phy_sscan_en_mask; 1686 __le32 phy_synth_sel_mask; 1687 __le32 phy_adfs_freq; 1688 __le32 cck_fir_settings; 1689 __le32 phy_dyn_pri_chan; 1690 __le32 cca_thresh; 1691 __le32 dyn_cca_status; 1692 __le32 rxdesense_thresh_hw; 1693 __le32 rxdesense_thresh_sw; 1694 } __packed; 1695 1696 struct ath12k_htt_phy_reset_counters_tlv { 1697 __le32 pdev_id; 1698 __le32 cf_active_low_fail_cnt; 1699 __le32 cf_active_low_pass_cnt; 1700 __le32 phy_off_through_vreg_cnt; 1701 __le32 force_calibration_cnt; 1702 __le32 rf_mode_switch_phy_off_cnt; 1703 __le32 temperature_recal_cnt; 1704 } __packed; 1705 1706 struct ath12k_htt_phy_tpc_stats_tlv { 1707 __le32 pdev_id; 1708 __le32 tx_power_scale; 1709 __le32 tx_power_scale_db; 1710 __le32 min_negative_tx_power; 1711 __le32 reg_ctl_domain; 1712 __le32 max_reg_allowed_power[ATH12K_HTT_STATS_MAX_CHAINS]; 1713 __le32 max_reg_allowed_power_6ghz[ATH12K_HTT_STATS_MAX_CHAINS]; 1714 __le32 twice_max_rd_power; 1715 __le32 max_tx_power; 1716 __le32 home_max_tx_power; 1717 __le32 psd_power; 1718 __le32 eirp_power; 1719 __le32 power_type_6ghz; 1720 __le32 sub_band_cfreq[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1721 __le32 sub_band_txpower[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1722 } __packed; 1723 1724 struct ath12k_htt_t2h_soc_txrx_stats_common_tlv { 1725 __le32 inv_peers_msdu_drop_count_hi; 1726 __le32 inv_peers_msdu_drop_count_lo; 1727 } __packed; 1728 1729 #define ATH12K_HTT_AST_PDEV_ID_INFO GENMASK(1, 0) 1730 #define ATH12K_HTT_AST_VDEV_ID_INFO GENMASK(9, 2) 1731 #define ATH12K_HTT_AST_NEXT_HOP_INFO BIT(10) 1732 #define ATH12K_HTT_AST_MCAST_INFO BIT(11) 1733 #define ATH12K_HTT_AST_MONITOR_DIRECT_INFO BIT(12) 1734 #define ATH12K_HTT_AST_MESH_STA_INFO BIT(13) 1735 #define ATH12K_HTT_AST_MEC_INFO BIT(14) 1736 #define ATH12K_HTT_AST_INTRA_BSS_INFO BIT(15) 1737 1738 struct ath12k_htt_ast_entry_tlv { 1739 __le32 sw_peer_id; 1740 __le32 ast_index; 1741 struct htt_mac_addr mac_addr; 1742 __le32 info; 1743 } __packed; 1744 1745 enum ath12k_htt_stats_direction { 1746 ATH12K_HTT_STATS_DIRECTION_TX, 1747 ATH12K_HTT_STATS_DIRECTION_RX 1748 }; 1749 1750 enum ath12k_htt_stats_ppdu_type { 1751 ATH12K_HTT_STATS_PPDU_TYPE_MODE_SU, 1752 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_MIMO, 1753 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_MIMO, 1754 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, 1755 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_OFDMA 1756 }; 1757 1758 enum ath12k_htt_stats_param_type { 1759 ATH12K_HTT_STATS_PREAM_OFDM, 1760 ATH12K_HTT_STATS_PREAM_CCK, 1761 ATH12K_HTT_STATS_PREAM_HT, 1762 ATH12K_HTT_STATS_PREAM_VHT, 1763 ATH12K_HTT_STATS_PREAM_HE, 1764 ATH12K_HTT_STATS_PREAM_EHT, 1765 ATH12K_HTT_STATS_PREAM_RSVD1, 1766 ATH12K_HTT_STATS_PREAM_COUNT, 1767 }; 1768 1769 #define ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT 32 1770 1771 struct ath12k_htt_pdev_puncture_stats_tlv { 1772 __le32 mac_id__word; 1773 __le32 direction; 1774 __le32 preamble; 1775 __le32 ppdu_type; 1776 __le32 subband_cnt; 1777 __le32 last_used_pattern_mask; 1778 __le32 num_subbands_used_cnt[ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT]; 1779 } __packed; 1780 1781 struct ath12k_htt_dmac_reset_stats_tlv { 1782 __le32 reset_count; 1783 __le32 reset_time_lo_ms; 1784 __le32 reset_time_hi_ms; 1785 __le32 disengage_time_lo_ms; 1786 __le32 disengage_time_hi_ms; 1787 __le32 engage_time_lo_ms; 1788 __le32 engage_time_hi_ms; 1789 __le32 disengage_count; 1790 __le32 engage_count; 1791 __le32 drain_dest_ring_mask; 1792 } __packed; 1793 1794 struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv { 1795 __le32 mac_id__word; 1796 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1797 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1798 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM]; 1799 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1800 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1801 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1802 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1803 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM]; 1804 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM]; 1805 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM]; 1806 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM]; 1807 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM]; 1808 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM]; 1809 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM]; 1810 } __packed; 1811 1812 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS 4 1813 #define ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS 8 1814 #define ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS 14 1815 1816 enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE { 1817 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26, 1818 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52, 1819 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26, 1820 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106, 1821 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26, 1822 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242, 1823 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484, 1824 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242, 1825 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996, 1826 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484, 1827 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 1828 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2, 1829 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 1830 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3, 1831 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 1832 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4, 1833 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS, 1834 }; 1835 1836 enum ATH12K_HTT_RC_MODE { 1837 ATH12K_HTT_RC_MODE_SU_OL, 1838 ATH12K_HTT_RC_MODE_SU_BF, 1839 ATH12K_HTT_RC_MODE_MU1_INTF, 1840 ATH12K_HTT_RC_MODE_MU2_INTF, 1841 ATH12K_HTT_RC_MODE_MU3_INTF, 1842 ATH12K_HTT_RC_MODE_MU4_INTF, 1843 ATH12K_HTT_RC_MODE_MU5_INTF, 1844 ATH12K_HTT_RC_MODE_MU6_INTF, 1845 ATH12K_HTT_RC_MODE_MU7_INTF, 1846 ATH12K_HTT_RC_MODE_2D_COUNT 1847 }; 1848 1849 enum ath12k_htt_stats_rc_mode { 1850 ATH12K_HTT_STATS_RC_MODE_DLSU = 0, 1851 ATH12K_HTT_STATS_RC_MODE_DLMUMIMO = 1, 1852 ATH12K_HTT_STATS_RC_MODE_DLOFDMA = 2, 1853 ATH12K_HTT_STATS_RC_MODE_ULMUMIMO = 3, 1854 ATH12K_HTT_STATS_RC_MODE_ULOFDMA = 4, 1855 }; 1856 1857 enum ath12k_htt_stats_ru_type { 1858 ATH12K_HTT_STATS_RU_TYPE_INVALID, 1859 ATH12K_HTT_STATS_RU_TYPE_SINGLE_RU_ONLY, 1860 ATH12K_HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU, 1861 }; 1862 1863 struct ath12k_htt_tx_rate_stats { 1864 __le32 ppdus_tried; 1865 __le32 ppdus_ack_failed; 1866 __le32 mpdus_tried; 1867 __le32 mpdus_failed; 1868 } __packed; 1869 1870 struct ath12k_htt_tx_per_rate_stats_tlv { 1871 __le32 rc_mode; 1872 __le32 last_probed_mcs; 1873 __le32 last_probed_nss; 1874 __le32 last_probed_bw; 1875 struct ath12k_htt_tx_rate_stats per_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS]; 1876 struct ath12k_htt_tx_rate_stats per_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1877 struct ath12k_htt_tx_rate_stats per_mcs[ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS]; 1878 struct ath12k_htt_tx_rate_stats per_bw320; 1879 __le32 probe_cnt[ATH12K_HTT_RC_MODE_2D_COUNT]; 1880 __le32 ru_type; 1881 struct ath12k_htt_tx_rate_stats ru[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1882 } __packed; 1883 1884 #define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16 1885 #define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5 1886 #define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4 1887 #define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4 1888 1889 struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv { 1890 __le32 mac_id__word; 1891 __le32 be_ofdma_tx_ldpc; 1892 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1893 __le32 be_ofdma_tx_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1894 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS]; 1895 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1896 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1897 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS]; 1898 } __packed; 1899 1900 struct ath12k_htt_pdev_mbssid_ctrl_frame_tlv { 1901 __le32 mac_id__word; 1902 __le32 basic_trigger_across_bss; 1903 __le32 basic_trigger_within_bss; 1904 __le32 bsr_trigger_across_bss; 1905 __le32 bsr_trigger_within_bss; 1906 __le32 mu_rts_across_bss; 1907 __le32 mu_rts_within_bss; 1908 __le32 ul_mumimo_trigger_across_bss; 1909 __le32 ul_mumimo_trigger_within_bss; 1910 } __packed; 1911 1912 struct ath12k_htt_pdev_tdma_stats_tlv { 1913 __le32 mac_id__word; 1914 __le32 num_tdma_active_schedules; 1915 __le32 num_tdma_reserved_schedules; 1916 __le32 num_tdma_restricted_schedules; 1917 __le32 num_tdma_unconfigured_schedules; 1918 __le32 num_tdma_slot_switches; 1919 __le32 num_tdma_edca_switches; 1920 } __packed; 1921 1922 struct ath12k_htt_mlo_sched_stats_tlv { 1923 __le32 pref_link_num_sec_link_sched; 1924 __le32 pref_link_num_pref_link_timeout; 1925 __le32 pref_link_num_pref_link_sch_delay_ipc; 1926 __le32 pref_link_num_pref_link_timeout_ipc; 1927 } __packed; 1928 1929 #define ATH12K_HTT_HWMLO_MAX_LINKS 6 1930 #define ATH12K_HTT_MLO_MAX_IPC_RINGS 7 1931 1932 struct ath12k_htt_pdev_mlo_ipc_stats_tlv { 1933 __le32 mlo_ipc_ring_cnt[ATH12K_HTT_HWMLO_MAX_LINKS][ATH12K_HTT_MLO_MAX_IPC_RINGS]; 1934 } __packed; 1935 1936 struct ath12k_htt_stats_pdev_rtt_resp_stats_tlv { 1937 __le32 pdev_id; 1938 __le32 tx_11mc_ftm_suc; 1939 __le32 tx_11mc_ftm_suc_retry; 1940 __le32 tx_11mc_ftm_fail; 1941 __le32 rx_11mc_ftmr_cnt; 1942 __le32 rx_11mc_ftmr_dup_cnt; 1943 __le32 rx_11mc_iftmr_cnt; 1944 __le32 rx_11mc_iftmr_dup_cnt; 1945 __le32 ftmr_drop_11mc_resp_role_not_enabled_cnt; 1946 __le32 initiator_active_responder_rejected_cnt; 1947 __le32 responder_terminate_cnt; 1948 __le32 active_rsta_open; 1949 __le32 active_rsta_mac; 1950 __le32 active_rsta_mac_phy; 1951 __le32 num_assoc_ranging_peers; 1952 __le32 num_unassoc_ranging_peers; 1953 __le32 responder_alloc_cnt; 1954 __le32 responder_alloc_failure; 1955 __le32 pn_check_failure_cnt; 1956 __le32 pasn_m1_auth_recv_cnt; 1957 __le32 pasn_m1_auth_drop_cnt; 1958 __le32 pasn_m2_auth_recv_cnt; 1959 __le32 pasn_m2_auth_tx_fail_cnt; 1960 __le32 pasn_m3_auth_recv_cnt; 1961 __le32 pasn_m3_auth_drop_cnt; 1962 __le32 pasn_peer_create_request_cnt; 1963 __le32 pasn_peer_create_timeout_cnt; 1964 __le32 pasn_peer_created_cnt; 1965 __le32 sec_ranging_not_supported_mfp_not_setup; 1966 __le32 non_sec_ranging_discarded_for_assoc_peer; 1967 __le32 open_ranging_discarded_set_for_pasn_peer; 1968 __le32 unassoc_non_pasn_ranging_not_supported; 1969 __le32 num_req_bw_20_mhz; 1970 __le32 num_req_bw_40_mhz; 1971 __le32 num_req_bw_80_mhz; 1972 __le32 num_req_bw_160_mhz; 1973 __le32 tx_11az_ftm_successful; 1974 __le32 tx_11az_ftm_failed; 1975 __le32 rx_11az_ftmr_cnt; 1976 __le32 rx_11az_ftmr_dup_cnt; 1977 __le32 rx_11az_iftmr_dup_cnt; 1978 __le32 malformed_ftmr; 1979 __le32 ftmr_drop_ntb_resp_role_not_enabled_cnt; 1980 __le32 ftmr_drop_tb_resp_role_not_enabled_cnt; 1981 __le32 invalid_ftm_request_params; 1982 __le32 requested_bw_format_not_supported; 1983 __le32 ntb_unsec_unassoc_ranging_peer_alloc_failed; 1984 __le32 tb_unassoc_unsec_pasn_peer_creation_failed; 1985 __le32 num_ranging_sequences_processed; 1986 __le32 ntb_tx_ndp; 1987 __le32 ndp_rx_cnt; 1988 __le32 num_ntb_ranging_ndpas_recv; 1989 __le32 recv_lmr; 1990 __le32 invalid_ftmr_cnt; 1991 __le32 max_time_bw_meas_exp_cnt; 1992 } __packed; 1993 1994 #define ATH12K_HTT_MAX_SCH_CMD_RESULT 25 1995 #define ATH12K_HTT_SCH_CMD_STATUS_CNT 9 1996 1997 struct ath12k_htt_stats_pdev_rtt_init_stats_tlv { 1998 __le32 pdev_id; 1999 __le32 tx_11mc_ftmr_cnt; 2000 __le32 tx_11mc_ftmr_fail; 2001 __le32 tx_11mc_ftmr_suc_retry; 2002 __le32 rx_11mc_ftm_cnt; 2003 __le32 tx_meas_req_count; 2004 __le32 init_role_not_enabled; 2005 __le32 initiator_terminate_cnt; 2006 __le32 tx_11az_ftmr_fail; 2007 __le32 tx_11az_ftmr_start; 2008 __le32 tx_11az_ftmr_stop; 2009 __le32 rx_11az_ftm_cnt; 2010 __le32 active_ista; 2011 __le32 invalid_preamble; 2012 __le32 invalid_chan_bw_format; 2013 __le32 mgmt_buff_alloc_fail_cnt; 2014 __le32 ftm_parse_failure; 2015 __le32 ranging_negotiation_successful_cnt; 2016 __le32 incompatible_ftm_params; 2017 __le32 sec_ranging_req_in_open_mode; 2018 __le32 ftmr_tx_failed_null_11az_peer; 2019 __le32 ftmr_retry_timeout; 2020 __le32 max_time_bw_meas_exp_cnt; 2021 __le32 tb_meas_duration_expiry_cnt; 2022 __le32 num_tb_ranging_requests; 2023 __le32 ntbr_triggered_successfully; 2024 __le32 ntbr_trigger_failed; 2025 __le32 invalid_or_no_vreg_idx; 2026 __le32 set_vreg_params_failed; 2027 __le32 sac_mismatch; 2028 __le32 pasn_m1_auth_recv_cnt; 2029 __le32 pasn_m1_auth_tx_fail_cnt; 2030 __le32 pasn_m2_auth_recv_cnt; 2031 __le32 pasn_m2_auth_drop_cnt; 2032 __le32 pasn_m3_auth_recv_cnt; 2033 __le32 pasn_m3_auth_tx_fail_cnt; 2034 __le32 pasn_peer_create_request_cnt; 2035 __le32 pasn_peer_create_timeout_cnt; 2036 __le32 pasn_peer_created_cnt; 2037 __le32 ntbr_ndpa_failed; 2038 __le32 ntbr_sequence_successful; 2039 __le32 ntbr_ndp_failed; 2040 __le32 sch_cmd_status_cnts[ATH12K_HTT_SCH_CMD_STATUS_CNT]; 2041 __le32 lmr_timeout; 2042 __le32 lmr_recv; 2043 __le32 num_trigger_frames_received; 2044 __le32 num_tb_ranging_ndpas_recv; 2045 __le32 ndp_rx_cnt; 2046 } __packed; 2047 2048 struct ath12k_htt_stats_pdev_rtt_hw_stats_tlv { 2049 __le32 ista_ranging_ndpa_cnt; 2050 __le32 ista_ranging_ndp_cnt; 2051 __le32 ista_ranging_i2r_lmr_cnt; 2052 __le32 rtsa_ranging_resp_cnt; 2053 __le32 rtsa_ranging_ndp_cnt; 2054 __le32 rsta_ranging_lmr_cnt; 2055 __le32 tb_ranging_cts2s_rcvd_cnt; 2056 __le32 tb_ranging_ndp_rcvd_cnt; 2057 __le32 tb_ranging_lmr_rcvd_cnt; 2058 __le32 tb_ranging_tf_poll_resp_sent_cnt; 2059 __le32 tb_ranging_tf_sound_resp_sent_cnt; 2060 __le32 tb_ranging_tf_report_resp_sent_cnt; 2061 } __packed; 2062 2063 enum ath12k_htt_stats_txsend_ftype { 2064 ATH12K_HTT_FTYPE_TF_POLL, 2065 ATH12K_HTT_FTYPE_TF_SOUND, 2066 ATH12K_HTT_FTYPE_TBR_NDPA, 2067 ATH12K_HTT_FTYPE_TBR_NDP, 2068 ATH12K_HTT_FTYPE_TBR_LMR, 2069 ATH12K_HTT_FTYPE_TF_RPRT, 2070 ATH12K_HTT_FTYPE_MAX 2071 }; 2072 2073 struct ath12k_htt_stats_pdev_rtt_tbr_tlv { 2074 __le32 su_ftype[ATH12K_HTT_FTYPE_MAX]; 2075 __le32 mu_ftype[ATH12K_HTT_FTYPE_MAX]; 2076 } __packed; 2077 2078 struct ath12k_htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv { 2079 __le32 tbr_num_sch_cmd_result_buckets; 2080 __le32 su_res[ATH12K_HTT_FTYPE_MAX][ATH12K_HTT_MAX_SCH_CMD_RESULT]; 2081 __le32 mu_res[ATH12K_HTT_FTYPE_MAX][ATH12K_HTT_MAX_SCH_CMD_RESULT]; 2082 } __packed; 2083 2084 struct htt_rx_pdev_fw_stats_tlv { 2085 __le32 mac_id__word; 2086 __le32 ppdu_recvd; 2087 __le32 mpdu_cnt_fcs_ok; 2088 __le32 mpdu_cnt_fcs_err; 2089 __le32 tcp_msdu_cnt; 2090 __le32 tcp_ack_msdu_cnt; 2091 __le32 udp_msdu_cnt; 2092 __le32 other_msdu_cnt; 2093 __le32 fw_ring_mpdu_ind; 2094 __le32 fw_ring_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 2095 __le32 fw_ring_ctrl_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 2096 __le32 fw_ring_mcast_data_msdu; 2097 __le32 fw_ring_bcast_data_msdu; 2098 __le32 fw_ring_ucast_data_msdu; 2099 __le32 fw_ring_null_data_msdu; 2100 __le32 fw_ring_mpdu_drop; 2101 __le32 ofld_local_data_ind_cnt; 2102 __le32 ofld_local_data_buf_recycle_cnt; 2103 __le32 drx_local_data_ind_cnt; 2104 __le32 drx_local_data_buf_recycle_cnt; 2105 __le32 local_nondata_ind_cnt; 2106 __le32 local_nondata_buf_recycle_cnt; 2107 __le32 fw_status_buf_ring_refill_cnt; 2108 __le32 fw_status_buf_ring_empty_cnt; 2109 __le32 fw_pkt_buf_ring_refill_cnt; 2110 __le32 fw_pkt_buf_ring_empty_cnt; 2111 __le32 fw_link_buf_ring_refill_cnt; 2112 __le32 fw_link_buf_ring_empty_cnt; 2113 __le32 host_pkt_buf_ring_refill_cnt; 2114 __le32 host_pkt_buf_ring_empty_cnt; 2115 __le32 mon_pkt_buf_ring_refill_cnt; 2116 __le32 mon_pkt_buf_ring_empty_cnt; 2117 __le32 mon_status_buf_ring_refill_cnt; 2118 __le32 mon_status_buf_ring_empty_cnt; 2119 __le32 mon_desc_buf_ring_refill_cnt; 2120 __le32 mon_desc_buf_ring_empty_cnt; 2121 __le32 mon_dest_ring_update_cnt; 2122 __le32 mon_dest_ring_full_cnt; 2123 __le32 rx_suspend_cnt; 2124 __le32 rx_suspend_fail_cnt; 2125 __le32 rx_resume_cnt; 2126 __le32 rx_resume_fail_cnt; 2127 __le32 rx_ring_switch_cnt; 2128 __le32 rx_ring_restore_cnt; 2129 __le32 rx_flush_cnt; 2130 __le32 rx_recovery_reset_cnt; 2131 __le32 rx_lwm_prom_filter_dis; 2132 __le32 rx_hwm_prom_filter_en; 2133 __le32 bytes_received_low_32; 2134 __le32 bytes_received_high_32; 2135 } __packed; 2136 2137 struct htt_tx_hwq_stats_cmn_tlv { 2138 __le32 mac_id__hwq_id__word; 2139 __le32 xretry; 2140 __le32 underrun_cnt; 2141 __le32 flush_cnt; 2142 __le32 filt_cnt; 2143 __le32 null_mpdu_bmap; 2144 __le32 user_ack_failure; 2145 __le32 ack_tlv_proc; 2146 __le32 sched_id_proc; 2147 __le32 null_mpdu_tx_count; 2148 __le32 mpdu_bmap_not_recvd; 2149 __le32 num_bar; 2150 __le32 rts; 2151 __le32 cts2self; 2152 __le32 qos_null; 2153 __le32 mpdu_tried_cnt; 2154 __le32 mpdu_queued_cnt; 2155 __le32 mpdu_ack_fail_cnt; 2156 __le32 mpdu_filt_cnt; 2157 __le32 false_mpdu_ack_count; 2158 __le32 txq_timeout; 2159 } __packed; 2160 2161 #define ATH12K_HTT_CHAN_SWITCH_STATS_BUF_LEN 10 2162 2163 #define ATH12K_HTT_STATS_CHAN_SWITCH_BW_MHZ GENMASK(15, 0) 2164 #define ATH12K_HTT_STATS_CHAN_SWITCH_BAND_FREQ GENMASK(31, 16) 2165 #define ATH12K_HTT_STATS_CHAN_SWITCH_PHY_MODE GENMASK(7, 0) 2166 #define ATH12K_HTT_STATS_CHAN_SWITCH_TX_CHAINMASK GENMASK(15, 8) 2167 #define ATH12K_HTT_STATS_CHAN_SWITCH_RX_CHAINMASK GENMASK(23, 16) 2168 #define ATH12K_HTT_STATS_CHAN_SWITCH_SW_PROFILE GENMASK(31, 24) 2169 2170 struct ath12k_htt_chan_switch_stats_tlv { 2171 struct { 2172 __le32 chan_switch_freq; 2173 __le32 chan_switch_profile; 2174 __le32 chan_switch_time; 2175 __le32 cal_module_time; 2176 __le32 ini_module_time; 2177 __le32 tpc_module_time; 2178 __le32 misc_module_time; 2179 __le32 ctl_module_time; 2180 __le32 reserved; 2181 } chan_stats[ATH12K_HTT_CHAN_SWITCH_STATS_BUF_LEN]; 2182 __le32 switch_count; /* shows how many channel changes have occurred */ 2183 } __packed; 2184 2185 #endif 2186