1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) 11 #define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 12 #define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 13 #define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 14 #define ATH12K_HTT_STATS_SUBTYPE_MAX 16 15 #define ATH12K_HTT_MAX_STRING_LEN 256 16 17 #define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f) 18 #define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f) 19 #define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \ 20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx)) 21 #define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \ 22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx)) 23 24 void ath12k_debugfs_htt_stats_register(struct ath12k *ar); 25 26 #ifdef CONFIG_ATH12K_DEBUGFS 27 void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 28 struct sk_buff *skb); 29 #else /* CONFIG_ATH12K_DEBUGFS */ 30 static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 31 struct sk_buff *skb) 32 { 33 } 34 #endif 35 36 /** 37 * DOC: target -> host extended statistics upload 38 * 39 * The following field definitions describe the format of the HTT 40 * target to host stats upload confirmation message. 41 * The message contains a cookie echoed from the HTT host->target stats 42 * upload request, which identifies which request the confirmation is 43 * for, and a single stats can span over multiple HTT stats indication 44 * due to the HTT message size limitation so every HTT ext stats 45 * indication will have tag-length-value stats information elements. 46 * The tag-length header for each HTT stats IND message also includes a 47 * status field, to indicate whether the request for the stat type in 48 * question was fully met, partially met, unable to be met, or invalid 49 * (if the stat type in question is disabled in the target). 50 * A Done bit 1's indicate the end of the of stats info elements. 51 * 52 * 53 * |31 16|15 12|11|10 8|7 5|4 0| 54 * |--------------------------------------------------------------| 55 * | reserved | msg type | 56 * |--------------------------------------------------------------| 57 * | cookie LSBs | 58 * |--------------------------------------------------------------| 59 * | cookie MSBs | 60 * |--------------------------------------------------------------| 61 * | stats entry length | rsvd | D| S | stat type | 62 * |--------------------------------------------------------------| 63 * | type-specific stats info | 64 * | (see debugfs_htt_stats.h) | 65 * |--------------------------------------------------------------| 66 * Header fields: 67 * - MSG_TYPE 68 * Bits 7:0 69 * Purpose: Identifies this is a extended statistics upload confirmation 70 * message. 71 * Value: 0x1c 72 * - COOKIE_LSBS 73 * Bits 31:0 74 * Purpose: Provide a mechanism to match a target->host stats confirmation 75 * message with its preceding host->target stats request message. 76 * Value: MSBs of the opaque cookie specified by the host-side requestor 77 * - COOKIE_MSBS 78 * Bits 31:0 79 * Purpose: Provide a mechanism to match a target->host stats confirmation 80 * message with its preceding host->target stats request message. 81 * Value: MSBs of the opaque cookie specified by the host-side requestor 82 * 83 * Stats Information Element tag-length header fields: 84 * - STAT_TYPE 85 * Bits 7:0 86 * Purpose: identifies the type of statistics info held in the 87 * following information element 88 * Value: ath12k_dbg_htt_ext_stats_type 89 * - STATUS 90 * Bits 10:8 91 * Purpose: indicate whether the requested stats are present 92 * Value: 93 * 0 -> The requested stats have been delivered in full 94 * 1 -> The requested stats have been delivered in part 95 * 2 -> The requested stats could not be delivered (error case) 96 * 3 -> The requested stat type is either not recognized (invalid) 97 * - DONE 98 * Bits 11 99 * Purpose: 100 * Indicates the completion of the stats entry, this will be the last 101 * stats conf HTT segment for the requested stats type. 102 * Value: 103 * 0 -> the stats retrieval is ongoing 104 * 1 -> the stats retrieval is complete 105 * - LENGTH 106 * Bits 31:16 107 * Purpose: indicate the stats information size 108 * Value: This field specifies the number of bytes of stats information 109 * that follows the element tag-length header. 110 * It is expected but not required that this length is a multiple of 111 * 4 bytes. 112 */ 113 114 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 115 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 116 117 struct ath12k_htt_extd_stats_msg { 118 __le32 info0; 119 __le64 cookie; 120 __le32 info1; 121 u8 data[]; 122 } __packed; 123 124 /* htt_dbg_ext_stats_type */ 125 enum ath12k_dbg_htt_ext_stats_type { 126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0, 127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, 128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, 129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, 130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, 131 132 /* keep this last */ 133 ATH12K_DBG_HTT_NUM_EXT_STATS, 134 }; 135 136 enum ath12k_dbg_htt_tlv_tag { 137 HTT_STATS_TX_PDEV_CMN_TAG = 0, 138 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 139 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 140 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 141 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 142 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 143 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 144 HTT_STATS_TX_TQM_CMN_TAG = 14, 145 HTT_STATS_TX_TQM_PDEV_TAG = 15, 146 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 147 HTT_STATS_TX_SCHED_CMN_TAG = 37, 148 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 149 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 150 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 151 HTT_STATS_HW_INTR_MISC_TAG = 54, 152 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 153 HTT_STATS_WHAL_TX_TAG = 66, 154 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 155 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 156 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 157 HTT_STATS_HW_WAR_TAG = 89, 158 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, 159 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, 160 HTT_STATS_MU_PPDU_DIST_TAG = 129, 161 162 HTT_STATS_MAX_TAG, 163 }; 164 165 #define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0) 166 167 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 168 #define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 169 170 /* MU MIMO distribution stats is a 2-dimensional array 171 * with dimension one denoting stats for nr4[0] or nr8[1] 172 */ 173 #define ATH12K_HTT_STATS_NUM_NR_BINS 2 174 #define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 175 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 176 #define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9 177 #define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \ 178 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS) 179 #define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \ 180 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 181 182 enum ath12k_htt_tx_pdev_underrun_enum { 183 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 184 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 185 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 186 HTT_TX_PDEV_MAX_URRN_STATS = 3, 187 }; 188 189 enum ath12k_htt_stats_reset_cfg_param_alloc_pos { 190 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1, 191 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES, 192 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES, 193 }; 194 195 struct debug_htt_stats_req { 196 bool done; 197 bool override_cfg_param; 198 u8 pdev_id; 199 enum ath12k_dbg_htt_ext_stats_type type; 200 u32 cfg_param[4]; 201 u8 peer_addr[ETH_ALEN]; 202 struct completion htt_stats_rcvd; 203 u32 buf_len; 204 u8 buf[]; 205 }; 206 207 struct ath12k_htt_tx_pdev_stats_cmn_tlv { 208 __le32 mac_id__word; 209 __le32 hw_queued; 210 __le32 hw_reaped; 211 __le32 underrun; 212 __le32 hw_paused; 213 __le32 hw_flush; 214 __le32 hw_filt; 215 __le32 tx_abort; 216 __le32 mpdu_requed; 217 __le32 tx_xretry; 218 __le32 data_rc; 219 __le32 mpdu_dropped_xretry; 220 __le32 illgl_rate_phy_err; 221 __le32 cont_xretry; 222 __le32 tx_timeout; 223 __le32 pdev_resets; 224 __le32 phy_underrun; 225 __le32 txop_ovf; 226 __le32 seq_posted; 227 __le32 seq_failed_queueing; 228 __le32 seq_completed; 229 __le32 seq_restarted; 230 __le32 mu_seq_posted; 231 __le32 seq_switch_hw_paused; 232 __le32 next_seq_posted_dsr; 233 __le32 seq_posted_isr; 234 __le32 seq_ctrl_cached; 235 __le32 mpdu_count_tqm; 236 __le32 msdu_count_tqm; 237 __le32 mpdu_removed_tqm; 238 __le32 msdu_removed_tqm; 239 __le32 mpdus_sw_flush; 240 __le32 mpdus_hw_filter; 241 __le32 mpdus_truncated; 242 __le32 mpdus_ack_failed; 243 __le32 mpdus_expired; 244 __le32 mpdus_seq_hw_retry; 245 __le32 ack_tlv_proc; 246 __le32 coex_abort_mpdu_cnt_valid; 247 __le32 coex_abort_mpdu_cnt; 248 __le32 num_total_ppdus_tried_ota; 249 __le32 num_data_ppdus_tried_ota; 250 __le32 local_ctrl_mgmt_enqued; 251 __le32 local_ctrl_mgmt_freed; 252 __le32 local_data_enqued; 253 __le32 local_data_freed; 254 __le32 mpdu_tried; 255 __le32 isr_wait_seq_posted; 256 257 __le32 tx_active_dur_us_low; 258 __le32 tx_active_dur_us_high; 259 __le32 remove_mpdus_max_retries; 260 __le32 comp_delivered; 261 __le32 ppdu_ok; 262 __le32 self_triggers; 263 __le32 tx_time_dur_data; 264 __le32 seq_qdepth_repost_stop; 265 __le32 mu_seq_min_msdu_repost_stop; 266 __le32 seq_min_msdu_repost_stop; 267 __le32 seq_txop_repost_stop; 268 __le32 next_seq_cancel; 269 __le32 fes_offsets_err_cnt; 270 __le32 num_mu_peer_blacklisted; 271 __le32 mu_ofdma_seq_posted; 272 __le32 ul_mumimo_seq_posted; 273 __le32 ul_ofdma_seq_posted; 274 275 __le32 thermal_suspend_cnt; 276 __le32 dfs_suspend_cnt; 277 __le32 tx_abort_suspend_cnt; 278 __le32 tgt_specific_opaque_txq_suspend_info; 279 __le32 last_suspend_reason; 280 } __packed; 281 282 struct ath12k_htt_tx_pdev_stats_urrn_tlv { 283 DECLARE_FLEX_ARRAY(__le32, urrn_stats); 284 } __packed; 285 286 struct ath12k_htt_tx_pdev_stats_flush_tlv { 287 DECLARE_FLEX_ARRAY(__le32, flush_errs); 288 } __packed; 289 290 struct ath12k_htt_tx_pdev_stats_phy_err_tlv { 291 DECLARE_FLEX_ARRAY(__le32, phy_errs); 292 } __packed; 293 294 struct ath12k_htt_tx_pdev_stats_sifs_tlv { 295 DECLARE_FLEX_ARRAY(__le32, sifs_status); 296 } __packed; 297 298 struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv { 299 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 300 } __packed; 301 302 struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv { 303 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status); 304 } __packed; 305 306 enum ath12k_htt_stats_hw_mode { 307 ATH12K_HTT_STATS_HWMODE_AC = 0, 308 ATH12K_HTT_STATS_HWMODE_AX = 1, 309 ATH12K_HTT_STATS_HWMODE_BE = 2, 310 }; 311 312 struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv { 313 __le32 hw_mode; 314 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS]; 315 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 316 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS]; 317 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 318 } __packed; 319 320 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 321 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 322 323 #define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 324 325 struct ath12k_htt_stats_tx_sched_cmn_tlv { 326 __le32 mac_id__word; 327 __le32 current_timestamp; 328 } __packed; 329 330 struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv { 331 __le32 mac_id__word; 332 __le32 sched_policy; 333 __le32 last_sched_cmd_posted_timestamp; 334 __le32 last_sched_cmd_compl_timestamp; 335 __le32 sched_2_tac_lwm_count; 336 __le32 sched_2_tac_ring_full; 337 __le32 sched_cmd_post_failure; 338 __le32 num_active_tids; 339 __le32 num_ps_schedules; 340 __le32 sched_cmds_pending; 341 __le32 num_tid_register; 342 __le32 num_tid_unregister; 343 __le32 num_qstats_queried; 344 __le32 qstats_update_pending; 345 __le32 last_qstats_query_timestamp; 346 __le32 num_tqm_cmdq_full; 347 __le32 num_de_sched_algo_trigger; 348 __le32 num_rt_sched_algo_trigger; 349 __le32 num_tqm_sched_algo_trigger; 350 __le32 notify_sched; 351 __le32 dur_based_sendn_term; 352 __le32 su_notify2_sched; 353 __le32 su_optimal_queued_msdus_sched; 354 __le32 su_delay_timeout_sched; 355 __le32 su_min_txtime_sched_delay; 356 __le32 su_no_delay; 357 __le32 num_supercycles; 358 __le32 num_subcycles_with_sort; 359 __le32 num_subcycles_no_sort; 360 } __packed; 361 362 struct ath12k_htt_sched_txq_cmd_posted_tlv { 363 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted); 364 } __packed; 365 366 struct ath12k_htt_sched_txq_cmd_reaped_tlv { 367 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped); 368 } __packed; 369 370 struct ath12k_htt_sched_txq_sched_order_su_tlv { 371 DECLARE_FLEX_ARRAY(__le32, sched_order_su); 372 } __packed; 373 374 struct ath12k_htt_sched_txq_sched_ineligibility_tlv { 375 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility); 376 } __packed; 377 378 enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum { 379 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, 380 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, 381 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, 382 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, 383 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, 384 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, 385 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, 386 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 387 }; 388 389 struct ath12k_htt_sched_txq_supercycle_triggers_tlv { 390 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers); 391 } __packed; 392 393 struct ath12k_htt_hw_stats_pdev_errs_tlv { 394 __le32 mac_id__word; 395 __le32 tx_abort; 396 __le32 tx_abort_fail_count; 397 __le32 rx_abort; 398 __le32 rx_abort_fail_count; 399 __le32 warm_reset; 400 __le32 cold_reset; 401 __le32 tx_flush; 402 __le32 tx_glb_reset; 403 __le32 tx_txq_reset; 404 __le32 rx_timeout_reset; 405 __le32 mac_cold_reset_restore_cal; 406 __le32 mac_cold_reset; 407 __le32 mac_warm_reset; 408 __le32 mac_only_reset; 409 __le32 phy_warm_reset; 410 __le32 phy_warm_reset_ucode_trig; 411 __le32 mac_warm_reset_restore_cal; 412 __le32 mac_sfm_reset; 413 __le32 phy_warm_reset_m3_ssr; 414 __le32 phy_warm_reset_reason_phy_m3; 415 __le32 phy_warm_reset_reason_tx_hw_stuck; 416 __le32 phy_warm_reset_reason_num_rx_frame_stuck; 417 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy; 418 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng; 419 __le32 phy_warm_reset_reason_mac_conv_phy_reset; 420 __le32 wal_rx_recovery_rst_mac_hang_cnt; 421 __le32 wal_rx_recovery_rst_known_sig_cnt; 422 __le32 wal_rx_recovery_rst_no_rx_cnt; 423 __le32 wal_rx_recovery_rst_no_rx_consec_cnt; 424 __le32 wal_rx_recovery_rst_rx_busy_cnt; 425 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt; 426 __le32 rx_flush_cnt; 427 __le32 phy_warm_reset_reason_tx_exp_cca_stuck; 428 __le32 phy_warm_reset_reason_tx_consec_flsh_war; 429 __le32 phy_warm_reset_reason_tx_hwsch_reset_war; 430 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war; 431 __le32 fw_rx_rings_reset; 432 __le32 rx_dest_drain_rx_descs_leak_prevented; 433 __le32 rx_dest_drain_rx_descs_saved_cnt; 434 __le32 rx_dest_drain_rxdma2reo_leak_detected; 435 __le32 rx_dest_drain_rxdma2fw_leak_detected; 436 __le32 rx_dest_drain_rxdma2wbm_leak_detected; 437 __le32 rx_dest_drain_rxdma1_2sw_leak_detected; 438 __le32 rx_dest_drain_rx_drain_ok_mac_idle; 439 __le32 rx_dest_drain_ok_mac_not_idle; 440 __le32 rx_dest_drain_prerequisite_invld; 441 __le32 rx_dest_drain_skip_non_lmac_reset; 442 __le32 rx_dest_drain_hw_fifo_notempty_post_wait; 443 } __packed; 444 445 #define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8 446 struct ath12k_htt_hw_stats_intr_misc_tlv { 447 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN]; 448 __le32 mask; 449 __le32 count; 450 } __packed; 451 452 struct ath12k_htt_hw_stats_whal_tx_tlv { 453 __le32 mac_id__word; 454 __le32 last_unpause_ppdu_id; 455 __le32 hwsch_unpause_wait_tqm_write; 456 __le32 hwsch_dummy_tlv_skipped; 457 __le32 hwsch_misaligned_offset_received; 458 __le32 hwsch_reset_count; 459 __le32 hwsch_dev_reset_war; 460 __le32 hwsch_delayed_pause; 461 __le32 hwsch_long_delayed_pause; 462 __le32 sch_rx_ppdu_no_response; 463 __le32 sch_selfgen_response; 464 __le32 sch_rx_sifs_resp_trigger; 465 } __packed; 466 467 struct ath12k_htt_hw_war_stats_tlv { 468 __le32 mac_id__word; 469 DECLARE_FLEX_ARRAY(__le32, hw_wars); 470 } __packed; 471 472 struct ath12k_htt_tx_tqm_cmn_stats_tlv { 473 __le32 mac_id__word; 474 __le32 max_cmdq_id; 475 __le32 list_mpdu_cnt_hist_intvl; 476 __le32 add_msdu; 477 __le32 q_empty; 478 __le32 q_not_empty; 479 __le32 drop_notification; 480 __le32 desc_threshold; 481 __le32 hwsch_tqm_invalid_status; 482 __le32 missed_tqm_gen_mpdus; 483 __le32 tqm_active_tids; 484 __le32 tqm_inactive_tids; 485 __le32 tqm_active_msduq_flows; 486 __le32 msduq_timestamp_updates; 487 __le32 msduq_updates_mpdu_head_info_cmd; 488 __le32 msduq_updates_emp_to_nonemp_status; 489 __le32 get_mpdu_head_info_cmds_by_query; 490 __le32 get_mpdu_head_info_cmds_by_tac; 491 __le32 gen_mpdu_cmds_by_query; 492 __le32 high_prio_q_not_empty; 493 } __packed; 494 495 struct ath12k_htt_tx_tqm_error_stats_tlv { 496 __le32 q_empty_failure; 497 __le32 q_not_empty_failure; 498 __le32 add_msdu_failure; 499 __le32 tqm_cache_ctl_err; 500 __le32 tqm_soft_reset; 501 __le32 tqm_reset_num_in_use_link_descs; 502 __le32 tqm_reset_num_lost_link_descs; 503 __le32 tqm_reset_num_lost_host_tx_buf_cnt; 504 __le32 tqm_reset_num_in_use_internal_tqm; 505 __le32 tqm_reset_num_in_use_idle_link_rng; 506 __le32 tqm_reset_time_to_tqm_hang_delta_ms; 507 __le32 tqm_reset_recovery_time_ms; 508 __le32 tqm_reset_num_peers_hdl; 509 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt; 510 __le32 tqm_reset_cumm_dirty_hw_msduq_proc; 511 __le32 tqm_reset_flush_cache_cmd_su_cnt; 512 __le32 tqm_reset_flush_cache_cmd_other_cnt; 513 __le32 tqm_reset_flush_cache_cmd_trig_type; 514 __le32 tqm_reset_flush_cache_cmd_trig_cfg; 515 __le32 tqm_reset_flush_cmd_skp_status_null; 516 } __packed; 517 518 struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv { 519 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason); 520 } __packed; 521 522 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 523 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 524 525 struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv { 526 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason); 527 } __packed; 528 529 struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv { 530 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist); 531 } __packed; 532 533 struct ath12k_htt_tx_tqm_pdev_stats_tlv { 534 __le32 msdu_count; 535 __le32 mpdu_count; 536 __le32 remove_msdu; 537 __le32 remove_mpdu; 538 __le32 remove_msdu_ttl; 539 __le32 send_bar; 540 __le32 bar_sync; 541 __le32 notify_mpdu; 542 __le32 sync_cmd; 543 __le32 write_cmd; 544 __le32 hwsch_trigger; 545 __le32 ack_tlv_proc; 546 __le32 gen_mpdu_cmd; 547 __le32 gen_list_cmd; 548 __le32 remove_mpdu_cmd; 549 __le32 remove_mpdu_tried_cmd; 550 __le32 mpdu_queue_stats_cmd; 551 __le32 mpdu_head_info_cmd; 552 __le32 msdu_flow_stats_cmd; 553 __le32 remove_msdu_cmd; 554 __le32 remove_msdu_ttl_cmd; 555 __le32 flush_cache_cmd; 556 __le32 update_mpduq_cmd; 557 __le32 enqueue; 558 __le32 enqueue_notify; 559 __le32 notify_mpdu_at_head; 560 __le32 notify_mpdu_state_valid; 561 __le32 sched_udp_notify1; 562 __le32 sched_udp_notify2; 563 __le32 sched_nonudp_notify1; 564 __le32 sched_nonudp_notify2; 565 } __packed; 566 567 #endif 568