1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include "qmi.h" 17 #include "htc.h" 18 #include "wmi.h" 19 #include "hal.h" 20 #include "dp.h" 21 #include "ce.h" 22 #include "mac.h" 23 #include "hw.h" 24 #include "hal_rx.h" 25 #include "reg.h" 26 #include "dbring.h" 27 28 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 29 30 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 31 32 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 33 34 /* Pending management packets threshold for dropping probe responses */ 35 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 36 37 /* SMBIOS type containing Board Data File Name Extension */ 38 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 39 40 /* SMBIOS type structure length (excluding strings-set) */ 41 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 42 43 /* The magic used by QCA spec */ 44 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 45 46 #define ATH12K_INVALID_HW_MAC_ID 0xFF 47 #define ATH12K_RX_RATE_TABLE_NUM 320 48 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 49 50 #define ATH12K_MON_TIMER_INTERVAL 10 51 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 52 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 53 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 54 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 55 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 56 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 57 58 enum ath12k_bdf_search { 59 ATH12K_BDF_SEARCH_DEFAULT, 60 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 61 }; 62 63 enum wme_ac { 64 WME_AC_BE, 65 WME_AC_BK, 66 WME_AC_VI, 67 WME_AC_VO, 68 WME_NUM_AC 69 }; 70 71 #define ATH12K_HT_MCS_MAX 7 72 #define ATH12K_VHT_MCS_MAX 9 73 #define ATH12K_HE_MCS_MAX 11 74 75 enum ath12k_crypt_mode { 76 /* Only use hardware crypto engine */ 77 ATH12K_CRYPT_MODE_HW, 78 /* Only use software crypto */ 79 ATH12K_CRYPT_MODE_SW, 80 }; 81 82 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 83 { 84 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 85 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 86 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 87 WME_AC_VO); 88 } 89 90 enum ath12k_skb_flags { 91 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 92 ATH12K_SKB_CIPHER_SET = BIT(1), 93 }; 94 95 struct ath12k_skb_cb { 96 dma_addr_t paddr; 97 struct ath12k *ar; 98 struct ieee80211_vif *vif; 99 dma_addr_t paddr_ext_desc; 100 u32 cipher; 101 u8 flags; 102 }; 103 104 struct ath12k_skb_rxcb { 105 dma_addr_t paddr; 106 bool is_first_msdu; 107 bool is_last_msdu; 108 bool is_continuation; 109 bool is_mcbc; 110 bool is_eapol; 111 struct hal_rx_desc *rx_desc; 112 u8 err_rel_src; 113 u8 err_code; 114 u8 mac_id; 115 u8 unmapped; 116 u8 is_frag; 117 u8 tid; 118 u16 peer_id; 119 }; 120 121 enum ath12k_hw_rev { 122 ATH12K_HW_QCN9274_HW10, 123 ATH12K_HW_QCN9274_HW20, 124 ATH12K_HW_WCN7850_HW20 125 }; 126 127 enum ath12k_firmware_mode { 128 /* the default mode, standard 802.11 functionality */ 129 ATH12K_FIRMWARE_MODE_NORMAL, 130 131 /* factory tests etc */ 132 ATH12K_FIRMWARE_MODE_FTM, 133 }; 134 135 #define ATH12K_IRQ_NUM_MAX 57 136 #define ATH12K_EXT_IRQ_NUM_MAX 16 137 138 struct ath12k_ext_irq_grp { 139 struct ath12k_base *ab; 140 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 141 u32 num_irq; 142 u32 grp_id; 143 u64 timestamp; 144 struct napi_struct napi; 145 struct net_device napi_ndev; 146 }; 147 148 struct ath12k_smbios_bdf { 149 struct dmi_header hdr; 150 u32 padding; 151 u8 bdf_enabled; 152 u8 bdf_ext[]; 153 } __packed; 154 155 #define HEHANDLE_CAP_PHYINFO_SIZE 3 156 #define HECAP_PHYINFO_SIZE 9 157 #define HECAP_MACINFO_SIZE 5 158 #define HECAP_TXRX_MCS_NSS_SIZE 2 159 #define HECAP_PPET16_PPET8_MAX_SIZE 25 160 161 #define HE_PPET16_PPET8_SIZE 8 162 163 /* 802.11ax PPE (PPDU packet Extension) threshold */ 164 struct he_ppe_threshold { 165 u32 numss_m1; 166 u32 ru_mask; 167 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 168 }; 169 170 struct ath12k_he { 171 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 172 u32 hecap_rxmcsnssmap; 173 u32 hecap_txmcsnssmap; 174 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 175 struct he_ppe_threshold hecap_ppet; 176 u32 heop_param; 177 }; 178 179 #define MAX_RADIOS 3 180 181 enum { 182 WMI_HOST_TP_SCALE_MAX = 0, 183 WMI_HOST_TP_SCALE_50 = 1, 184 WMI_HOST_TP_SCALE_25 = 2, 185 WMI_HOST_TP_SCALE_12 = 3, 186 WMI_HOST_TP_SCALE_MIN = 4, 187 WMI_HOST_TP_SCALE_SIZE = 5, 188 }; 189 190 enum ath12k_scan_state { 191 ATH12K_SCAN_IDLE, 192 ATH12K_SCAN_STARTING, 193 ATH12K_SCAN_RUNNING, 194 ATH12K_SCAN_ABORTING, 195 }; 196 197 enum ath12k_dev_flags { 198 ATH12K_CAC_RUNNING, 199 ATH12K_FLAG_CRASH_FLUSH, 200 ATH12K_FLAG_RAW_MODE, 201 ATH12K_FLAG_HW_CRYPTO_DISABLED, 202 ATH12K_FLAG_RECOVERY, 203 ATH12K_FLAG_UNREGISTERING, 204 ATH12K_FLAG_REGISTERED, 205 ATH12K_FLAG_QMI_FAIL, 206 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 207 ATH12K_FLAG_CE_IRQ_ENABLED, 208 ATH12K_FLAG_EXT_IRQ_ENABLED, 209 }; 210 211 enum ath12k_monitor_flags { 212 ATH12K_FLAG_MONITOR_ENABLED, 213 }; 214 215 struct ath12k_vif { 216 u32 vdev_id; 217 enum wmi_vdev_type vdev_type; 218 enum wmi_vdev_subtype vdev_subtype; 219 u32 beacon_interval; 220 u32 dtim_period; 221 u16 ast_hash; 222 u16 ast_idx; 223 u16 tcl_metadata; 224 u8 hal_addr_search_flags; 225 u8 search_type; 226 227 struct ath12k *ar; 228 struct ieee80211_vif *vif; 229 230 int bank_id; 231 u8 vdev_id_check_en; 232 233 struct wmi_wmm_params_all_arg wmm_params; 234 struct list_head list; 235 union { 236 struct { 237 u32 uapsd; 238 } sta; 239 struct { 240 /* 127 stations; wmi limit */ 241 u8 tim_bitmap[16]; 242 u8 tim_len; 243 u32 ssid_len; 244 u8 ssid[IEEE80211_MAX_SSID_LEN]; 245 bool hidden_ssid; 246 /* P2P_IE with NoA attribute for P2P_GO case */ 247 u32 noa_len; 248 u8 *noa_data; 249 } ap; 250 } u; 251 252 bool is_started; 253 bool is_up; 254 u32 aid; 255 u8 bssid[ETH_ALEN]; 256 struct cfg80211_bitrate_mask bitrate_mask; 257 int num_legacy_stations; 258 int rtscts_prot_mode; 259 int txpower; 260 bool rsnie_present; 261 bool wpaie_present; 262 struct ieee80211_chanctx_conf chanctx; 263 u32 key_cipher; 264 u8 tx_encap_type; 265 u8 vdev_stats_id; 266 u32 punct_bitmap; 267 }; 268 269 struct ath12k_vif_iter { 270 u32 vdev_id; 271 struct ath12k_vif *arvif; 272 }; 273 274 #define HAL_AST_IDX_INVALID 0xFFFF 275 #define HAL_RX_MAX_MCS 12 276 #define HAL_RX_MAX_MCS_HT 31 277 #define HAL_RX_MAX_MCS_VHT 9 278 #define HAL_RX_MAX_MCS_HE 11 279 #define HAL_RX_MAX_NSS 8 280 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 281 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 282 #define ATH12K_RX_RATE_TABLE_NUM 320 283 284 struct ath12k_rx_peer_rate_stats { 285 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 286 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 287 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 288 u64 nss_count[HAL_RX_MAX_NSS]; 289 u64 bw_count[HAL_RX_BW_MAX]; 290 u64 gi_count[HAL_RX_GI_MAX]; 291 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 292 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 293 }; 294 295 struct ath12k_rx_peer_stats { 296 u64 num_msdu; 297 u64 num_mpdu_fcs_ok; 298 u64 num_mpdu_fcs_err; 299 u64 tcp_msdu_count; 300 u64 udp_msdu_count; 301 u64 other_msdu_count; 302 u64 ampdu_msdu_count; 303 u64 non_ampdu_msdu_count; 304 u64 stbc_count; 305 u64 beamformed_count; 306 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 307 u64 nss_count[HAL_RX_MAX_NSS]; 308 u64 bw_count[HAL_RX_BW_MAX]; 309 u64 gi_count[HAL_RX_GI_MAX]; 310 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 311 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 312 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 313 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 314 u64 rx_duration; 315 u64 dcm_count; 316 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 317 struct ath12k_rx_peer_rate_stats pkt_stats; 318 struct ath12k_rx_peer_rate_stats byte_stats; 319 }; 320 321 #define ATH12K_HE_MCS_NUM 12 322 #define ATH12K_VHT_MCS_NUM 10 323 #define ATH12K_BW_NUM 5 324 #define ATH12K_NSS_NUM 4 325 #define ATH12K_LEGACY_NUM 12 326 #define ATH12K_GI_NUM 4 327 #define ATH12K_HT_MCS_NUM 32 328 329 enum ath12k_pkt_rx_err { 330 ATH12K_PKT_RX_ERR_FCS, 331 ATH12K_PKT_RX_ERR_TKIP, 332 ATH12K_PKT_RX_ERR_CRYPT, 333 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 334 ATH12K_PKT_RX_ERR_MAX, 335 }; 336 337 enum ath12k_ampdu_subfrm_num { 338 ATH12K_AMPDU_SUBFRM_NUM_10, 339 ATH12K_AMPDU_SUBFRM_NUM_20, 340 ATH12K_AMPDU_SUBFRM_NUM_30, 341 ATH12K_AMPDU_SUBFRM_NUM_40, 342 ATH12K_AMPDU_SUBFRM_NUM_50, 343 ATH12K_AMPDU_SUBFRM_NUM_60, 344 ATH12K_AMPDU_SUBFRM_NUM_MORE, 345 ATH12K_AMPDU_SUBFRM_NUM_MAX, 346 }; 347 348 enum ath12k_amsdu_subfrm_num { 349 ATH12K_AMSDU_SUBFRM_NUM_1, 350 ATH12K_AMSDU_SUBFRM_NUM_2, 351 ATH12K_AMSDU_SUBFRM_NUM_3, 352 ATH12K_AMSDU_SUBFRM_NUM_4, 353 ATH12K_AMSDU_SUBFRM_NUM_MORE, 354 ATH12K_AMSDU_SUBFRM_NUM_MAX, 355 }; 356 357 enum ath12k_counter_type { 358 ATH12K_COUNTER_TYPE_BYTES, 359 ATH12K_COUNTER_TYPE_PKTS, 360 ATH12K_COUNTER_TYPE_MAX, 361 }; 362 363 enum ath12k_stats_type { 364 ATH12K_STATS_TYPE_SUCC, 365 ATH12K_STATS_TYPE_FAIL, 366 ATH12K_STATS_TYPE_RETRY, 367 ATH12K_STATS_TYPE_AMPDU, 368 ATH12K_STATS_TYPE_MAX, 369 }; 370 371 struct ath12k_htt_data_stats { 372 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 373 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 374 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 375 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 376 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 377 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 378 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 379 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 380 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 381 }; 382 383 struct ath12k_htt_tx_stats { 384 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 385 u64 tx_duration; 386 u64 ba_fails; 387 u64 ack_fails; 388 u16 ru_start; 389 u16 ru_tones; 390 u32 mu_group[MAX_MU_GROUP_ID]; 391 }; 392 393 struct ath12k_per_ppdu_tx_stats { 394 u16 succ_pkts; 395 u16 failed_pkts; 396 u16 retry_pkts; 397 u32 succ_bytes; 398 u32 failed_bytes; 399 u32 retry_bytes; 400 }; 401 402 struct ath12k_wbm_tx_stats { 403 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 404 }; 405 406 struct ath12k_sta { 407 struct ath12k_vif *arvif; 408 409 /* the following are protected by ar->data_lock */ 410 u32 changed; /* IEEE80211_RC_* */ 411 u32 bw; 412 u32 nss; 413 u32 smps; 414 enum hal_pn_type pn_type; 415 416 struct work_struct update_wk; 417 struct rate_info txrate; 418 struct rate_info last_txrate; 419 u64 rx_duration; 420 u64 tx_duration; 421 u8 rssi_comb; 422 struct ath12k_rx_peer_stats *rx_stats; 423 struct ath12k_wbm_tx_stats *wbm_tx_stats; 424 u32 bw_prev; 425 }; 426 427 #define ATH12K_MIN_5G_FREQ 4150 428 #define ATH12K_MIN_6G_FREQ 5925 429 #define ATH12K_MAX_6G_FREQ 7115 430 #define ATH12K_NUM_CHANS 100 431 #define ATH12K_MAX_5G_CHAN 173 432 433 enum ath12k_state { 434 ATH12K_STATE_OFF, 435 ATH12K_STATE_ON, 436 ATH12K_STATE_RESTARTING, 437 ATH12K_STATE_RESTARTED, 438 ATH12K_STATE_WEDGED, 439 /* Add other states as required */ 440 }; 441 442 /* Antenna noise floor */ 443 #define ATH12K_DEFAULT_NOISE_FLOOR -95 444 445 struct ath12k_fw_stats { 446 u32 pdev_id; 447 u32 stats_id; 448 struct list_head pdevs; 449 struct list_head vdevs; 450 struct list_head bcn; 451 }; 452 453 struct ath12k_per_peer_tx_stats { 454 u32 succ_bytes; 455 u32 retry_bytes; 456 u32 failed_bytes; 457 u32 duration; 458 u16 succ_pkts; 459 u16 retry_pkts; 460 u16 failed_pkts; 461 u16 ru_start; 462 u16 ru_tones; 463 u8 ba_fails; 464 u8 ppdu_type; 465 u32 mu_grpid; 466 u32 mu_pos; 467 bool is_ampdu; 468 }; 469 470 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 471 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 472 473 struct ath12k { 474 struct ath12k_base *ab; 475 struct ath12k_pdev *pdev; 476 struct ath12k_hw *ah; 477 struct ath12k_wmi_pdev *wmi; 478 struct ath12k_pdev_dp dp; 479 u8 mac_addr[ETH_ALEN]; 480 u32 ht_cap_info; 481 u32 vht_cap_info; 482 struct ath12k_he ar_he; 483 enum ath12k_state state; 484 bool supports_6ghz; 485 struct { 486 struct completion started; 487 struct completion completed; 488 struct completion on_channel; 489 struct delayed_work timeout; 490 enum ath12k_scan_state state; 491 bool is_roc; 492 int vdev_id; 493 int roc_freq; 494 bool roc_notify; 495 } scan; 496 497 struct { 498 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 499 struct ieee80211_sband_iftype_data 500 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 501 } mac; 502 503 unsigned long dev_flags; 504 unsigned int filter_flags; 505 unsigned long monitor_flags; 506 u32 min_tx_power; 507 u32 max_tx_power; 508 u32 txpower_limit_2g; 509 u32 txpower_limit_5g; 510 u32 txpower_scale; 511 u32 power_scale; 512 u32 chan_tx_pwr; 513 u32 num_stations; 514 u32 max_num_stations; 515 bool monitor_present; 516 /* To synchronize concurrent synchronous mac80211 callback operations, 517 * concurrent debugfs configuration and concurrent FW statistics events. 518 */ 519 struct mutex conf_mutex; 520 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 521 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 522 * channel context data, survey info, test mode data. 523 */ 524 spinlock_t data_lock; 525 526 struct list_head arvifs; 527 /* should never be NULL; needed for regular htt rx */ 528 struct ieee80211_channel *rx_channel; 529 530 /* valid during scan; needed for mgmt rx during scan */ 531 struct ieee80211_channel *scan_channel; 532 533 u8 cfg_tx_chainmask; 534 u8 cfg_rx_chainmask; 535 u8 num_rx_chains; 536 u8 num_tx_chains; 537 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 538 u8 pdev_idx; 539 u8 lmac_id; 540 u8 hw_link_id; 541 542 struct completion peer_assoc_done; 543 struct completion peer_delete_done; 544 545 int install_key_status; 546 struct completion install_key_done; 547 548 int last_wmi_vdev_start_status; 549 struct completion vdev_setup_done; 550 struct completion vdev_delete_done; 551 552 int num_peers; 553 int max_num_peers; 554 u32 num_started_vdevs; 555 u32 num_created_vdevs; 556 unsigned long long allocated_vdev_map; 557 558 struct idr txmgmt_idr; 559 /* protects txmgmt_idr data */ 560 spinlock_t txmgmt_idr_lock; 561 atomic_t num_pending_mgmt_tx; 562 wait_queue_head_t txmgmt_empty_waitq; 563 564 /* cycle count is reported twice for each visited channel during scan. 565 * access protected by data_lock 566 */ 567 u32 survey_last_rx_clear_count; 568 u32 survey_last_cycle_count; 569 570 /* Channel info events are expected to come in pairs without and with 571 * COMPLETE flag set respectively for each channel visit during scan. 572 * 573 * However there are deviations from this rule. This flag is used to 574 * avoid reporting garbage data. 575 */ 576 bool ch_info_can_report_survey; 577 struct survey_info survey[ATH12K_NUM_CHANS]; 578 struct completion bss_survey_done; 579 580 struct work_struct regd_update_work; 581 582 struct work_struct wmi_mgmt_tx_work; 583 struct sk_buff_head wmi_mgmt_tx_queue; 584 585 struct ath12k_per_peer_tx_stats peer_tx_stats; 586 struct list_head ppdu_stats_info; 587 u32 ppdu_stat_list_depth; 588 589 struct ath12k_per_peer_tx_stats cached_stats; 590 u32 last_ppdu_id; 591 u32 cached_ppdu_id; 592 593 bool dfs_block_radar_events; 594 bool monitor_conf_enabled; 595 bool monitor_vdev_created; 596 bool monitor_started; 597 int monitor_vdev_id; 598 }; 599 600 struct ath12k_hw { 601 struct ieee80211_hw *hw; 602 603 u8 num_radio; 604 struct ath12k radio[] __aligned(sizeof(void *)); 605 }; 606 607 struct ath12k_band_cap { 608 u32 phy_id; 609 u32 max_bw_supported; 610 u32 ht_cap_info; 611 u32 he_cap_info[2]; 612 u32 he_mcs; 613 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 614 struct ath12k_wmi_ppe_threshold_arg he_ppet; 615 u16 he_6ghz_capa; 616 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 617 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 618 u32 eht_mcs_20_only; 619 u32 eht_mcs_80; 620 u32 eht_mcs_160; 621 u32 eht_mcs_320; 622 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 623 u32 eht_cap_info_internal; 624 }; 625 626 struct ath12k_pdev_cap { 627 u32 supported_bands; 628 u32 ampdu_density; 629 u32 vht_cap; 630 u32 vht_mcs; 631 u32 he_mcs; 632 u32 tx_chain_mask; 633 u32 rx_chain_mask; 634 u32 tx_chain_mask_shift; 635 u32 rx_chain_mask_shift; 636 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 637 }; 638 639 struct mlo_timestamp { 640 u32 info; 641 u32 sync_timestamp_lo_us; 642 u32 sync_timestamp_hi_us; 643 u32 mlo_offset_lo; 644 u32 mlo_offset_hi; 645 u32 mlo_offset_clks; 646 u32 mlo_comp_clks; 647 u32 mlo_comp_timer; 648 }; 649 650 struct ath12k_pdev { 651 struct ath12k *ar; 652 u32 pdev_id; 653 struct ath12k_pdev_cap cap; 654 u8 mac_addr[ETH_ALEN]; 655 struct mlo_timestamp timestamp; 656 }; 657 658 struct ath12k_fw_pdev { 659 u32 pdev_id; 660 u32 phy_id; 661 u32 supported_bands; 662 }; 663 664 struct ath12k_board_data { 665 const struct firmware *fw; 666 const void *data; 667 size_t len; 668 }; 669 670 struct ath12k_soc_dp_tx_err_stats { 671 /* TCL Ring Descriptor unavailable */ 672 u32 desc_na[DP_TCL_NUM_RING_MAX]; 673 /* Other failures during dp_tx due to mem allocation failure 674 * idr unavailable etc. 675 */ 676 atomic_t misc_fail; 677 }; 678 679 struct ath12k_soc_dp_stats { 680 u32 err_ring_pkts; 681 u32 invalid_rbm; 682 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 683 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 684 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 685 struct ath12k_soc_dp_tx_err_stats tx_err; 686 }; 687 688 /* Master structure to hold the hw data which may be used in core module */ 689 struct ath12k_base { 690 enum ath12k_hw_rev hw_rev; 691 struct platform_device *pdev; 692 struct device *dev; 693 struct ath12k_qmi qmi; 694 struct ath12k_wmi_base wmi_ab; 695 struct completion fw_ready; 696 int num_radios; 697 /* HW channel counters frequency value in hertz common to all MACs */ 698 u32 cc_freq_hz; 699 700 struct ath12k_htc htc; 701 702 struct ath12k_dp dp; 703 704 void __iomem *mem; 705 unsigned long mem_len; 706 707 struct { 708 enum ath12k_bus bus; 709 const struct ath12k_hif_ops *ops; 710 } hif; 711 712 struct ath12k_ce ce; 713 struct timer_list rx_replenish_retry; 714 struct ath12k_hal hal; 715 /* To synchronize core_start/core_stop */ 716 struct mutex core_lock; 717 /* Protects data like peers */ 718 spinlock_t base_lock; 719 720 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 721 * 722 * Firmware maintains data for all bands but advertises a single 723 * phy to the host which is stored as a single element in this 724 * array. 725 * 726 * Other devices: 727 * 728 * This array will contain as many elements as the number of 729 * radios. 730 */ 731 struct ath12k_pdev pdevs[MAX_RADIOS]; 732 733 /* struct ath12k_hw_params::single_pdev_only devices use this to 734 * store phy specific data 735 */ 736 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 737 u8 fw_pdev_count; 738 739 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 740 741 /* Holds information of wiphy (hw) registration. 742 * 743 * In Multi/Single Link Operation case, all pdevs are registered as 744 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 745 * registered as separate wiphys. 746 */ 747 struct ath12k_hw *ah[MAX_RADIOS]; 748 u8 num_hw; 749 750 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 751 unsigned long long free_vdev_map; 752 unsigned long long free_vdev_stats_id_map; 753 struct list_head peers; 754 wait_queue_head_t peer_mapping_wq; 755 u8 mac_addr[ETH_ALEN]; 756 bool wmi_ready; 757 u32 wlan_init_status; 758 int irq_num[ATH12K_IRQ_NUM_MAX]; 759 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 760 struct napi_struct *napi; 761 struct ath12k_wmi_target_cap_arg target_caps; 762 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 763 bool pdevs_macaddr_valid; 764 765 const struct ath12k_hw_params *hw_params; 766 767 const struct firmware *cal_file; 768 769 /* Below regd's are protected by ab->data_lock */ 770 /* This is the regd set for every radio 771 * by the firmware during initialization 772 */ 773 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 774 /* This regd is set during dynamic country setting 775 * This may or may not be used during the runtime 776 */ 777 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 778 779 /* Current DFS Regulatory */ 780 enum ath12k_dfs_region dfs_region; 781 struct ath12k_soc_dp_stats soc_stats; 782 783 unsigned long dev_flags; 784 struct completion driver_recovery; 785 struct workqueue_struct *workqueue; 786 struct work_struct restart_work; 787 struct workqueue_struct *workqueue_aux; 788 struct work_struct reset_work; 789 atomic_t reset_count; 790 atomic_t recovery_count; 791 atomic_t recovery_start_count; 792 bool is_reset; 793 struct completion reset_complete; 794 struct completion reconfigure_complete; 795 struct completion recovery_start; 796 /* continuous recovery fail count */ 797 atomic_t fail_cont_count; 798 unsigned long reset_fail_timeout; 799 struct { 800 /* protected by data_lock */ 801 u32 fw_crash_counter; 802 } stats; 803 u32 pktlog_defs_checksum; 804 805 struct ath12k_dbring_cap *db_caps; 806 u32 num_db_cap; 807 808 struct timer_list mon_reap_timer; 809 810 struct completion htc_suspend; 811 812 u64 fw_soc_drop_count; 813 bool static_window_map; 814 815 struct work_struct rfkill_work; 816 /* true means radio is on */ 817 bool rfkill_radio_on; 818 819 struct { 820 enum ath12k_bdf_search bdf_search; 821 u32 vendor; 822 u32 device; 823 u32 subsystem_vendor; 824 u32 subsystem_device; 825 } id; 826 827 /* must be last */ 828 u8 drv_priv[] __aligned(sizeof(void *)); 829 }; 830 831 struct ath12k_pdev_map { 832 struct ath12k_base *ab; 833 u8 pdev_idx; 834 }; 835 836 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 837 int ath12k_core_pre_init(struct ath12k_base *ab); 838 int ath12k_core_init(struct ath12k_base *ath12k); 839 void ath12k_core_deinit(struct ath12k_base *ath12k); 840 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 841 enum ath12k_bus bus); 842 void ath12k_core_free(struct ath12k_base *ath12k); 843 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 844 struct ath12k_board_data *bd, 845 char *filename); 846 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 847 struct ath12k_board_data *bd); 848 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 849 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 850 int ath12k_core_check_dt(struct ath12k_base *ath12k); 851 int ath12k_core_check_smbios(struct ath12k_base *ab); 852 void ath12k_core_halt(struct ath12k *ar); 853 int ath12k_core_resume(struct ath12k_base *ab); 854 int ath12k_core_suspend(struct ath12k_base *ab); 855 856 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 857 const char *filename); 858 859 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 860 { 861 switch (state) { 862 case ATH12K_SCAN_IDLE: 863 return "idle"; 864 case ATH12K_SCAN_STARTING: 865 return "starting"; 866 case ATH12K_SCAN_RUNNING: 867 return "running"; 868 case ATH12K_SCAN_ABORTING: 869 return "aborting"; 870 } 871 872 return "unknown"; 873 } 874 875 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 876 { 877 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 878 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 879 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 880 } 881 882 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 883 { 884 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 885 return (struct ath12k_skb_rxcb *)skb->cb; 886 } 887 888 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 889 { 890 return (struct ath12k_vif *)vif->drv_priv; 891 } 892 893 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta) 894 { 895 return (struct ath12k_sta *)sta->drv_priv; 896 } 897 898 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 899 int mac_id) 900 { 901 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 902 } 903 904 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 905 const char *filename, 906 void *buf, size_t buf_len) 907 { 908 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 909 ab->hw_params->fw.dir, filename); 910 } 911 912 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 913 { 914 switch (bus) { 915 case ATH12K_BUS_PCI: 916 return "pci"; 917 } 918 919 return "unknown"; 920 } 921 922 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 923 { 924 return hw->priv; 925 } 926 927 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah) 928 { 929 return ah->radio; 930 } 931 932 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 933 { 934 return ar->ah->hw; 935 } 936 #endif /* _CORE_H_ */ 937