1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/panic_notifier.h> 19 #include <linux/average.h> 20 #include <linux/of.h> 21 #include "qmi.h" 22 #include "htc.h" 23 #include "wmi.h" 24 #include "hal.h" 25 #include "dp.h" 26 #include "ce.h" 27 #include "mac.h" 28 #include "hw.h" 29 #include "hal_rx.h" 30 #include "reg.h" 31 #include "dbring.h" 32 #include "fw.h" 33 #include "acpi.h" 34 #include "wow.h" 35 #include "debugfs_htt_stats.h" 36 #include "coredump.h" 37 38 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 39 40 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 41 42 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 43 44 /* Pending management packets threshold for dropping probe responses */ 45 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 46 47 /* SMBIOS type containing Board Data File Name Extension */ 48 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 49 50 /* SMBIOS type structure length (excluding strings-set) */ 51 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 52 53 /* The magic used by QCA spec */ 54 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 55 56 #define ATH12K_INVALID_HW_MAC_ID 0xFF 57 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 58 59 #define ATH12K_MON_TIMER_INTERVAL 10 60 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 61 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 62 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 63 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 64 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 65 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 66 67 #define ATH12K_MAX_DEVICES 3 68 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS) 69 #define ATH12K_INVALID_GROUP_ID 0xFF 70 #define ATH12K_INVALID_DEVICE_ID 0xFF 71 72 #define ATH12K_MAX_MLO_PEERS 256 73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF 74 75 enum ath12k_bdf_search { 76 ATH12K_BDF_SEARCH_DEFAULT, 77 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 78 }; 79 80 enum wme_ac { 81 WME_AC_BE, 82 WME_AC_BK, 83 WME_AC_VI, 84 WME_AC_VO, 85 WME_NUM_AC 86 }; 87 88 #define ATH12K_HT_MCS_MAX 7 89 #define ATH12K_VHT_MCS_MAX 9 90 #define ATH12K_HE_MCS_MAX 11 91 #define ATH12K_EHT_MCS_MAX 15 92 93 enum ath12k_crypt_mode { 94 /* Only use hardware crypto engine */ 95 ATH12K_CRYPT_MODE_HW, 96 /* Only use software crypto */ 97 ATH12K_CRYPT_MODE_SW, 98 }; 99 100 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 101 { 102 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 103 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 104 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 105 WME_AC_VO); 106 } 107 108 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo) 109 { 110 u64 hi64 = le32_to_cpu(hi); 111 u64 lo64 = le32_to_cpu(lo); 112 113 return (hi64 << 32) | lo64; 114 } 115 116 enum ath12k_skb_flags { 117 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 118 ATH12K_SKB_CIPHER_SET = BIT(1), 119 }; 120 121 struct ath12k_skb_cb { 122 dma_addr_t paddr; 123 struct ath12k *ar; 124 struct ieee80211_vif *vif; 125 dma_addr_t paddr_ext_desc; 126 u32 cipher; 127 u8 flags; 128 u8 link_id; 129 }; 130 131 struct ath12k_skb_rxcb { 132 dma_addr_t paddr; 133 bool is_first_msdu; 134 bool is_last_msdu; 135 bool is_continuation; 136 bool is_mcbc; 137 bool is_eapol; 138 struct hal_rx_desc *rx_desc; 139 u8 err_rel_src; 140 u8 err_code; 141 u8 hw_link_id; 142 u8 unmapped; 143 u8 is_frag; 144 u8 tid; 145 u16 peer_id; 146 bool is_end_of_ppdu; 147 }; 148 149 enum ath12k_hw_rev { 150 ATH12K_HW_QCN9274_HW10, 151 ATH12K_HW_QCN9274_HW20, 152 ATH12K_HW_WCN7850_HW20, 153 ATH12K_HW_IPQ5332_HW10, 154 }; 155 156 enum ath12k_firmware_mode { 157 /* the default mode, standard 802.11 functionality */ 158 ATH12K_FIRMWARE_MODE_NORMAL, 159 160 /* factory tests etc */ 161 ATH12K_FIRMWARE_MODE_FTM, 162 }; 163 164 #define ATH12K_IRQ_NUM_MAX 57 165 #define ATH12K_EXT_IRQ_NUM_MAX 16 166 #define ATH12K_MAX_TCL_RING_NUM 3 167 168 struct ath12k_ext_irq_grp { 169 struct ath12k_base *ab; 170 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 171 u32 num_irq; 172 u32 grp_id; 173 u64 timestamp; 174 bool napi_enabled; 175 struct napi_struct napi; 176 struct net_device *napi_ndev; 177 }; 178 179 enum ath12k_smbios_cc_type { 180 /* disable country code setting from SMBIOS */ 181 ATH12K_SMBIOS_CC_DISABLE = 0, 182 183 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */ 184 ATH12K_SMBIOS_CC_ISO = 1, 185 186 /* worldwide regdomain */ 187 ATH12K_SMBIOS_CC_WW = 2, 188 }; 189 190 struct ath12k_smbios_bdf { 191 struct dmi_header hdr; 192 u8 features_disabled; 193 194 /* enum ath12k_smbios_cc_type */ 195 u8 country_code_flag; 196 197 /* To set specific country, you need to set country code 198 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United 199 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'= 200 * 0x53). To set country to INDONESIA, then country code value = 201 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag = 202 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory 203 * setting. 204 */ 205 u16 cc_code; 206 207 u8 bdf_enabled; 208 u8 bdf_ext[]; 209 } __packed; 210 211 #define HEHANDLE_CAP_PHYINFO_SIZE 3 212 #define HECAP_PHYINFO_SIZE 9 213 #define HECAP_MACINFO_SIZE 5 214 #define HECAP_TXRX_MCS_NSS_SIZE 2 215 #define HECAP_PPET16_PPET8_MAX_SIZE 25 216 217 #define HE_PPET16_PPET8_SIZE 8 218 219 /* 802.11ax PPE (PPDU packet Extension) threshold */ 220 struct he_ppe_threshold { 221 u32 numss_m1; 222 u32 ru_mask; 223 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 224 }; 225 226 struct ath12k_he { 227 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 228 u32 hecap_rxmcsnssmap; 229 u32 hecap_txmcsnssmap; 230 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 231 struct he_ppe_threshold hecap_ppet; 232 u32 heop_param; 233 }; 234 235 enum { 236 WMI_HOST_TP_SCALE_MAX = 0, 237 WMI_HOST_TP_SCALE_50 = 1, 238 WMI_HOST_TP_SCALE_25 = 2, 239 WMI_HOST_TP_SCALE_12 = 3, 240 WMI_HOST_TP_SCALE_MIN = 4, 241 WMI_HOST_TP_SCALE_SIZE = 5, 242 }; 243 244 enum ath12k_scan_state { 245 ATH12K_SCAN_IDLE, 246 ATH12K_SCAN_STARTING, 247 ATH12K_SCAN_RUNNING, 248 ATH12K_SCAN_ABORTING, 249 }; 250 251 enum ath12k_11d_state { 252 ATH12K_11D_IDLE, 253 ATH12K_11D_PREPARING, 254 ATH12K_11D_RUNNING, 255 }; 256 257 enum ath12k_hw_group_flags { 258 ATH12K_GROUP_FLAG_REGISTERED, 259 ATH12K_GROUP_FLAG_UNREGISTER, 260 }; 261 262 enum ath12k_dev_flags { 263 ATH12K_FLAG_CAC_RUNNING, 264 ATH12K_FLAG_CRASH_FLUSH, 265 ATH12K_FLAG_RAW_MODE, 266 ATH12K_FLAG_HW_CRYPTO_DISABLED, 267 ATH12K_FLAG_RECOVERY, 268 ATH12K_FLAG_UNREGISTERING, 269 ATH12K_FLAG_REGISTERED, 270 ATH12K_FLAG_QMI_FAIL, 271 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 272 ATH12K_FLAG_CE_IRQ_ENABLED, 273 ATH12K_FLAG_EXT_IRQ_ENABLED, 274 ATH12K_FLAG_QMI_FW_READY_COMPLETE, 275 ATH12K_FLAG_FTM_SEGMENTED, 276 ATH12K_FLAG_FIXED_MEM_REGION, 277 }; 278 279 struct ath12k_tx_conf { 280 bool changed; 281 u16 ac; 282 struct ieee80211_tx_queue_params tx_queue_params; 283 }; 284 285 struct ath12k_key_conf { 286 enum set_key_cmd cmd; 287 struct list_head list; 288 struct ieee80211_sta *sta; 289 struct ieee80211_key_conf *key; 290 }; 291 292 struct ath12k_vif_cache { 293 struct ath12k_tx_conf tx_conf; 294 struct ath12k_key_conf key_conf; 295 u32 bss_conf_changed; 296 }; 297 298 struct ath12k_rekey_data { 299 u8 kck[NL80211_KCK_LEN]; 300 u8 kek[NL80211_KCK_LEN]; 301 u64 replay_ctr; 302 bool enable_offload; 303 }; 304 305 struct ath12k_link_vif { 306 u32 vdev_id; 307 u32 beacon_interval; 308 u32 dtim_period; 309 u16 ast_hash; 310 u16 ast_idx; 311 u16 tcl_metadata; 312 u8 hal_addr_search_flags; 313 u8 search_type; 314 315 struct ath12k *ar; 316 317 int bank_id; 318 u8 vdev_id_check_en; 319 bool beacon_prot; 320 321 struct wmi_wmm_params_all_arg wmm_params; 322 struct list_head list; 323 324 bool is_created; 325 bool is_started; 326 bool is_up; 327 u8 bssid[ETH_ALEN]; 328 struct cfg80211_bitrate_mask bitrate_mask; 329 struct delayed_work connection_loss_work; 330 int num_legacy_stations; 331 int rtscts_prot_mode; 332 int txpower; 333 bool rsnie_present; 334 bool wpaie_present; 335 u8 vdev_stats_id; 336 u32 punct_bitmap; 337 u8 link_id; 338 struct ath12k_vif *ahvif; 339 struct ath12k_rekey_data rekey_data; 340 struct ath12k_link_stats link_stats; 341 spinlock_t link_stats_lock; /* Protects updates to link_stats */ 342 343 u8 current_cntdown_counter; 344 345 /* only used in station mode */ 346 bool is_sta_assoc_link; 347 348 struct ath12k_reg_tpc_power_info reg_tpc_info; 349 350 bool group_key_valid; 351 struct wmi_vdev_install_key_arg group_key; 352 bool pairwise_key_done; 353 u16 num_stations; 354 }; 355 356 struct ath12k_vif { 357 enum wmi_vdev_type vdev_type; 358 enum wmi_vdev_subtype vdev_subtype; 359 struct ieee80211_vif *vif; 360 struct ath12k_hw *ah; 361 362 union { 363 struct { 364 u32 uapsd; 365 } sta; 366 struct { 367 /* 127 stations; wmi limit */ 368 u8 tim_bitmap[16]; 369 u8 tim_len; 370 u32 ssid_len; 371 u8 ssid[IEEE80211_MAX_SSID_LEN]; 372 bool hidden_ssid; 373 /* P2P_IE with NoA attribute for P2P_GO case */ 374 u32 noa_len; 375 u8 *noa_data; 376 } ap; 377 } u; 378 379 u32 aid; 380 u32 key_cipher; 381 u8 tx_encap_type; 382 bool ps; 383 atomic_t mcbc_gsn; 384 385 struct ath12k_link_vif deflink; 386 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS]; 387 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS]; 388 /* indicates bitmap of link vif created in FW */ 389 u32 links_map; 390 /* Must be last - ends in a flexible-array member. 391 * 392 * FIXME: Driver should not copy struct ieee80211_chanctx_conf, 393 * especially because it has a flexible array. Find a better way. 394 */ 395 struct ieee80211_chanctx_conf chanctx; 396 }; 397 398 struct ath12k_vif_iter { 399 u32 vdev_id; 400 struct ath12k *ar; 401 struct ath12k_link_vif *arvif; 402 }; 403 404 #define HAL_AST_IDX_INVALID 0xFFFF 405 #define HAL_RX_MAX_MCS 12 406 #define HAL_RX_MAX_MCS_HT 31 407 #define HAL_RX_MAX_MCS_VHT 9 408 #define HAL_RX_MAX_MCS_HE 11 409 #define HAL_RX_MAX_MCS_BE 15 410 #define HAL_RX_MAX_NSS 8 411 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 412 413 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ) 414 415 struct ath12k_rx_peer_rate_stats { 416 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 417 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 418 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 419 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1]; 420 u64 nss_count[HAL_RX_MAX_NSS]; 421 u64 bw_count[HAL_RX_BW_MAX]; 422 u64 gi_count[HAL_RX_GI_MAX]; 423 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 424 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1]; 425 }; 426 427 struct ath12k_rx_peer_stats { 428 u64 num_msdu; 429 u64 num_mpdu_fcs_ok; 430 u64 num_mpdu_fcs_err; 431 u64 tcp_msdu_count; 432 u64 udp_msdu_count; 433 u64 other_msdu_count; 434 u64 ampdu_msdu_count; 435 u64 non_ampdu_msdu_count; 436 u64 stbc_count; 437 u64 beamformed_count; 438 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 439 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 440 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 441 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 442 u64 rx_duration; 443 u64 dcm_count; 444 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 445 struct ath12k_rx_peer_rate_stats pkt_stats; 446 struct ath12k_rx_peer_rate_stats byte_stats; 447 }; 448 449 #define ATH12K_HE_MCS_NUM 12 450 #define ATH12K_VHT_MCS_NUM 10 451 #define ATH12K_BW_NUM 5 452 #define ATH12K_NSS_NUM 4 453 #define ATH12K_LEGACY_NUM 12 454 #define ATH12K_GI_NUM 4 455 #define ATH12K_HT_MCS_NUM 32 456 457 enum ath12k_pkt_rx_err { 458 ATH12K_PKT_RX_ERR_FCS, 459 ATH12K_PKT_RX_ERR_TKIP, 460 ATH12K_PKT_RX_ERR_CRYPT, 461 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 462 ATH12K_PKT_RX_ERR_MAX, 463 }; 464 465 enum ath12k_ampdu_subfrm_num { 466 ATH12K_AMPDU_SUBFRM_NUM_10, 467 ATH12K_AMPDU_SUBFRM_NUM_20, 468 ATH12K_AMPDU_SUBFRM_NUM_30, 469 ATH12K_AMPDU_SUBFRM_NUM_40, 470 ATH12K_AMPDU_SUBFRM_NUM_50, 471 ATH12K_AMPDU_SUBFRM_NUM_60, 472 ATH12K_AMPDU_SUBFRM_NUM_MORE, 473 ATH12K_AMPDU_SUBFRM_NUM_MAX, 474 }; 475 476 enum ath12k_amsdu_subfrm_num { 477 ATH12K_AMSDU_SUBFRM_NUM_1, 478 ATH12K_AMSDU_SUBFRM_NUM_2, 479 ATH12K_AMSDU_SUBFRM_NUM_3, 480 ATH12K_AMSDU_SUBFRM_NUM_4, 481 ATH12K_AMSDU_SUBFRM_NUM_MORE, 482 ATH12K_AMSDU_SUBFRM_NUM_MAX, 483 }; 484 485 enum ath12k_counter_type { 486 ATH12K_COUNTER_TYPE_BYTES, 487 ATH12K_COUNTER_TYPE_PKTS, 488 ATH12K_COUNTER_TYPE_MAX, 489 }; 490 491 enum ath12k_stats_type { 492 ATH12K_STATS_TYPE_SUCC, 493 ATH12K_STATS_TYPE_FAIL, 494 ATH12K_STATS_TYPE_RETRY, 495 ATH12K_STATS_TYPE_AMPDU, 496 ATH12K_STATS_TYPE_MAX, 497 }; 498 499 struct ath12k_htt_data_stats { 500 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 501 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 502 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 503 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 504 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 505 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 506 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 507 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 508 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 509 }; 510 511 struct ath12k_htt_tx_stats { 512 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 513 u64 tx_duration; 514 u64 ba_fails; 515 u64 ack_fails; 516 u16 ru_start; 517 u16 ru_tones; 518 u32 mu_group[MAX_MU_GROUP_ID]; 519 }; 520 521 struct ath12k_per_ppdu_tx_stats { 522 u16 succ_pkts; 523 u16 failed_pkts; 524 u16 retry_pkts; 525 u32 succ_bytes; 526 u32 failed_bytes; 527 u32 retry_bytes; 528 }; 529 530 struct ath12k_wbm_tx_stats { 531 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 532 }; 533 534 DECLARE_EWMA(avg_rssi, 10, 8) 535 536 struct ath12k_link_sta { 537 struct ath12k_link_vif *arvif; 538 struct ath12k_sta *ahsta; 539 540 /* link address similar to ieee80211_link_sta */ 541 u8 addr[ETH_ALEN]; 542 543 /* the following are protected by ar->data_lock */ 544 u32 changed; /* IEEE80211_RC_* */ 545 u32 bw; 546 u32 nss; 547 u32 smps; 548 549 struct wiphy_work update_wk; 550 struct rate_info txrate; 551 struct rate_info last_txrate; 552 u64 rx_duration; 553 u64 tx_duration; 554 u8 rssi_comb; 555 struct ewma_avg_rssi avg_rssi; 556 u8 link_id; 557 struct ath12k_rx_peer_stats *rx_stats; 558 struct ath12k_wbm_tx_stats *wbm_tx_stats; 559 u32 bw_prev; 560 u32 peer_nss; 561 s8 rssi_beacon; 562 563 /* For now the assoc link will be considered primary */ 564 bool is_assoc_link; 565 566 /* for firmware use only */ 567 u8 link_idx; 568 u32 tx_retry_failed; 569 u32 tx_retry_count; 570 }; 571 572 struct ath12k_reoq_buf { 573 void *vaddr; 574 dma_addr_t paddr_aligned; 575 u32 size; 576 }; 577 578 struct ath12k_sta { 579 struct ath12k_vif *ahvif; 580 enum hal_pn_type pn_type; 581 struct ath12k_link_sta deflink; 582 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 583 /* indicates bitmap of link sta created in FW */ 584 u16 links_map; 585 u8 assoc_link_id; 586 u16 ml_peer_id; 587 u8 num_peer; 588 589 enum ieee80211_sta_state state; 590 591 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1]; 592 }; 593 594 #define ATH12K_HALF_20MHZ_BW 10 595 #define ATH12K_2GHZ_MIN_CENTER 2412 596 #define ATH12K_2GHZ_MAX_CENTER 2484 597 #define ATH12K_5GHZ_MIN_CENTER 4900 598 #define ATH12K_5GHZ_MAX_CENTER 5920 599 #define ATH12K_6GHZ_MIN_CENTER 5935 600 #define ATH12K_6GHZ_MAX_CENTER 7115 601 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1) 602 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1) 603 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 604 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 605 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 606 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 607 #define ATH12K_NUM_CHANS 101 608 #define ATH12K_MAX_5GHZ_CHAN 173 609 610 static inline bool ath12k_is_2ghz_channel_freq(u32 freq) 611 { 612 return freq >= ATH12K_MIN_2GHZ_FREQ && 613 freq <= ATH12K_MAX_2GHZ_FREQ; 614 } 615 616 enum ath12k_hw_state { 617 ATH12K_HW_STATE_OFF, 618 ATH12K_HW_STATE_ON, 619 ATH12K_HW_STATE_RESTARTING, 620 ATH12K_HW_STATE_RESTARTED, 621 ATH12K_HW_STATE_WEDGED, 622 ATH12K_HW_STATE_TM, 623 /* Add other states as required */ 624 }; 625 626 /* Antenna noise floor */ 627 #define ATH12K_DEFAULT_NOISE_FLOOR -95 628 629 struct ath12k_ftm_event_obj { 630 u32 data_pos; 631 u32 expected_seq; 632 u8 *eventdata; 633 }; 634 635 struct ath12k_fw_stats { 636 u32 pdev_id; 637 u32 stats_id; 638 struct list_head pdevs; 639 struct list_head vdevs; 640 struct list_head bcn; 641 u32 num_vdev_recvd; 642 u32 num_bcn_recvd; 643 }; 644 645 struct ath12k_dbg_htt_stats { 646 enum ath12k_dbg_htt_ext_stats_type type; 647 u32 cfg_param[4]; 648 u8 reset; 649 struct debug_htt_stats_req *stats_req; 650 }; 651 652 struct ath12k_debug { 653 struct dentry *debugfs_pdev; 654 struct dentry *debugfs_pdev_symlink; 655 struct ath12k_dbg_htt_stats htt_stats; 656 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type; 657 bool tpc_request; 658 struct completion tpc_complete; 659 struct wmi_tpc_stats_arg *tpc_stats; 660 u32 rx_filter; 661 bool extd_rx_stats; 662 }; 663 664 struct ath12k_per_peer_tx_stats { 665 u32 succ_bytes; 666 u32 retry_bytes; 667 u32 failed_bytes; 668 u32 duration; 669 u16 succ_pkts; 670 u16 retry_pkts; 671 u16 failed_pkts; 672 u16 ru_start; 673 u16 ru_tones; 674 u8 ba_fails; 675 u8 ppdu_type; 676 u32 mu_grpid; 677 u32 mu_pos; 678 bool is_ampdu; 679 }; 680 681 struct ath12k_pdev_rssi_offsets { 682 s32 temp_offset; 683 s8 min_nf_dbm; 684 /* Cache the sum here to avoid calculating it every time in hot path 685 * noise_floor = min_nf_dbm + temp_offset 686 */ 687 s32 noise_floor; 688 }; 689 690 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 691 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 692 693 struct ath12k { 694 struct ath12k_base *ab; 695 struct ath12k_pdev *pdev; 696 struct ath12k_hw *ah; 697 struct ath12k_wmi_pdev *wmi; 698 struct ath12k_pdev_dp dp; 699 u8 mac_addr[ETH_ALEN]; 700 u32 ht_cap_info; 701 u32 vht_cap_info; 702 struct ath12k_he ar_he; 703 bool supports_6ghz; 704 struct { 705 struct completion started; 706 struct completion completed; 707 struct completion on_channel; 708 struct delayed_work timeout; 709 enum ath12k_scan_state state; 710 bool is_roc; 711 int roc_freq; 712 bool roc_notify; 713 struct wiphy_work vdev_clean_wk; 714 struct ath12k_link_vif *arvif; 715 } scan; 716 717 struct { 718 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 719 struct ieee80211_sband_iftype_data 720 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 721 } mac; 722 723 unsigned long dev_flags; 724 unsigned int filter_flags; 725 u32 min_tx_power; 726 u32 max_tx_power; 727 u32 txpower_limit_2g; 728 u32 txpower_limit_5g; 729 u32 txpower_scale; 730 u32 power_scale; 731 u32 chan_tx_pwr; 732 u32 num_stations; 733 u32 max_num_stations; 734 735 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 736 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info, 737 * channel context data, survey info, test mode data, regd_channel_update_queue. 738 */ 739 spinlock_t data_lock; 740 741 struct list_head arvifs; 742 /* should never be NULL; needed for regular htt rx */ 743 struct ieee80211_channel *rx_channel; 744 745 /* valid during scan; needed for mgmt rx during scan */ 746 struct ieee80211_channel *scan_channel; 747 748 u8 cfg_tx_chainmask; 749 u8 cfg_rx_chainmask; 750 u8 num_rx_chains; 751 u8 num_tx_chains; 752 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 753 u8 pdev_idx; 754 u8 lmac_id; 755 u8 hw_link_id; 756 757 struct completion peer_assoc_done; 758 struct completion peer_delete_done; 759 760 int install_key_status; 761 struct completion install_key_done; 762 763 int last_wmi_vdev_start_status; 764 struct completion vdev_setup_done; 765 struct completion vdev_delete_done; 766 767 int num_peers; 768 int max_num_peers; 769 u32 num_started_vdevs; 770 u32 num_created_vdevs; 771 unsigned long long allocated_vdev_map; 772 773 struct idr txmgmt_idr; 774 /* protects txmgmt_idr data */ 775 spinlock_t txmgmt_idr_lock; 776 atomic_t num_pending_mgmt_tx; 777 wait_queue_head_t txmgmt_empty_waitq; 778 779 /* cycle count is reported twice for each visited channel during scan. 780 * access protected by data_lock 781 */ 782 u32 survey_last_rx_clear_count; 783 u32 survey_last_cycle_count; 784 785 /* Channel info events are expected to come in pairs without and with 786 * COMPLETE flag set respectively for each channel visit during scan. 787 * 788 * However there are deviations from this rule. This flag is used to 789 * avoid reporting garbage data. 790 */ 791 bool ch_info_can_report_survey; 792 struct survey_info survey[ATH12K_NUM_CHANS]; 793 struct completion bss_survey_done; 794 795 struct work_struct regd_update_work; 796 struct work_struct regd_channel_update_work; 797 struct list_head regd_channel_update_queue; 798 799 struct wiphy_work wmi_mgmt_tx_work; 800 struct sk_buff_head wmi_mgmt_tx_queue; 801 802 struct ath12k_wow wow; 803 struct completion target_suspend; 804 bool target_suspend_ack; 805 struct ath12k_per_peer_tx_stats peer_tx_stats; 806 struct list_head ppdu_stats_info; 807 u32 ppdu_stat_list_depth; 808 809 struct ath12k_per_peer_tx_stats cached_stats; 810 u32 last_ppdu_id; 811 u32 cached_ppdu_id; 812 #ifdef CONFIG_ATH12K_DEBUGFS 813 struct ath12k_debug debug; 814 #endif 815 816 bool dfs_block_radar_events; 817 bool monitor_vdev_created; 818 bool monitor_started; 819 int monitor_vdev_id; 820 821 struct wiphy_radio_freq_range freq_range; 822 823 bool nlo_enabled; 824 825 /* Protected by wiphy::mtx lock. */ 826 u32 vdev_id_11d_scan; 827 struct completion completed_11d_scan; 828 enum ath12k_11d_state state_11d; 829 u8 alpha2[REG_ALPHA2_LEN]; 830 bool regdom_set_by_user; 831 struct completion regd_update_completed; 832 833 struct completion fw_stats_complete; 834 struct completion fw_stats_done; 835 836 struct completion mlo_setup_done; 837 u32 mlo_setup_status; 838 u8 ftm_msgref; 839 struct ath12k_fw_stats fw_stats; 840 unsigned long last_tx_power_update; 841 842 s8 max_allowed_tx_power; 843 struct ath12k_pdev_rssi_offsets rssi_info; 844 }; 845 846 struct ath12k_hw { 847 struct ieee80211_hw *hw; 848 struct device *dev; 849 850 /* Protect the write operation of the hardware state ath12k_hw::state 851 * between hardware start<=>reconfigure<=>stop transitions. 852 */ 853 struct mutex hw_mutex; 854 enum ath12k_hw_state state; 855 bool regd_updated; 856 bool use_6ghz_regd; 857 858 u8 num_radio; 859 860 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS); 861 862 /* protected by wiphy_lock() */ 863 struct list_head ml_peers; 864 865 /* Keep last */ 866 struct ath12k radio[] __aligned(sizeof(void *)); 867 }; 868 869 struct ath12k_band_cap { 870 u32 phy_id; 871 u32 max_bw_supported; 872 u32 ht_cap_info; 873 u32 he_cap_info[2]; 874 u32 he_mcs; 875 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 876 struct ath12k_wmi_ppe_threshold_arg he_ppet; 877 u16 he_6ghz_capa; 878 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 879 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 880 u32 eht_mcs_20_only; 881 u32 eht_mcs_80; 882 u32 eht_mcs_160; 883 u32 eht_mcs_320; 884 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 885 u32 eht_cap_info_internal; 886 }; 887 888 struct ath12k_pdev_cap { 889 u32 supported_bands; 890 u32 ampdu_density; 891 u32 vht_cap; 892 u32 vht_mcs; 893 u32 he_mcs; 894 u32 tx_chain_mask; 895 u32 rx_chain_mask; 896 u32 tx_chain_mask_shift; 897 u32 rx_chain_mask_shift; 898 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 899 u32 eml_cap; 900 u32 mld_cap; 901 bool nss_ratio_enabled; 902 u8 nss_ratio_info; 903 }; 904 905 struct mlo_timestamp { 906 u32 info; 907 u32 sync_timestamp_lo_us; 908 u32 sync_timestamp_hi_us; 909 u32 mlo_offset_lo; 910 u32 mlo_offset_hi; 911 u32 mlo_offset_clks; 912 u32 mlo_comp_clks; 913 u32 mlo_comp_timer; 914 }; 915 916 struct ath12k_pdev { 917 struct ath12k *ar; 918 u32 pdev_id; 919 u32 hw_link_id; 920 struct ath12k_pdev_cap cap; 921 u8 mac_addr[ETH_ALEN]; 922 struct mlo_timestamp timestamp; 923 }; 924 925 struct ath12k_fw_pdev { 926 u32 pdev_id; 927 u32 phy_id; 928 u32 supported_bands; 929 }; 930 931 struct ath12k_board_data { 932 const struct firmware *fw; 933 const void *data; 934 size_t len; 935 }; 936 937 struct ath12k_device_dp_tx_err_stats { 938 /* TCL Ring Descriptor unavailable */ 939 u32 desc_na[DP_TCL_NUM_RING_MAX]; 940 /* Other failures during dp_tx due to mem allocation failure 941 * idr unavailable etc. 942 */ 943 atomic_t misc_fail; 944 }; 945 946 struct ath12k_device_dp_stats { 947 u32 err_ring_pkts; 948 u32 invalid_rbm; 949 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 950 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 951 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 952 struct ath12k_device_dp_tx_err_stats tx_err; 953 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES]; 954 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES]; 955 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON]; 956 u32 fw_tx_status[MAX_FW_TX_STATUS]; 957 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX]; 958 u32 tx_enqueued[DP_TCL_NUM_RING_MAX]; 959 u32 tx_completed[DP_TCL_NUM_RING_MAX]; 960 }; 961 962 struct ath12k_reg_freq { 963 u32 start_freq; 964 u32 end_freq; 965 }; 966 967 struct ath12k_mlo_memory { 968 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 969 int mlo_mem_size; 970 bool init_done; 971 }; 972 973 struct ath12k_hw_link { 974 u8 device_id; 975 u8 pdev_idx; 976 }; 977 978 /* Holds info on the group of devices that are registered as a single 979 * wiphy, protected with struct ath12k_hw_group::mutex. 980 */ 981 struct ath12k_hw_group { 982 struct list_head list; 983 u8 id; 984 u8 num_devices; 985 u8 num_probed; 986 u8 num_started; 987 unsigned long flags; 988 struct ath12k_base *ab[ATH12K_MAX_DEVICES]; 989 990 /* protects access to this struct */ 991 struct mutex mutex; 992 993 /* Holds information of wiphy (hw) registration. 994 * 995 * In Multi/Single Link Operation case, all pdevs are registered as 996 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 997 * registered as separate wiphys. 998 */ 999 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO]; 1000 u8 num_hw; 1001 bool mlo_capable; 1002 struct device_node *wsi_node[ATH12K_MAX_DEVICES]; 1003 struct ath12k_mlo_memory mlo_mem; 1004 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO]; 1005 bool hw_link_id_init_done; 1006 }; 1007 1008 /* Holds WSI info specific to each device, excluding WSI group info */ 1009 struct ath12k_wsi_info { 1010 u32 index; 1011 u32 hw_link_id_base; 1012 }; 1013 1014 struct ath12k_dp_profile_params { 1015 u32 tx_comp_ring_size; 1016 u32 rxdma_monitor_buf_ring_size; 1017 u32 rxdma_monitor_dst_ring_size; 1018 u32 num_pool_tx_desc; 1019 u32 rx_desc_count; 1020 }; 1021 1022 struct ath12k_mem_profile_based_param { 1023 u32 num_vdevs; 1024 u32 max_client_single; 1025 u32 max_client_dbs; 1026 u32 max_client_dbs_sbs; 1027 struct ath12k_dp_profile_params dp_params; 1028 }; 1029 1030 /* Master structure to hold the hw data which may be used in core module */ 1031 struct ath12k_base { 1032 enum ath12k_hw_rev hw_rev; 1033 struct platform_device *pdev; 1034 struct device *dev; 1035 struct ath12k_qmi qmi; 1036 struct ath12k_wmi_base wmi_ab; 1037 struct completion fw_ready; 1038 u8 device_id; 1039 int num_radios; 1040 /* HW channel counters frequency value in hertz common to all MACs */ 1041 u32 cc_freq_hz; 1042 1043 struct ath12k_dump_file_data *dump_data; 1044 size_t ath12k_coredump_len; 1045 struct work_struct dump_work; 1046 1047 struct ath12k_htc htc; 1048 1049 struct ath12k_dp dp; 1050 1051 void __iomem *mem; 1052 unsigned long mem_len; 1053 1054 void __iomem *mem_ce; 1055 u32 ce_remap_base_addr; 1056 bool ce_remap; 1057 1058 struct { 1059 enum ath12k_bus bus; 1060 const struct ath12k_hif_ops *ops; 1061 } hif; 1062 1063 struct { 1064 struct completion wakeup_completed; 1065 u32 wmi_conf_rx_decap_mode; 1066 } wow; 1067 1068 struct ath12k_ce ce; 1069 struct timer_list rx_replenish_retry; 1070 struct ath12k_hal hal; 1071 /* To synchronize core_start/core_stop */ 1072 struct mutex core_lock; 1073 /* Protects data like peers */ 1074 spinlock_t base_lock; 1075 1076 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 1077 * 1078 * Firmware maintains data for all bands but advertises a single 1079 * phy to the host which is stored as a single element in this 1080 * array. 1081 * 1082 * Other devices: 1083 * 1084 * This array will contain as many elements as the number of 1085 * radios. 1086 */ 1087 struct ath12k_pdev pdevs[MAX_RADIOS]; 1088 1089 /* struct ath12k_hw_params::single_pdev_only devices use this to 1090 * store phy specific data 1091 */ 1092 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 1093 u8 fw_pdev_count; 1094 1095 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 1096 1097 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 1098 unsigned long long free_vdev_map; 1099 unsigned long long free_vdev_stats_id_map; 1100 struct list_head peers; 1101 wait_queue_head_t peer_mapping_wq; 1102 u8 mac_addr[ETH_ALEN]; 1103 bool wmi_ready; 1104 u32 wlan_init_status; 1105 int irq_num[ATH12K_IRQ_NUM_MAX]; 1106 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 1107 struct napi_struct *napi; 1108 struct ath12k_wmi_target_cap_arg target_caps; 1109 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 1110 bool pdevs_macaddr_valid; 1111 1112 const struct ath12k_hw_params *hw_params; 1113 1114 const struct firmware *cal_file; 1115 1116 /* Below regd's are protected by ab->data_lock */ 1117 /* This is the regd set for every radio 1118 * by the firmware during initialization 1119 */ 1120 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 1121 /* This regd is set during dynamic country setting 1122 * This may or may not be used during the runtime 1123 */ 1124 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 1125 1126 struct ath12k_reg_info *reg_info[MAX_RADIOS]; 1127 1128 /* Current DFS Regulatory */ 1129 enum ath12k_dfs_region dfs_region; 1130 struct ath12k_device_dp_stats device_stats; 1131 #ifdef CONFIG_ATH12K_DEBUGFS 1132 struct dentry *debugfs_soc; 1133 #endif 1134 1135 unsigned long dev_flags; 1136 struct completion driver_recovery; 1137 struct workqueue_struct *workqueue; 1138 struct work_struct restart_work; 1139 struct workqueue_struct *workqueue_aux; 1140 struct work_struct reset_work; 1141 atomic_t reset_count; 1142 atomic_t recovery_count; 1143 bool is_reset; 1144 struct completion reset_complete; 1145 /* continuous recovery fail count */ 1146 atomic_t fail_cont_count; 1147 unsigned long reset_fail_timeout; 1148 struct work_struct update_11d_work; 1149 u8 new_alpha2[2]; 1150 struct { 1151 /* protected by data_lock */ 1152 u32 fw_crash_counter; 1153 } stats; 1154 u32 pktlog_defs_checksum; 1155 1156 struct ath12k_dbring_cap *db_caps; 1157 u32 num_db_cap; 1158 1159 struct completion htc_suspend; 1160 1161 u64 fw_soc_drop_count; 1162 bool static_window_map; 1163 1164 struct work_struct rfkill_work; 1165 /* true means radio is on */ 1166 bool rfkill_radio_on; 1167 1168 struct { 1169 enum ath12k_bdf_search bdf_search; 1170 u32 vendor; 1171 u32 device; 1172 u32 subsystem_vendor; 1173 u32 subsystem_device; 1174 } id; 1175 1176 struct { 1177 u32 api_version; 1178 1179 const struct firmware *fw; 1180 const u8 *amss_data; 1181 size_t amss_len; 1182 const u8 *amss_dualmac_data; 1183 size_t amss_dualmac_len; 1184 const u8 *m3_data; 1185 size_t m3_len; 1186 1187 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 1188 bool fw_features_valid; 1189 } fw; 1190 1191 const struct hal_rx_ops *hal_rx_ops; 1192 1193 struct completion restart_completed; 1194 1195 #ifdef CONFIG_ACPI 1196 1197 struct { 1198 bool started; 1199 u32 func_bit; 1200 bool acpi_tas_enable; 1201 bool acpi_bios_sar_enable; 1202 bool acpi_disable_11be; 1203 bool acpi_disable_rfkill; 1204 bool acpi_cca_enable; 1205 bool acpi_band_edge_enable; 1206 bool acpi_enable_bdf; 1207 u32 bit_flag; 1208 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN]; 1209 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 1210 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 1211 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 1212 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 1213 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 1214 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 1215 } acpi; 1216 1217 #endif /* CONFIG_ACPI */ 1218 1219 struct notifier_block panic_nb; 1220 1221 struct ath12k_hw_group *ag; 1222 struct ath12k_wsi_info wsi_info; 1223 enum ath12k_firmware_mode fw_mode; 1224 struct ath12k_ftm_event_obj ftm_event_obj; 1225 bool hw_group_ref; 1226 1227 /* Denote whether MLO is possible within the device */ 1228 bool single_chip_mlo_support; 1229 1230 struct ath12k_reg_freq reg_freq_2ghz; 1231 struct ath12k_reg_freq reg_freq_5ghz; 1232 struct ath12k_reg_freq reg_freq_6ghz; 1233 const struct ath12k_mem_profile_based_param *profile_param; 1234 1235 /* must be last */ 1236 u8 drv_priv[] __aligned(sizeof(void *)); 1237 }; 1238 1239 struct ath12k_pdev_map { 1240 struct ath12k_base *ab; 1241 u8 pdev_idx; 1242 }; 1243 1244 struct ath12k_fw_stats_vdev { 1245 struct list_head list; 1246 1247 u32 vdev_id; 1248 u32 beacon_snr; 1249 u32 data_snr; 1250 u32 num_tx_frames[WLAN_MAX_AC]; 1251 u32 num_rx_frames; 1252 u32 num_tx_frames_retries[WLAN_MAX_AC]; 1253 u32 num_tx_frames_failures[WLAN_MAX_AC]; 1254 u32 num_rts_fail; 1255 u32 num_rts_success; 1256 u32 num_rx_err; 1257 u32 num_rx_discard; 1258 u32 num_tx_not_acked; 1259 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 1260 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 1261 }; 1262 1263 struct ath12k_fw_stats_bcn { 1264 struct list_head list; 1265 1266 u32 vdev_id; 1267 u32 tx_bcn_succ_cnt; 1268 u32 tx_bcn_outage_cnt; 1269 }; 1270 1271 struct ath12k_fw_stats_pdev { 1272 struct list_head list; 1273 1274 /* PDEV stats */ 1275 s32 ch_noise_floor; 1276 u32 tx_frame_count; 1277 u32 rx_frame_count; 1278 u32 rx_clear_count; 1279 u32 cycle_count; 1280 u32 phy_err_count; 1281 u32 chan_tx_power; 1282 u32 ack_rx_bad; 1283 u32 rts_bad; 1284 u32 rts_good; 1285 u32 fcs_bad; 1286 u32 no_beacons; 1287 u32 mib_int_count; 1288 1289 /* PDEV TX stats */ 1290 s32 comp_queued; 1291 s32 comp_delivered; 1292 s32 msdu_enqued; 1293 s32 mpdu_enqued; 1294 s32 wmm_drop; 1295 s32 local_enqued; 1296 s32 local_freed; 1297 s32 hw_queued; 1298 s32 hw_reaped; 1299 s32 underrun; 1300 s32 tx_abort; 1301 s32 mpdus_requed; 1302 u32 tx_ko; 1303 u32 data_rc; 1304 u32 self_triggers; 1305 u32 sw_retry_failure; 1306 u32 illgl_rate_phy_err; 1307 u32 pdev_cont_xretry; 1308 u32 pdev_tx_timeout; 1309 u32 pdev_resets; 1310 u32 stateless_tid_alloc_failure; 1311 u32 phy_underrun; 1312 u32 txop_ovf; 1313 1314 /* PDEV RX stats */ 1315 s32 mid_ppdu_route_change; 1316 s32 status_rcvd; 1317 s32 r0_frags; 1318 s32 r1_frags; 1319 s32 r2_frags; 1320 s32 r3_frags; 1321 s32 htt_msdus; 1322 s32 htt_mpdus; 1323 s32 loc_msdus; 1324 s32 loc_mpdus; 1325 s32 oversize_amsdu; 1326 s32 phy_errs; 1327 s32 phy_err_drop; 1328 s32 mpdu_errs; 1329 }; 1330 1331 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 1332 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag); 1333 int ath12k_core_pre_init(struct ath12k_base *ab); 1334 int ath12k_core_init(struct ath12k_base *ath12k); 1335 void ath12k_core_deinit(struct ath12k_base *ath12k); 1336 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 1337 enum ath12k_bus bus); 1338 void ath12k_core_free(struct ath12k_base *ath12k); 1339 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 1340 struct ath12k_board_data *bd, 1341 char *filename); 1342 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 1343 struct ath12k_board_data *bd); 1344 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 1345 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 1346 int ath12k_core_check_dt(struct ath12k_base *ath12k); 1347 int ath12k_core_check_smbios(struct ath12k_base *ab); 1348 void ath12k_core_halt(struct ath12k *ar); 1349 int ath12k_core_resume_early(struct ath12k_base *ab); 1350 int ath12k_core_resume(struct ath12k_base *ab); 1351 int ath12k_core_suspend(struct ath12k_base *ab); 1352 int ath12k_core_suspend_late(struct ath12k_base *ab); 1353 void ath12k_core_hw_group_unassign(struct ath12k_base *ab); 1354 u8 ath12k_get_num_partner_link(struct ath12k *ar); 1355 1356 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 1357 const char *filename); 1358 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 1359 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 1360 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab); 1361 1362 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag); 1363 void ath12k_fw_stats_init(struct ath12k *ar); 1364 void ath12k_fw_stats_bcn_free(struct list_head *head); 1365 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats); 1366 void ath12k_fw_stats_reset(struct ath12k *ar); 1367 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab, 1368 int index); 1369 1370 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 1371 { 1372 switch (state) { 1373 case ATH12K_SCAN_IDLE: 1374 return "idle"; 1375 case ATH12K_SCAN_STARTING: 1376 return "starting"; 1377 case ATH12K_SCAN_RUNNING: 1378 return "running"; 1379 case ATH12K_SCAN_ABORTING: 1380 return "aborting"; 1381 } 1382 1383 return "unknown"; 1384 } 1385 1386 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 1387 { 1388 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 1389 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1390 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1391 } 1392 1393 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 1394 { 1395 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 1396 return (struct ath12k_skb_rxcb *)skb->cb; 1397 } 1398 1399 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif) 1400 { 1401 return (struct ath12k_vif *)vif->drv_priv; 1402 } 1403 1404 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta) 1405 { 1406 return (struct ath12k_sta *)sta->drv_priv; 1407 } 1408 1409 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta) 1410 { 1411 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv); 1412 } 1413 1414 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif) 1415 { 1416 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv); 1417 } 1418 1419 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1420 int mac_id) 1421 { 1422 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1423 } 1424 1425 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1426 const char *filename, 1427 void *buf, size_t buf_len) 1428 { 1429 const char *fw_name = NULL; 1430 1431 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name); 1432 1433 if (fw_name && strncmp(filename, "board", 5)) 1434 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR, 1435 ab->hw_params->fw.dir, fw_name, filename); 1436 else 1437 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1438 ab->hw_params->fw.dir, filename); 1439 } 1440 1441 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1442 { 1443 switch (bus) { 1444 case ATH12K_BUS_PCI: 1445 return "pci"; 1446 case ATH12K_BUS_AHB: 1447 return "ahb"; 1448 } 1449 1450 return "unknown"; 1451 } 1452 1453 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1454 { 1455 return hw->priv; 1456 } 1457 1458 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1459 { 1460 if (WARN(hw_link_id >= ah->num_radio, 1461 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1462 hw_link_id = 0; 1463 1464 return &ah->radio[hw_link_id]; 1465 } 1466 1467 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar) 1468 { 1469 return ar->ah; 1470 } 1471 1472 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1473 { 1474 return ar->ah->hw; 1475 } 1476 1477 #define for_each_ar(ah, ar, index) \ 1478 for ((index) = 0; ((index) < (ah)->num_radio && \ 1479 ((ar) = &(ah)->radio[(index)])); (index)++) 1480 1481 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx) 1482 { 1483 return ag->ah[idx]; 1484 } 1485 1486 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx, 1487 struct ath12k_hw *ah) 1488 { 1489 ag->ah[idx] = ah; 1490 } 1491 1492 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab) 1493 { 1494 return ab->ag; 1495 } 1496 1497 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag, 1498 u8 device_id) 1499 { 1500 return ag->ab[device_id]; 1501 } 1502 1503 static inline s32 ath12k_pdev_get_noise_floor(struct ath12k *ar) 1504 { 1505 lockdep_assert_held(&ar->data_lock); 1506 1507 return ar->rssi_info.noise_floor; 1508 } 1509 1510 #endif /* _CORE_H_ */ 1511